Commit graph

466 commits

Author SHA1 Message Date
michael
cfba157fdd spi_slave: add valid check for DMA buffers
The DMA cannot receive data correctly when the buffer address is not
WORD aligned. Currently we only check whether the buffer is in the DRAM
region.

The DMA always write in WORDs, so the length arguments should also be
multiples of 32 bits.

A check is added to see whether the buffer is WORD aligned and has valid
length.
2018-11-26 03:49:26 +00:00
Ivan Grokhotkov
00a13bd8d3 Merge branch 'bugfix/init_memctl' into 'master'
bootloader, esp32: add workaround for Tensilica erratum 572

See merge request idf/esp-idf!3605
2018-11-19 18:36:47 +08:00
Ivan Grokhotkov
a46b884a14 Merge branch 'feature/unit_test_example' into 'master'
Move Unity into components, add unit test example

See merge request idf/esp-idf!3562
2018-11-19 18:35:54 +08:00
Ivan Grokhotkov
964f5a91f7 bootloader, esp32: add workaround for Tensilica erratum 572
If zero-overhead loop buffer is enabled, under certain rare conditions
when executing a zero-overhead loop, the CPU may attempt to execute an invalid instruction. Work around by disabling the buffer.
2018-11-19 04:39:35 +00:00
Ivan Grokhotkov
6091021e83 unity: separate common and IDF specific functionality
New unity component can be used for testing other applications.
Upstream version of Unity is included as a submodule.
Utilities specific to ESP-IDF unit tests (partitions, leak checking
setup/teardown functions, etc) are kept only in unit-test-app.
Kconfig options are added to allow disabling certain Unity features.
2018-11-19 12:36:31 +08:00
Renz Bagaporo
63411fc556 tools: implement linker script generation 2018-11-16 12:42:02 +08:00
Ivan Grokhotkov
7efb3926c5 Merge branch 'feature/build_system_multi_target' into 'master'
build system: support for multiple targets (CMake only)

See merge request idf/esp-idf!3499
2018-11-12 15:30:36 +08:00
Ivan Grokhotkov
ccfa134533 build system: support for multiple targets 2018-11-11 21:46:02 +08:00
shawwwn
288d9b75e9 rtc_clk: bugfix: incorrect divider setting in rtc_clk_cpu_freq_to_config()
Merges https://github.com/espressif/esp-idf/pull/2404
2018-11-08 15:57:10 +05:30
Konstantin Kondrashov
8bba348528 aes/sha/mpi: Bugfix a use of shared registers.
This commit resolves a blocking in esp_aes_block function.

Introduce:
The problem was in the fact that AES is switched off at the moment when he should give out the processed data. But because of the disabled, the operation can not be completed successfully, there is an infinite hang. The reason for this behavior is that the registers for controlling the inclusion of AES, SHA, MPI have shared registers and they were not protected from sharing.

Fix some related issue with shared using of AES SHA RSA accelerators.

Closes: https://github.com/espressif/esp-idf/issues/2295#issuecomment-432898137
2018-11-05 04:22:47 +00:00
Michael (XIAO Xufeng)
4132834faa test: fix the unit test fail issue under single_core config
Introduced in 97e3542947.

The previous commit frees the IRAM part when single core, but doesn't
change the memory layout functions. The unit test mallocs IRAM memory
from the heap, accidently into the new-released region, which doesn't
match the memory layout function.

This commit update the memory layout function to fix this.
2018-10-31 17:04:32 +08:00
Jiang Jiang Jian
97e3542947 Merge branch 'bugfix/release_some_memory_on_single_core_mode' into 'master'
release memory not used in single core mode

See merge request idf/esp-idf!2733
2018-10-30 15:53:31 +08:00
Michael (XIAO Xufeng)
d0361a32d7 test: fix the IRAM type conflict issue using heap_caps_malloc 2018-10-25 12:31:44 +08:00
Renz Bagaporo
cc774111bf cmake: Add support for test build 2018-10-20 12:07:24 +08:00
Ivan Grokhotkov
bd11965f6c Merge branch 'bugfix/ndebug_build' into 'master'
soc,sdmmc: fix build failures when NDEBUG is used

See merge request idf/esp-idf!3352
2018-10-19 11:55:37 +08:00
Angus Gratton
f53fef9936 Secure Boot & Flash encryption: Support 3/4 Coding Scheme
Includes esptool update to v2.6-beta1
2018-10-16 16:24:10 +11:00
Ivan Grokhotkov
a20d9287fe soc: use _EARLY versions of ESP_LOG
Some logging done in soc component may happen before logging via
stdout is possible. Use _EARLY version of log calls to make sure that
output is visible. The downside is that application does not have a
way to silence these logs. However since the soc component doesn’t
use any LOGV/LOGD/LOGI and only logs warnings and errors, this should
not impact the application.
2018-10-15 14:59:46 +08:00
Ivan Grokhotkov
ab68b9d90d soc,sdmmc: fix build failures when NDEBUG is used
Use explicit error checking instead of asserts, use SOC_LOG to print
error/warning messages where needed.
2018-10-15 14:57:12 +08:00
Ivan Grokhotkov
22b840f3df bootloader: don’t reload RTC_FAST DRAM after deep sleep
When CONFIG_ESP32_RTCDATA_IN_FAST_MEM is enabled, RTC data is placed
into RTC_FAST memory region, viewed from the data bus. However the
bootloader was missing a check that this region should not be
overwritten after deep sleep, which caused .rtc.bss segment to loose
its contents after wakeup.
2018-09-29 14:02:16 +08:00
Jack
2efd6859ed release memory not used in single core mode
1. do not start ipc task in single core mode
2. do not use APP cpu cache memory in single core mode
3. relase data used in rom by APP cpu
2018-09-25 15:13:47 +08:00
negativekelvin
8e2856b83d soc: fix CPU frequency not updated in rtc_clk_init
Add missing call to rtc_clk_cpu_freq_set_config

Merges https://github.com/espressif/esp-idf/pull/2398
2018-09-12 21:13:42 +08:00
Renz Christian Bagaporo
d9939cedd9 cmake: make main a component again 2018-09-11 09:44:12 +08:00
Angus Gratton
cff2ef695a Merge branch 'master' into feature/cmake 2018-09-06 20:23:04 +08:00
Angus Gratton
b355854d4d Merge branch 'master' into feature/cmake 2018-09-05 10:35:04 +08:00
Konstantin Kondrashov
38098b713f esp32/sleep: Add a function to disable logging from ROM code 2018-09-04 16:03:18 +08:00
Konstantin Kondrashov
9c715d7946 bootloader_support: Fix enable rtc_wdt for resolve issue with varying supply
Eliminates the issue with the lock up in the bootloader due to a power drawdown during its operation.

Closes https://github.com/espressif/esp-idf/issues/1814
2018-09-03 05:43:01 +00:00
Angus Gratton
5fbfd20f10 Merge branch 'master' into feature/cmake 2018-08-30 18:52:31 +08:00
Angus Gratton
a9c4ed7139 Merge branch 'master' into feature/cmake 2018-08-30 18:51:01 +08:00
Ivan Grokhotkov
78fab8a0f9 sdmmc: implement partial DDR support
Works for 3.3V eMMC in 4 line mode.
Not implemented:
- DDR mode for SD cards (UHS-I) also need voltage to be switched to 1.8V.
- 8-line DDR mode for eMMC to be implemented later.
2018-08-30 13:11:54 +08:00
Mahavir Jain
f0fa66a50e rtc_wdt: fix overflow issue with setting wdt interval
Signed-off-by: Mahavir Jain <mahavir@espressif.com>
2018-08-24 18:06:39 +05:30
Ivan Grokhotkov
88d40e01b4 Merge branch 'feature/rtc_slowclk_extra_options' into 'master'
Add more RTC_SLOW_CLK options

See merge request idf/esp-idf!2984
2018-08-23 11:27:14 +08:00
Ivan Grokhotkov
902344c516 Merge branch 'bugfix/trace_mem_layout_pro_cpu' into 'master'
soc: fix trace memory region for single core mode

See merge request idf/esp-idf!3029
2018-08-22 16:51:43 +08:00
Ivan Grokhotkov
5bf3654637 soc/rtc: Force power on 8M clock if it is used to derive RTC slow clock 2018-08-22 11:33:20 +08:00
Ivan Grokhotkov
8365f0f5d2 soc/rtc: add support for external 32k oscillator
Compared to external 32k XTAL, when active oscillator is used as input,
some parameters need to be set differently.
2018-08-22 11:33:20 +08:00
Ivan Grokhotkov
90f5456dba Merge branch 'feature/rtc_cpu_freq_config' into 'master'
soc/rtc: Refactoring, support CPU frequencies lower than XTAL

See merge request idf/esp-idf!2856
2018-08-22 11:32:08 +08:00
Ivan Grokhotkov
e59571eece soc/rtc_clk: reduce data size by disabling CSWTCH generation
Saves about 200 bytes of DRAM at the expense of 4 bytes in IRAM.
2018-08-21 13:02:46 +08:00
Ivan Grokhotkov
db2f0f45be soc/rtc_clk: split rtc_clk_init into separate object file
rtc_clk_init and related functions don’t need to be in IRAM/DRAM.
2018-08-21 13:02:46 +08:00
Ivan Grokhotkov
bcf79e5cf2 tests: use new CPU frequency setting API 2018-08-21 13:02:46 +08:00
Ivan Grokhotkov
bec70ce298 esp32: use new CPU frequency setting API 2018-08-21 13:02:46 +08:00
Ivan Grokhotkov
2e31cce390 soc/rtc: CPU frequency settings refactoring
Previous APIs used to set CPU frequency used CPU frequencies listed in
rtc_cpu_freq_t enumeration. This was problematic for two reasons.
First, supporting many possible frequency values obtained by dividing
XTAL frequency was hard, as every value would have to be listed in
the enumeration. Since different base XTAL frequencies are supported,
this further complicated things, since not all of these divided
frequencies would be valid for any given XTAL frequency. Second,
having to deal with enumeration values often involved switch
statements to convert between enumeration and MHz values, handle
PLL/XTAL frequencies separately, etc.

This change introduces rtc_cpu_freq_config_t structure, which contains
CPU frequency (in MHz) and information on how this frequency has to
be generated: clock source (XTAL/PLL), source frequency, clock
divider value. More fields can be added to this structure in the
future. This structure simplifies many parts of the code, since both
frequency value and frequency generation settings can be accessed in
any place in code without the need for conversions.

Additionally, this change adds setting of REF_TICK dividers to support
frequencies lower then XTAL with DFS.
2018-08-21 13:02:03 +08:00
Jiang Jiang Jian
00ef8bf726 Merge branch 'feature/decrease_bt_contrller_memory_with_new_mem_reserved' into 'master'
decrease bt contrller memory with new mem reserved

See merge request idf/esp-idf!2791
2018-08-16 19:12:44 +08:00
Angus Gratton
ff2404a272 Merge branch 'master' into feature/cmake 2018-08-16 17:14:17 +10:00
Mahavir Jain
0075e2f316 soc: fix trace memory region for single core mode
Signed-off-by: Mahavir Jain <mahavir@espressif.com>
2018-08-15 20:52:39 +05:30
Konstantin Kondrashov
a8e46775c6 soc/rtc_wdt: Add API functions for rtc_wdt
Added functions:
rtc_wdt_protect_off/on
rtc_wdt_set_length_of_reset_signal
rtc_wdt_set_stage
rtc_wdt_set_time
rtc_wdt_feed
rtc_wdt_disable/enable
2018-08-14 17:48:02 +05:00
Tian Hao
ee787085f9 component/bt : decrease memory consumption by conn number
1. BLE only with 9(max) connection will decrease 3K DRAM
2. BR/EDR only with 7(max) connection will decrease 16K DRAM
3. Any of BLE or BR/EDR connection number decrease will also decrease DRAM consumption
4. Decrease one BLE connection will save about 1KB DRAM
5. Decrease one BR/EDR ACL connection will save about 1.2KB DRAM
6. Decrease one BR/EDR SCO/eSCO will save 2KB DRAM.
7. fix some definition and kconfig
8. remove 1.2k of vhci tx cache and make .bss & .data to heap about 1.4K
9. modify BT Reserved Memory size and modify example to support new bt kconfig
2018-08-14 02:29:17 +00:00
Ivan Grokhotkov
8739111218 Merge branch 'bugfix/gpio_reset_bitmask' into 'master'
gpio: Bitmask overflow fix in gpio_reset_pin

See merge request idf/esp-idf!2966
2018-08-10 17:35:26 +08:00
Taavi Hein
f7749e18a8 gpio: Bitmask overflow fix in gpio_reset_pin
For pins 32 and up the BIT(nr) macro used here overflowed,
causing undetermined GPIO pins to be reset.
Example: freeing SPI device/bus where CS is on pin 33
caused debug UART to cease communication, TXD0 was
disabled.

Fixed as BIT64(nr) macro, to be used elsewhere as needed.
For example in definitions like GPIO_SEL_32..GPIO_SEL_39.
2018-08-08 15:31:17 +03:00
Angus Gratton
a5ae5ac4b3 soc: Allow components to reserve fixed memory ranges that they need
No longer necessary to keep all reserved addresses in 'soc'.

Means 'soc' does not need to know about 'bt', for example.

Also means that Bluetooth can be enabled in config without any memory being reserved for BT
controller. Only if code calling the BT controller is linked in, will this memory be reserved...
2018-08-06 01:37:55 +00:00
David Cermak
409c91bcb9 removed possible uint16 access to 32bit register, noted fifo use not recommended 2018-07-23 07:57:18 +02:00
Ivan Grokhotkov
fec079cd44 Merge branch 'bugfix/rtc_io_hold_regs' into 'master'
Fix errors in rtc_gpio_desc values

See merge request idf/esp-idf!2765
2018-07-19 15:04:42 +08:00
Ivan Grokhotkov
5376a06d7b Merge branch 'bugfix/range_CONFIG_ESP32_RTC_CLK_CAL_CYCLES' into 'master'
soc/clk: Fix range CONFIG_ESP32_RTC_CLK_CAL_CYCLES

See merge request idf/esp-idf!2719
2018-07-17 19:43:11 +08:00
negativekelvin
8a9e3875ed
Fix errors in rtc_gpio_desc values 2018-07-12 23:16:15 -07:00
Angus Gratton
a67d5d89e0 Replace all DOS line endings with Unix
Command run was:
git ls-tree -r HEAD --name-only | xargs dos2unix
2018-07-12 19:10:37 +08:00
Konstantin Kondrashov
ac3508615a soc/clk: Fix range CONFIG_ESP32_RTC_CLK_CAL_CYCLES
Fixed the error division on zero.
Also fixed range CONFIG_ESP32_RTC_CLK_CAL_CYCLES in Kconfig.
Fixed a overflow error by TIMG in the function rtc_clk_cal_internal. This error was due to a limit in values TIMG_RTC_CALI_MAX=0x7FFF (to write the slowclk_cycles) and TIMG_RTC_CALI_VALUE=0x1FFFFFF (to read xtal_cycles). Added assert finctions.

Closes https://github.com/espressif/esp-idf/issues/2147
2018-07-10 11:56:12 +05:00
Darian Leung
1d2727f4c8 CAN Driver
The following commit contains the first version of the ESP32 CAN Driver.

closes #544
2018-07-04 14:01:57 +08:00
Konstantin Kondrashov
32da455384 soc: Fix check_long_hold_gpio and move def to soc
Fix factory_reset_pin init as input
Move definition a structure rtc_gpio_desc to soc

Closes https://github.com/espressif/esp-idf/issues/2030
2018-06-22 09:20:27 +05:00
Ivan Grokhotkov
4b91c82cc4 Merge branch 'feat/sdio_pullup' into 'master'
feature(sdio): add features to make SDIO slave compatible with more devkits

See merge request idf/esp-idf!2454
2018-06-20 13:58:56 +08:00
michael
5b37a96ddc feature(sdio): allow to enable internal pullups of the SDIO host and slave as a debug feature
NOTE: the internal pullups are not totally reliable, please do add external pullups on your bus.
2018-06-14 12:04:22 +08:00
Michael (XIAO Xufeng)
ebfda40b7c refactor(spi): move pin information into soc folder 2018-06-14 11:29:15 +08:00
Michael (XIAO Xufeng)
939e5693a5 chore(spi): fix the terms of native to iomux 2018-06-06 06:08:39 +00:00
michael
5cf7d3768d feat(spi_master): fine tune the timing of SPI 2018-06-06 06:08:39 +00:00
Angus Gratton
6b9784cc45 Merge branch 'master' into feature/cmake_update 2018-05-31 14:46:23 +10:00
Angus Gratton
3e1a93e5a7 soc: rtc_vddsdio_get_config() In default configuration, VDD_SDIO LDO is always enabled
When using bootstrapping pin to enable VDD_SDIO, the internal LDO is always enabled at either 1.8V
or 3.3V.
2018-05-25 15:14:13 +10:00
Angus Gratton
d775cc4c4c soc: Fix description of rtc_config_t.tieh, add macros
Usage of TIEH was correct but description had 1.8V & 3.3V backwards.

Add macro definitions for TIEH values to improve readability.
2018-05-25 14:58:37 +10:00
Angus Gratton
b8312a26c0 Merge branch 'feature/sdio_slave' into 'master'
feature(sdio_slave): add support for sdio_slave

See merge request idf/esp-idf!1829
2018-05-22 09:43:35 +08:00
Konstantin Kondrashov
e5b280f173 dport: Bigfix dport_read code move to IRAM
A new method of workaround an error with DPORT is to ensure that the APB is read and followed by the DPORT register without interruptions and pauses. This fix places this implementation in the IRAM to exclude errors associated with the cache miss.
2018-05-21 22:00:51 +05:00
Michael (XIAO Xufeng)
c73575de4f feat(sdio_slave): add headers for sdio slave components: slc, host, hinf 2018-05-21 23:48:33 +08:00
wangmengyang
22e21b38f7 component/bt: implement bluetooth modem sleep mode, one mode for BLE only and another for dual mode bluetooth
1. provide options for bluetooth low power mode
2. provide two options for bluetooth low power clock: main XTAL and external 32kHz XTAL
3. provide function and callbacks to control bluetooth low power mode, including enable/disable sleep, software wakeup request, low power clock settings, check power state, etc
4. modify vhci API vhci_host_send_packet to use blocking mode
5. note that DFS and bluetooth modem sleep can not be used together currently.
2018-05-19 15:37:26 +08:00
Angus Gratton
7ae1e9463e Merge branch 'bugfix/rtc_xtal_tests' into 'master'
ci: Only run XTAL unit tests assuming board has an XTAL

See merge request idf/esp-idf!2401
2018-05-15 18:44:46 +08:00
Angus Gratton
05e09a5bac ci: Only run XTAL unit tests assuming board has an XTAL, run less repeats 2018-05-15 15:43:24 +08:00
Angus Gratton
d1066e9d7f Merge branch 'feature/dport_access' into 'master'
soc: Dport access with pre-read register APB

See merge request idf/esp-idf!2257
2018-05-15 15:32:28 +08:00
Angus Gratton
662fe55996 Merge branch 'bugfix/select_rtc_slow_clk' into 'master'
esp32/clk: Fix starting rtc oscillator if it bad

See merge request idf/esp-idf!2215
2018-05-15 12:57:22 +08:00
Konstantin Kondrashov
9ad0760b9d esp32/clk:Fix starting rtc oscillator if it is bad
If the RTC crystal is bad or has no matched capacitance, then you do not need to start such the crystal. It is necessary to determine this case, output an error (about impossibility to start from the oscillator) and start from the internal RC of the chain.

Reduced the default value of the number of bootstrap cycles. Because we can oscillating the oscillator which then stops. (in Kconfig). Changed from 100 to 5.

The number of calibration cycles has been increased. It is the main criterion for estimating the launch of an oscillator. A large increase leads to an increase in the load time, as well as the stability of recognition of this case. (in Kconfig).
Changed from 1024 to 3000.
2018-05-15 08:59:15 +05:00
Konstantin Kondrashov
8f80cc733d soc: Change DPORT access
When two CPUs read the area of the DPORT and the area of the APB, the result is corrupted for the CPU that read the APB area.
And another CPU has valid data.

The method of eliminating this error.
Before reading the registers of the DPORT, make a preliminary reading of the APB register.
In this case, the joint access of the two CPUs to the registers of the APB and the DPORT is successful.
2018-05-14 17:54:57 +05:00
jack
c384fa2492 rename clock enable and reset bits for SPI modules
1.The names of clock enable and reset bits do not match with TRM, just rename them.
2018-05-14 16:45:03 +08:00
Jiang Jiang Jian
db90f49758 Merge branch 'bugfix/update_emac_h' into 'master'
update emac_reg_v2.h

See merge request idf/esp-idf!2050
2018-05-07 16:16:52 +08:00
Angus Gratton
1cb5712463 cmake: Add component dependency support
Components should set the COMPONENT_REQUIRES & COMPONENT_PRIVATE_REQUIRES variables to define their
requirements.
2018-04-30 09:59:20 +10:00
Angus Gratton
c671a0c3eb build system: Initial cmake support, work in progress 2018-04-30 09:59:20 +10:00
Ivan Grokhotkov
94250e42a0 sleep: optimize light sleep wakeup latency 2018-04-26 19:36:47 +08:00
Ivan Grokhotkov
ac623a9756 soc/rtc: restore dbg attenuation when waking from sleep
This fixes inability to enter deep sleep after waking up from light sleep
2018-04-26 18:52:46 +08:00
Ivan Grokhotkov
d38b22b11b soc/rtc, sleep: don’t lower the bias for wakeup state
This fixes watchdog resets occurring during wakeup from light sleep.
2018-04-26 18:52:45 +08:00
Ivan Grokhotkov
b0a91630fb soc/rtc: allow main XTAL to be powered on in sleep 2018-04-26 18:52:45 +08:00
Ivan Grokhotkov
3c78faa0a9 soc/rtc: don’t switch frequency in rtc_sleep_init 2018-04-26 18:52:45 +08:00
shangke
5fc130f2c0 update emac_reg_v2.h 2018-04-25 14:54:09 +08:00
Ivan Grokhotkov
52f9a5ca16 Merge branch 'bugfix/sdspi_wp_cd_pins' into 'master'
sdmmc, sdspi: fix handling of CD and WP

See merge request idf/esp-idf!2285
2018-04-24 20:53:47 +08:00
Ivan Grokhotkov
85ab4fc83e sdmmc host: add handling of CD and WP pins
Previous version of the code only connected CD and WP to the
peripheral, in fact the hardware does not use the values of these
signals automatically. This adds code to read CD and WP values when
command is executed and return errors if card is not present, or
write command is executed when WP signal is active.
2018-04-24 19:08:44 +08:00
Ivan Grokhotkov
9c7207ed3c Merge branch 'bugfix/soc_clk_out_fields' into 'master'
soc/io_mux: make CLK_OUT fields compatible with REG_SET/GET_FIELD

See merge request idf/esp-idf!2133
2018-04-13 19:42:20 +08:00
Ivan Grokhotkov
ee600784c5 sdmmc: add SDIO support
- Add SDIO support at protocol layer (probing, data transfer, interrupts)
- Add SDIO interrupts support in SDMMC host
- Add test (communicate with ESP32 in SDIO download mode)
2018-04-11 11:07:13 +08:00
Ivan Grokhotkov
2522c1b2f9 Merge branch 'bugfix/rtc_clk_fixes' into 'master'
Power management and RTC fixes

See merge request idf/esp-idf!2131
2018-04-10 18:17:02 +08:00
Angus Gratton
53234ef2bc Merge branch 'refactor/rtc_split_module' into 'master'
bugfix(rtc): make sure peripherals (DAC, HALL) are turned off before conversion.

See merge request idf/esp-idf!1848
2018-04-04 09:00:58 +08:00
Angus Gratton
da27816314 Merge branch 'feat/add_efuse_cpu_freq_rating' into 'master'
efuse/add cpu freq rating

See merge request idf/esp-idf!1994
2018-03-29 05:59:52 +08:00
Michael (Xiao Xufeng)
cef8baf424 bugfix(rtc): make sure peripherals (DAC, HALL) are turned off before conversion.
refactor structure of ``rtc_module.c`` to make it more clearly.

Closes https://github.com/espressif/esp-idf/issues/1517
2018-03-28 17:10:01 +08:00
Ivan Grokhotkov
b007b89b84 soc/io_mux: make CLK_OUT fields compatible with REG_SET/GET_FIELD 2018-03-27 12:10:18 +08:00
Ivan Grokhotkov
43b5fdd5c9 soc/rtc: fix switching between 80/160 and 240MHz
Previous code contained a check for PLL frequency to be 240MHz, while
in fact 240MHz was a CPU frequency; corresponding PLL frequency is
480MHz. Fixed the comparison and replaced integer MHz values with an
enum.
2018-03-27 10:55:59 +08:00
Ivan Grokhotkov
48d55e22e7 soc/rtc: run 32k XTAL startup test only in PSRAM config
PSRAM tests run on ESP-WROVER-KIT boards, which have the 32k XTAL
installed.
2018-03-26 10:14:13 +08:00
Ivan Grokhotkov
887b6e2925 Merge branch 'bugfix/rtc_clk_32k_bootstrap' into 'master'
bugfix/rtc_clk_32k_bootstrap: Fix starting 32k RTC

See merge request idf/esp-idf!2085
2018-03-21 18:38:49 +08:00
Konstantin Kondrashov
f7df532ec0 bugfix/rtc_clk_32k_bootstrap: Fix starting 32k RTC
1. External 32kHz crystal is started for too long or it may not start at all. It is often observed at the first start.
2. At the first start, it is possible that the crystal did not start. And the recorded period was recorded as 0. Which led to a division error by zero during the transition to the deep sleep mode (Maybe somewhere else).
3. Added a unit test to test a new method of oscillation an external crystal.
4. Added a new method of oscillating of an external crystal. The legs of the crystal are fed with a 32 kHz frequency.

The new method eliminates these errors.

Added unit test: `\esp-idf\components\soc\esp32\test\test_rtc_clk.c`: `make TEST_COMPONENTS=soc`
- 8 Test starting external RTC crystal. Will pass.

`Bootstrap cycles for external 32kHz crystal` - is specified in the file Kconfig by default 100.

QA tested a new method of oscillation the crystal on 25 boards. The supply of square waves on the crystal showed a 100% result in contrast to the previous method of launching the crystal. After the tests, the old method was deleted.

Closes TW19143
2018-03-21 13:27:56 +05:00
Ivan Grokhotkov
1618dbc9a5 soc/rtc: wait for frequency switch to complete
The fast path of CPU frequency switch function, used in DFS, was not
waiting for the frequency switch to complete when switching from XTAL
to PLL. This resulted in incorrect reads from peripherals on APB,
where two consecutive reads could return the same value. For example,
in esp_timer, read of FRC_COUNT_REG would return same value as the
preceding read of FRC_ALARM_REG, causing time to jump by the value of
FRC_ALARM_REG / apb_freq_mhz.
2018-03-20 18:27:32 +08:00
Darian Leung
8b1277c55f efuse/add cpu freq rating
This commit adds support for CPU max freqeuency rating
bits in CPU. Bootloader will now print an error if attempting
to 160MHz rated ESP32 at 240MHz.

EFUSE_CHIP_VER_RESERVE has been replaced by the
frequency rating bits. Dependancies on EFUSE_CHIP_VER_RESERVE
have been changed to use EFUSE_CHIP_VER_PKG
2018-03-07 12:16:51 +08:00
Darian Leung
0c9e2c0fba esp_adc_cal/Remove lookup table
This commit removes the lookup table mode due to inferior performance when compared
to linear mode under attenuation 0, 1 and 2. However small portions of the lookup table
are kept for the higher voltages of atten 3 (above ADC reading 2880). That voltage range
in atten 3 has non linear characteristics making the LUT performan better than linear mode.
2018-02-22 20:01:41 +08:00
Darian Leung
73cdfbfe79 esp_adc_cal/Add eFuse functionality
This commit updates the esp_adc_cal ocmponent to support new calibration methods
which utilize calibratoin values stored in eFuse. This commit includes LUT mode
2018-02-13 21:22:48 +08:00
Ivan Grokhotkov
e381c6adde Merge branch 'bugfix/fix_i2s_adc_mode' into 'master'
driver(i2s): fix broken i2s adc mode

See merge request idf/esp-idf!1653
2018-02-11 12:58:58 +08:00
Wangjialin
451f69cc2e driver(i2s): fix broken i2s adc mode
1. Move i2s reset code from i2s_stop to i2s_start.
2. add RTC API to set sw mode for ADC
3. add description for adc_power_always_on()
4. add lock for i2s dma and RTC ADC functions.
5. add ADC read task in example

reported from bbs:  https://esp32.com/viewtopic.php?f=13&t=3490&p=17522#p17522
reported from github: https://github.com/espressif/esp-idf/issues/1333
2018-02-07 17:17:20 +08:00
Jeroen Domburg
70ab924dbb Especially when internal memory fills up, some FreeRTOS structures (queues etc) get allocated in psram. These structures also contain a spinlock, which needs an atomic-compare-swap operation to work. The psram hardware, however, does not support this operation. As a workaround, this patch detects these spinlocks and will, instead of S32C1I, use equivalent C-code to simulate the behaviour, with an (internal) mux for atomicity. 2018-02-02 17:11:06 +08:00
Angus Gratton
4297c337f9 esp32: Add IO_MUX_GPIOxx register names to match iomux names used in TRM
The TRM describes IOMUX registers are IO_MUX_x_REG for x in GPIO0-39.

Until now ESP-IDF describes them as PERIPHS_IO_MUX_(pinname)_U

This commit adds additional IOMUX register names which match the ones used in the TRM.
2018-01-30 17:09:37 +08:00
Ivan Grokhotkov
ffaf145056 Merge branch 'bugfix/xtal_freq_estimation' into 'master'
soc/rtc_clk: fix loss of precision in estimation of XTAL frequency

See merge request !1763
2018-01-23 15:37:47 +08:00
kooho
492db0591d Fix uart fifo overflow bug 2018-01-12 14:42:54 +08:00
Ivan Grokhotkov
914ab07567 Merge branch 'feature/ulp_i2c_reg' into 'master'
soc,ulp: add register definitions of RTC_I2C peripheral

See merge request !1762
2018-01-11 12:08:25 +08:00
Deng Xin
337f790fd3 bug fix of assert happen in PSRAM 2018-01-09 20:01:06 +08:00
Ivan Grokhotkov
7c584e80b0 soc/rtc_clk: fix loss of precision in estimation of XTAL frequency
RTC_FAST_CLK_FREQ_APPROX is defined as 8500000, so 0.5MHz part was lost
when dividing by MHZ. Since cal_val is 64-bit the parens can be removed.

With 40MHz XTAL for a nominal ESP32 chip, this fixes estimated XTAL
frequency from 38 to 40MHz.
2018-01-08 23:31:21 +08:00
Ivan Grokhotkov
dba291416f soc,ulp: add register definitions of RTC_I2C peripheral 2018-01-08 21:28:14 +08:00
Angus Gratton
c69af42b96 esp32: Fix backwards compatibility for pre-v2.1 bootloaders
Older bootloaders don't set RTC_XTAL_FREQ_REG or call rtc_clk_init(),
app needs to pick this up.

Reported at
https://esp32.com/viewtopic.php?f=2&t=3939&p=17836
2017-12-18 13:45:57 +11:00
Ivan Grokhotkov
a99483a727 docs: add information about execution time of ULP instructions 2017-12-11 14:05:41 +08:00
Ivan Grokhotkov
ca751648fa ulp: document the need to wait for RTC to be ready for wakeup 2017-12-11 12:11:46 +08:00
krzychb
421592a8eb LEDC Driver: Added back original definitions of 'duty_resolution' and 'clock_divider'. This update is to provide backward compatibility with ESP-IDF 2.1. 2017-12-04 21:12:56 +01:00
Jiang Jiang Jian
c672fc54fd Merge branch 'feature/ledc_more_meaningful_parameter_names' into 'master'
Provided more meaningful parameter names by renaming 'bit_num' to 'duty_resoluti…

See merge request !1440
2017-12-01 19:33:53 +08:00
Vitor Massaru Iha
cf768380b1 soc: Remove redefinition of MCU_SEL_M
Signed-off-by: Vitor Massaru Iha <vitor@massaru.org>

Merges #1290
2017-11-22 11:01:42 +08:00
Ivan Grokhotkov
3369f15fa3 soc/rtc: don't power down BIAS_I2C along with APLL if other PLL is used
If enable == false, and SOC_CLK_SEL == PLL, the code would would
erroneously set RTC_CNTL_BIAS_I2C_FORCE_PD. This change fixes the logic.
2017-11-20 15:27:16 +08:00
krzychb
d488bb7bac Provided more meaningful parameter names by renaming 'bit_num' to 'duty_resolution' and 'div_num' to 'clock_divider' 2017-11-15 08:08:12 +01:00
Ivan Grokhotkov
f22c681c1c soc/rtc: raise core voltage when 80MHz flash frequency is used
To achieve reliable operation with GD flash at 80MHz, need to raise
core voltage.
This causes the following current consumption increase:

At 80MHz: from 29mA to 33mA
At 160MHz: from 41mA to 47mA

Test conditions: 2 cores running code from IRAM, remaining peripherals
clock gated.
2017-11-08 21:13:02 +08:00
Jiang Jiang Jian
abacf8d2a0 Merge branch 'bugfix/rtc_and_restart_fixes' into 'master'
rtc_clk and esp_restart fixes

See merge request !1458
2017-11-04 01:34:38 +08:00
Ivan Grokhotkov
a02b30ccda efuse: add package definitions for PICOD2/D4 2017-11-03 15:49:10 +08:00
Ivan Grokhotkov
fb9c106bcb soc/rtc: add function to get/set VDDSDIO configuration
Also consider case of VDDSDIO force powered on in rtc_sleep.
2017-11-03 15:49:09 +08:00
Ivan Grokhotkov
5a294c9acd soc/gpio: fix description of GPIO_STRAP_REG 2017-11-03 15:49:09 +08:00
Ivan Grokhotkov
80eb3b6ddb Merge branch 'bugfix/light_sleep_current' into 'master'
soc/rtc: fix increased current consumption in light sleep

See merge request !1483
2017-11-02 18:26:23 +08:00
XiaXiaotian
42cefc173f refractor WiFi clock setting
Do not set WiFi clock in PHY initializing function, move it to WiFi
   start/stop function.
2017-11-02 15:24:21 +08:00
wangmengyang
bd6394db92 component/bt: clean up WIFI_CLK_EN_REG settings for Bluetooth
1. move settings of WIFI_CLK_EN_REG for bluetooth into controller init/deinit APIs
2. modify the bit mask used in phy_rf init/deinit to use WIFI-BT shared bits
2017-11-02 15:24:21 +08:00
Ivan Grokhotkov
9bfb45aa1d soc/rtc: fix increased current consumption in light sleep
This fixes a configuration issue of RTC, which caused light sleep current
to be 1.35mA instead of 0.85mA.
2017-11-02 13:57:26 +08:00
Ivan Grokhotkov
eb5752c635 esp_restart: fix possible race while stalling other CPU, enable WDT early
Previously esp_restart would stall the other CPU before enabling RTC_WDT.
If the other CPU was executing an s32c1i instruction, the lock signal
from CPU to the arbiter would still be held after CPU was stalled. If
the CPU running esp_restart would then try to access the same locked
memory pool, it would be stuck, because lock signal would never be
released.

With this change, esp_restart resets the other CPU before stalling it.
Ideally, we would want to reset the CPU and keep it in reset, but the
hardware doesn't have such feature for PRO_CPU (it is possible to hold
APP_CPU in reset using DPORT register). Given that ROM code will not use
s32c1i in the first few hundred cycles, doing reset and then stall seems
to be safe.

In addition to than, RTC_WDT initialization is moved to the beginning of
the function, to prevent possible lock-up if CPU stalling still has any
issue.
2017-10-26 19:53:53 +08:00
Ivan Grokhotkov
f11ad0c904 soc/rtc: fix spurious warnings about XTAL frequency on startup
1. Make sure that 8MD256 clock used to estimate XTAL frequency is enabled
   before trying to use rtc_clk_cal_ratio.
   This fixes "Bogus XTAL frequency: 0 MHz" warnings after software reset.

2. Don't call rtc_clk_xtal_freq_estimate if XTAL frequency is already
   known. This reduces startup time after deep sleep or software reset.

3. Compare known XTAL frequency and estimated one before printing a
   warning. This fixes "Possibly invalid CONFIG_ESP32_XTAL_FREQ setting
   (40MHz). Detected 40 MHz." warnings.
2017-10-26 19:53:53 +08:00
Ivan Grokhotkov
9317cb3434 soc/rtc: add tests for CPU frequency switching
These tests switch between PLL and XTAL frequencies for 10 seconds.
2017-10-26 19:53:53 +08:00
Ivan Grokhotkov
6d4ed4ff6c soc/rtc: wait for SLOW_CLK cycle when switching CPU clock
Previous implementation waited for 20us after setting
RTC_CNTL_SOC_CLK_SEL_XTL register, using ets_delay_us, assuming that
the CPU was running at XTAL frequency. In reality, clock switch happened
on the next RTC_SLOW_CLK cycle, and CPU could be running at the previous
frequency (for example, 240 MHz) until then.
ets_delay_us would wait for 20 us * 40 cycles per us = 800 CPU cycles
(assuming 40 MHz XTAL; even less with a 26 MHz XTAL).
But if CPU was running at 240 MHz, 800 cycles would pass in just 3.3us,
while SLOW_CLK cycle could happen as much as 1/150kHz = 6.7us after
RTC_CNTL_SOC_CLK_SEL_XTL was set. So the software would not actually wait
long enough for the clock switch to happen, and would disable the PLL
while CPU was still clocked from PLL, leading to a halt.

This implementation uses rtc_clk_wait_for_slow_cycle() function to wait
until the clock switch, removing the need to wait for a fixed number of
CPU cycles.
2017-10-26 19:53:53 +08:00
Ivan Grokhotkov
05a0fbd49b soc/rtc: add a function to wait for slow clock cycle
Some RTC features are synchronized to RTC_SLOW_CLK, so sometimes
software needs to wait for the next slow clock cycle.
This function implements waiting using Timer Group clock calibration
feature.
2017-10-26 19:53:53 +08:00
esp32de
7c0020bfd0 feat(adc2): append adc2 support and api and the lock with WIFI module
append adc support and api
- esp_err_t adc2_config_width(adc_bits_width_t width_bit);
- esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten);
- int adc2_get_voltage(adc2_channel_t channel);
2017-10-26 14:35:29 +08:00
Ivan Grokhotkov
59b7d98fec Merge branch 'feature/dfs' into 'master'
Dynamic frequency scaling

See merge request !1189
2017-10-22 12:34:11 +08:00
Ivan Grokhotkov
b6f37bda97 Merge branch 'feature/i2s_built_in_adc' into 'master'
feature(I2S-ADC): add ADC mode for I2S.

See merge request !1077
2017-10-20 15:52:56 +08:00
Ivan Grokhotkov
099565635b soc: correct values of SOC_BYTE_ACCESSIBLE_LOW, SOC_MEM_INTERNAL_LOW
Internal byte accessible memory starts with Internal ROM 1 at 0x3FF90000.
Region of RTC fast memory starting at 0x3FF80000 is not used in IDF as
it is mapped to PRO CPU only.
2017-10-19 21:35:21 +08:00
Ivan Grokhotkov
fba9678c56 uart: add support for REF_TICK 2017-10-18 14:19:20 +08:00
Ivan Grokhotkov
b03e08dc4e soc/rtc: add function to convert CPU frequency in MHz to rtc_cpu_freq_t 2017-10-18 14:19:15 +08:00
Ivan Grokhotkov
a242ae6d0b soc/rtc: add fast paths for switching between PLL and XTAL 2017-10-18 14:19:14 +08:00
Jeroen Domburg
740f8a79f0 Add logic to make external RAM usable with malloc() 2017-09-28 17:17:50 +08:00
michael
9d9e771933 fix(global, log): fix esp_log(_early)_timestamp readings after startup by correct the CCOUNT register when switching CPU clock.
TW#13332, Closes #700
2017-09-26 15:18:17 +08:00
Tian Hao
3e2ee24e4f component/bt : support bluetooth controller DRAM release dynamically
1. remove CONFIG_BT_DRAM_RELEASE from Kconfig
2. add API to release bluetooth controller DRAM to heap
2017-09-21 14:31:20 +08:00
michael
8244fa95fe feat(log): add new function to log buffer with level and hex dump. 2017-09-18 11:44:54 +08:00
Wangjialin
2fceec4d85 feature(I2S-ADC): add ADC mode for I2S.
1. Support built-in ADC for I2S.
2. Modify code of ADC, made no change to the original APIs.
3. Add APIs in I2S:
esp_err_t i2s_set_adc_mode(adc_unit_t adc_unit, adc1_channel_t adc_channel);
4. Add I2S ADC/DAC example code.
5. add old-fashion definition to make it more compatible
6. replase spi_flash_ APIs with esp_partition_ APIs
7. add example of generating audio table from wav
8. change example sound
2017-09-14 13:24:08 +08:00
Jeroen Domburg
875ae6a134 Add option to allocate external RAM using heap_alloc_caps 2017-09-14 10:47:44 +08:00
Ivan Grokhotkov
1e7c3854d3 Merge branch 'bugfix/warn_on_invalid_xtal_freq' into 'master'
soc/rtc: warn if detected XTAL frequency does not match configured one

See merge request !1242
2017-09-11 18:15:11 +08:00
Ivan Grokhotkov
de038f502c Merge branch 'feature/gpio_channel_macro' into 'master'
feat(global): add macros for GPIO->channel lookup

See merge request !1170
2017-09-11 12:15:08 +08:00
Ivan Grokhotkov
5a88f90a33 soc/rtc: warn if detected XTAL frequency does not match configured one
Since 9a8c0392, XTAL frequency is set to 40MHz by default, and users
of 26MHz boards need to select 26MHz manually. Most users are not aware
of this change, and existing getting started guides do not mention that
XTAL frequency needs to be set for some boards. So users are left with
garbage output from UART without any clue what to check.

This change adds a warning in case specific XTAL frequency was set, and
it does not match automatically detected one. This should help users
fix the issue.
2017-09-11 11:42:26 +08:00
Angus Gratton
1c7b8aa3a5 Heap tracing support 2017-09-07 16:32:05 +10:00
michael
08b9fbc242 feat(global): add macros for GPIO->channel lookup
including: macros for dac, adc, touch, rtc_gpio, uart and clk_out.

TW#13970
2017-09-07 10:40:25 +08:00
Jeroen Domburg
34372a091c Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet. 2017-09-04 12:05:49 +08:00
Ivan Grokhotkov
5666fc0a56 Merge branch 'feature/esp_timer_improvements' into 'master'
esp_timer improvements

See merge request !1172
2017-09-01 16:14:01 +08:00
Ivan Grokhotkov
d2acf1ce77 sleep: add light sleep, factor out APIs common for deep/light sleep 2017-09-01 10:36:14 +08:00
Ivan Grokhotkov
f8b719d911 soc/rtc: add sleep flag to control powerdown of VDD_SDIO 2017-09-01 10:36:14 +08:00
Ivan Grokhotkov
c743bdac88 soc/rtc: round APB clock frequency to nearest MHz 2017-09-01 10:34:36 +08:00
Ivan Grokhotkov
a25eb825e1 Merge branch 'bugfix/dport_protect_crypto' into 'master'
add protection for crypto registers in DPORT

See merge request !928
2017-08-30 11:45:35 +08:00
Ivan Grokhotkov
547ef83020 Merge branch 'feature/disable_some_perip_clk_when_cpu_start' into 'master'
Disable some peripheral clocks when cpu starts

See merge request !1089
2017-08-30 11:43:38 +08:00
XiaXiaotian
4776f73ca4 Disable some peripheral clocks when cpu starts
All peripheral clocks are default enabled after chip is powered on.
    When CPU starts, if reset reason is CPU reset, disable those clocks
    that are not enabled before reset. Otherwise, disable all those
    useless clocks.
    These peripheral clocks must be enabled when the peripherals are
    initialized and disabled when they are deinitialized.
2017-08-29 11:18:42 +08:00
michael
c7173e0d08 fix(struct_h): add extern "C" protection to *_struct.h header files. 2017-08-28 18:10:46 +08:00
Ivan Grokhotkov
82763a02af Merge branch 'feature/ets_timer' into 'master'
esp_timer: add high-resolution timer api

See merge request !1090
2017-08-28 16:38:11 +08:00
Ivan Grokhotkov
d8b66e5088 soc: release interrupts which are not reserved by timers any more 2017-08-28 11:35:27 +08:00
Ivan Grokhotkov
b636f81619 Merge branch 'bugfix/spi_command' into 'master'
fix(spi_master): fix the command field to make it more intuitive to use.

See merge request !1119
2017-08-28 10:29:56 +08:00
Angus Gratton
2624e10055 esp32 hwcrypto: Use AES registers directly 2017-08-25 16:08:03 +10:00
Angus Gratton
cb31222e8b dport access: Add _DPORT_REG_SET_BIT & _DPORT_REG_CLR_BIT 2017-08-25 16:08:02 +10:00
Ivan Grokhotkov
08287852ab esp32: add protection for DPORT registers of RSA 2017-08-25 16:08:02 +10:00
Ivan Grokhotkov
a66df0826e soc: fix/update definitions related to FRC timers
1. BIT(8) of CTRL is actually read-only bit indicating interrupt status

2. BIT(0) or CTRL had inverted meaning: 1 is “level”, 0 is “edge”

3. Add definitions of prescaler values
2017-08-24 16:33:12 +08:00
Wang Jia Lin
f1ecffb46c Merge branch 'bugfix/touch_pad_driver' into 'master'
driver(touch): fix bug and add more features

See merge request !1056
2017-08-23 19:12:39 +08:00
Wangjialin
842caaab21 driver(touch): fix bug and add more features
1. add sens_struct.h
2. add definition of RTCCNTL and RTCIO
3. modify touch pad examples
4. update example code.
5. add comments add option in menuconfig
6. fix issue that pad index 8 and 9 are mismatched
7. add touch_pad_read_filtered() api to get value filtered by iir filter
8. modify touch pad isr func
9. Make the items in perihperal.ld in the sequence of address
10. delete Kconfig for touch pad
11. add touchpad filter APIs to adjust the filter
12. add touch_pad into index.rst
13. add touch_pad in Doxyfile
14. add touch_pad.rst
2017-08-22 21:21:39 +08:00
michael
4c9754726f fix(spi_master): fix the command field to make it more intuitive to use. 2017-08-21 20:37:57 +08:00
michael
ed1d084aea fix(spi_master): make the address field more intuitive to use.
The address field should be placed at the highest bits of address and slv_wr_status registers. Instead of breaking the address into two parts and fill in each register, move the address to the highest bits and write to the registers respectively.

Breaking change: if you fill-in the SPI address filed in a previous version in some way and it works correctly, you still have to rewrite the address, in a more intuitive way.
2017-08-15 14:49:31 +08:00
michael
99769f0b00 fix(spi_master): fix the bug that VSPI no respond when host changed
from HSPI to VSPI, and vice versa.

fix the SPI control bits written wrong in the headers.

TW#12123, Github#477
2017-07-21 14:50:17 +08:00
Angus Gratton
17adb40ca8 bootloader: Calculate SHA256 hash of image on every boot
Makes app image booting more reliable (256-bit rather than 8-bit verification.)

Some measurements, time to boot a 655KB app.bin file and run to app_main() execution.

(All for rev 1 silicon, ie no 340ms spurious WDT delay.)

80MHz QIO mode:
before = 300ms
after = 140ms

40MHz DIO mode:
before = 712ms
after = 577ms

40MHz DIO mode, secure boot enabled
before = 1380ms
after = 934ms

(Secure boot involves two ECC signature verifications (partition table, app) that take approx 300ms each with 80MHz CPU.)
2017-07-19 18:31:59 +10:00
Ivan Grokhotkov
0ae916d555 Merge branch 'feature/high_level_interrupts' into 'master'
Break out high-level interrupts so a component can override them

See merge request !675
2017-07-18 10:42:31 +08:00
Ivan Grokhotkov
7fc25f18d2 Merge branch 'feature/enable_brownout_detector' into 'master'
Enable brownout detector

See merge request !811
2017-07-13 11:40:37 +08:00
Angus Gratton
ad60c30de0 heap: Rename memory "tags" to "types" to avoid confusion w/ old tag allocator API 2017-07-10 17:46:03 +08:00
Angus Gratton
8d7074ed5c soc: Move esp_ptr_dma_capable() function to soc_memory_layout.h 2017-07-10 17:46:03 +08:00
Angus Gratton
71c70cb15c heap: Refactor heap regions/capabilities out of FreeRTOS
Remove tagged heap API, rename caps_xxx to heap_caps_xxx

Also includes additional heap_caps_xxx inspection functions.
2017-07-10 17:46:03 +08:00
Angus Gratton
5ee49fd311 heap: Add new multi_heap heap implementation to replace FreeRTOS-based tagged heaps 2017-07-10 17:46:03 +08:00
Ivan Grokhotkov
01b185977c brownout detector: enable by default
Because of errata related to BOD reset function, brownout is handled as follows:

- attach an ISR to brownout interrupt
- when ISR happens, print a message and do a software restart
- esp_restart_nonos enables RTC watchdog, so if restart fails,
  there will be  one more attempt to restart (using the RTC
  watchdog)
2017-07-10 17:25:55 +08:00
Ivan Grokhotkov
780569c04a esp32: fix RTC watchdog configuration in esp_restart
RTC watchdog didn’t have any actions configured for any of the stages.
This change configures it to use SW_SYSTEM_RESET at stage 0 and a
full reset at stage 1. The timeout is now calculated based on
RTC_SLOW_CLK frequency.
2017-07-10 17:21:49 +08:00
Tian Hao
7a79d31db0 fix reg operation missing 2017-07-07 20:04:24 +08:00
Jeroen Domburg
d3290479b2 Merge panic and dport high level interrupt code to both use int level 4 2017-07-07 12:51:33 +08:00
Ivan Grokhotkov
6b2e16e51b soc: fix typo in register name 2017-07-06 12:36:06 +08:00
Jack
ab9f63aba7 fix bug that uart register base address macro was wrong 2017-06-23 19:56:12 +08:00
Tian Hao
09f7cf45dd component/bt : fix interrupt number conflict
1. the typical problem is when push keyboard on serial tool, the bluetooth may stop.
2017-06-15 19:41:54 +08:00
Ivan Grokhotkov
06accaf851 add C++ include guards to header files which are missing them
Fixes https://github.com/espressif/esp-idf/issues/628
2017-05-31 17:20:17 +08:00
Jiang Jiang Jian
9229902dff Merge branch 'bugfix/lib_dport_access' into 'master'
component/esp32 : fix library dport access protections.

1. add esp32 library access DPORT register protections.
2. add bluetooth library access DPORT register protections.
3. change register operation(suffix/prefix) to new style.

See merge request !757
2017-05-18 14:56:38 +08:00
Tian Hao
52515d0edf component/esp32 : update wifi library and phy library 2017-05-17 11:46:53 +08:00
Ivan Grokhotkov
98e15df7f6 examples: add ULP ADC example 2017-05-16 13:15:02 +08:00
Tian Hao
3d22f1ee2f component/esp32 : fix library sport access protections.
1. add esp32 library access DPORT register protections.
2. add bluetooth library access DPORT register protections.
3. change register operation(suffix/prefix) to new style.
2017-05-13 19:55:11 +08:00
Jiang Jiang Jian
a6608648db Merge branch 'driver_merge_tmp/mcpwm' into 'master'
feature: Motor Control PWM(mcpwm) driver and examples



See merge request !698
2017-05-12 18:21:38 +08:00
Jiang Jiang Jian
bb25ac91f4 Merge branch 'bugfix/dualcore' into 'master'
component/soc: fix register access protection missing

- fix dport register access protection missing
- add rom function protect
- add normal register function check

See merge request !747
2017-05-12 18:19:31 +08:00
Kewal M Shah
2008f4d88c feature: add Motor Control PWM(mcpwm) driver
1. Name change from chopper to carrier, block diagram update, minor changes to example codes
2. mcpwm_reg.h changed, brought uniformity in comments, worked on suggestions, duty to accept float. Some name changes!
3. Minor readme changes and Indetation
4. Minor change:  move mcpwm_reg.h and mcpwm_struct.h to new path
5. Minor change: addition of BLDC example code and Readme
6. Name changed from epwm to mcpwm
7. Improve the reg name in mcpwm_struct.h
8. Name change chopper>carrier, deadband>deadtime
2017-05-12 15:47:59 +08:00
Tian Hao
377a1f5ea1 component/esp32 : do more fix of dualcore bug
1. the cache API in romcode will access DPORT register, so protect it.
2. fix STALL spelling.
3. check dport access by non-dport access function
2017-05-12 15:41:51 +08:00
Ivan Grokhotkov
15a6145961 Merge branch 'feature/get_chip_ver' into 'master'
add API to get chip info

This change adds an API to get chip info, such as chip model, enabled capabilities, size of embedded flash, silicon revision.

Hello_world example is modified to print out the information about the chip. The example is also simplified by moving all code into the main task.

Ref TW12031.

See merge request !549
2017-05-11 12:05:55 +08:00
Tian Hao
26a3cb93c7 component/soc : move dport access header files to soc
1. move dport access header files to soc
2. reduce dport register write protection. Only protect read operation
2017-05-09 18:06:00 +08:00
Tian Hao
f7e8856520 component/esp32 : fix dualcore bug
1. When dual core cpu run access DPORT register, must do protection.
2. If access DPORT register, must use DPORT_REG_READ/DPORT_REG_WRITE and DPORT_XXX register operation macro.
2017-05-08 21:53:43 +08:00
Ivan Grokhotkov
2260c714e7 add esp_chip_info API 2017-05-05 17:28:30 +08:00
Tian Hao
5c0d0d4854 component/bt : change VHCI interrupt type to software interrupt(int no 7) 2017-04-28 17:20:06 +08:00
Jeroen Domburg
46fa2cfb46 Merge branch 'feature/spi_slave' into 'master'
Split common SPI stuff out of master driver; add slave driver; add workaround for DMA issue.

This merge req mainly adds a slave device. In order to do this, the original master driver is refactored into common code shared by master and slave modes, and a slave driver is added.

The other things added are:
- Added a workaround for a 'feature' of the ESP32 silicon that can lock up the receive DMA channel in some situations. This can only be fixed by resetting *both* DMA channels. The workaround implemented makes sure that the reset only happens when both channels are idle
- Got rid of the automatic choice between register- and DMA-based transfers. The master (and slave) code will now always go for a DMA transfer if a DMA channel is given, and always go for register-based transfers if no DMA channel is given.
- Add in a bunch of fixes for outstanding Github issues.

See merge request !659
2017-04-27 12:28:42 +08:00
Jeroen Domburg
e9c372bc2d SPI: Split common SPI stuff out of master driver; add slave driver; add workaround for DMA issue. 2017-04-27 11:49:04 +08:00
Ivan Grokhotkov
0fe765a977 Merge branch 'feature/32k_xtal' into 'master'
add support for 32k XTAL as RTC_SLOW_CLK source

- RTC_CNTL_SLOWCLK_FREQ define is removed; rtc_clk_slow_freq_get_hz
  function can be used instead to get an approximate RTC_SLOW_CLK
  frequency

- Clock calibration is performed at startup. The value is saved and used
  for timekeeping and when entering deep sleep.

- When using the 32k XTAL, startup code will wait for the oscillator to
  start up. This can be possibly optimized by starting a separate task
  to wait for oscillator startup, and performing clock switch in that
  task.

- Fix a bug that 32k XTAL would be disabled in rtc_clk_init.

- Fix a rounding error in rtc_clk_cal, which caused systematic frequency
  error.

- Fix an overflow bug which caused rtc_clk_cal to timeout early if the
  slow_clk_cycles argument would exceed certain value

- Improve 32k XTAL oscillator startup time by introducing bootstrapping
  code, which uses internal pullup/pulldown resistors on 32K_N/32K_P
  pins to set better initial conditions for the oscillator.

Ref TW11683.

Ref https://esp32.com/viewtopic.php?f=13&t=1570

Fixes https://github.com/espressif/esp-idf/issues/337.

See merge request !696
2017-04-26 14:01:59 +08:00
Ivan Grokhotkov
6353bc40d7 Add support for 32k XTAL as RTC_SLOW_CLK source
- RTC_CNTL_SLOWCLK_FREQ define is removed; rtc_clk_slow_freq_get_hz
  function can be used instead to get an approximate RTC_SLOW_CLK
  frequency

- Clock calibration is performed at startup. The value is saved and used
  for timekeeping and when entering deep sleep.

- When using the 32k XTAL, startup code will wait for the oscillator to
  start up. This can be possibly optimized by starting a separate task
  to wait for oscillator startup, and performing clock switch in that
  task.

- Fix a bug that 32k XTAL would be disabled in rtc_clk_init.

- Fix a rounding error in rtc_clk_cal, which caused systematic frequency
  error.

- Fix an overflow bug which caused rtc_clk_cal to timeout early if the
  slow_clk_cycles argument would exceed certain value

- Improve 32k XTAL oscillator startup time by introducing bootstrapping
  code, which uses internal pullup/pulldown resistors on 32K_N/32K_P
  pins to set better initial conditions for the oscillator.
2017-04-26 12:43:22 +08:00
Angus Gratton
e2479b46f7 secure boot: Fix bootloader image verification failure
* Failure prevented secure boot from enabling.
* Also adds unit test cases for esp_image_basic_verify()

Ref https://esp32.com/viewtopic.php?f=2&t=1602
TW11878
2017-04-26 11:23:35 +10:00
Ivan Grokhotkov
3323f31cfb soc: implement XTAL frequency detection
ROM code already implements XTAL frequency detection, but it uses the 8M
clock before the clock tuning parameters are initialized. With the
zero clock tuning parameter, 8M clock has significant frequency deviation
at high temperatures, which can lead to erroneous detection of 40 MHz
crystal as a 26 MHz one.

This change adds XTAL frequency detection code to rtc_clk_init routine,
and detection is performed after the 8M clock tuning parameter as been
initialized.
2017-04-24 15:29:30 +08:00
Alexey Gerenkov
77a92e6dcc esp32: Added dumping info from traceport upon reset by any WDT
- Last PC info and waiti mode indication are printed for both CPUs
 - Raw traceport regs values are printed only for log levels higher than DEBUG
2017-04-23 22:07:56 +03:00
Ivan Grokhotkov
404e89da4d Merge branch 'bugfix/rtc_reg_fields' into 'master'
soc: allow REG_SET_FIELD to be used for bit fields

- Fixes an issue with `rtc_clk_apll_enable`: https://esp32.com/viewtopic.php?f=13&t=1673
- Fixes `rtc_clk_fast_freq_set` function always selecting XTAL/4 as fast clock source.
- Fixes regression in deep sleep current (7uA instead of 5uA).

See merge request !674
2017-04-21 19:40:45 +08:00
Ivan Grokhotkov
6e9d60ef70 rtc_clk_init: handle case when XTAL frequency has already been set
On first reset, ROM code writes the estimated XTAL frequency into
RTC_APB_FREQ_REG (aka STORE5). If the application doesn’t specify exact
XTAL frequency (which is always the case for now), rtc_clk_init will
guess what kind of XTAL is used (26M or 40M), based on the estimated
frequency. Later, detected frequency is written into RTC_XTAL_FREQ_REG
(aka STORE4).

When the application switches clock source to PLL, APB frequency changes
and RTC_APB_FREQ_REG is updated. If the application encounters an RTC
WDT reset, RTC_APB_FREQ_REG will not be updated prior to reset. Once the
application starts up again, it will attempt to auto-detect XTAL
frequency based on RTC_APB_FREQ_REG, which now has value of 80000000.
This will fail, and rtc_clk_xtal_freq_estimate will fall back to the
default value of 26 MHz. Due to an incorrect XTAL frequency, PLL
initialization will also take incorrect path, and PLL will run at a
different frequency. Depending on the application this may cause just
garbage output on UART or a crash (if WiFi is used).
2017-04-21 10:33:58 +08:00
Ivan Grokhotkov
5d1bb42c18 soc: allow REG_SET_FIELD to be used with single-bit fields 2017-04-18 17:34:26 +08:00
Ivan Grokhotkov
faaf59ccb3 soc: define missing M, V macros for nrx, bb, fe, emac, iomux
Recipe:
- Add _M and _V for single-bit fields
  Search: (#define (\w+)\s*(\(BIT\(\d+\)\)))
  Replace: \1\n#define \2_M \3\n#define \2_V 1

- Add _M and _V for multi-bit fields
  Search: (#define (\w+)\s*(0x[\dA-Fa-f]+))
  Replace: \1\n#define \2_M (\2_V << \2_S)\n#define \2_V \3
2017-04-18 17:34:26 +08:00
Jeroen Domburg
0b79d07d34 add detection of invalid cache access
- fix level 4 interrupt vectors to produce correct backtrace
- initialize invalid cache access interrupt on startup
- handle invalid cache access in panic handler
2017-04-13 15:27:38 +08:00
Ivan Grokhotkov
3c6c1e36ec soc: add invalid cache access interrupt bits to dport_reg 2017-04-13 15:27:38 +08:00
Ivan Grokhotkov
7ee8ee8b7e soc: add source code of rtc_clk, rtc_pm 2017-04-11 15:45:54 +08:00
Ivan Grokhotkov
9ff446e6f9 soc: convert line endings to unix 2017-04-11 15:44:22 +08:00
Ivan Grokhotkov
d6dbf15a1f soc: move header files into soc component 2017-04-11 14:06:40 +08:00