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soc,sdmmc: fix build failures when NDEBUG is used 

Use explicit error checking instead of asserts, use SOC_LOG to print
error/warning messages where needed.
This commit is contained in:
Ivan Grokhotkov 2018-09-25 10:58:43 +08:00
parent 1ee2bc46ed
commit ab68b9d90d
4 changed files with 29 additions and 15 deletions
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2
components/sdmmc/sdmmc_common.c
View File

@ -113,7 +113,7 @@ esp_err_t sdmmc_init_cid(sdmmc_card_t* card)
esp_err_t sdmmc_init_csd(sdmmc_card_t* card)
{
assert(card->is_mem);
assert(card->is_mem == 1);
/* Get and decode the contents of CSD register. Determine card capacity. */
esp_err_t err = sdmmc_send_cmd_send_csd(card, &card->csd);
if (err != ESP_OK) {

16
components/soc/esp32/rtc_clk.c
View File

@ -15,7 +15,6 @@
#include <stdbool.h>
#include <stdint.h>
#include <stddef.h>
#include <assert.h>
#include <stdlib.h>
#include "rom/ets_sys.h"
#include "rom/rtc.h"
@ -102,6 +101,8 @@ static bool rtc_clk_cpu_freq_from_mhz_internal(int mhz, rtc_cpu_freq_t* out_val)
// Current PLL frequency, in MHZ (320 or 480). Zero if PLL is not enabled.
static int s_cur_pll_freq;
static const char* TAG = "rtc_clk";
static void rtc_clk_32k_enable_common(int dac, int dres, int dbias)
{
SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
@ -447,7 +448,8 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
dbias = DIG_DBIAS_240M;
per_conf = 2;
} else {
assert(false && "invalid frequency");
SOC_LOGE(TAG, "invalid frequency");
abort();
}
DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, per_conf);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias);
@ -504,7 +506,7 @@ uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq)
case RTC_CPU_FREQ_240M:
return 240 * MHZ;
default:
assert(false && "invalid rtc_cpu_freq_t value");
SOC_LOGE(TAG, "invalid rtc_cpu_freq_t value");
return 0;
}
}
@ -571,7 +573,7 @@ void rtc_clk_cpu_freq_to_config(rtc_cpu_freq_t cpu_freq, rtc_cpu_freq_config_t*
freq_mhz = 240;
break;
default:
assert(false && "invalid rtc_cpu_freq_t value");
SOC_LOGE(TAG, "invalid rtc_cpu_freq_t value");
abort();
}
@ -685,7 +687,8 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t* out_config)
div = 2;
freq_mhz = 240;
} else {
assert(false && "unsupported frequency configuration");
SOC_LOGE(TAG, "unsupported frequency configuration");
abort();
}
break;
}
@ -697,7 +700,8 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t* out_config)
break;
case RTC_CNTL_SOC_CLK_SEL_APLL:
default:
assert(false && "unsupported frequency configuration");
SOC_LOGE(TAG, "unsupported frequency configuration");
abort();
}
*out_config = (rtc_cpu_freq_config_t) {
.source = source,

6
components/soc/esp32/rtc_clk_init.c
View File

@ -15,7 +15,6 @@
#include <stdbool.h>
#include <stdint.h>
#include <stddef.h>
#include <assert.h>
#include <stdlib.h>
#include "rom/ets_sys.h"
#include "rom/rtc.h"
@ -118,7 +117,10 @@ void rtc_clk_init(rtc_clk_config_t cfg)
uint32_t freq_before = old_config.freq_mhz;
bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config);
assert(res && "invalid CPU frequency value");
if (!res) {
SOC_LOGE(TAG, "invalid CPU frequency value");
abort();
}
rtc_clk_cpu_freq_set_config(&new_config);
/* Configure REF_TICK */

20
components/soc/esp32/rtc_time.c
View File

@ -17,10 +17,12 @@
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/timer_group_reg.h"
#include "assert.h"
#include "soc_log.h"
#define MHZ (1000000)
static const char* TAG = "rtc_time";
/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of
* RTC_SLOW_CLK cycles.
@ -58,21 +60,27 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
/* Figure out how long to wait for calibration to finish */
uint32_t expected_freq;
rtc_slow_freq_t slow_freq = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
uint32_t us_timer_max = 0xFFFFFFFF;
if (cal_clk == RTC_CAL_32K_XTAL ||
(cal_clk == RTC_CAL_RTC_MUX && slow_freq == RTC_SLOW_FREQ_32K_XTAL)) {
expected_freq = 32768; /* standard 32k XTAL */
us_timer_max = (uint32_t) (TIMG_RTC_CALI_VALUE / rtc_clk_xtal_freq_get());
} else if (cal_clk == RTC_CAL_8MD256 ||
(cal_clk == RTC_CAL_RTC_MUX && slow_freq == RTC_SLOW_FREQ_8MD256)) {
expected_freq = RTC_FAST_CLK_FREQ_APPROX / 256;
} else {
expected_freq = 150000; /* 150k internal oscillator */
us_timer_max = (uint32_t) (TIMG_RTC_CALI_VALUE / rtc_clk_xtal_freq_get());
}
uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq);
// The required amount of slowclk_cycles can produce in a counter TIMG a overflow error. Decrease the slowclk_cycles for fix it.
assert(us_time_estimate < us_timer_max);
/* Check if the required number of slowclk_cycles may result in an overflow of TIMG_RTC_CALI_VALUE */
rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
/* XTAL frequency is not known yet; assume worst case (40 MHz) */
xtal_freq = RTC_XTAL_FREQ_40M;
}
const uint32_t us_timer_max = TIMG_RTC_CALI_VALUE / (uint32_t) xtal_freq;
if (us_time_estimate >= us_timer_max) {
SOC_LOGE(TAG, "slowclk_cycles value too large, possible overflow");
return 0;
}
/* Start calibration */
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);