Merge panic and dport high level interrupt code to both use int level 4
This commit is contained in:
Jeroen Domburg
parent
1d748db209
commit
d3290479b2
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@ -35,7 +35,6 @@ COMPONENT_ADD_LDFLAGS := -lesp32 \
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-L $(COMPONENT_PATH)/ld \
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-T esp32_out.ld \
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-u ld_include_panic_highint_hdl \
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-u ld_include_dport_highint_hdl \
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$(addprefix -T ,$(LINKER_SCRIPTS))
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ALL_LIB_FILES := $(patsubst %,$(COMPONENT_PATH)/lib/lib%.a,$(LIBS))
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@ -1,93 +0,0 @@
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#include <xtensa/coreasm.h>
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#include <xtensa/corebits.h>
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#include <xtensa/config/system.h>
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#include <xtensa/simcall.h>
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#include "freertos/xtensa_context.h"
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#include "esp_panic.h"
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#include "soc/dport_reg.h"
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#define L5_INTR_STACK_SIZE 8
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#define L5_INTR_A2_OFFSET 0
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#define L5_INTR_A3_OFFSET 4
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.data
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_l5_intr_stack:
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.space L5_INTR_STACK_SIZE
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.section .iram1,"ax"
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.global xt_highint5
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.type xt_highint5,@function
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.align 4
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xt_highint5:
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/* This section is for access dport register protection */
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/* Allocate exception frame and save minimal context. */
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/* Because the interrupt cause code have protection that only
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allow one cpu enter in L5 interrupt at one time, so
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there needn't have two _l5_intr_stack for each cpu */
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movi a0, _l5_intr_stack
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s32i a2, a0, L5_INTR_A2_OFFSET
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s32i a3, a0, L5_INTR_A3_OFFSET
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/* Check interrupt */
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rsr a0, INTERRUPT
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extui a0, a0, ETS_DPORT_INUM, 1 /* get dport int bit */
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beqz a0, 1f
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/* handle dport interrupt */
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/* get CORE_ID */
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getcoreid a0
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beqz a0, 2f
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/* current cpu is 1 */
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movi a0, DPORT_CPU_INTR_FROM_CPU_3_REG
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movi a2, 0
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s32i a2, a0, 0 /* clear intr */
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movi a0, 0 /* other cpu id */
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j 3f
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2:
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/* current cpu is 0 */
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movi a0, DPORT_CPU_INTR_FROM_CPU_2_REG
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movi a2, 0
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s32i a2, a0, 0 /* clear intr */
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movi a0, 1 /* other cpu id */
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3:
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/* set and wait flag */
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movi a2, dport_access_start
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addx4 a2, a0, a2
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movi a3, 1
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s32i a3, a2, 0
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memw
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movi a2, dport_access_end
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addx4 a2, a0, a2
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.check_dport_access_end:
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l32i a3, a2, 0
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beqz a3, .check_dport_access_end
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1:
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movi a0, _l5_intr_stack
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l32i a2, a0, L5_INTR_A2_OFFSET
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l32i a3, a0, L5_INTR_A3_OFFSET
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rsync /* ensure register restored */
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rsr a0, EXCSAVE_5 /* restore a0 */
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rfi 5
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.align 4
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.L_xt_highint5_exit:
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rsr a0, EXCSAVE_5 /* restore a0 */
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rfi 5
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/* The linker has no reason to link in this file; all symbols it exports are already defined
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(weakly!) in the default int handler. Define a symbol here so we can use it to have the
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linker inspect this anyway. */
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.global ld_include_dport_highint_hdl
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ld_include_dport_highint_hdl:
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@ -21,25 +21,34 @@
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#include "esp_panic.h"
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#include "soc/dport_reg.h"
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/*
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In some situations, the panic handler needs to be invoked even when (low/medium priority) interrupts
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are disabled. In that case, we use a high interrupt to panic anyway. This is the high-level interrupt
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handler for such a situation. We use interrupt level 4 for this.
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Interrupt , a high-priority interrupt, is used for several things:
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- Dport access mediation
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- Cache error panic handler
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- Interrupt watchdog panic handler
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*/
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#define L4_INTR_STACK_SIZE 8
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#define L4_INTR_A2_OFFSET 0
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#define L4_INTR_A3_OFFSET 4
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.data
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_l4_intr_stack:
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.space L4_INTR_STACK_SIZE
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.section .iram1,"ax"
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.global xt_highint4
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.type xt_highint4,@function
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.align 4
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xt_highint4:
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/* On the ESP32, this level is used for panic events that are detected by hardware and should
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also panic when interrupts are disabled. At the moment, these are the interrupt watchdog
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as well as the cache invalid access interrupt. (24 and 25) */
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/* See if we're here for the dport access interrupt */
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rsr a0, INTERRUPT
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extui a0, a0, ETS_DPORT_INUM, 1
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bnez a0, .handle_dport_access_int
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/* Allocate exception frame and save minimal context. */
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mov a0, sp
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@ -119,6 +128,66 @@ xt_highint4:
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.align 4
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.handle_dport_access_int:
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/* This section is for dport access register protection */
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/* Allocate exception frame and save minimal context. */
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/* Because the interrupt cause code has protection that only
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allows one cpu to enter in the dport section of the L4
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interrupt at one time, there's no need to have two
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_l4_intr_stack for each cpu */
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/* This int is edge-triggered and needs clearing. */
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movi a0, (1<<ETS_DPORT_INUM)
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wsr a0, INTCLEAR
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/* Save A2, A3 so we can use those registers */
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movi a0, _l4_intr_stack
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s32i a2, a0, L4_INTR_A2_OFFSET
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s32i a3, a0, L4_INTR_A3_OFFSET
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/* handle dport interrupt */
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/* get CORE_ID */
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getcoreid a0
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beqz a0, 2f
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/* current cpu is 1 */
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movi a0, DPORT_CPU_INTR_FROM_CPU_3_REG
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movi a2, 0
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s32i a2, a0, 0 /* clear intr */
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movi a0, 0 /* other cpu id */
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j 3f
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2:
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/* current cpu is 0 */
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movi a0, DPORT_CPU_INTR_FROM_CPU_2_REG
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movi a2, 0
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s32i a2, a0, 0 /* clear intr */
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movi a0, 1 /* other cpu id */
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3:
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/* set and wait flag */
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movi a2, dport_access_start
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addx4 a2, a0, a2
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movi a3, 1
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s32i a3, a2, 0
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memw
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movi a2, dport_access_end
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addx4 a2, a0, a2
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.check_dport_access_end:
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l32i a3, a2, 0
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beqz a3, .check_dport_access_end
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/* Done. Restore registers and return. */
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movi a0, _l4_intr_stack
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l32i a2, a0, L4_INTR_A2_OFFSET
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l32i a3, a0, L4_INTR_A3_OFFSET
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rsync /* ensure register restored */
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rsr a0, EXCSAVE_4 /* restore a0 */
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rfi 4
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/* The linker has no reason to link in this file; all symbols it exports are already defined
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(weakly!) in the default int handler. Define a symbol here so we can use it to have the
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linker inspect this anyway. */
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@ -126,3 +195,6 @@ xt_highint4:
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.global ld_include_panic_highint_hdl
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ld_include_panic_highint_hdl:
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@ -370,12 +370,12 @@
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* 23 3 extern level
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* 24 4 extern level TG1_WDT
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* 25 4 extern level CACHEERR
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* 26 5 extern level Reserved Reserved
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* 26 5 extern level
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* 27 3 extern level Reserved Reserved
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* 28 4 extern edge
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* 28 4 extern edge DPORT ACCESS DPORT ACCESS
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* 29 3 software Reserved Reserved
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* 30 4 extern edge Reserved Reserved
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* 31 5 extern level DPORT ACCESS DPORT ACCESS
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* 31 5 extern level
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*************************************************************************************************************
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*/
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@ -387,7 +387,7 @@
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#define ETS_FRC1_INUM 22
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#define ETS_T1_WDT_INUM 24
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#define ETS_CACHEERR_INUM 25
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#define ETS_DPORT_INUM 31
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#define ETS_DPORT_INUM 28
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//CPU0 Interrupt number used in ROM, should be cancelled in SDK
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#define ETS_SLC_INUM 1
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