Taavi Hein f7749e18a8 gpio: Bitmask overflow fix in gpio_reset_pin ... For pins 32 and up the BIT(nr) macro used here overflowed, causing undetermined GPIO pins to be reset. Example: freeing SPI device/bus where CS is on pin 33 caused debug UART to cease communication, TXD0 was disabled. Fixed as BIT64(nr) macro, to be used elsewhere as needed. For example in definitions like GPIO_SEL_32..GPIO_SEL_39.		2018-08-08 15:31:17 +03:00
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esp32	gpio: Bitmask overflow fix in gpio_reset_pin	2018-08-08 15:31:17 +03:00
include/soc	Replace all DOS line endings with Unix	2018-07-12 19:10:37 +08:00
test	soc: add source code of rtc_clk, rtc_pm	2017-04-11 15:45:54 +08:00
component.mk	Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet.	2017-09-04 12:05:49 +08:00