Angus Gratton 4297c337f9 esp32: Add IO_MUX_GPIOxx register names to match iomux names used in TRM ... The TRM describes IOMUX registers are IO_MUX_x_REG for x in GPIO0-39. Until now ESP-IDF describes them as PERIPHS_IO_MUX_(pinname)_U This commit adds additional IOMUX register names which match the ones used in the TRM.		2018-01-30 17:09:37 +08:00
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esp32	esp32: Add IO_MUX_GPIOxx register names to match iomux names used in TRM	2018-01-30 17:09:37 +08:00
include/soc	Add logic to make external RAM usable with malloc()	2017-09-28 17:17:50 +08:00
test	soc: add source code of rtc_clk, rtc_pm	2017-04-11 15:45:54 +08:00
component.mk	Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet.	2017-09-04 12:05:49 +08:00