Jiang Jiang Jian abacf8d2a0 Merge branch 'bugfix/rtc_and_restart_fixes' into 'master' ... rtc_clk and esp_restart fixes See merge request !1458		2017-11-04 01:34:38 +08:00
..
esp32	Merge branch 'bugfix/rtc_and_restart_fixes' into 'master'	2017-11-04 01:34:38 +08:00
include/soc	Add logic to make external RAM usable with malloc()	2017-09-28 17:17:50 +08:00
test	soc: add source code of rtc_clk, rtc_pm	2017-04-11 15:45:54 +08:00
component.mk	Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet.	2017-09-04 12:05:49 +08:00