global: move the soc component out of the common list
This MR removes the common dependency from every IDF components to the SOC component.
Currently, in the ``idf_functions.cmake`` script, we include the header path of SOC component by default for all components.
But for better code organization (or maybe also benifits to the compiling speed), we may remove the dependency to SOC components for most components except the driver and kernel related components.
In CMAKE, we have two kinds of header visibilities (set by include path visibility):
(Assume component A --(depends on)--> B, B is the current component)
1. public (``COMPONENT_ADD_INCLUDEDIRS``): means this path is visible to other depending components (A) (visible to A and B)
2. private (``COMPONENT_PRIV_INCLUDEDIRS``): means this path is only visible to source files inside the component (visible to B only)
and we have two kinds of depending ways:
(Assume component A --(depends on)--> B --(depends on)--> C, B is the current component)
1. public (```COMPONENT_REQUIRES```): means B can access to public include path of C. All other components rely on you (A) will also be available for the public headers. (visible to A, B)
2. private (``COMPONENT_PRIV_REQUIRES``): means B can access to public include path of C, but don't propagate this relation to other components (A). (visible to B)
1. remove the common requirement in ``idf_functions.cmake``, this makes the SOC components invisible to all other components by default.
2. if a component (for example, DRIVER) really needs the dependency to SOC, add a private dependency to SOC for it.
3. some other components that don't really depends on the SOC may still meet some errors saying "can't find header soc/...", this is because it's depended component (DRIVER) incorrectly include the header of SOC in its public headers. Moving all this kind of #include into source files, or private headers
4. Fix the include requirements for some file which miss sufficient #include directives. (Previously they include some headers by the long long long header include link)
This is a breaking change. Previous code may depends on the long include chain.
You may need to include the following headers for some files after this commit:
- soc/soc.h
- soc/soc_memory_layout.h
- driver/gpio.h
- esp_sleep.h
The major broken include chain includes:
1. esp_system.h no longer includes esp_sleep.h. The latter includes driver/gpio.h and driver/touch_pad.h.
2. ets_sys.h no longer includes soc/soc.h
3. freertos/portmacro.h no longer includes soc/soc_memory_layout.h
some peripheral headers no longer includes their hw related headers, e.g. rom/gpio.h no longer includes soc/gpio_pins.h and soc/gpio_reg.h
BREAKING CHANGE
2019-04-03 05:17:38 +00:00
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// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
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2016-08-17 15:08:22 +00:00
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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2017-04-18 04:09:19 +00:00
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//
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2016-08-17 15:08:22 +00:00
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _ESP32_SOC_H_
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#define _ESP32_SOC_H_
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2017-03-18 09:27:19 +00:00
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#ifndef __ASSEMBLER__
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2016-08-17 15:08:22 +00:00
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#include <stdint.h>
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2017-05-10 07:45:04 +00:00
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#include "esp_assert.h"
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2017-03-18 09:27:19 +00:00
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#endif
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2016-08-17 15:08:22 +00:00
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global: move the soc component out of the common list
This MR removes the common dependency from every IDF components to the SOC component.
Currently, in the ``idf_functions.cmake`` script, we include the header path of SOC component by default for all components.
But for better code organization (or maybe also benifits to the compiling speed), we may remove the dependency to SOC components for most components except the driver and kernel related components.
In CMAKE, we have two kinds of header visibilities (set by include path visibility):
(Assume component A --(depends on)--> B, B is the current component)
1. public (``COMPONENT_ADD_INCLUDEDIRS``): means this path is visible to other depending components (A) (visible to A and B)
2. private (``COMPONENT_PRIV_INCLUDEDIRS``): means this path is only visible to source files inside the component (visible to B only)
and we have two kinds of depending ways:
(Assume component A --(depends on)--> B --(depends on)--> C, B is the current component)
1. public (```COMPONENT_REQUIRES```): means B can access to public include path of C. All other components rely on you (A) will also be available for the public headers. (visible to A, B)
2. private (``COMPONENT_PRIV_REQUIRES``): means B can access to public include path of C, but don't propagate this relation to other components (A). (visible to B)
1. remove the common requirement in ``idf_functions.cmake``, this makes the SOC components invisible to all other components by default.
2. if a component (for example, DRIVER) really needs the dependency to SOC, add a private dependency to SOC for it.
3. some other components that don't really depends on the SOC may still meet some errors saying "can't find header soc/...", this is because it's depended component (DRIVER) incorrectly include the header of SOC in its public headers. Moving all this kind of #include into source files, or private headers
4. Fix the include requirements for some file which miss sufficient #include directives. (Previously they include some headers by the long long long header include link)
This is a breaking change. Previous code may depends on the long include chain.
You may need to include the following headers for some files after this commit:
- soc/soc.h
- soc/soc_memory_layout.h
- driver/gpio.h
- esp_sleep.h
The major broken include chain includes:
1. esp_system.h no longer includes esp_sleep.h. The latter includes driver/gpio.h and driver/touch_pad.h.
2. ets_sys.h no longer includes soc/soc.h
3. freertos/portmacro.h no longer includes soc/soc_memory_layout.h
some peripheral headers no longer includes their hw related headers, e.g. rom/gpio.h no longer includes soc/gpio_pins.h and soc/gpio_reg.h
BREAKING CHANGE
2019-04-03 05:17:38 +00:00
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#include <esp_bit_defs.h>
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2016-08-17 15:08:22 +00:00
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2016-09-13 15:02:03 +00:00
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#define PRO_CPU_NUM (0)
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#define APP_CPU_NUM (1)
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2017-05-10 07:45:04 +00:00
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/* Overall memory map */
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2018-10-19 04:00:16 +00:00
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#define SOC_IROM_LOW 0x400D0000
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#define SOC_IROM_HIGH 0x40400000
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#define SOC_DROM_LOW 0x3F400000
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#define SOC_DROM_HIGH 0x3F800000
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2019-04-25 09:29:48 +00:00
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#define SOC_DRAM_LOW 0x3FFAE000
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2018-10-19 04:00:16 +00:00
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#define SOC_DRAM_HIGH 0x40000000
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#define SOC_RTC_IRAM_LOW 0x400C0000
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#define SOC_RTC_IRAM_HIGH 0x400C2000
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#define SOC_RTC_DATA_LOW 0x50000000
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#define SOC_RTC_DATA_HIGH 0x50002000
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#define SOC_EXTRAM_DATA_LOW 0x3F800000
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#define SOC_EXTRAM_DATA_HIGH 0x3FC00000
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2017-07-20 08:26:35 +00:00
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2019-03-10 23:49:51 +00:00
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#define SOC_MAX_CONTIGUOUS_RAM_SIZE 0x400000 ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
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2017-05-10 07:45:04 +00:00
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#define DR_REG_DPORT_BASE 0x3ff00000
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2017-08-15 22:58:33 +00:00
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#define DR_REG_AES_BASE 0x3ff01000
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2017-05-10 07:45:04 +00:00
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#define DR_REG_RSA_BASE 0x3ff02000
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#define DR_REG_SHA_BASE 0x3ff03000
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2018-01-03 11:47:42 +00:00
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#define DR_REG_FLASH_MMU_TABLE_PRO 0x3ff10000
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#define DR_REG_FLASH_MMU_TABLE_APP 0x3ff12000
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#define DR_REG_DPORT_END 0x3ff13FFC
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2017-05-10 07:45:04 +00:00
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#define DR_REG_UART_BASE 0x3ff40000
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#define DR_REG_SPI1_BASE 0x3ff42000
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#define DR_REG_SPI0_BASE 0x3ff43000
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#define DR_REG_GPIO_BASE 0x3ff44000
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#define DR_REG_GPIO_SD_BASE 0x3ff44f00
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#define DR_REG_FE2_BASE 0x3ff45000
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#define DR_REG_FE_BASE 0x3ff46000
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#define DR_REG_FRC_TIMER_BASE 0x3ff47000
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#define DR_REG_RTCCNTL_BASE 0x3ff48000
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#define DR_REG_RTCIO_BASE 0x3ff48400
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#define DR_REG_SENS_BASE 0x3ff48800
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2018-01-08 13:27:28 +00:00
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#define DR_REG_RTC_I2C_BASE 0x3ff48C00
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2017-05-10 07:45:04 +00:00
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#define DR_REG_IO_MUX_BASE 0x3ff49000
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#define DR_REG_HINF_BASE 0x3ff4B000
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#define DR_REG_UHCI1_BASE 0x3ff4C000
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#define DR_REG_I2S_BASE 0x3ff4F000
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#define DR_REG_UART1_BASE 0x3ff50000
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#define DR_REG_BT_BASE 0x3ff51000
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#define DR_REG_I2C_EXT_BASE 0x3ff53000
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#define DR_REG_UHCI0_BASE 0x3ff54000
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#define DR_REG_SLCHOST_BASE 0x3ff55000
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#define DR_REG_RMT_BASE 0x3ff56000
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#define DR_REG_PCNT_BASE 0x3ff57000
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#define DR_REG_SLC_BASE 0x3ff58000
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#define DR_REG_LEDC_BASE 0x3ff59000
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#define DR_REG_EFUSE_BASE 0x3ff5A000
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#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000
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#define DR_REG_NRX_BASE 0x3ff5CC00
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#define DR_REG_BB_BASE 0x3ff5D000
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#define DR_REG_PWM_BASE 0x3ff5E000
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#define DR_REG_TIMERGROUP0_BASE 0x3ff5F000
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#define DR_REG_TIMERGROUP1_BASE 0x3ff60000
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2018-01-08 13:27:28 +00:00
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#define DR_REG_RTCMEM0_BASE 0x3ff61000
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#define DR_REG_RTCMEM1_BASE 0x3ff62000
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#define DR_REG_RTCMEM2_BASE 0x3ff63000
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2017-05-10 07:45:04 +00:00
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#define DR_REG_SPI2_BASE 0x3ff64000
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#define DR_REG_SPI3_BASE 0x3ff65000
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2018-01-08 13:27:28 +00:00
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#define DR_REG_SYSCON_BASE 0x3ff66000
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#define DR_REG_APB_CTRL_BASE 0x3ff66000 /* Old name for SYSCON, to be removed */
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2017-05-10 07:45:04 +00:00
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#define DR_REG_I2C1_EXT_BASE 0x3ff67000
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#define DR_REG_SDMMC_BASE 0x3ff68000
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#define DR_REG_EMAC_BASE 0x3ff69000
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2017-12-18 12:32:29 +00:00
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#define DR_REG_CAN_BASE 0x3ff6B000
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2017-05-10 07:45:04 +00:00
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#define DR_REG_PWM1_BASE 0x3ff6C000
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#define DR_REG_I2S1_BASE 0x3ff6D000
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#define DR_REG_UART2_BASE 0x3ff6E000
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#define DR_REG_PWM2_BASE 0x3ff6F000
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#define DR_REG_PWM3_BASE 0x3ff70000
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2017-07-20 08:26:35 +00:00
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#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE
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2017-05-10 07:45:04 +00:00
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2016-08-17 15:08:22 +00:00
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//Registers Operation {{
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#define ETS_UNCACHED_ADDR(addr) (addr)
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2018-10-19 04:00:16 +00:00
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#define ETS_CACHED_ADDR(addr) (addr)
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2016-08-17 15:08:22 +00:00
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2017-03-09 12:50:39 +00:00
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#ifndef __ASSEMBLER__
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2017-05-10 07:45:04 +00:00
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#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END)
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#if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_FREERTOS_UNICORE ) && defined( ESP_PLATFORM )
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#define ASSERT_IF_DPORT_REG(_r, OP) TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP));
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#else
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#define ASSERT_IF_DPORT_REG(_r, OP)
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#endif
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2016-09-06 12:21:47 +00:00
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//write value to register
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2017-05-10 07:45:04 +00:00
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#define REG_WRITE(_r, _v) ({ \
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2017-07-07 11:10:02 +00:00
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ASSERT_IF_DPORT_REG((_r), REG_WRITE); \
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2017-05-10 07:45:04 +00:00
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(*(volatile uint32_t *)(_r)) = (_v); \
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})
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2016-09-06 12:21:47 +00:00
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//read value from register
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2017-05-10 07:45:04 +00:00
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#define REG_READ(_r) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_READ); \
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2017-07-07 11:10:02 +00:00
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(*(volatile uint32_t *)(_r)); \
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2017-05-10 07:45:04 +00:00
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})
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2016-08-17 15:08:22 +00:00
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2016-09-06 12:21:47 +00:00
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//get bit or get bits from register
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2017-05-10 07:45:04 +00:00
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#define REG_GET_BIT(_r, _b) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_GET_BIT); \
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(*(volatile uint32_t*)(_r) & (_b)); \
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})
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2016-09-06 12:21:47 +00:00
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//set bit or set bits to register
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2017-05-10 07:45:04 +00:00
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#define REG_SET_BIT(_r, _b) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_SET_BIT); \
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(*(volatile uint32_t*)(_r) |= (_b)); \
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})
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2016-09-06 12:21:47 +00:00
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//clear bit or clear bits of register
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2017-05-10 07:45:04 +00:00
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#define REG_CLR_BIT(_r, _b) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_CLR_BIT); \
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(*(volatile uint32_t*)(_r) &= ~(_b)); \
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})
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2016-09-06 12:21:47 +00:00
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//set bits of register controlled by mask
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2017-05-10 07:45:04 +00:00
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#define REG_SET_BITS(_r, _b, _m) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_SET_BITS); \
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(*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))); \
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})
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2016-08-31 13:53:23 +00:00
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2016-11-11 06:00:34 +00:00
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//get field from register, uses field _S & _V to determine mask
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2017-05-10 07:45:04 +00:00
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#define REG_GET_FIELD(_r, _f) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_GET_FIELD); \
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((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \
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})
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2016-09-06 12:21:47 +00:00
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2017-04-18 04:09:19 +00:00
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//set field of a register from variable, uses field _S & _V to determine mask
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2017-05-10 07:45:04 +00:00
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#define REG_SET_FIELD(_r, _f, _v) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_SET_FIELD); \
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(REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))); \
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})
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2016-09-06 12:21:47 +00:00
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//get field value from a variable, used when _f is not left shifted by _f##_S
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2016-08-17 15:08:22 +00:00
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#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
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2016-09-06 12:21:47 +00:00
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//get field value from a variable, used when _f is left shifted by _f##_S
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2016-08-17 15:08:22 +00:00
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#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
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2016-09-06 12:21:47 +00:00
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//set field value to a variable, used when _f is not left shifted by _f##_S
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2016-08-17 15:08:22 +00:00
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#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
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2016-09-06 12:21:47 +00:00
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//set field value to a variable, used when _f is left shifted by _f##_S
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2016-08-17 15:08:22 +00:00
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#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
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2016-09-06 12:21:47 +00:00
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//generate a value from a field value, used when _f is not left shifted by _f##_S
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2016-08-17 15:08:22 +00:00
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#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
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2016-09-06 12:21:47 +00:00
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//generate a value from a field value, used when _f is left shifted by _f##_S
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#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
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2016-08-17 15:08:22 +00:00
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2016-09-06 12:21:47 +00:00
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//read value from register
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2017-05-10 07:45:04 +00:00
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#define READ_PERI_REG(addr) ({ \
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ASSERT_IF_DPORT_REG((addr), READ_PERI_REG); \
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(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \
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})
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2016-09-06 12:21:47 +00:00
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//write value to register
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2017-05-10 07:45:04 +00:00
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#define WRITE_PERI_REG(addr, val) ({ \
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|
ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG); \
|
|
|
|
|
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \
|
|
|
|
|
})
|
2016-09-06 12:21:47 +00:00
|
|
|
|
|
|
|
|
//clear bits of register controlled by mask
|
2017-05-10 07:45:04 +00:00
|
|
|
#define CLEAR_PERI_REG_MASK(reg, mask) ({ \
|
|
|
|
|
ASSERT_IF_DPORT_REG((reg), CLEAR_PERI_REG_MASK); \
|
|
|
|
|
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \
|
|
|
|
|
})
|
2016-09-06 12:21:47 +00:00
|
|
|
|
|
|
|
|
//set bits of register controlled by mask
|
2017-05-10 07:45:04 +00:00
|
|
|
#define SET_PERI_REG_MASK(reg, mask) ({ \
|
|
|
|
|
ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_MASK); \
|
|
|
|
|
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \
|
|
|
|
|
})
|
2016-09-06 12:21:47 +00:00
|
|
|
|
|
|
|
|
//get bits of register controlled by mask
|
2017-05-10 07:45:04 +00:00
|
|
|
#define GET_PERI_REG_MASK(reg, mask) ({ \
|
|
|
|
|
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK); \
|
|
|
|
|
(READ_PERI_REG(reg) & (mask)); \
|
|
|
|
|
})
|
2016-09-06 12:21:47 +00:00
|
|
|
|
|
|
|
|
//get bits of register controlled by highest bit and lowest bit
|
2017-05-10 07:45:04 +00:00
|
|
|
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \
|
|
|
|
|
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS); \
|
|
|
|
|
((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \
|
|
|
|
|
})
|
2016-09-06 12:21:47 +00:00
|
|
|
|
|
|
|
|
//set bits of register controlled by mask and shift
|
2017-05-10 07:45:04 +00:00
|
|
|
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({ \
|
|
|
|
|
ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_BITS); \
|
|
|
|
|
(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )); \
|
|
|
|
|
})
|
2016-09-06 12:21:47 +00:00
|
|
|
|
|
|
|
|
//get field of register
|
2017-05-10 07:45:04 +00:00
|
|
|
#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \
|
|
|
|
|
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS2); \
|
|
|
|
|
((READ_PERI_REG(reg)>>(shift))&(mask)); \
|
|
|
|
|
})
|
2016-08-17 15:08:22 +00:00
|
|
|
|
2017-03-09 12:50:39 +00:00
|
|
|
#endif /* !__ASSEMBLER__ */
|
2017-05-10 07:45:04 +00:00
|
|
|
//}}
|
2017-03-09 12:50:39 +00:00
|
|
|
|
2016-08-17 15:08:22 +00:00
|
|
|
//Periheral Clock {{
|
2016-11-21 14:59:46 +00:00
|
|
|
#define APB_CLK_FREQ_ROM ( 26*1000000 )
|
2016-08-17 15:08:22 +00:00
|
|
|
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
|
|
|
|
|
#define CPU_CLK_FREQ APB_CLK_FREQ
|
2016-11-21 14:59:46 +00:00
|
|
|
#define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz
|
2017-08-21 14:30:23 +00:00
|
|
|
#define REF_CLK_FREQ ( 1000000 )
|
2016-08-17 15:08:22 +00:00
|
|
|
#define UART_CLK_FREQ APB_CLK_FREQ
|
2016-08-31 13:53:23 +00:00
|
|
|
#define WDT_CLK_FREQ APB_CLK_FREQ
|
2016-08-17 15:08:22 +00:00
|
|
|
#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16
|
|
|
|
|
#define SPI_CLK_DIV 4
|
2016-08-31 13:53:23 +00:00
|
|
|
#define TICKS_PER_US_ROM 26 // CPU is 80MHz
|
2019-01-23 09:07:03 +00:00
|
|
|
#define GPIO_MATRIX_DELAY_NS 25
|
2016-08-17 15:08:22 +00:00
|
|
|
//}}
|
|
|
|
|
|
2017-04-28 04:08:58 +00:00
|
|
|
/* Overall memory map */
|
2017-08-21 14:03:53 +00:00
|
|
|
#define SOC_DROM_LOW 0x3F400000
|
|
|
|
|
#define SOC_DROM_HIGH 0x3F800000
|
2017-04-28 04:08:58 +00:00
|
|
|
#define SOC_IROM_LOW 0x400D0000
|
|
|
|
|
#define SOC_IROM_HIGH 0x40400000
|
2018-12-02 22:57:26 +00:00
|
|
|
#define SOC_IROM_MASK_LOW 0x40000000
|
|
|
|
|
#define SOC_IROM_MASK_HIGH 0x40070000
|
2018-10-31 08:51:09 +00:00
|
|
|
#define SOC_CACHE_PRO_LOW 0x40070000
|
|
|
|
|
#define SOC_CACHE_PRO_HIGH 0x40078000
|
|
|
|
|
#define SOC_CACHE_APP_LOW 0x40078000
|
|
|
|
|
#define SOC_CACHE_APP_HIGH 0x40080000
|
2017-04-28 04:08:58 +00:00
|
|
|
#define SOC_IRAM_LOW 0x40080000
|
|
|
|
|
#define SOC_IRAM_HIGH 0x400A0000
|
|
|
|
|
#define SOC_RTC_IRAM_LOW 0x400C0000
|
|
|
|
|
#define SOC_RTC_IRAM_HIGH 0x400C2000
|
2018-09-29 02:54:06 +00:00
|
|
|
#define SOC_RTC_DRAM_LOW 0x3FF80000
|
|
|
|
|
#define SOC_RTC_DRAM_HIGH 0x3FF82000
|
2017-04-28 04:08:58 +00:00
|
|
|
#define SOC_RTC_DATA_LOW 0x50000000
|
|
|
|
|
#define SOC_RTC_DATA_HIGH 0x50002000
|
|
|
|
|
|
2017-05-03 08:03:28 +00:00
|
|
|
//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
|
|
|
|
|
#define SOC_DIRAM_IRAM_LOW 0x400A0000
|
|
|
|
|
#define SOC_DIRAM_IRAM_HIGH 0x400BFFFC
|
|
|
|
|
#define SOC_DIRAM_DRAM_LOW 0x3FFE0000
|
|
|
|
|
#define SOC_DIRAM_DRAM_HIGH 0x3FFFFFFC
|
|
|
|
|
|
2017-05-05 04:16:02 +00:00
|
|
|
// Region of memory accessible via DMA. See esp_ptr_dma_capable().
|
|
|
|
|
#define SOC_DMA_LOW 0x3FFAE000
|
|
|
|
|
#define SOC_DMA_HIGH 0x40000000
|
|
|
|
|
|
2017-09-22 08:02:39 +00:00
|
|
|
// Region of memory that is byte-accessible. See esp_ptr_byte_accessible().
|
2017-10-18 04:18:38 +00:00
|
|
|
#define SOC_BYTE_ACCESSIBLE_LOW 0x3FF90000
|
2017-08-21 14:03:53 +00:00
|
|
|
#define SOC_BYTE_ACCESSIBLE_HIGH 0x40000000
|
|
|
|
|
|
2017-10-18 04:18:38 +00:00
|
|
|
//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
|
|
|
|
|
//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
|
|
|
|
|
#define SOC_MEM_INTERNAL_LOW 0x3FF90000
|
2017-09-22 08:02:39 +00:00
|
|
|
#define SOC_MEM_INTERNAL_HIGH 0x400C2000
|
|
|
|
|
|
2016-08-31 13:53:23 +00:00
|
|
|
//Interrupt hardware source table
|
|
|
|
|
//This table is decided by hardware, don't touch this.
|
|
|
|
|
#define ETS_WIFI_MAC_INTR_SOURCE 0/**< interrupt of WiFi MAC, level*/
|
|
|
|
|
#define ETS_WIFI_MAC_NMI_SOURCE 1/**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
|
|
|
|
|
#define ETS_WIFI_BB_INTR_SOURCE 2/**< interrupt of WiFi BB, level, we can do some calibartion*/
|
|
|
|
|
#define ETS_BT_MAC_INTR_SOURCE 3/**< will be cancelled*/
|
|
|
|
|
#define ETS_BT_BB_INTR_SOURCE 4/**< interrupt of BT BB, level*/
|
|
|
|
|
#define ETS_BT_BB_NMI_SOURCE 5/**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
|
|
|
|
|
#define ETS_RWBT_INTR_SOURCE 6/**< interrupt of RWBT, level*/
|
|
|
|
|
#define ETS_RWBLE_INTR_SOURCE 7/**< interrupt of RWBLE, level*/
|
|
|
|
|
#define ETS_RWBT_NMI_SOURCE 8/**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
|
|
|
|
|
#define ETS_RWBLE_NMI_SOURCE 9/**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
|
|
|
|
|
#define ETS_SLC0_INTR_SOURCE 10/**< interrupt of SLC0, level*/
|
|
|
|
|
#define ETS_SLC1_INTR_SOURCE 11/**< interrupt of SLC1, level*/
|
|
|
|
|
#define ETS_UHCI0_INTR_SOURCE 12/**< interrupt of UHCI0, level*/
|
|
|
|
|
#define ETS_UHCI1_INTR_SOURCE 13/**< interrupt of UHCI1, level*/
|
|
|
|
|
#define ETS_TG0_T0_LEVEL_INTR_SOURCE 14/**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/
|
|
|
|
|
#define ETS_TG0_T1_LEVEL_INTR_SOURCE 15/**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/
|
|
|
|
|
#define ETS_TG0_WDT_LEVEL_INTR_SOURCE 16/**< interrupt of TIMER_GROUP0, WATCHDOG, level*/
|
|
|
|
|
#define ETS_TG0_LACT_LEVEL_INTR_SOURCE 17/**< interrupt of TIMER_GROUP0, LACT, level*/
|
|
|
|
|
#define ETS_TG1_T0_LEVEL_INTR_SOURCE 18/**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/
|
|
|
|
|
#define ETS_TG1_T1_LEVEL_INTR_SOURCE 19/**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/
|
|
|
|
|
#define ETS_TG1_WDT_LEVEL_INTR_SOURCE 20/**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
|
|
|
|
|
#define ETS_TG1_LACT_LEVEL_INTR_SOURCE 21/**< interrupt of TIMER_GROUP1, LACT, level*/
|
|
|
|
|
#define ETS_GPIO_INTR_SOURCE 22/**< interrupt of GPIO, level*/
|
|
|
|
|
#define ETS_GPIO_NMI_SOURCE 23/**< interrupt of GPIO, NMI*/
|
2016-11-01 09:53:59 +00:00
|
|
|
#define ETS_FROM_CPU_INTR0_SOURCE 24/**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
|
|
|
|
|
#define ETS_FROM_CPU_INTR1_SOURCE 25/**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
|
2017-05-08 12:03:04 +00:00
|
|
|
#define ETS_FROM_CPU_INTR2_SOURCE 26/**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
|
|
|
|
|
#define ETS_FROM_CPU_INTR3_SOURCE 27/**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
|
2016-08-31 13:53:23 +00:00
|
|
|
#define ETS_SPI0_INTR_SOURCE 28/**< interrupt of SPI0, level, SPI0 is for Cache Access, do not use this*/
|
|
|
|
|
#define ETS_SPI1_INTR_SOURCE 29/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
|
|
|
|
|
#define ETS_SPI2_INTR_SOURCE 30/**< interrupt of SPI2, level*/
|
|
|
|
|
#define ETS_SPI3_INTR_SOURCE 31/**< interrupt of SPI3, level*/
|
|
|
|
|
#define ETS_I2S0_INTR_SOURCE 32/**< interrupt of I2S0, level*/
|
|
|
|
|
#define ETS_I2S1_INTR_SOURCE 33/**< interrupt of I2S1, level*/
|
|
|
|
|
#define ETS_UART0_INTR_SOURCE 34/**< interrupt of UART0, level*/
|
|
|
|
|
#define ETS_UART1_INTR_SOURCE 35/**< interrupt of UART1, level*/
|
|
|
|
|
#define ETS_UART2_INTR_SOURCE 36/**< interrupt of UART2, level*/
|
|
|
|
|
#define ETS_SDIO_HOST_INTR_SOURCE 37/**< interrupt of SD/SDIO/MMC HOST, level*/
|
|
|
|
|
#define ETS_ETH_MAC_INTR_SOURCE 38/**< interrupt of ethernet mac, level*/
|
|
|
|
|
#define ETS_PWM0_INTR_SOURCE 39/**< interrupt of PWM0, level, Reserved*/
|
|
|
|
|
#define ETS_PWM1_INTR_SOURCE 40/**< interrupt of PWM1, level, Reserved*/
|
|
|
|
|
#define ETS_PWM2_INTR_SOURCE 41/**< interrupt of PWM2, level*/
|
|
|
|
|
#define ETS_PWM3_INTR_SOURCE 42/**< interruot of PWM3, level*/
|
|
|
|
|
#define ETS_LEDC_INTR_SOURCE 43/**< interrupt of LED PWM, level*/
|
|
|
|
|
#define ETS_EFUSE_INTR_SOURCE 44/**< interrupt of efuse, level, not likely to use*/
|
|
|
|
|
#define ETS_CAN_INTR_SOURCE 45/**< interrupt of can, level*/
|
|
|
|
|
#define ETS_RTC_CORE_INTR_SOURCE 46/**< interrupt of rtc core, level, include rtc watchdog*/
|
|
|
|
|
#define ETS_RMT_INTR_SOURCE 47/**< interrupt of remote controller, level*/
|
|
|
|
|
#define ETS_PCNT_INTR_SOURCE 48/**< interrupt of pluse count, level*/
|
|
|
|
|
#define ETS_I2C_EXT0_INTR_SOURCE 49/**< interrupt of I2C controller1, level*/
|
|
|
|
|
#define ETS_I2C_EXT1_INTR_SOURCE 50/**< interrupt of I2C controller0, level*/
|
|
|
|
|
#define ETS_RSA_INTR_SOURCE 51/**< interrupt of RSA accelerator, level*/
|
|
|
|
|
#define ETS_SPI1_DMA_INTR_SOURCE 52/**< interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this*/
|
|
|
|
|
#define ETS_SPI2_DMA_INTR_SOURCE 53/**< interrupt of SPI2 DMA, level*/
|
|
|
|
|
#define ETS_SPI3_DMA_INTR_SOURCE 54/**< interrupt of SPI3 DMA, level*/
|
|
|
|
|
#define ETS_WDT_INTR_SOURCE 55/**< will be cancelled*/
|
|
|
|
|
#define ETS_TIMER1_INTR_SOURCE 56/**< will be cancelled*/
|
|
|
|
|
#define ETS_TIMER2_INTR_SOURCE 57/**< will be cancelled*/
|
|
|
|
|
#define ETS_TG0_T0_EDGE_INTR_SOURCE 58/**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/
|
|
|
|
|
#define ETS_TG0_T1_EDGE_INTR_SOURCE 59/**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/
|
|
|
|
|
#define ETS_TG0_WDT_EDGE_INTR_SOURCE 60/**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/
|
|
|
|
|
#define ETS_TG0_LACT_EDGE_INTR_SOURCE 61/**< interrupt of TIMER_GROUP0, LACT, EDGE*/
|
|
|
|
|
#define ETS_TG1_T0_EDGE_INTR_SOURCE 62/**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/
|
|
|
|
|
#define ETS_TG1_T1_EDGE_INTR_SOURCE 63/**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/
|
|
|
|
|
#define ETS_TG1_WDT_EDGE_INTR_SOURCE 64/**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/
|
|
|
|
|
#define ETS_TG1_LACT_EDGE_INTR_SOURCE 65/**< interrupt of TIMER_GROUP0, LACT, EDGE*/
|
|
|
|
|
#define ETS_MMU_IA_INTR_SOURCE 66/**< interrupt of MMU Invalid Access, LEVEL*/
|
|
|
|
|
#define ETS_MPU_IA_INTR_SOURCE 67/**< interrupt of MPU Invalid Access, LEVEL*/
|
|
|
|
|
#define ETS_CACHE_IA_INTR_SOURCE 68/**< interrupt of Cache Invalied Access, LEVEL*/
|
2016-08-17 15:08:22 +00:00
|
|
|
|
2016-08-31 13:53:23 +00:00
|
|
|
//interrupt cpu using table, Please see the core-isa.h
|
|
|
|
|
/*************************************************************************************************************
|
|
|
|
|
* Intr num Level Type PRO CPU usage APP CPU uasge
|
|
|
|
|
* 0 1 extern level WMAC Reserved
|
2017-04-28 09:17:39 +00:00
|
|
|
* 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA
|
2016-12-08 04:38:22 +00:00
|
|
|
* 2 1 extern level
|
|
|
|
|
* 3 1 extern level
|
2016-08-31 13:53:23 +00:00
|
|
|
* 4 1 extern level WBB
|
2017-04-28 09:17:39 +00:00
|
|
|
* 5 1 extern level BT/BLE Controller BT/BLE Controller
|
2016-08-31 13:53:23 +00:00
|
|
|
* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
|
2017-04-28 09:17:39 +00:00
|
|
|
* 7 1 software BT/BLE VHCI BT/BLE VHCI
|
|
|
|
|
* 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX)
|
2016-12-08 04:38:22 +00:00
|
|
|
* 9 1 extern level
|
2017-08-21 14:29:50 +00:00
|
|
|
* 10 1 extern edge
|
2016-08-31 13:53:23 +00:00
|
|
|
* 11 3 profiling
|
|
|
|
|
* 12 1 extern level
|
|
|
|
|
* 13 1 extern level
|
|
|
|
|
* 14 7 nmi Reserved Reserved
|
|
|
|
|
* 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3)
|
|
|
|
|
* 16 5 timer
|
|
|
|
|
* 17 1 extern level
|
|
|
|
|
* 18 1 extern level
|
|
|
|
|
* 19 2 extern level
|
|
|
|
|
* 20 2 extern level
|
|
|
|
|
* 21 2 extern level
|
2017-08-21 14:29:50 +00:00
|
|
|
* 22 3 extern edge
|
2016-08-31 13:53:23 +00:00
|
|
|
* 23 3 extern level
|
2016-11-02 09:17:28 +00:00
|
|
|
* 24 4 extern level TG1_WDT
|
2017-03-09 12:50:39 +00:00
|
|
|
* 25 4 extern level CACHEERR
|
2017-05-26 09:41:18 +00:00
|
|
|
* 26 5 extern level
|
2016-08-31 13:53:23 +00:00
|
|
|
* 27 3 extern level Reserved Reserved
|
2017-05-26 09:41:18 +00:00
|
|
|
* 28 4 extern edge DPORT ACCESS DPORT ACCESS
|
2016-08-31 13:53:23 +00:00
|
|
|
* 29 3 software Reserved Reserved
|
|
|
|
|
* 30 4 extern edge Reserved Reserved
|
2017-05-26 09:41:18 +00:00
|
|
|
* 31 5 extern level
|
2016-08-31 13:53:23 +00:00
|
|
|
*************************************************************************************************************
|
|
|
|
|
*/
|
2016-08-17 15:08:22 +00:00
|
|
|
|
2016-08-31 13:53:23 +00:00
|
|
|
//CPU0 Interrupt number reserved, not touch this.
|
|
|
|
|
#define ETS_WMAC_INUM 0
|
|
|
|
|
#define ETS_BT_HOST_INUM 1
|
|
|
|
|
#define ETS_WBB_INUM 4
|
|
|
|
|
#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
|
2016-11-02 09:17:28 +00:00
|
|
|
#define ETS_FRC1_INUM 22
|
|
|
|
|
#define ETS_T1_WDT_INUM 24
|
2017-03-09 12:50:39 +00:00
|
|
|
#define ETS_CACHEERR_INUM 25
|
2017-05-26 09:41:18 +00:00
|
|
|
#define ETS_DPORT_INUM 28
|
2016-08-17 15:08:22 +00:00
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2016-11-02 09:17:28 +00:00
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//CPU0 Interrupt number used in ROM, should be cancelled in SDK
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2016-08-31 13:53:23 +00:00
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#define ETS_SLC_INUM 1
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#define ETS_UART0_INUM 5
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#define ETS_UART1_INUM 5
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2016-09-13 15:02:03 +00:00
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//Other interrupt number should be managed by the user
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2016-08-17 15:08:22 +00:00
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2017-06-15 09:20:25 +00:00
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//Invalid interrupt for number interrupt matrix
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#define ETS_INVALID_INUM 6
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2016-08-17 15:08:22 +00:00
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#endif /* _ESP32_SOC_H_ */
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