Crash_Override/OVMS3-idf
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Only modify headers in soc/ .

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Pass compiling under esp-idf-tests/merge_soc_tmp/merge_for_soc_headers branch.(only change some names of register and INUM).
This commit is contained in:
Wangjialin 2016-09-13 23:02:03 +08:00 committed by Wu Jian Gang
parent fb64393f63
commit 41d397cf3f
30 changed files with 31346 additions and 9669 deletions
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18
components/bootloader/src/main/bootloader_start.c
View file

@ -27,7 +27,7 @@
#include "soc/io_mux_reg.h"
#include "soc/efuse_reg.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/timers_reg.h"
#include "soc/timer_group_reg.h"
#include "sdkconfig.h"
@ -99,9 +99,9 @@ void IRAM_ATTR call_start_cpu0()
Cache_Flush(0);
Cache_Flush(1);
mmu_init(0);
REG_SET_BIT(APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
mmu_init(1);
REG_CLR_BIT(APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
/* (above steps probably unnecessary for most serial bootloader
usage, all that's absolutely needed is that we unmask DROM0
cache on the following two lines - normal ROM boot exits with
@ -112,8 +112,8 @@ void IRAM_ATTR call_start_cpu0()
The lines which manipulate DPORT_APP_CACHE_MMU_IA_CLR bit are
necessary to work around a hardware bug.
*/
REG_CLR_BIT(PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);
REG_CLR_BIT(APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0);
REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);
REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0);
bootloader_main();
}
@ -291,8 +291,8 @@ void bootloader_main()
log_notice( "compile time %s\n", __TIME__ );
/* close watch dog here */
REG_CLR_BIT( RTC_WDTCONFIG0, RTC_CNTL_WDT_FLASHBOOT_MOD_EN );
REG_CLR_BIT( WDTCONFIG0(0), TIMERS_WDT_FLASHBOOT_MOD_EN );
REG_CLR_BIT( RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN );
REG_CLR_BIT( TIMG_WDTCONFIG0_REG(0), TIMG_WDT_FLASHBOOT_MOD_EN );
SPIUnlock();
/*register first sector in drom0 page 0 */
boot_cache_redirect( 0, 0x5000 );
@ -485,8 +485,8 @@ void IRAM_ATTR set_cache_and_start_app(
log_debug( "rc=%d", rc );
rc = cache_flash_mmu_set( 1, 0, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count );
log_debug( "rc=%d", rc );
REG_CLR_BIT( PRO_CACHE_CTRL1_REG, (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) | (DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 | DPORT_PRO_CACHE_MASK_DRAM1 );
REG_CLR_BIT( APP_CACHE_CTRL1_REG, (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) | (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 | DPORT_APP_CACHE_MASK_DRAM1 );
REG_CLR_BIT( DPORT_PRO_CACHE_CTRL1_REG, (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) | (DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 | DPORT_PRO_CACHE_MASK_DRAM1 );
REG_CLR_BIT( DPORT_APP_CACHE_CTRL1_REG, (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) | (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 | DPORT_APP_CACHE_MASK_DRAM1 );
Cache_Read_Enable( 0 );
Cache_Read_Enable( 1 );

16
components/bootloader/src/main/flash_encrypt.c
View file

@ -101,7 +101,7 @@ bool flash_encrypt_write(uint32_t pos, uint32_t len)
bool flash_encrypt(bootloader_state_t *bs)
{
uint32_t bin_len = 0;
uint32_t flash_crypt_cnt = REG_GET_FIELD(EFUSE_BLK0_RDATA0, EFUSE_FLASH_CRYPT_CNT);
uint32_t flash_crypt_cnt = REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_FLASH_CRYPT_CNT);
uint8_t count = bitcount(flash_crypt_cnt);
int i = 0;
log_debug("flash crypt cnt %x, count %d\n", flash_crypt_cnt, count);
@ -174,14 +174,14 @@ bool flash_encrypt(bootloader_state_t *bs)
log_error("encrypt ota binfo error");
return false;
}
REG_SET_FIELD(EFUSE_BLK0_WDATA0, EFUSE_FLASH_CRYPT_CNT, 0x04);
REG_WRITE(EFUSE_CONF, 0x5A5A); /* efuse_pgm_op_ena, force no rd/wr disable */
REG_WRITE(EFUSE_CMD, 0x02); /* efuse_pgm_cmd */
while (REG_READ(EFUSE_CMD)); /* wait for efuse_pagm_cmd=0 */
REG_SET_FIELD(EFUSE_BLK0_WDATA0_REG, EFUSE_FLASH_CRYPT_CNT, 0x04);
REG_WRITE(EFUSE_CONF_REG, 0x5A5A); /* efuse_pgm_op_ena, force no rd/wr disable */
REG_WRITE(EFUSE_CMD_REG, 0x02); /* efuse_pgm_cmd */
while (REG_READ(EFUSE_CMD_REG)); /* wait for efuse_pagm_cmd=0 */
log_warn("burn flash_crypt_cnt\n");
REG_WRITE(EFUSE_CONF, 0x5AA5); /* efuse_read_op_ena, release force */
REG_WRITE(EFUSE_CMD, 0x01); /* efuse_read_cmd */
while (REG_READ(EFUSE_CMD)); /* wait for efuse_read_cmd=0 */
REG_WRITE(EFUSE_CONF_REG, 0x5AA5); /* efuse_read_op_ena, release force */
REG_WRITE(EFUSE_CMD_REG, 0x01); /* efuse_read_cmd */
while (REG_READ(EFUSE_CMD_REG)); /* wait for efuse_read_cmd=0 */
return true;
} else {
log_info("flash already encrypted.\n");

18
components/bootloader/src/main/secure_boot.c
View file

@ -94,7 +94,7 @@ bool secure_boot_generate(uint32_t bin_len){
*/
bool secure_boot(void){
uint32_t bin_len = 0;
if (REG_READ(EFUSE_BLK0_RDATA6) & EFUSE_RD_ABS_DONE_0)
if (REG_READ(EFUSE_BLK0_RDATA6_REG) & EFUSE_RD_ABS_DONE_0)
{
log_info("already secure boot !\n");
return true;
@ -111,15 +111,15 @@ bool secure_boot(void){
}
}
REG_SET_BIT(EFUSE_BLK0_WDATA6, EFUSE_RD_ABS_DONE_0);
REG_WRITE(EFUSE_CONF, 0x5A5A); /* efuse_pgm_op_ena, force no rd/wr disable */
REG_WRITE(EFUSE_CMD, 0x02); /* efuse_pgm_cmd */
while (REG_READ(EFUSE_CMD)); /* wait for efuse_pagm_cmd=0 */
REG_SET_BIT(EFUSE_BLK0_WDATA6_REG, EFUSE_RD_ABS_DONE_0);
REG_WRITE(EFUSE_CONF_REG, 0x5A5A); /* efuse_pgm_op_ena, force no rd/wr disable */
REG_WRITE(EFUSE_CMD_REG, 0x02); /* efuse_pgm_cmd */
while (REG_READ(EFUSE_CMD_REG)); /* wait for efuse_pagm_cmd=0 */
log_warn("burn abstract_done_0\n");
REG_WRITE(EFUSE_CONF, 0x5AA5); /* efuse_read_op_ena, release force */
REG_WRITE(EFUSE_CMD, 0x01); /* efuse_read_cmd */
while (REG_READ(EFUSE_CMD)); /* wait for efuse_read_cmd=0 */
log_debug("read EFUSE_BLK0_RDATA6 %x\n", REG_READ(EFUSE_BLK0_RDATA6));
REG_WRITE(EFUSE_CONF_REG, 0x5AA5); /* efuse_read_op_ena, release force */
REG_WRITE(EFUSE_CMD_REG, 0x01); /* efuse_read_cmd */
while (REG_READ(EFUSE_CMD_REG)); /* wait for efuse_read_cmd=0 */
log_debug("read EFUSE_BLK0_RDATA6 %x\n", REG_READ(EFUSE_BLK0_RDATA6_REG));
return true;
}

10
components/esp32/cpu_start.c
View file

@ -118,17 +118,17 @@ void IRAM_ATTR call_user_start_cpu0() {
#ifndef CONFIG_FREERTOS_UNICORE
ets_printf("Starting app cpu, entry point is %p\n", call_user_start_cpu1);
SET_PERI_REG_MASK(APPCPU_CTRL_REG_B, DPORT_APPCPU_CLKGATE_EN);
CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_C, DPORT_APPCPU_RUNSTALL);
SET_PERI_REG_MASK(APPCPU_CTRL_REG_A, DPORT_APPCPU_RESETTING);
CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_A, DPORT_APPCPU_RESETTING);
SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
ets_set_appcpu_boot_addr((uint32_t)call_user_start_cpu1);
while (!app_cpu_started) {
ets_delay_us(100);
}
#else
CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_B, DPORT_APPCPU_CLKGATE_EN);
CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
#endif
ets_printf("Pro cpu start user code\n");
user_start_cpu0();

2
components/esp32/include/rom/spi_flash.h
View file

@ -20,7 +20,7 @@
#include "esp_attr.h"
#include "soc/spi_register.h"
#include "soc/spi_reg.h"
#ifdef __cplusplus
extern "C" {

5564
components/esp32/include/soc/dport_reg.h
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File diff suppressed because it is too large Load diff

1370
components/esp32/include/soc/efuse_reg.h
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File diff suppressed because it is too large Load diff

11305
components/esp32/include/soc/gpio_reg.h
View file

File diff suppressed because it is too large Load diff

182
components/esp32/include/soc/gpio_sd_reg.h
View file

@ -15,66 +15,146 @@
#define _SOC_GPIO_SD_REG_H_
#include "soc.h"
#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0000)
/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD0_PRESCALE 0x000000FF
#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S))
#define GPIO_SD0_PRESCALE_V 0xFF
#define GPIO_SD0_PRESCALE_S 8
/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD0_IN 0x000000FF
#define GPIO_SD0_IN_M ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S))
#define GPIO_SD0_IN_V 0xFF
#define GPIO_SD0_IN_S 0
#define SIGMADELTA0 (DR_REG_GPIO_SD_BASE + 0x0000)
#define SIGMADELTA_SD0_PRESCALE 0x000000FF
#define SIGMADELTA_SD0_PRESCALE_S 8
#define SIGMADELTA_SD0_IN 0x000000FF
#define SIGMADELTA_SD0_IN_S 0
#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x0004)
/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD1_PRESCALE 0x000000FF
#define GPIO_SD1_PRESCALE_M ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S))
#define GPIO_SD1_PRESCALE_V 0xFF
#define GPIO_SD1_PRESCALE_S 8
/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD1_IN 0x000000FF
#define GPIO_SD1_IN_M ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S))
#define GPIO_SD1_IN_V 0xFF
#define GPIO_SD1_IN_S 0
#define SIGMADELTA1 (DR_REG_GPIO_SD_BASE + 0x0004)
#define SIGMADELTA_SD1_PRESCALE 0x000000FF
#define SIGMADELTA_SD1_PRESCALE_S 8
#define SIGMADELTA_SD1_IN 0x000000FF
#define SIGMADELTA_SD1_IN_S 0
#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x0008)
/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD2_PRESCALE 0x000000FF
#define GPIO_SD2_PRESCALE_M ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S))
#define GPIO_SD2_PRESCALE_V 0xFF
#define GPIO_SD2_PRESCALE_S 8
/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD2_IN 0x000000FF
#define GPIO_SD2_IN_M ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S))
#define GPIO_SD2_IN_V 0xFF
#define GPIO_SD2_IN_S 0
#define SIGMADELTA2 (DR_REG_GPIO_SD_BASE + 0x0008)
#define SIGMADELTA_SD2_PRESCALE 0x000000FF
#define SIGMADELTA_SD2_PRESCALE_S 8
#define SIGMADELTA_SD2_IN 0x000000FF
#define SIGMADELTA_SD2_IN_S 0
#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0x000c)
/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD3_PRESCALE 0x000000FF
#define GPIO_SD3_PRESCALE_M ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S))
#define GPIO_SD3_PRESCALE_V 0xFF
#define GPIO_SD3_PRESCALE_S 8
/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD3_IN 0x000000FF
#define GPIO_SD3_IN_M ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S))
#define GPIO_SD3_IN_V 0xFF
#define GPIO_SD3_IN_S 0
#define SIGMADELTA3 (DR_REG_GPIO_SD_BASE + 0x000c)
#define SIGMADELTA_SD3_PRESCALE 0x000000FF
#define SIGMADELTA_SD3_PRESCALE_S 8
#define SIGMADELTA_SD3_IN 0x000000FF
#define SIGMADELTA_SD3_IN_S 0
#define GPIO_SIGMADELTA4_REG (DR_REG_GPIO_SD_BASE + 0x0010)
/* GPIO_SD4_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD4_PRESCALE 0x000000FF
#define GPIO_SD4_PRESCALE_M ((GPIO_SD4_PRESCALE_V)<<(GPIO_SD4_PRESCALE_S))
#define GPIO_SD4_PRESCALE_V 0xFF
#define GPIO_SD4_PRESCALE_S 8
/* GPIO_SD4_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD4_IN 0x000000FF
#define GPIO_SD4_IN_M ((GPIO_SD4_IN_V)<<(GPIO_SD4_IN_S))
#define GPIO_SD4_IN_V 0xFF
#define GPIO_SD4_IN_S 0
#define SIGMADELTA4 (DR_REG_GPIO_SD_BASE + 0x0010)
#define SIGMADELTA_SD4_PRESCALE 0x000000FF
#define SIGMADELTA_SD4_PRESCALE_S 8
#define SIGMADELTA_SD4_IN 0x000000FF
#define SIGMADELTA_SD4_IN_S 0
#define GPIO_SIGMADELTA5_REG (DR_REG_GPIO_SD_BASE + 0x0014)
/* GPIO_SD5_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD5_PRESCALE 0x000000FF
#define GPIO_SD5_PRESCALE_M ((GPIO_SD5_PRESCALE_V)<<(GPIO_SD5_PRESCALE_S))
#define GPIO_SD5_PRESCALE_V 0xFF
#define GPIO_SD5_PRESCALE_S 8
/* GPIO_SD5_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD5_IN 0x000000FF
#define GPIO_SD5_IN_M ((GPIO_SD5_IN_V)<<(GPIO_SD5_IN_S))
#define GPIO_SD5_IN_V 0xFF
#define GPIO_SD5_IN_S 0
#define SIGMADELTA5 (DR_REG_GPIO_SD_BASE + 0x0014)
#define SIGMADELTA_SD5_PRESCALE 0x000000FF
#define SIGMADELTA_SD5_PRESCALE_S 8
#define SIGMADELTA_SD5_IN 0x000000FF
#define SIGMADELTA_SD5_IN_S 0
#define GPIO_SIGMADELTA6_REG (DR_REG_GPIO_SD_BASE + 0x0018)
/* GPIO_SD6_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD6_PRESCALE 0x000000FF
#define GPIO_SD6_PRESCALE_M ((GPIO_SD6_PRESCALE_V)<<(GPIO_SD6_PRESCALE_S))
#define GPIO_SD6_PRESCALE_V 0xFF
#define GPIO_SD6_PRESCALE_S 8
/* GPIO_SD6_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD6_IN 0x000000FF
#define GPIO_SD6_IN_M ((GPIO_SD6_IN_V)<<(GPIO_SD6_IN_S))
#define GPIO_SD6_IN_V 0xFF
#define GPIO_SD6_IN_S 0
#define SIGMADELTA6 (DR_REG_GPIO_SD_BASE + 0x0018)
#define SIGMADELTA_SD6_PRESCALE 0x000000FF
#define SIGMADELTA_SD6_PRESCALE_S 8
#define SIGMADELTA_SD6_IN 0x000000FF
#define SIGMADELTA_SD6_IN_S 0
#define GPIO_SIGMADELTA7_REG (DR_REG_GPIO_SD_BASE + 0x001c)
/* GPIO_SD7_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD7_PRESCALE 0x000000FF
#define GPIO_SD7_PRESCALE_M ((GPIO_SD7_PRESCALE_V)<<(GPIO_SD7_PRESCALE_S))
#define GPIO_SD7_PRESCALE_V 0xFF
#define GPIO_SD7_PRESCALE_S 8
/* GPIO_SD7_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD7_IN 0x000000FF
#define GPIO_SD7_IN_M ((GPIO_SD7_IN_V)<<(GPIO_SD7_IN_S))
#define GPIO_SD7_IN_V 0xFF
#define GPIO_SD7_IN_S 0
#define SIGMADELTA7 (DR_REG_GPIO_SD_BASE + 0x001c)
#define SIGMADELTA_SD7_PRESCALE 0x000000FF
#define SIGMADELTA_SD7_PRESCALE_S 8
#define SIGMADELTA_SD7_IN 0x000000FF
#define SIGMADELTA_SD7_IN_S 0
#define GPIO_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x0020)
/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define GPIO_SD_CLK_EN (BIT(31))
#define GPIO_SD_CLK_EN_M (BIT(31))
#define GPIO_SD_CLK_EN_V 0x1
#define GPIO_SD_CLK_EN_S 31
#define SIGMADELTA_CG (DR_REG_GPIO_SD_BASE + 0x0020)
#define SIGMADELTA_GPIO_SD_CLK_EN (BIT(31))
#define SIGMADELTA_GPIO_SD_CLK_EN_S 31
#define GPIO_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x0024)
/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define GPIO_SPI_SWAP (BIT(31))
#define GPIO_SPI_SWAP_M (BIT(31))
#define GPIO_SPI_SWAP_V 0x1
#define GPIO_SPI_SWAP_S 31
#define SIGMADELTA_MISC (DR_REG_GPIO_SD_BASE + 0x0024)
#define SIGMADELTA_SPI_SWAP (BIT(31))
#define SIGMADELTA_SPI_SWAP_S 31
#define SIGMADELTA_VERSION (DR_REG_GPIO_SD_BASE + 0x0028)
#define SIGMADELTA_GPIO_SD_DATE 0x0FFFFFFF
#define SIGMADELTA_GPIO_SD_DATE_S 0
#define GPIO_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0x0028)
/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h1506190 ; */
/*description: */
#define GPIO_SD_DATE 0x0FFFFFFF
#define GPIO_SD_DATE_M ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S))
#define GPIO_SD_DATE_V 0xFFFFFFF
#define GPIO_SD_DATE_S 0
#define SIGMADELTA_GPIO_SD_DATE_VERSION 0x1506190
#endif /* _SOC_GPIO_SD_REG_H_ */
#endif /*_SOC_GPIO_SD_REG_H_ */

949
components/esp32/include/soc/i2c_reg.h Normal file
View file

@ -0,0 +1,949 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_I2C_REG_H_
#define _SOC_I2C_REG_H_
#include "soc.h"
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0000)
/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This register is used to configure the low level width of SCL clock.*/
#define I2C_SCL_LOW_PERIOD 0x00003FFF
#define I2C_SCL_LOW_PERIOD_M ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S))
#define I2C_SCL_LOW_PERIOD_V 0x3FFF
#define I2C_SCL_LOW_PERIOD_S 0
#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x0004)
/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: This is the clock gating control bit for reading or writing registers.*/
#define I2C_CLK_EN (BIT(8))
#define I2C_CLK_EN_M (BIT(8))
#define I2C_CLK_EN_V 0x1
#define I2C_CLK_EN_S 8
/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */
/*description: This bit is used to control the storage mode for received datas.
1: receive data from most significant bit 0: receive data from least significant bit*/
#define I2C_RX_LSB_FIRST (BIT(7))
#define I2C_RX_LSB_FIRST_M (BIT(7))
#define I2C_RX_LSB_FIRST_V 0x1
#define I2C_RX_LSB_FIRST_S 7
/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: This bit is used to control the sending mode for data need to
be send. 1: receive data from most significant bit 0: receive data from least significant bit*/
#define I2C_TX_LSB_FIRST (BIT(6))
#define I2C_TX_LSB_FIRST_M (BIT(6))
#define I2C_TX_LSB_FIRST_V 0x1
#define I2C_TX_LSB_FIRST_S 6
/* I2C_TRANS_START : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: Set this bit to start sending data in txfifo.*/
#define I2C_TRANS_START (BIT(5))
#define I2C_TRANS_START_M (BIT(5))
#define I2C_TRANS_START_V 0x1
#define I2C_TRANS_START_S 5
/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: Set this bit to configure the module as i2c master clear this
bit to configure the module as i2c slave.*/
#define I2C_MS_MODE (BIT(4))
#define I2C_MS_MODE_M (BIT(4))
#define I2C_MS_MODE_V 0x1
#define I2C_MS_MODE_S 4
/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set this bit to sample data in SCL low level. clear this bit
to sample data in SCL high level.*/
#define I2C_SAMPLE_SCL_LEVEL (BIT(2))
#define I2C_SAMPLE_SCL_LEVEL_M (BIT(2))
#define I2C_SAMPLE_SCL_LEVEL_V 0x1
#define I2C_SAMPLE_SCL_LEVEL_S 2
/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: 1: normally ouput scl clock 0: exchange the function of scl_o
and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/
#define I2C_SCL_FORCE_OUT (BIT(1))
#define I2C_SCL_FORCE_OUT_M (BIT(1))
#define I2C_SCL_FORCE_OUT_V 0x1
#define I2C_SCL_FORCE_OUT_S 1
/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: 1: normally ouput sda data 0: exchange the function of sda_o
and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/
#define I2C_SDA_FORCE_OUT (BIT(0))
#define I2C_SDA_FORCE_OUT_M (BIT(0))
#define I2C_SDA_FORCE_OUT_V 0x1
#define I2C_SDA_FORCE_OUT_S 0
#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x0008)
/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */
/*description: This register stores the value of state machine to produce SCL.
3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/
#define I2C_SCL_STATE_LAST 0x00000007
#define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S))
#define I2C_SCL_STATE_LAST_V 0x7
#define I2C_SCL_STATE_LAST_S 28
/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */
/*description: This register stores the value of state machine for i2c module.
3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/
#define I2C_SCL_MAIN_STATE_LAST 0x00000007
#define I2C_SCL_MAIN_STATE_LAST_M ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S))
#define I2C_SCL_MAIN_STATE_LAST_V 0x7
#define I2C_SCL_MAIN_STATE_LAST_S 24
/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */
/*description: This register stores the amount of received data in ram.*/
#define I2C_TXFIFO_CNT 0x0000003F
#define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S))
#define I2C_TXFIFO_CNT_V 0x3F
#define I2C_TXFIFO_CNT_S 18
/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */
/*description: This register represent the amount of data need to send.*/
#define I2C_RXFIFO_CNT 0x0000003F
#define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S))
#define I2C_RXFIFO_CNT_V 0x3F
#define I2C_RXFIFO_CNT_S 8
/* I2C_BYTE_TRANS : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: This register changes to high level when one byte is transferred.*/
#define I2C_BYTE_TRANS (BIT(6))
#define I2C_BYTE_TRANS_M (BIT(6))
#define I2C_BYTE_TRANS_V 0x1
#define I2C_BYTE_TRANS_S 6
/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: when configured as i2c slave and the address send by master
is equal to slave's address then this bit will be high level.*/
#define I2C_SLAVE_ADDRESSED (BIT(5))
#define I2C_SLAVE_ADDRESSED_M (BIT(5))
#define I2C_SLAVE_ADDRESSED_V 0x1
#define I2C_SLAVE_ADDRESSED_S 5
/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: 1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/
#define I2C_BUS_BUSY (BIT(4))
#define I2C_BUS_BUSY_M (BIT(4))
#define I2C_BUS_BUSY_V 0x1
#define I2C_BUS_BUSY_S 4
/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: when I2C lost control of SDA line this register changes to high level.*/
#define I2C_ARB_LOST (BIT(3))
#define I2C_ARB_LOST_M (BIT(3))
#define I2C_ARB_LOST_V 0x1
#define I2C_ARB_LOST_S 3
/* I2C_TIME_OUT : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: when I2C takes more than time_out_reg clocks to receive a data
then this register changes to high level.*/
#define I2C_TIME_OUT (BIT(2))
#define I2C_TIME_OUT_M (BIT(2))
#define I2C_TIME_OUT_V 0x1
#define I2C_TIME_OUT_S 2
/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: when in slave mode 1: master read slave 0: master write slave.*/
#define I2C_SLAVE_RW (BIT(1))
#define I2C_SLAVE_RW_M (BIT(1))
#define I2C_SLAVE_RW_V 0x1
#define I2C_SLAVE_RW_S 1
/* I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: This register stores the value of ACK bit.*/
#define I2C_ACK_REC (BIT(0))
#define I2C_ACK_REC_M (BIT(0))
#define I2C_ACK_REC_V 0x1
#define I2C_ACK_REC_S 0
#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0x000c)
/* I2C_TIME_OUT_REG : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
/*description: This register is used to configure the max clock number of receiving a data.*/
#define I2C_TIME_OUT_REG 0x000FFFFF
#define I2C_TIME_OUT_REG_M ((I2C_TIME_OUT_REG_V)<<(I2C_TIME_OUT_REG_S))
#define I2C_TIME_OUT_REG_V 0xFFFFF
#define I2C_TIME_OUT_REG_S 0
#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0010)
/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: This register is used to enable slave 10bit address mode.*/
#define I2C_ADDR_10BIT_EN (BIT(31))
#define I2C_ADDR_10BIT_EN_M (BIT(31))
#define I2C_ADDR_10BIT_EN_V 0x1
#define I2C_ADDR_10BIT_EN_S 31
/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
/*description: when configured as i2c slave this register is used to configure
slave's address.*/
#define I2C_SLAVE_ADDR 0x00007FFF
#define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S))
#define I2C_SLAVE_ADDR_V 0x7FFF
#define I2C_SLAVE_ADDR_S 0
#define I2C_RXFIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x0014)
/* I2C_TXFIFO_END_ADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */
/*description: This is the offset address of the last sending data as described
in nonfifo_tx_thres register.*/
#define I2C_TXFIFO_END_ADDR 0x0000001F
#define I2C_TXFIFO_END_ADDR_M ((I2C_TXFIFO_END_ADDR_V)<<(I2C_TXFIFO_END_ADDR_S))
#define I2C_TXFIFO_END_ADDR_V 0x1F
#define I2C_TXFIFO_END_ADDR_S 15
/* I2C_TXFIFO_START_ADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */
/*description: This is the offset address of the first sending data as described
in nonfifo_tx_thres register.*/
#define I2C_TXFIFO_START_ADDR 0x0000001F
#define I2C_TXFIFO_START_ADDR_M ((I2C_TXFIFO_START_ADDR_V)<<(I2C_TXFIFO_START_ADDR_S))
#define I2C_TXFIFO_START_ADDR_V 0x1F
#define I2C_TXFIFO_START_ADDR_S 10
/* I2C_RXFIFO_END_ADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */
/*description: This is the offset address of the first receiving data as described
in nonfifo_rx_thres_register.*/
#define I2C_RXFIFO_END_ADDR 0x0000001F
#define I2C_RXFIFO_END_ADDR_M ((I2C_RXFIFO_END_ADDR_V)<<(I2C_RXFIFO_END_ADDR_S))
#define I2C_RXFIFO_END_ADDR_V 0x1F
#define I2C_RXFIFO_END_ADDR_S 5
/* I2C_RXFIFO_START_ADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */
/*description: This is the offset address of the last receiving data as described
in nonfifo_rx_thres_register.*/
#define I2C_RXFIFO_START_ADDR 0x0000001F
#define I2C_RXFIFO_START_ADDR_M ((I2C_RXFIFO_START_ADDR_V)<<(I2C_RXFIFO_START_ADDR_S))
#define I2C_RXFIFO_START_ADDR_V 0x1F
#define I2C_RXFIFO_START_ADDR_S 0
#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x0018)
/* I2C_NONFIFO_TX_THRES : R/W ;bitpos:[25:20] ;default: 6'h15 ; */
/*description: when I2C sends more than nonfifo_tx_thres data it will produce
tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/
#define I2C_NONFIFO_TX_THRES 0x0000003F
#define I2C_NONFIFO_TX_THRES_M ((I2C_NONFIFO_TX_THRES_V)<<(I2C_NONFIFO_TX_THRES_S))
#define I2C_NONFIFO_TX_THRES_V 0x3F
#define I2C_NONFIFO_TX_THRES_S 20
/* I2C_NONFIFO_RX_THRES : R/W ;bitpos:[19:14] ;default: 6'h15 ; */
/*description: when I2C receives more than nonfifo_rx_thres data it will produce
rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/
#define I2C_NONFIFO_RX_THRES 0x0000003F
#define I2C_NONFIFO_RX_THRES_M ((I2C_NONFIFO_RX_THRES_V)<<(I2C_NONFIFO_RX_THRES_S))
#define I2C_NONFIFO_RX_THRES_V 0x3F
#define I2C_NONFIFO_RX_THRES_S 14
/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: Set this bit to reset tx fifo when using apb fifo access.*/
#define I2C_TX_FIFO_RST (BIT(13))
#define I2C_TX_FIFO_RST_M (BIT(13))
#define I2C_TX_FIFO_RST_V 0x1
#define I2C_TX_FIFO_RST_S 13
/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: Set this bit to reset rx fifo when using apb fifo access.*/
#define I2C_RX_FIFO_RST (BIT(12))
#define I2C_RX_FIFO_RST_M (BIT(12))
#define I2C_RX_FIFO_RST_V 0x1
#define I2C_RX_FIFO_RST_S 12
/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: When this bit is set to 1 then the byte after address represent
the offset address of I2C Slave's ram.*/
#define I2C_FIFO_ADDR_CFG_EN (BIT(11))
#define I2C_FIFO_ADDR_CFG_EN_M (BIT(11))
#define I2C_FIFO_ADDR_CFG_EN_V 0x1
#define I2C_FIFO_ADDR_CFG_EN_S 11
/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: Set this bit to enble apb nonfifo access.*/
#define I2C_NONFIFO_EN (BIT(10))
#define I2C_NONFIFO_EN_M (BIT(10))
#define I2C_NONFIFO_EN_V 0x1
#define I2C_NONFIFO_EN_S 10
/* I2C_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */
/*description: Config txfifo empty threhd value when using apb fifo access*/
#define I2C_TXFIFO_EMPTY_THRHD 0x0000001F
#define I2C_TXFIFO_EMPTY_THRHD_M ((I2C_TXFIFO_EMPTY_THRHD_V)<<(I2C_TXFIFO_EMPTY_THRHD_S))
#define I2C_TXFIFO_EMPTY_THRHD_V 0x1F
#define I2C_TXFIFO_EMPTY_THRHD_S 5
/* I2C_RXFIFO_FULL_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */
/*description: */
#define I2C_RXFIFO_FULL_THRHD 0x0000001F
#define I2C_RXFIFO_FULL_THRHD_M ((I2C_RXFIFO_FULL_THRHD_V)<<(I2C_RXFIFO_FULL_THRHD_S))
#define I2C_RXFIFO_FULL_THRHD_V 0x1F
#define I2C_RXFIFO_FULL_THRHD_S 0
#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x001c)
/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */
/*description: The register represent the byte data read from rxfifo when use apb fifo access*/
#define I2C_FIFO_RDATA 0x000000FF
#define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S))
#define I2C_FIFO_RDATA_V 0xFF
#define I2C_FIFO_RDATA_S 0
#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x0020)
/* I2C_TX_SEND_EMPTY_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for tx_send_empty_int interrupt.when
I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/
#define I2C_TX_SEND_EMPTY_INT_RAW (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_RAW_M (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_RAW_V 0x1
#define I2C_TX_SEND_EMPTY_INT_RAW_S 12
/* I2C_RX_REC_FULL_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for rx_rec_full_int interrupt. when
I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/
#define I2C_RX_REC_FULL_INT_RAW (BIT(11))
#define I2C_RX_REC_FULL_INT_RAW_M (BIT(11))
#define I2C_RX_REC_FULL_INT_RAW_V 0x1
#define I2C_RX_REC_FULL_INT_RAW_S 11
/* I2C_ACK_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for ack_err_int interrupt. when
I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/
#define I2C_ACK_ERR_INT_RAW (BIT(10))
#define I2C_ACK_ERR_INT_RAW_M (BIT(10))
#define I2C_ACK_ERR_INT_RAW_V 0x1
#define I2C_ACK_ERR_INT_RAW_S 10
/* I2C_TRANS_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for trans_start_int interrupt. when
I2C sends the START bit it will produce trans_start_int interrupt.*/
#define I2C_TRANS_START_INT_RAW (BIT(9))
#define I2C_TRANS_START_INT_RAW_M (BIT(9))
#define I2C_TRANS_START_INT_RAW_V 0x1
#define I2C_TRANS_START_INT_RAW_S 9
/* I2C_TIME_OUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for time_out_int interrupt. when
I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/
#define I2C_TIME_OUT_INT_RAW (BIT(8))
#define I2C_TIME_OUT_INT_RAW_M (BIT(8))
#define I2C_TIME_OUT_INT_RAW_V 0x1
#define I2C_TIME_OUT_INT_RAW_S 8
/* I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for trans_complete_int interrupt.
when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/
#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7))
#define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7))
#define I2C_TRANS_COMPLETE_INT_RAW_V 0x1
#define I2C_TRANS_COMPLETE_INT_RAW_S 7
/* I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for master_tra_comp_int interrupt.
when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/
#define I2C_MASTER_TRAN_COMP_INT_RAW (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1
#define I2C_MASTER_TRAN_COMP_INT_RAW_S 6
/* I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for arbitration_lost_int interrupt.when
I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/
#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5))
#define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5))
#define I2C_ARBITRATION_LOST_INT_RAW_V 0x1
#define I2C_ARBITRATION_LOST_INT_RAW_S 5
/* I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for slave_tran_comp_int interrupt.
when I2C Slave detectsthe STOP bit it will produce slave_tran_comp_int interrupt.*/
#define I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1
#define I2C_SLAVE_TRAN_COMP_INT_RAW_S 4
/* I2C_END_DETECT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for end_detect_int interrupt. when
I2C deals with the END command it will produce end_detect_int interrupt.*/
#define I2C_END_DETECT_INT_RAW (BIT(3))
#define I2C_END_DETECT_INT_RAW_M (BIT(3))
#define I2C_END_DETECT_INT_RAW_V 0x1
#define I2C_END_DETECT_INT_RAW_S 3
/* I2C_RXFIFO_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for receiving data overflow when
use apb fifo access.*/
#define I2C_RXFIFO_OVF_INT_RAW (BIT(2))
#define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2))
#define I2C_RXFIFO_OVF_INT_RAW_V 0x1
#define I2C_RXFIFO_OVF_INT_RAW_S 2
/* I2C_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for txfifo empty when use apb fifo access.*/
#define I2C_TXFIFO_EMPTY_INT_RAW (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_RAW_M (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_RAW_V 0x1
#define I2C_TXFIFO_EMPTY_INT_RAW_S 1
/* I2C_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for rxfifo full when use apb fifo access.*/
#define I2C_RXFIFO_FULL_INT_RAW (BIT(0))
#define I2C_RXFIFO_FULL_INT_RAW_M (BIT(0))
#define I2C_RXFIFO_FULL_INT_RAW_V 0x1
#define I2C_RXFIFO_FULL_INT_RAW_S 0
#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x0024)
/* I2C_TX_SEND_EMPTY_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
/*description: Set this bit to clear the tx_send_empty_int interrupt.*/
#define I2C_TX_SEND_EMPTY_INT_CLR (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_CLR_M (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_CLR_V 0x1
#define I2C_TX_SEND_EMPTY_INT_CLR_S 12
/* I2C_RX_REC_FULL_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
/*description: Set this bit to clear the rx_rec_full_int interrupt.*/
#define I2C_RX_REC_FULL_INT_CLR (BIT(11))
#define I2C_RX_REC_FULL_INT_CLR_M (BIT(11))
#define I2C_RX_REC_FULL_INT_CLR_V 0x1
#define I2C_RX_REC_FULL_INT_CLR_S 11
/* I2C_ACK_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
/*description: Set this bit to clear the ack_err_int interrupt.*/
#define I2C_ACK_ERR_INT_CLR (BIT(10))
#define I2C_ACK_ERR_INT_CLR_M (BIT(10))
#define I2C_ACK_ERR_INT_CLR_V 0x1
#define I2C_ACK_ERR_INT_CLR_S 10
/* I2C_TRANS_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
/*description: Set this bit to clear the trans_start_int interrupt.*/
#define I2C_TRANS_START_INT_CLR (BIT(9))
#define I2C_TRANS_START_INT_CLR_M (BIT(9))
#define I2C_TRANS_START_INT_CLR_V 0x1
#define I2C_TRANS_START_INT_CLR_S 9
/* I2C_TIME_OUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
/*description: Set this bit to clear the time_out_int interrupt.*/
#define I2C_TIME_OUT_INT_CLR (BIT(8))
#define I2C_TIME_OUT_INT_CLR_M (BIT(8))
#define I2C_TIME_OUT_INT_CLR_V 0x1
#define I2C_TIME_OUT_INT_CLR_S 8
/* I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
/*description: Set this bit to clear the trans_complete_int interrupt.*/
#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7))
#define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7))
#define I2C_TRANS_COMPLETE_INT_CLR_V 0x1
#define I2C_TRANS_COMPLETE_INT_CLR_S 7
/* I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
/*description: Set this bit to clear the master_tran_comp interrupt.*/
#define I2C_MASTER_TRAN_COMP_INT_CLR (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1
#define I2C_MASTER_TRAN_COMP_INT_CLR_S 6
/* I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
/*description: Set this bit to clear the arbitration_lost_int interrupt.*/
#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5))
#define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5))
#define I2C_ARBITRATION_LOST_INT_CLR_V 0x1
#define I2C_ARBITRATION_LOST_INT_CLR_S 5
/* I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
/*description: Set this bit to clear the slave_tran_comp_int interrupt.*/
#define I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1
#define I2C_SLAVE_TRAN_COMP_INT_CLR_S 4
/* I2C_END_DETECT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
/*description: Set this bit to clear the end_detect_int interrupt.*/
#define I2C_END_DETECT_INT_CLR (BIT(3))
#define I2C_END_DETECT_INT_CLR_M (BIT(3))
#define I2C_END_DETECT_INT_CLR_V 0x1
#define I2C_END_DETECT_INT_CLR_S 3
/* I2C_RXFIFO_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set this bit to clear the rxfifo_ovf_int interrupt.*/
#define I2C_RXFIFO_OVF_INT_CLR (BIT(2))
#define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2))
#define I2C_RXFIFO_OVF_INT_CLR_V 0x1
#define I2C_RXFIFO_OVF_INT_CLR_S 2
/* I2C_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
/*description: Set this bit to clear the txfifo_empty_int interrupt.*/
#define I2C_TXFIFO_EMPTY_INT_CLR (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_CLR_M (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_CLR_V 0x1
#define I2C_TXFIFO_EMPTY_INT_CLR_S 1
/* I2C_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to clear the rxfifo_full_int interrupt.*/
#define I2C_RXFIFO_FULL_INT_CLR (BIT(0))
#define I2C_RXFIFO_FULL_INT_CLR_M (BIT(0))
#define I2C_RXFIFO_FULL_INT_CLR_V 0x1
#define I2C_RXFIFO_FULL_INT_CLR_S 0
#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x0028)
/* I2C_TX_SEND_EMPTY_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: The enable bit for tx_send_empty_int interrupt.*/
#define I2C_TX_SEND_EMPTY_INT_ENA (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_ENA_M (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_ENA_V 0x1
#define I2C_TX_SEND_EMPTY_INT_ENA_S 12
/* I2C_RX_REC_FULL_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: The enable bit for rx_rec_full_int interrupt.*/
#define I2C_RX_REC_FULL_INT_ENA (BIT(11))
#define I2C_RX_REC_FULL_INT_ENA_M (BIT(11))
#define I2C_RX_REC_FULL_INT_ENA_V 0x1
#define I2C_RX_REC_FULL_INT_ENA_S 11
/* I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: The enable bit for ack_err_int interrupt.*/
#define I2C_ACK_ERR_INT_ENA (BIT(10))
#define I2C_ACK_ERR_INT_ENA_M (BIT(10))
#define I2C_ACK_ERR_INT_ENA_V 0x1
#define I2C_ACK_ERR_INT_ENA_S 10
/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: The enable bit for trans_start_int interrupt.*/
#define I2C_TRANS_START_INT_ENA (BIT(9))
#define I2C_TRANS_START_INT_ENA_M (BIT(9))
#define I2C_TRANS_START_INT_ENA_V 0x1
#define I2C_TRANS_START_INT_ENA_S 9
/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: The enable bit for time_out_int interrupt.*/
#define I2C_TIME_OUT_INT_ENA (BIT(8))
#define I2C_TIME_OUT_INT_ENA_M (BIT(8))
#define I2C_TIME_OUT_INT_ENA_V 0x1
#define I2C_TIME_OUT_INT_ENA_S 8
/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: The enable bit for trans_complete_int interrupt.*/
#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7))
#define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7))
#define I2C_TRANS_COMPLETE_INT_ENA_V 0x1
#define I2C_TRANS_COMPLETE_INT_ENA_S 7
/* I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: The enable bit for master_tran_comp_int interrupt.*/
#define I2C_MASTER_TRAN_COMP_INT_ENA (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1
#define I2C_MASTER_TRAN_COMP_INT_ENA_S 6
/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: The enable bit for arbitration_lost_int interrupt.*/
#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5))
#define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5))
#define I2C_ARBITRATION_LOST_INT_ENA_V 0x1
#define I2C_ARBITRATION_LOST_INT_ENA_S 5
/* I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The enable bit for slave_tran_comp_int interrupt.*/
#define I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1
#define I2C_SLAVE_TRAN_COMP_INT_ENA_S 4
/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: The enable bit for end_detect_int interrupt.*/
#define I2C_END_DETECT_INT_ENA (BIT(3))
#define I2C_END_DETECT_INT_ENA_M (BIT(3))
#define I2C_END_DETECT_INT_ENA_V 0x1
#define I2C_END_DETECT_INT_ENA_S 3
/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: The enable bit for rxfifo_ovf_int interrupt.*/
#define I2C_RXFIFO_OVF_INT_ENA (BIT(2))
#define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2))
#define I2C_RXFIFO_OVF_INT_ENA_V 0x1
#define I2C_RXFIFO_OVF_INT_ENA_S 2
/* I2C_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The enable bit for txfifo_empty_int interrupt.*/
#define I2C_TXFIFO_EMPTY_INT_ENA (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_ENA_M (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_ENA_V 0x1
#define I2C_TXFIFO_EMPTY_INT_ENA_S 1
/* I2C_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The enable bit for rxfifo_full_int interrupt.*/
#define I2C_RXFIFO_FULL_INT_ENA (BIT(0))
#define I2C_RXFIFO_FULL_INT_ENA_M (BIT(0))
#define I2C_RXFIFO_FULL_INT_ENA_V 0x1
#define I2C_RXFIFO_FULL_INT_ENA_S 0
#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x002c)
/* I2C_TX_SEND_EMPTY_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
/*description: The masked interrupt status for tx_send_empty_int interrupt.*/
#define I2C_TX_SEND_EMPTY_INT_ST (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_ST_M (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_ST_V 0x1
#define I2C_TX_SEND_EMPTY_INT_ST_S 12
/* I2C_RX_REC_FULL_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
/*description: The masked interrupt status for rx_rec_full_int interrupt.*/
#define I2C_RX_REC_FULL_INT_ST (BIT(11))
#define I2C_RX_REC_FULL_INT_ST_M (BIT(11))
#define I2C_RX_REC_FULL_INT_ST_V 0x1
#define I2C_RX_REC_FULL_INT_ST_S 11
/* I2C_ACK_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: The masked interrupt status for ack_err_int interrupt.*/
#define I2C_ACK_ERR_INT_ST (BIT(10))
#define I2C_ACK_ERR_INT_ST_M (BIT(10))
#define I2C_ACK_ERR_INT_ST_V 0x1
#define I2C_ACK_ERR_INT_ST_S 10
/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: The masked interrupt status for trans_start_int interrupt.*/
#define I2C_TRANS_START_INT_ST (BIT(9))
#define I2C_TRANS_START_INT_ST_M (BIT(9))
#define I2C_TRANS_START_INT_ST_V 0x1
#define I2C_TRANS_START_INT_ST_S 9
/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: The masked interrupt status for time_out_int interrupt.*/
#define I2C_TIME_OUT_INT_ST (BIT(8))
#define I2C_TIME_OUT_INT_ST_M (BIT(8))
#define I2C_TIME_OUT_INT_ST_V 0x1
#define I2C_TIME_OUT_INT_ST_S 8
/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: The masked interrupt status for trans_complete_int interrupt.*/
#define I2C_TRANS_COMPLETE_INT_ST (BIT(7))
#define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7))
#define I2C_TRANS_COMPLETE_INT_ST_V 0x1
#define I2C_TRANS_COMPLETE_INT_ST_S 7
/* I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The masked interrupt status for master_tran_comp_int interrupt.*/
#define I2C_MASTER_TRAN_COMP_INT_ST (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_ST_V 0x1
#define I2C_MASTER_TRAN_COMP_INT_ST_S 6
/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: The masked interrupt status for arbitration_lost_int interrupt.*/
#define I2C_ARBITRATION_LOST_INT_ST (BIT(5))
#define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5))
#define I2C_ARBITRATION_LOST_INT_ST_V 0x1
#define I2C_ARBITRATION_LOST_INT_ST_S 5
/* I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: The masked interrupt status for slave_tran_comp_int interrupt.*/
#define I2C_SLAVE_TRAN_COMP_INT_ST (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1
#define I2C_SLAVE_TRAN_COMP_INT_ST_S 4
/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The masked interrupt status for end_detect_int interrupt.*/
#define I2C_END_DETECT_INT_ST (BIT(3))
#define I2C_END_DETECT_INT_ST_M (BIT(3))
#define I2C_END_DETECT_INT_ST_V 0x1
#define I2C_END_DETECT_INT_ST_S 3
/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: The masked interrupt status for rxfifo_ovf_int interrupt.*/
#define I2C_RXFIFO_OVF_INT_ST (BIT(2))
#define I2C_RXFIFO_OVF_INT_ST_M (BIT(2))
#define I2C_RXFIFO_OVF_INT_ST_V 0x1
#define I2C_RXFIFO_OVF_INT_ST_S 2
/* I2C_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: The masked interrupt status for txfifo_empty_int interrupt.*/
#define I2C_TXFIFO_EMPTY_INT_ST (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_ST_M (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_ST_V 0x1
#define I2C_TXFIFO_EMPTY_INT_ST_S 1
/* I2C_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The masked interrupt status for rxfifo_full_int interrupt.*/
#define I2C_RXFIFO_FULL_INT_ST (BIT(0))
#define I2C_RXFIFO_FULL_INT_ST_M (BIT(0))
#define I2C_RXFIFO_FULL_INT_ST_V 0x1
#define I2C_RXFIFO_FULL_INT_ST_S 0
#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0030)
/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
/*description: This register is used to configure the clock num I2C used to
hold the data after the negedge of SCL.*/
#define I2C_SDA_HOLD_TIME 0x000003FF
#define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S))
#define I2C_SDA_HOLD_TIME_V 0x3FF
#define I2C_SDA_HOLD_TIME_S 0
#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x0034)
/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
/*description: This register is used to configure the clock num I2C used to
sample data on SDA after the posedge of SCL*/
#define I2C_SDA_SAMPLE_TIME 0x000003FF
#define I2C_SDA_SAMPLE_TIME_M ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S))
#define I2C_SDA_SAMPLE_TIME_V 0x3FF
#define I2C_SDA_SAMPLE_TIME_S 0
#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0038)
/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This register is used to configure the clock num during SCL is low level.*/
#define I2C_SCL_HIGH_PERIOD 0x00003FFF
#define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S))
#define I2C_SCL_HIGH_PERIOD_V 0x3FFF
#define I2C_SCL_HIGH_PERIOD_S 0
#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0040)
/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */
/*description: This register is used to configure the clock num between the
negedge of SDA and negedge of SCL for start mark.*/
#define I2C_SCL_START_HOLD_TIME 0x000003FF
#define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S))
#define I2C_SCL_START_HOLD_TIME_V 0x3FF
#define I2C_SCL_START_HOLD_TIME_S 0
#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x0044)
/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */
/*description: This register is used to configure the clock num between the
posedge of SCL and the negedge of SDA for restart mark.*/
#define I2C_SCL_RSTART_SETUP_TIME 0x000003FF
#define I2C_SCL_RSTART_SETUP_TIME_M ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S))
#define I2C_SCL_RSTART_SETUP_TIME_V 0x3FF
#define I2C_SCL_RSTART_SETUP_TIME_S 0
#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0048)
/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This register is used to configure the clock num after the STOP bit's posedge.*/
#define I2C_SCL_STOP_HOLD_TIME 0x00003FFF
#define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S))
#define I2C_SCL_STOP_HOLD_TIME_V 0x3FFF
#define I2C_SCL_STOP_HOLD_TIME_S 0
#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x004C)
/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
/*description: This register is used to configure the clock num between the
posedge of SCL and the posedge of SDA.*/
#define I2C_SCL_STOP_SETUP_TIME 0x000003FF
#define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S))
#define I2C_SCL_STOP_SETUP_TIME_V 0x3FF
#define I2C_SCL_STOP_SETUP_TIME_S 0
#define I2C_SCL_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0050)
/* I2C_SCL_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: This is the filter enable bit for SCL.*/
#define I2C_SCL_FILTER_EN (BIT(3))
#define I2C_SCL_FILTER_EN_M (BIT(3))
#define I2C_SCL_FILTER_EN_V 0x1
#define I2C_SCL_FILTER_EN_S 3
/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
/*description: When input SCL's pulse width is smaller than this register value
I2C ignores this pulse.*/
#define I2C_SCL_FILTER_THRES 0x00000007
#define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S))
#define I2C_SCL_FILTER_THRES_V 0x7
#define I2C_SCL_FILTER_THRES_S 0
#define I2C_SDA_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0054)
/* I2C_SDA_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: This is the filter enable bit for SDA.*/
#define I2C_SDA_FILTER_EN (BIT(3))
#define I2C_SDA_FILTER_EN_M (BIT(3))
#define I2C_SDA_FILTER_EN_V 0x1
#define I2C_SDA_FILTER_EN_S 3
/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
/*description: When input SCL's pulse width is smaller than this register value
I2C ignores this pulse.*/
#define I2C_SDA_FILTER_THRES 0x00000007
#define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S))
#define I2C_SDA_FILTER_THRES_V 0x7
#define I2C_SDA_FILTER_THRES_S 0
#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x0058)
/* I2C_COMMAND0_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command0 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND0_DONE (BIT(31))
#define I2C_COMMAND0_DONE_M (BIT(31))
#define I2C_COMMAND0_DONE_V 0x1
#define I2C_COMMAND0_DONE_S 31
/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command0. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND0 0x00003FFF
#define I2C_COMMAND0_M ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S))
#define I2C_COMMAND0_V 0x3FFF
#define I2C_COMMAND0_S 0
#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x005C)
/* I2C_COMMAND1_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command1 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND1_DONE (BIT(31))
#define I2C_COMMAND1_DONE_M (BIT(31))
#define I2C_COMMAND1_DONE_V 0x1
#define I2C_COMMAND1_DONE_S 31
/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command1. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND1 0x00003FFF
#define I2C_COMMAND1_M ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S))
#define I2C_COMMAND1_V 0x3FFF
#define I2C_COMMAND1_S 0
#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x0060)
/* I2C_COMMAND2_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command2 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND2_DONE (BIT(31))
#define I2C_COMMAND2_DONE_M (BIT(31))
#define I2C_COMMAND2_DONE_V 0x1
#define I2C_COMMAND2_DONE_S 31
/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command2. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND2 0x00003FFF
#define I2C_COMMAND2_M ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S))
#define I2C_COMMAND2_V 0x3FFF
#define I2C_COMMAND2_S 0
#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x0064)
/* I2C_COMMAND3_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command3 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND3_DONE (BIT(31))
#define I2C_COMMAND3_DONE_M (BIT(31))
#define I2C_COMMAND3_DONE_V 0x1
#define I2C_COMMAND3_DONE_S 31
/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command3. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND3 0x00003FFF
#define I2C_COMMAND3_M ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S))
#define I2C_COMMAND3_V 0x3FFF
#define I2C_COMMAND3_S 0
#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x0068)
/* I2C_COMMAND4_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command4 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND4_DONE (BIT(31))
#define I2C_COMMAND4_DONE_M (BIT(31))
#define I2C_COMMAND4_DONE_V 0x1
#define I2C_COMMAND4_DONE_S 31
/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command4. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND4 0x00003FFF
#define I2C_COMMAND4_M ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S))
#define I2C_COMMAND4_V 0x3FFF
#define I2C_COMMAND4_S 0
#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x006C)
/* I2C_COMMAND5_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command5 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND5_DONE (BIT(31))
#define I2C_COMMAND5_DONE_M (BIT(31))
#define I2C_COMMAND5_DONE_V 0x1
#define I2C_COMMAND5_DONE_S 31
/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command5. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND5 0x00003FFF
#define I2C_COMMAND5_M ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S))
#define I2C_COMMAND5_V 0x3FFF
#define I2C_COMMAND5_S 0
#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x0070)
/* I2C_COMMAND6_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command6 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND6_DONE (BIT(31))
#define I2C_COMMAND6_DONE_M (BIT(31))
#define I2C_COMMAND6_DONE_V 0x1
#define I2C_COMMAND6_DONE_S 31
/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command6. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND6 0x00003FFF
#define I2C_COMMAND6_M ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S))
#define I2C_COMMAND6_V 0x3FFF
#define I2C_COMMAND6_S 0
#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x0074)
/* I2C_COMMAND7_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command7 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND7_DONE (BIT(31))
#define I2C_COMMAND7_DONE_M (BIT(31))
#define I2C_COMMAND7_DONE_V 0x1
#define I2C_COMMAND7_DONE_S 31
/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command7. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND7 0x00003FFF
#define I2C_COMMAND7_M ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S))
#define I2C_COMMAND7_V 0x3FFF
#define I2C_COMMAND7_S 0
#define I2C_COMD8_REG(i) (REG_I2C_BASE(i) + 0x0078)
/* I2C_COMMAND8_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command8 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND8_DONE (BIT(31))
#define I2C_COMMAND8_DONE_M (BIT(31))
#define I2C_COMMAND8_DONE_V 0x1
#define I2C_COMMAND8_DONE_S 31
/* I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command8. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND8 0x00003FFF
#define I2C_COMMAND8_M ((I2C_COMMAND8_V)<<(I2C_COMMAND8_S))
#define I2C_COMMAND8_V 0x3FFF
#define I2C_COMMAND8_S 0
#define I2C_COMD9_REG(i) (REG_I2C_BASE(i) + 0x007C)
/* I2C_COMMAND9_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command9 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND9_DONE (BIT(31))
#define I2C_COMMAND9_DONE_M (BIT(31))
#define I2C_COMMAND9_DONE_V 0x1
#define I2C_COMMAND9_DONE_S 31
/* I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command9. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND9 0x00003FFF
#define I2C_COMMAND9_M ((I2C_COMMAND9_V)<<(I2C_COMMAND9_S))
#define I2C_COMMAND9_V 0x3FFF
#define I2C_COMMAND9_S 0
#define I2C_COMD10_REG(i) (REG_I2C_BASE(i) + 0x0080)
/* I2C_COMMAND10_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command10 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND10_DONE (BIT(31))
#define I2C_COMMAND10_DONE_M (BIT(31))
#define I2C_COMMAND10_DONE_V 0x1
#define I2C_COMMAND10_DONE_S 31
/* I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command10. It consists of three part.
op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND10 0x00003FFF
#define I2C_COMMAND10_M ((I2C_COMMAND10_V)<<(I2C_COMMAND10_S))
#define I2C_COMMAND10_V 0x3FFF
#define I2C_COMMAND10_S 0
#define I2C_COMD11_REG(i) (REG_I2C_BASE(i) + 0x0084)
/* I2C_COMMAND11_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command11 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND11_DONE (BIT(31))
#define I2C_COMMAND11_DONE_M (BIT(31))
#define I2C_COMMAND11_DONE_V 0x1
#define I2C_COMMAND11_DONE_S 31
/* I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command11. It consists of three part.
op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND11 0x00003FFF
#define I2C_COMMAND11_M ((I2C_COMMAND11_V)<<(I2C_COMMAND11_S))
#define I2C_COMMAND11_V 0x3FFF
#define I2C_COMMAND11_S 0
#define I2C_COMD12_REG(i) (REG_I2C_BASE(i) + 0x0088)
/* I2C_COMMAND12_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command12 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND12_DONE (BIT(31))
#define I2C_COMMAND12_DONE_M (BIT(31))
#define I2C_COMMAND12_DONE_V 0x1
#define I2C_COMMAND12_DONE_S 31
/* I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command12. It consists of three part.
op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND12 0x00003FFF
#define I2C_COMMAND12_M ((I2C_COMMAND12_V)<<(I2C_COMMAND12_S))
#define I2C_COMMAND12_V 0x3FFF
#define I2C_COMMAND12_S 0
#define I2C_COMD13_REG(i) (REG_I2C_BASE(i) + 0x008C)
/* I2C_COMMAND13_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command13 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND13_DONE (BIT(31))
#define I2C_COMMAND13_DONE_M (BIT(31))
#define I2C_COMMAND13_DONE_V 0x1
#define I2C_COMMAND13_DONE_S 31
/* I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command13. It consists of three part.
op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND13 0x00003FFF
#define I2C_COMMAND13_M ((I2C_COMMAND13_V)<<(I2C_COMMAND13_S))
#define I2C_COMMAND13_V 0x3FFF
#define I2C_COMMAND13_S 0
#define I2C_COMD14_REG(i) (REG_I2C_BASE(i) + 0x0090)
/* I2C_COMMAND14_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command14 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND14_DONE (BIT(31))
#define I2C_COMMAND14_DONE_M (BIT(31))
#define I2C_COMMAND14_DONE_V 0x1
#define I2C_COMMAND14_DONE_S 31
/* I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command14. It consists of three part.
op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND14 0x00003FFF
#define I2C_COMMAND14_M ((I2C_COMMAND14_V)<<(I2C_COMMAND14_S))
#define I2C_COMMAND14_V 0x3FFF
#define I2C_COMMAND14_S 0
#define I2C_COMD15_REG(i) (REG_I2C_BASE(i) + 0x0094)
/* I2C_COMMAND15_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command15 is done in I2C Master mode this bit changes to high level.*/
#define I2C_COMMAND15_DONE (BIT(31))
#define I2C_COMMAND15_DONE_M (BIT(31))
#define I2C_COMMAND15_DONE_V 0x1
#define I2C_COMMAND15_DONE_S 31
/* I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command15. It consists of three part.
op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
#define I2C_COMMAND15 0x00003FFF
#define I2C_COMMAND15_M ((I2C_COMMAND15_V)<<(I2C_COMMAND15_S))
#define I2C_COMMAND15_V 0x3FFF
#define I2C_COMMAND15_S 0
#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0x00F8)
/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */
/*description: */
#define I2C_DATE 0xFFFFFFFF
#define I2C_DATE_M ((I2C_DATE_V)<<(I2C_DATE_S))
#define I2C_DATE_V 0xFFFFFFFF
#define I2C_DATE_S 0
#define I2C_FIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0100)
#endif /*_SOC_I2C_REG_H_ */

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components/esp32/include/soc/io_mux_reg.h
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#define MCU_SEL 0x7
#define MCU_SEL_S 12
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)

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components/esp32/include/soc/rtc_cntl_reg.h
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components/esp32/include/soc/saradc_reg.h Normal file
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components/esp32/include/soc/soc.h
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#define BIT0 0x00000001
//}}
#define PRO_CPU_NUM (0)
#define APP_CPU_NUM (1)
//Registers Operation {{
#define ETS_UNCACHED_ADDR(addr) (addr)
#define ETS_CACHED_ADDR(addr) (addr)
@ -138,46 +141,47 @@
//}}
#define DR_REG_DPORT_BASE 0x3ff00000
#define DR_REG_UART_BASE 0x3ff40000
#define DR_REG_SPI1_BASE 0x3ff42000
#define DR_REG_SPI0_BASE 0x3ff43000
#define DR_REG_GPIO_BASE 0x3ff44000
#define DR_REG_FE2_BASE 0x3ff45000
#define DR_REG_FE_BASE 0x3ff46000
#define DR_REG_TIMER_BASE 0x3ff47000
#define DR_REG_RTCCNTL_BASE 0x3ff48000
#define DR_REG_RTCIO_BASE 0x3ff48400
#define DR_REG_RTCMEM0_BASE 0x3ff61000
#define DR_REG_RTCMEM1_BASE 0x3ff62000
#define DR_REG_RTCMEM2_BASE 0x3ff63000
#define DR_REG_IO_MUX_BASE 0x3ff49000
#define DR_REG_WDG_BASE 0x3ff4A000
#define DR_REG_HINF_BASE 0x3ff4B000
#define DR_REG_UHCI1_BASE 0x3ff4C000
#define DR_REG_I2C_BASE 0x3ff4E000
#define DR_REG_I2S_BASE 0x3ff4F000
#define DR_REG_I2S1_BASE 0x3ff6D000
#define DR_REG_UART1_BASE 0x3ff50000
#define DR_REG_BT_BASE 0x3ff51000
#define DR_REG_I2C_EXT_BASE 0x3ff53000
#define DR_REG_UHCI0_BASE 0x3ff54000
#define DR_REG_SLCHOST_BASE 0x3ff55000
#define DR_REG_RMT_BASE 0x3ff56000
#define DR_REG_PCNT_BASE 0x3ff57000
#define DR_REG_SLC_BASE 0x3ff58000
#define DR_REG_LEDC_BASE 0x3ff59000
#define DR_REG_EFUSE_BASE 0x3ff5A000
#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000
#define DR_REG_BB_BASE 0x3ff5C000
#define DR_REG_PWM_BASE 0x3ff5E000
#define DR_REG_TIMERS_BASE(i) (0x3ff5F000 + i * (0x1000))
#define DR_REG_GPIO_SD_BASE 0x3ff44f00
//}}
#define REG_SPI_BASE(i) (DR_REG_SPI0_BASE - i*(0x1000))
#define PERIPHS_TIMER_BASEDDR DR_REG_TIMER_BASE
#define DR_REG_UART_BASE 0x3ff40000
#define DR_REG_SPI1_BASE 0x3ff42000
#define DR_REG_SPI0_BASE 0x3ff43000
#define DR_REG_GPIO_BASE 0x3ff44000
#define DR_REG_GPIO_SD_BASE 0x3ff44f00
#define DR_REG_FE2_BASE 0x3ff45000
#define DR_REG_FE_BASE 0x3ff46000
#define DR_REG_RTCCNTL_BASE 0x3ff48000
#define DR_REG_RTCIO_BASE 0x3ff48400
#define DR_REG_SARADC_BASE 0x3ff48800
#define DR_REG_IO_MUX_BASE 0x3ff49000
#define DR_REG_RTCMEM0_BASE 0x3ff61000
#define DR_REG_RTCMEM1_BASE 0x3ff62000
#define DR_REG_RTCMEM2_BASE 0x3ff63000
#define DR_REG_HINF_BASE 0x3ff4B000
#define DR_REG_UHCI1_BASE 0x3ff4C000
#define DR_REG_I2S_BASE 0x3ff4F000
#define DR_REG_UART1_BASE 0x3ff50000
#define DR_REG_BT_BASE 0x3ff51000
#define DR_REG_I2C_EXT_BASE 0x3ff53000
#define DR_REG_UHCI0_BASE 0x3ff54000
#define DR_REG_SLCHOST_BASE 0x3ff55000
#define DR_REG_RMT_BASE 0x3ff56000
#define DR_REG_PCNT_BASE 0x3ff57000
#define DR_REG_SLC_BASE 0x3ff58000
#define DR_REG_LEDC_BASE 0x3ff59000
#define DR_REG_EFUSE_BASE 0x3ff5A000
#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000
#define DR_REG_PWM_BASE 0x3ff5E000
#define DR_REG_TIMERGROUP0_BASE 0x3ff5F000
#define DR_REG_TIMERGROUP1_BASE 0x3ff60000
#define DR_REG_SPI2_BASE 0x3ff64000
#define DR_REG_SPI3_BASE 0x3ff65000
#define DR_REG_I2C1_EXT_BASE 0x3ff67000
#define DR_REG_SDMMC_BASE 0x3ff68000
#define DR_REG_EMAC_BASE 0x3ff69000
#define DR_REG_PWM1_BASE 0x3ff6C000
#define DR_REG_I2S1_BASE 0x3ff6D000
#define DR_REG_UART2_BASE 0x3ff6E000
#define DR_REG_PWM2_BASE 0x3ff6F000
#define DR_REG_PWM3_BASE 0x3ff70000
#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE
//Interrupt hardware source table
@ -302,7 +306,7 @@
#define ETS_SLC_INUM 1
#define ETS_UART0_INUM 5
#define ETS_UART1_INUM 5
//Other interrupt number should be managed by the user
#endif /* _ESP32_SOC_H_ */

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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SPI_REG_H_
#define _SOC_SPI_REG_H_
#include "soc.h"
#define SPI_CMD( i ) (REG_SPI_BASE( i ) + 0x0)
#define SPI_FLASH_READ (BIT(31))
#define SPI_FLASH_WREN (BIT(30))
#define SPI_FLASH_WRDI (BIT(29))
#define SPI_FLASH_RDID (BIT(28))
#define SPI_FLASH_RDSR (BIT(27))
#define SPI_FLASH_WRSR (BIT(26))
#define SPI_FLASH_PP (BIT(25))
#define SPI_FLASH_SE (BIT(24))
#define SPI_FLASH_BE (BIT(23))
#define SPI_FLASH_CE (BIT(22))
#define SPI_FLASH_DP (BIT(21))
#define SPI_FLASH_RES (BIT(20))
#define SPI_FLASH_HPM (BIT(19))
#define SPI_USR (BIT(18))
#define SPI_FLASH_PES (BIT(17))
#define SPI_FLASH_PER (BIT(16))
#define SPI_ADDR( i ) (REG_SPI_BASE( i ) + 0x4)
#define SPI_CTRL( i ) (REG_SPI_BASE( i ) + 0x8)
#define SPI_WR_BIT_ORDER (BIT(26))
#define SPI_RD_BIT_ORDER (BIT(25))
#define SPI_FREAD_QIO (BIT(24))
#define SPI_FREAD_DIO (BIT(23))
#define SPI_WRSR_2B (BIT(22))
#define SPI_WP_REG (BIT(21))
#define SPI_FREAD_QUAD (BIT(20))
#define SPI_RESANDRES (BIT(15))
#define SPI_FREAD_DUAL (BIT(14))
#define SPI_FASTRD_MODE (BIT(13))
#define SPI_WAIT_FLASH_IDLE_EN (BIT(12))
#define SPI_TX_CRC_EN (BIT(11))
#define SPI_FCS_CRC_EN (BIT(10))
#define SPI_CTRL1( i ) (REG_SPI_BASE( i ) + 0xC)
#define SPI_CS_HOLD_DELAY 0x0000000F
#define SPI_CS_HOLD_DELAY_S 28
#define SPI_CS_HOLD_DELAY_RES 0x00000FFF
#define SPI_CS_HOLD_DELAY_RES_S 16
#define SPI_RD_STATUS( i ) (REG_SPI_BASE( i ) + 0x10)
#define SPI_STATUS_EXT 0x000000FF
#define SPI_STATUS_EXT_S 24
#define SPI_WB_MODE 0x000000FF
#define SPI_WB_MODE_S 16
#define SPI_STATUS 0x0000FFFF
#define SPI_STATUS_S 0
#define SPI_CTRL2( i ) (REG_SPI_BASE( i ) + 0x14)
#define SPI_CS_DELAY_NUM 0x0000000F
#define SPI_CS_DELAY_NUM_S 28
#define SPI_CS_DELAY_MODE 0x00000003
#define SPI_CS_DELAY_MODE_S 26
#define SPI_MOSI_DELAY_NUM 0x00000007
#define SPI_MOSI_DELAY_NUM_S 23
#define SPI_MOSI_DELAY_MODE 0x00000003
#define SPI_MOSI_DELAY_MODE_S 21
#define SPI_MISO_DELAY_NUM 0x00000007
#define SPI_MISO_DELAY_NUM_S 18
#define SPI_MISO_DELAY_MODE 0x00000003
#define SPI_MISO_DELAY_MODE_S 16
#define SPI_CK_OUT_HIGH_MODE 0x0000000F
#define SPI_CK_OUT_HIGH_MODE_S 12
#define SPI_CK_OUT_LOW_MODE 0x0000000F
#define SPI_CK_OUT_LOW_MODE_S 8
#define SPI_HOLD_TIME 0x0000000F
#define SPI_HOLD_TIME_S 4
#define SPI_SETUP_TIME 0x0000000F
#define SPI_SETUP_TIME_S 0
#define SPI_CLOCK( i ) (REG_SPI_BASE( i ) + 0x18)
#define SPI_CLK_EQU_SYSCLK (BIT(31))
#define SPI_CLKDIV_PRE 0x00001FFF
#define SPI_CLKDIV_PRE_S 18
#define SPI_CLKCNT_N 0x0000003F
#define SPI_CLKCNT_N_S 12
#define SPI_CLKCNT_H 0x0000003F
#define SPI_CLKCNT_H_S 6
#define SPI_CLKCNT_L 0x0000003F
#define SPI_CLKCNT_L_S 0
#define SPI_USER( i ) (REG_SPI_BASE( i ) + 0x1C)
#define SPI_USR_COMMAND (BIT(31))
#define SPI_USR_ADDR (BIT(30))
#define SPI_USR_DUMMY (BIT(29))
#define SPI_USR_MISO (BIT(28))
#define SPI_USR_MOSI (BIT(27))
#define SPI_USR_DUMMY_IDLE (BIT(26))
#define SPI_USR_MOSI_HIGHPART (BIT(25))
#define SPI_USR_MISO_HIGHPART (BIT(24))
#define SPI_USR_PREP_HOLD (BIT(23))
#define SPI_USR_CMD_HOLD (BIT(22))
#define SPI_USR_ADDR_HOLD (BIT(21))
#define SPI_USR_DUMMY_HOLD (BIT(20))
#define SPI_USR_DIN_HOLD (BIT(19))
#define SPI_USR_DOUT_HOLD (BIT(18))
#define SPI_USR_HOLD_POL (BIT(17))
#define SPI_SIO (BIT(16))
#define SPI_FWRITE_QIO (BIT(15))
#define SPI_FWRITE_DIO (BIT(14))
#define SPI_FWRITE_QUAD (BIT(13))
#define SPI_FWRITE_DUAL (BIT(12))
#define SPI_WR_BYTE_ORDER (BIT(11))
#define SPI_RD_BYTE_ORDER (BIT(10))
#define SPI_CK_OUT_EDGE (BIT(7))
#define SPI_CK_I_EDGE (BIT(6))
#define SPI_CS_SETUP (BIT(5))
#define SPI_CS_HOLD (BIT(4))
#define SPI_DOUTDIN (BIT(0))
#define SPI_USER1( i ) (REG_SPI_BASE( i ) + 0x20)
#define SPI_USR_ADDR_BITLEN 0x0000003F
#define SPI_USR_ADDR_BITLEN_S 26
#define SPI_USR_DUMMY_CYCLELEN 0x000000FF
#define SPI_USR_DUMMY_CYCLELEN_S 0
#define SPI_USER2( i ) (REG_SPI_BASE( i ) + 0x24)
#define SPI_USR_COMMAND_BITLEN 0x0000000F
#define SPI_USR_COMMAND_BITLEN_S 28
#define SPI_USR_COMMAND_VALUE 0x0000FFFF
#define SPI_USR_COMMAND_VALUE_S 0
#define SPI_MOSI_DLEN( i ) (REG_SPI_BASE( i ) + 0x28)
#define SPI_USR_MOSI_DBITLEN 0x00FFFFFF
#define SPI_USR_MOSI_DBITLEN_S 0
#define SPI_MISO_DLEN( i ) (REG_SPI_BASE( i ) + 0x2C)
#define SPI_USR_MISO_DBITLEN 0x00FFFFFF
#define SPI_USR_MISO_DBITLEN_S 0
#define SPI_SLV_WR_STATUS( i ) (REG_SPI_BASE( i ) + 0x30)
#define SPI_PIN( i ) (REG_SPI_BASE( i ) + 0x34)
#define SPI_CS_KEEP_ACTIVE (BIT(30))
#define SPI_CK_IDLE_EDGE (BIT(29))
#define SPI_CSCK_SEL (BIT(19))
#define SPI_MASTER_CK_SEL 0x0000001F
#define SPI_MASTER_CK_SEL_S 11
#define SPI_MASTER_CS_POL 0x0000001F
#define SPI_MASTER_CS_POL_S 6
#define SPI_CK_DIS (BIT(5))
#define SPI_CS2_DIS (BIT(2))
#define SPI_CS1_DIS (BIT(1))
#define SPI_CS0_DIS (BIT(0))
#define SPI_SLAVE( i ) (REG_SPI_BASE( i ) + 0x38)
#define SPI_SYNC_RESET (BIT(31))
#define SPI_SLAVE_MODE (BIT(30))
#define SPI_SLV_WR_RD_BUF_EN (BIT(29))
#define SPI_SLV_WR_RD_STA_EN (BIT(28))
#define SPI_SLV_CMD_DEFINE (BIT(27))
#define SPI_TRANS_CNT 0x0000000F
#define SPI_TRANS_CNT_S 23
#define SPI_SLV_LAST_STATE 0x00000007
#define SPI_SLV_LAST_STATE_S 20
#define SPI_SLV_LAST_COMMAND 0x00000007
#define SPI_SLV_LAST_COMMAND_S 17
#define SPI_CS_I_MODE 0x00000003
#define SPI_CS_I_MODE_S 10
#define SPI_INT_EN 0x0000001F
#define SPI_INT_EN_S 5
#define SPI_TRANS_DONE (BIT(4))
#define SPI_SLV_WR_STA_DONE (BIT(3))
#define SPI_SLV_RD_STA_DONE (BIT(2))
#define SPI_SLV_WR_BUF_DONE (BIT(1))
#define SPI_SLV_RD_BUF_DONE (BIT(0))
#define SPI_SLAVE1( i ) (REG_SPI_BASE( i ) + 0x3C)
#define SPI_SLV_STATUS_BITLEN 0x0000001F
#define SPI_SLV_STATUS_BITLEN_S 27
#define SPI_SLV_STATUS_FAST_EN (BIT(26))
#define SPI_SLV_STATUS_READBACK (BIT(25))
#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F
#define SPI_SLV_RD_ADDR_BITLEN_S 10
#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F
#define SPI_SLV_WR_ADDR_BITLEN_S 4
#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3))
#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2))
#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1))
#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0))
#define SPI_SLAVE2( i ) (REG_SPI_BASE( i ) + 0x40)
#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0x000000FF
#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24
#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0x000000FF
#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16
#define SPI_SLV_WRSTA_DUMMY_CYCLELEN 0x000000FF
#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_S 8
#define SPI_SLV_RDSTA_DUMMY_CYCLELEN 0x000000FF
#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_S 0
#define SPI_SLAVE3( i ) (REG_SPI_BASE( i ) + 0x44)
#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF
#define SPI_SLV_WRSTA_CMD_VALUE_S 24
#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF
#define SPI_SLV_RDSTA_CMD_VALUE_S 16
#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF
#define SPI_SLV_WRBUF_CMD_VALUE_S 8
#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF
#define SPI_SLV_RDBUF_CMD_VALUE_S 0
#define SPI_SLV_WRBUF_DLEN( i ) (REG_SPI_BASE( i ) + 0x48)
#define SPI_SLV_WRBUF_DBITLEN 0x00FFFFFF
#define SPI_SLV_WRBUF_DBITLEN_S 0
#define SPI_SLV_RDBUF_DLEN( i ) (REG_SPI_BASE( i ) + 0x4C)
#define SPI_SLV_RDBUF_DBITLEN 0x00FFFFFF
#define SPI_SLV_RDBUF_DBITLEN_S 0
#define SPI_CACHE_FCTRL( i ) (REG_SPI_BASE( i ) + 0x50)
#define SPI_CACHE_FLASH_PES_EN (BIT(3))
#define SPI_CACHE_FLASH_USR_CMD (BIT(2))
#define SPI_CACHE_USR_CMD_4BYTE (BIT(1))
#define SPI_CACHE_REQ_EN (BIT(0))
#define SPI_CACHE_SCTRL( i ) (REG_SPI_BASE( i ) + 0x54)
#define SPI_CACHE_SRAM_USR_WCMD (BIT(28))
#define SPI_SRAM_ADDR_BITLEN 0x0000003F
#define SPI_SRAM_ADDR_BITLEN_S 22
#define SPI_SRAM_DUMMY_CYCLELEN 0x000000FF
#define SPI_SRAM_DUMMY_CYCLELEN_S 14
#define SPI_SRAM_BYTES_LEN 0x000000FF
#define SPI_SRAM_BYTES_LEN_S 6
#define SPI_CACHE_SRAM_USR_RCMD (BIT(5))
#define SPI_USR_RD_SRAM_DUMMY (BIT(4))
#define SPI_USR_WR_SRAM_DUMMY (BIT(3))
#define SPI_USR_SRAM_QIO (BIT(2))
#define SPI_USR_SRAM_DIO (BIT(1))
#define SPI_SRAM_CMD( i ) (REG_SPI_BASE( i ) + 0x58)
#define SPI_SRAM_RSTIO (BIT(4))
#define SPI_SRAM_QIO (BIT(1))
#define SPI_SRAM_DIO (BIT(0))
#define SPI_SRAM_DRD_CMD( i ) (REG_SPI_BASE( i ) + 0x5C)
#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F
#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28
#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF
#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S 0
#define SPI_SRAM_DWR_CMD( i ) (REG_SPI_BASE( i ) + 0x60)
#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F
#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28
#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF
#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S 0
#define SPI_SLV_RD_BIT( i ) (REG_SPI_BASE( i ) + 0x64)
#define SPI_SLV_RDATA_BIT 0x00FFFFFF
#define SPI_SLV_RDATA_BIT_S 0
#define SPI_W0( i ) (REG_SPI_BASE( i ) + 0x80)
#define SPI_W1( i ) (REG_SPI_BASE( i ) + 0x84)
#define SPI_W2( i ) (REG_SPI_BASE( i ) + 0x88)
#define SPI_W3( i ) (REG_SPI_BASE( i ) + 0x8C)
#define SPI_W4( i ) (REG_SPI_BASE( i ) + 0x90)
#define SPI_W5( i ) (REG_SPI_BASE( i ) + 0x94)
#define SPI_W6( i ) (REG_SPI_BASE( i ) + 0x98)
#define SPI_W7( i ) (REG_SPI_BASE( i ) + 0x9C)
#define SPI_W8( i ) (REG_SPI_BASE( i ) + 0xA0)
#define SPI_W9( i ) (REG_SPI_BASE( i ) + 0xA4)
#define SPI_W10( i ) (REG_SPI_BASE( i ) + 0xA8)
#define SPI_W11( i ) (REG_SPI_BASE( i ) + 0xAC)
#define SPI_W12( i ) (REG_SPI_BASE( i ) + 0xB0)
#define SPI_W13( i ) (REG_SPI_BASE( i ) + 0xB4)
#define SPI_W14( i ) (REG_SPI_BASE( i ) + 0xB8)
#define SPI_W15( i ) (REG_SPI_BASE( i ) + 0xBC)
#define SPI_TX_CRC( i ) (REG_SPI_BASE( i ) + 0xC0)
#define SPI_EXT0( i ) (REG_SPI_BASE( i ) + 0xF0)
#define SPI_T_PP_ENA (BIT(31))
#define SPI_T_PP_SHIFT 0x0000000F
#define SPI_T_PP_SHIFT_S 16
#define SPI_T_PP_TIME 0x00000FFF
#define SPI_T_PP_TIME_S 0
#define SPI_EXT1( i ) (REG_SPI_BASE( i ) + 0xF4)
#define SPI_T_ERASE_ENA (BIT(31))
#define SPI_T_ERASE_SHIFT 0x0000000F
#define SPI_T_ERASE_SHIFT_S 16
#define SPI_T_ERASE_TIME 0x00000FFF
#define SPI_T_ERASE_TIME_S 0
#define SPI_EXT2( i ) (REG_SPI_BASE( i ) + 0xF8)
#define SPI_ST 0x00000007
#define SPI_ST_S 0
#define SPI_EXT3( i ) (REG_SPI_BASE( i ) + 0xFC)
#define SPI_INT_HOLD_ENA 0x00000003
#define SPI_INT_HOLD_ENA_S 0
#define SPI_DMA_CONF( i ) (REG_SPI_BASE( i ) + 0x100)
#define SPI_DMA_CONTINUE (BIT(16))
#define SPI_DMA_TX_STOP (BIT(15))
#define SPI_DMA_RX_STOP (BIT(14))
#define SPI_OUT_DATA_BURST_EN (BIT(12))
#define SPI_INDSCR_BURST_EN (BIT(11))
#define SPI_OUTDSCR_BURST_EN (BIT(10))
#define SPI_OUT_EOF_MODE (BIT(9))
#define SPI_OUT_AUTO_WRBACK (BIT(8))
#define SPI_OUT_LOOP_TEST (BIT(7))
#define SPI_IN_LOOP_TEST (BIT(6))
#define SPI_AHBM_RST (BIT(5))
#define SPI_AHBM_FIFO_RST (BIT(4))
#define SPI_OUT_RST (BIT(3))
#define SPI_IN_RST (BIT(2))
#define SPI_DMA_OUT_LINK( i ) (REG_SPI_BASE( i ) + 0x104)
#define SPI_OUTLINK_RESTART (BIT(30))
#define SPI_OUTLINK_START (BIT(29))
#define SPI_OUTLINK_STOP (BIT(28))
#define SPI_OUTLINK_ADDR 0x000FFFFF
#define SPI_OUTLINK_ADDR_S 0
#define SPI_DMA_IN_LINK( i ) (REG_SPI_BASE( i ) + 0x108)
#define SPI_INLINK_RESTART (BIT(30))
#define SPI_INLINK_START (BIT(29))
#define SPI_INLINK_STOP (BIT(28))
#define SPI_INLINK_AUTO_RET (BIT(20))
#define SPI_INLINK_ADDR 0x000FFFFF
#define SPI_INLINK_ADDR_S 0
#define SPI_DMA_STATUS( i ) (REG_SPI_BASE( i ) + 0x10C)
#define SPI_DMA_TX_EN (BIT(1))
#define SPI_DMA_RX_EN (BIT(0))
#define SPI_DMA_INT_ENA( i ) (REG_SPI_BASE( i ) + 0x110)
#define SPI_OUT_TOTAL_EOF_INT_ENA (BIT(8))
#define SPI_OUT_EOF_INT_ENA (BIT(7))
#define SPI_OUT_DONE_INT_ENA (BIT(6))
#define SPI_IN_SUC_EOF_INT_ENA (BIT(5))
#define SPI_IN_ERR_EOF_INT_ENA (BIT(4))
#define SPI_IN_DONE_INT_ENA (BIT(3))
#define SPI_INLINK_DSCR_ERROR_INT_ENA (BIT(2))
#define SPI_OUTLINK_DSCR_ERROR_INT_ENA (BIT(1))
#define SPI_INLINK_DSCR_EMPTY_INT_ENA (BIT(0))
#define SPI_DMA_INT_RAW( i ) (REG_SPI_BASE( i ) + 0x114)
#define SPI_OUT_TOTAL_EOF_INT_RAW (BIT(8))
#define SPI_OUT_EOF_INT_RAW (BIT(7))
#define SPI_OUT_DONE_INT_RAW (BIT(6))
#define SPI_IN_SUC_EOF_INT_RAW (BIT(5))
#define SPI_IN_ERR_EOF_INT_RAW (BIT(4))
#define SPI_IN_DONE_INT_RAW (BIT(3))
#define SPI_INLINK_DSCR_ERROR_INT_RAW (BIT(2))
#define SPI_OUTLINK_DSCR_ERROR_INT_RAW (BIT(1))
#define SPI_INLINK_DSCR_EMPTY_INT_RAW (BIT(0))
#define SPI_DMA_INT_ST( i ) (REG_SPI_BASE( i ) + 0x118)
#define SPI_OUT_TOTAL_EOF_INT_ST (BIT(8))
#define SPI_OUT_EOF_INT_ST (BIT(7))
#define SPI_OUT_DONE_INT_ST (BIT(6))
#define SPI_IN_SUC_EOF_INT_ST (BIT(5))
#define SPI_IN_ERR_EOF_INT_ST (BIT(4))
#define SPI_IN_DONE_INT_ST (BIT(3))
#define SPI_INLINK_DSCR_ERROR_INT_ST (BIT(2))
#define SPI_OUTLINK_DSCR_ERROR_INT_ST (BIT(1))
#define SPI_INLINK_DSCR_EMPTY_INT_ST (BIT(0))
#define SPI_DMA_INT_CLR( i ) (REG_SPI_BASE( i ) + 0x11C)
#define SPI_OUT_TOTAL_EOF_INT_CLR (BIT(8))
#define SPI_OUT_EOF_INT_CLR (BIT(7))
#define SPI_OUT_DONE_INT_CLR (BIT(6))
#define SPI_IN_SUC_EOF_INT_CLR (BIT(5))
#define SPI_IN_ERR_EOF_INT_CLR (BIT(4))
#define SPI_IN_DONE_INT_CLR (BIT(3))
#define SPI_INLINK_DSCR_ERROR_INT_CLR (BIT(2))
#define SPI_OUTLINK_DSCR_ERROR_INT_CLR (BIT(1))
#define SPI_INLINK_DSCR_EMPTY_INT_CLR (BIT(0))
#define SPI_IN_ERR_EOF_DES_ADDR( i ) (REG_SPI_BASE( i ) + 0x120)
#define SPI_IN_SUC_EOF_DES_ADDR( i ) (REG_SPI_BASE( i ) + 0x124)
#define SPI_INLINK_DSCR( i ) (REG_SPI_BASE( i ) + 0x128)
#define SPI_INLINK_DSCR_BF0( i ) (REG_SPI_BASE( i ) + 0x12C)
#define SPI_INLINK_DSCR_BF1( i ) (REG_SPI_BASE( i ) + 0x130)
#define SPI_OUT_EOF_BFR_DES_ADDR( i ) (REG_SPI_BASE( i ) + 0x134)
#define SPI_OUT_EOF_DES_ADDR( i ) (REG_SPI_BASE( i ) + 0x138)
#define SPI_OUTLINK_DSCR( i ) (REG_SPI_BASE( i ) + 0x13C)
#define SPI_OUTLINK_DSCR_BF0( i ) (REG_SPI_BASE( i ) + 0x140)
#define SPI_OUTLINK_DSCR_BF1( i ) (REG_SPI_BASE( i ) + 0x144)
#define SPI_DMA_RSTATUS( i ) (REG_SPI_BASE( i ) + 0x148)
#define SPI_DMA_TSTATUS( i ) (REG_SPI_BASE( i ) + 0x14C)
#define SPI_REG_DATE( i ) (REG_SPI_BASE( i ) + 0x3FC)
#define SPI_DATE 0x0FFFFFFF
#define SPI_DATE_S 0
#define SPI_DATE_VERSION 0x1604290
#endif /* _SOC_SPI_REG_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __TIMG_REG_H__
#define __TIMG_REG_H__
#include "soc.h"
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + i*0x1000)
#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000)
/* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: When set timer 0 time-base counter is enabled*/
#define TIMG_T0_EN (BIT(31))
#define TIMG_T0_EN_M (BIT(31))
#define TIMG_T0_EN_V 0x1
#define TIMG_T0_EN_S 31
/* TIMG_T0_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
/*description: When set timer 0 time-base counter increment. When cleared timer
0 time-base counter decrement.*/
#define TIMG_T0_INCREASE (BIT(30))
#define TIMG_T0_INCREASE_M (BIT(30))
#define TIMG_T0_INCREASE_V 0x1
#define TIMG_T0_INCREASE_S 30
/* TIMG_T0_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
/*description: When set timer 0 auto-reload at alarming is enabled*/
#define TIMG_T0_AUTORELOAD (BIT(29))
#define TIMG_T0_AUTORELOAD_M (BIT(29))
#define TIMG_T0_AUTORELOAD_V 0x1
#define TIMG_T0_AUTORELOAD_S 29
/* TIMG_T0_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
/*description: Timer 0 clock (T0_clk) prescale value.*/
#define TIMG_T0_DIVIDER 0x0000FFFF
#define TIMG_T0_DIVIDER_M ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S))
#define TIMG_T0_DIVIDER_V 0xFFFF
#define TIMG_T0_DIVIDER_S 13
/* TIMG_T0_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
/*description: When set edge type interrupt will be generated during alarm*/
#define TIMG_T0_EDGE_INT_EN (BIT(12))
#define TIMG_T0_EDGE_INT_EN_M (BIT(12))
#define TIMG_T0_EDGE_INT_EN_V 0x1
#define TIMG_T0_EDGE_INT_EN_S 12
/* TIMG_T0_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */
/*description: When set level type interrupt will be generated during alarm*/
#define TIMG_T0_LEVEL_INT_EN (BIT(11))
#define TIMG_T0_LEVEL_INT_EN_M (BIT(11))
#define TIMG_T0_LEVEL_INT_EN_V 0x1
#define TIMG_T0_LEVEL_INT_EN_S 11
/* TIMG_T0_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */
/*description: When set alarm is enabled*/
#define TIMG_T0_ALARM_EN (BIT(10))
#define TIMG_T0_ALARM_EN_M (BIT(10))
#define TIMG_T0_ALARM_EN_V 0x1
#define TIMG_T0_ALARM_EN_S 10
#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x0004)
/* TIMG_T0_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Register to store timer 0 time-base counter current value lower 32 bits.*/
#define TIMG_T0_LO 0xFFFFFFFF
#define TIMG_T0_LO_M ((TIMG_T0_LO_V)<<(TIMG_T0_LO_S))
#define TIMG_T0_LO_V 0xFFFFFFFF
#define TIMG_T0_LO_S 0
#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x0008)
/* TIMG_T0_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Register to store timer 0 time-base counter current value higher 32 bits.*/
#define TIMG_T0_HI 0xFFFFFFFF
#define TIMG_T0_HI_M ((TIMG_T0_HI_V)<<(TIMG_T0_HI_S))
#define TIMG_T0_HI_V 0xFFFFFFFF
#define TIMG_T0_HI_S 0
#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x000c)
/* TIMG_T0_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Write any value will trigger a timer 0 time-base counter value
update (timer 0 current value will be stored in registers above)*/
#define TIMG_T0_UPDATE 0xFFFFFFFF
#define TIMG_T0_UPDATE_M ((TIMG_T0_UPDATE_V)<<(TIMG_T0_UPDATE_S))
#define TIMG_T0_UPDATE_V 0xFFFFFFFF
#define TIMG_T0_UPDATE_S 0
#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0010)
/* TIMG_T0_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/
#define TIMG_T0_ALARM_LO 0xFFFFFFFF
#define TIMG_T0_ALARM_LO_M ((TIMG_T0_ALARM_LO_V)<<(TIMG_T0_ALARM_LO_S))
#define TIMG_T0_ALARM_LO_V 0xFFFFFFFF
#define TIMG_T0_ALARM_LO_S 0
#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0014)
/* TIMG_T0_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/
#define TIMG_T0_ALARM_HI 0xFFFFFFFF
#define TIMG_T0_ALARM_HI_M ((TIMG_T0_ALARM_HI_V)<<(TIMG_T0_ALARM_HI_S))
#define TIMG_T0_ALARM_HI_V 0xFFFFFFFF
#define TIMG_T0_ALARM_HI_S 0
#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x0018)
/* TIMG_T0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Lower 32 bits of the value that will load into timer 0 time-base counter*/
#define TIMG_T0_LOAD_LO 0xFFFFFFFF
#define TIMG_T0_LOAD_LO_M ((TIMG_T0_LOAD_LO_V)<<(TIMG_T0_LOAD_LO_S))
#define TIMG_T0_LOAD_LO_V 0xFFFFFFFF
#define TIMG_T0_LOAD_LO_S 0
#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x001c)
/* TIMG_T0_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: higher 32 bits of the value that will load into timer 0 time-base counter*/
#define TIMG_T0_LOAD_HI 0xFFFFFFFF
#define TIMG_T0_LOAD_HI_M ((TIMG_T0_LOAD_HI_V)<<(TIMG_T0_LOAD_HI_S))
#define TIMG_T0_LOAD_HI_V 0xFFFFFFFF
#define TIMG_T0_LOAD_HI_S 0
#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0020)
/* TIMG_T0_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Write any value will trigger timer 0 time-base counter reload*/
#define TIMG_T0_LOAD 0xFFFFFFFF
#define TIMG_T0_LOAD_M ((TIMG_T0_LOAD_V)<<(TIMG_T0_LOAD_S))
#define TIMG_T0_LOAD_V 0xFFFFFFFF
#define TIMG_T0_LOAD_S 0
#define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0024)
/* TIMG_T1_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: When set timer 1 time-base counter is enabled*/
#define TIMG_T1_EN (BIT(31))
#define TIMG_T1_EN_M (BIT(31))
#define TIMG_T1_EN_V 0x1
#define TIMG_T1_EN_S 31
/* TIMG_T1_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
/*description: When set timer 1 time-base counter increment. When cleared timer
1 time-base counter decrement.*/
#define TIMG_T1_INCREASE (BIT(30))
#define TIMG_T1_INCREASE_M (BIT(30))
#define TIMG_T1_INCREASE_V 0x1
#define TIMG_T1_INCREASE_S 30
/* TIMG_T1_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
/*description: When set timer 1 auto-reload at alarming is enabled*/
#define TIMG_T1_AUTORELOAD (BIT(29))
#define TIMG_T1_AUTORELOAD_M (BIT(29))
#define TIMG_T1_AUTORELOAD_V 0x1
#define TIMG_T1_AUTORELOAD_S 29
/* TIMG_T1_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
/*description: Timer 1 clock (T1_clk) prescale value.*/
#define TIMG_T1_DIVIDER 0x0000FFFF
#define TIMG_T1_DIVIDER_M ((TIMG_T1_DIVIDER_V)<<(TIMG_T1_DIVIDER_S))
#define TIMG_T1_DIVIDER_V 0xFFFF
#define TIMG_T1_DIVIDER_S 13
/* TIMG_T1_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
/*description: When set edge type interrupt will be generated during alarm*/
#define TIMG_T1_EDGE_INT_EN (BIT(12))
#define TIMG_T1_EDGE_INT_EN_M (BIT(12))
#define TIMG_T1_EDGE_INT_EN_V 0x1
#define TIMG_T1_EDGE_INT_EN_S 12
/* TIMG_T1_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */
/*description: When set level type interrupt will be generated during alarm*/
#define TIMG_T1_LEVEL_INT_EN (BIT(11))
#define TIMG_T1_LEVEL_INT_EN_M (BIT(11))
#define TIMG_T1_LEVEL_INT_EN_V 0x1
#define TIMG_T1_LEVEL_INT_EN_S 11
/* TIMG_T1_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */
/*description: When set alarm is enabled*/
#define TIMG_T1_ALARM_EN (BIT(10))
#define TIMG_T1_ALARM_EN_M (BIT(10))
#define TIMG_T1_ALARM_EN_V 0x1
#define TIMG_T1_ALARM_EN_S 10
#define TIMG_T1LO_REG(i) (REG_TIMG_BASE(i) + 0x0028)
/* TIMG_T1_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Register to store timer 1 time-base counter current value lower 32 bits.*/
#define TIMG_T1_LO 0xFFFFFFFF
#define TIMG_T1_LO_M ((TIMG_T1_LO_V)<<(TIMG_T1_LO_S))
#define TIMG_T1_LO_V 0xFFFFFFFF
#define TIMG_T1_LO_S 0
#define TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x002c)
/* TIMG_T1_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Register to store timer 1 time-base counter current value higher 32 bits.*/
#define TIMG_T1_HI 0xFFFFFFFF
#define TIMG_T1_HI_M ((TIMG_T1_HI_V)<<(TIMG_T1_HI_S))
#define TIMG_T1_HI_V 0xFFFFFFFF
#define TIMG_T1_HI_S 0
#define TIMG_T1UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x0030)
/* TIMG_T1_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Write any value will trigger a timer 1 time-base counter value
update (timer 1 current value will be stored in registers above)*/
#define TIMG_T1_UPDATE 0xFFFFFFFF
#define TIMG_T1_UPDATE_M ((TIMG_T1_UPDATE_V)<<(TIMG_T1_UPDATE_S))
#define TIMG_T1_UPDATE_V 0xFFFFFFFF
#define TIMG_T1_UPDATE_S 0
#define TIMG_T1ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0034)
/* TIMG_T1_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Timer 1 time-base counter value lower 32 bits that will trigger the alarm*/
#define TIMG_T1_ALARM_LO 0xFFFFFFFF
#define TIMG_T1_ALARM_LO_M ((TIMG_T1_ALARM_LO_V)<<(TIMG_T1_ALARM_LO_S))
#define TIMG_T1_ALARM_LO_V 0xFFFFFFFF
#define TIMG_T1_ALARM_LO_S 0
#define TIMG_T1ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0038)
/* TIMG_T1_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Timer 1 time-base counter value higher 32 bits that will trigger the alarm*/
#define TIMG_T1_ALARM_HI 0xFFFFFFFF
#define TIMG_T1_ALARM_HI_M ((TIMG_T1_ALARM_HI_V)<<(TIMG_T1_ALARM_HI_S))
#define TIMG_T1_ALARM_HI_V 0xFFFFFFFF
#define TIMG_T1_ALARM_HI_S 0
#define TIMG_T1LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x003c)
/* TIMG_T1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Lower 32 bits of the value that will load into timer 1 time-base counter*/
#define TIMG_T1_LOAD_LO 0xFFFFFFFF
#define TIMG_T1_LOAD_LO_M ((TIMG_T1_LOAD_LO_V)<<(TIMG_T1_LOAD_LO_S))
#define TIMG_T1_LOAD_LO_V 0xFFFFFFFF
#define TIMG_T1_LOAD_LO_S 0
#define TIMG_T1LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x0040)
/* TIMG_T1_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: higher 32 bits of the value that will load into timer 1 time-base counter*/
#define TIMG_T1_LOAD_HI 0xFFFFFFFF
#define TIMG_T1_LOAD_HI_M ((TIMG_T1_LOAD_HI_V)<<(TIMG_T1_LOAD_HI_S))
#define TIMG_T1_LOAD_HI_V 0xFFFFFFFF
#define TIMG_T1_LOAD_HI_S 0
#define TIMG_T1LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0044)
/* TIMG_T1_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Write any value will trigger timer 1 time-base counter reload*/
#define TIMG_T1_LOAD 0xFFFFFFFF
#define TIMG_T1_LOAD_M ((TIMG_T1_LOAD_V)<<(TIMG_T1_LOAD_S))
#define TIMG_T1_LOAD_V 0xFFFFFFFF
#define TIMG_T1_LOAD_S 0
#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x0048)
/* TIMG_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: When set SWDT is enabled*/
#define TIMG_WDT_EN (BIT(31))
#define TIMG_WDT_EN_M (BIT(31))
#define TIMG_WDT_EN_V 0x1
#define TIMG_WDT_EN_S 31
/* TIMG_WDT_STG0 : R/W ;bitpos:[30:29] ;default: 1'd0 ; */
/*description: Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
#define TIMG_WDT_STG0 0x00000003
#define TIMG_WDT_STG0_M ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S))
#define TIMG_WDT_STG0_V 0x3
#define TIMG_WDT_STG0_S 29
/* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 1'd0 ; */
/*description: Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
#define TIMG_WDT_STG1 0x00000003
#define TIMG_WDT_STG1_M ((TIMG_WDT_STG1_V)<<(TIMG_WDT_STG1_S))
#define TIMG_WDT_STG1_V 0x3
#define TIMG_WDT_STG1_S 27
/* TIMG_WDT_STG2 : R/W ;bitpos:[26:25] ;default: 1'd0 ; */
/*description: Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
#define TIMG_WDT_STG2 0x00000003
#define TIMG_WDT_STG2_M ((TIMG_WDT_STG2_V)<<(TIMG_WDT_STG2_S))
#define TIMG_WDT_STG2_V 0x3
#define TIMG_WDT_STG2_S 25
/* TIMG_WDT_STG3 : R/W ;bitpos:[24:23] ;default: 1'd0 ; */
/*description: Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
#define TIMG_WDT_STG3 0x00000003
#define TIMG_WDT_STG3_M ((TIMG_WDT_STG3_V)<<(TIMG_WDT_STG3_S))
#define TIMG_WDT_STG3_V 0x3
#define TIMG_WDT_STG3_S 23
/* TIMG_WDT_EDGE_INT_EN : R/W ;bitpos:[22] ;default: 1'h0 ; */
/*description: When set edge type interrupt generation is enabled*/
#define TIMG_WDT_EDGE_INT_EN (BIT(22))
#define TIMG_WDT_EDGE_INT_EN_M (BIT(22))
#define TIMG_WDT_EDGE_INT_EN_V 0x1
#define TIMG_WDT_EDGE_INT_EN_S 22
/* TIMG_WDT_LEVEL_INT_EN : R/W ;bitpos:[21] ;default: 1'h0 ; */
/*description: When set level type interrupt generation is enabled*/
#define TIMG_WDT_LEVEL_INT_EN (BIT(21))
#define TIMG_WDT_LEVEL_INT_EN_M (BIT(21))
#define TIMG_WDT_LEVEL_INT_EN_V 0x1
#define TIMG_WDT_LEVEL_INT_EN_S 21
/* TIMG_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[20:18] ;default: 3'h1 ; */
/*description: length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns
3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/
#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007
#define TIMG_WDT_CPU_RESET_LENGTH_M ((TIMG_WDT_CPU_RESET_LENGTH_V)<<(TIMG_WDT_CPU_RESET_LENGTH_S))
#define TIMG_WDT_CPU_RESET_LENGTH_V 0x7
#define TIMG_WDT_CPU_RESET_LENGTH_S 18
/* TIMG_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[17:15] ;default: 3'h1 ; */
/*description: length of system reset selection. 0: 100ns 1: 200ns 2: 300ns
3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/
#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007
#define TIMG_WDT_SYS_RESET_LENGTH_M ((TIMG_WDT_SYS_RESET_LENGTH_V)<<(TIMG_WDT_SYS_RESET_LENGTH_S))
#define TIMG_WDT_SYS_RESET_LENGTH_V 0x7
#define TIMG_WDT_SYS_RESET_LENGTH_S 15
/* TIMG_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */
/*description: When set flash boot protection is enabled*/
#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14))
#define TIMG_WDT_FLASHBOOT_MOD_EN_M (BIT(14))
#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x1
#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14
#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x004c)
/* TIMG_WDT_CLK_PRESCALE : R/W ;bitpos:[31:16] ;default: 16'h1 ; */
/*description: SWDT clock prescale value. Period = 12.5ns * value stored in this register*/
#define TIMG_WDT_CLK_PRESCALE 0x0000FFFF
#define TIMG_WDT_CLK_PRESCALE_M ((TIMG_WDT_CLK_PRESCALE_V)<<(TIMG_WDT_CLK_PRESCALE_S))
#define TIMG_WDT_CLK_PRESCALE_V 0xFFFF
#define TIMG_WDT_CLK_PRESCALE_S 16
#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x0050)
/* TIMG_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd26000000 ; */
/*description: Stage 0 timeout value in SWDT clock cycles*/
#define TIMG_WDT_STG0_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG0_HOLD_M ((TIMG_WDT_STG0_HOLD_V)<<(TIMG_WDT_STG0_HOLD_S))
#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFF
#define TIMG_WDT_STG0_HOLD_S 0
#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x0054)
/* TIMG_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'h7ffffff ; */
/*description: Stage 1 timeout value in SWDT clock cycles*/
#define TIMG_WDT_STG1_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG1_HOLD_M ((TIMG_WDT_STG1_HOLD_V)<<(TIMG_WDT_STG1_HOLD_S))
#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFF
#define TIMG_WDT_STG1_HOLD_S 0
#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x0058)
/* TIMG_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */
/*description: Stage 2 timeout value in SWDT clock cycles*/
#define TIMG_WDT_STG2_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG2_HOLD_M ((TIMG_WDT_STG2_HOLD_V)<<(TIMG_WDT_STG2_HOLD_S))
#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFF
#define TIMG_WDT_STG2_HOLD_S 0
#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x005c)
/* TIMG_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */
/*description: Stage 3 timeout value in SWDT clock cycles*/
#define TIMG_WDT_STG3_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG3_HOLD_M ((TIMG_WDT_STG3_HOLD_V)<<(TIMG_WDT_STG3_HOLD_S))
#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFF
#define TIMG_WDT_STG3_HOLD_S 0
#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x0060)
/* TIMG_WDT_FEED : WO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Write any value will feed SWDT*/
#define TIMG_WDT_FEED 0xFFFFFFFF
#define TIMG_WDT_FEED_M ((TIMG_WDT_FEED_V)<<(TIMG_WDT_FEED_S))
#define TIMG_WDT_FEED_V 0xFFFFFFFF
#define TIMG_WDT_FEED_S 0
#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x0064)
/* TIMG_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
/*description: If change its value from default then write protection is on.*/
#define TIMG_WDT_WKEY 0xFFFFFFFF
#define TIMG_WDT_WKEY_M ((TIMG_WDT_WKEY_V)<<(TIMG_WDT_WKEY_S))
#define TIMG_WDT_WKEY_V 0xFFFFFFFF
#define TIMG_WDT_WKEY_S 0
#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068)
/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_RTC_CALI_START (BIT(31))
#define TIMG_RTC_CALI_START_M (BIT(31))
#define TIMG_RTC_CALI_START_V 0x1
#define TIMG_RTC_CALI_START_S 31
/* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */
/*description: */
#define TIMG_RTC_CALI_MAX 0x00007FFF
#define TIMG_RTC_CALI_MAX_M ((TIMG_RTC_CALI_MAX_V)<<(TIMG_RTC_CALI_MAX_S))
#define TIMG_RTC_CALI_MAX_V 0x7FFF
#define TIMG_RTC_CALI_MAX_S 16
/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */
/*description: */
#define TIMG_RTC_CALI_RDY (BIT(15))
#define TIMG_RTC_CALI_RDY_M (BIT(15))
#define TIMG_RTC_CALI_RDY_V 0x1
#define TIMG_RTC_CALI_RDY_S 15
/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */
/*description: */
#define TIMG_RTC_CALI_CLK_SEL 0x00000003
#define TIMG_RTC_CALI_CLK_SEL_M ((TIMG_RTC_CALI_CLK_SEL_V)<<(TIMG_RTC_CALI_CLK_SEL_S))
#define TIMG_RTC_CALI_CLK_SEL_V 0x3
#define TIMG_RTC_CALI_CLK_SEL_S 13
/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */
/*description: */
#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_M (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_V 0x1
#define TIMG_RTC_CALI_START_CYCLING_S 12
#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c)
/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */
/*description: */
#define TIMG_RTC_CALI_VALUE 0x01FFFFFF
#define TIMG_RTC_CALI_VALUE_M ((TIMG_RTC_CALI_VALUE_V)<<(TIMG_RTC_CALI_VALUE_S))
#define TIMG_RTC_CALI_VALUE_V 0x1FFFFFF
#define TIMG_RTC_CALI_VALUE_S 7
#define TIMG_LACTCONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0070)
/* TIMG_LACT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_EN (BIT(31))
#define TIMG_LACT_EN_M (BIT(31))
#define TIMG_LACT_EN_V 0x1
#define TIMG_LACT_EN_S 31
/* TIMG_LACT_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
/*description: */
#define TIMG_LACT_INCREASE (BIT(30))
#define TIMG_LACT_INCREASE_M (BIT(30))
#define TIMG_LACT_INCREASE_V 0x1
#define TIMG_LACT_INCREASE_S 30
/* TIMG_LACT_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
/*description: */
#define TIMG_LACT_AUTORELOAD (BIT(29))
#define TIMG_LACT_AUTORELOAD_M (BIT(29))
#define TIMG_LACT_AUTORELOAD_V 0x1
#define TIMG_LACT_AUTORELOAD_S 29
/* TIMG_LACT_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
/*description: */
#define TIMG_LACT_DIVIDER 0x0000FFFF
#define TIMG_LACT_DIVIDER_M ((TIMG_LACT_DIVIDER_V)<<(TIMG_LACT_DIVIDER_S))
#define TIMG_LACT_DIVIDER_V 0xFFFF
#define TIMG_LACT_DIVIDER_S 13
/* TIMG_LACT_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_EDGE_INT_EN (BIT(12))
#define TIMG_LACT_EDGE_INT_EN_M (BIT(12))
#define TIMG_LACT_EDGE_INT_EN_V 0x1
#define TIMG_LACT_EDGE_INT_EN_S 12
/* TIMG_LACT_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_LEVEL_INT_EN (BIT(11))
#define TIMG_LACT_LEVEL_INT_EN_M (BIT(11))
#define TIMG_LACT_LEVEL_INT_EN_V 0x1
#define TIMG_LACT_LEVEL_INT_EN_S 11
/* TIMG_LACT_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_ALARM_EN (BIT(10))
#define TIMG_LACT_ALARM_EN_M (BIT(10))
#define TIMG_LACT_ALARM_EN_V 0x1
#define TIMG_LACT_ALARM_EN_S 10
/* TIMG_LACT_LAC_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */
/*description: */
#define TIMG_LACT_LAC_EN (BIT(9))
#define TIMG_LACT_LAC_EN_M (BIT(9))
#define TIMG_LACT_LAC_EN_V 0x1
#define TIMG_LACT_LAC_EN_S 9
/* TIMG_LACT_CPST_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */
/*description: */
#define TIMG_LACT_CPST_EN (BIT(8))
#define TIMG_LACT_CPST_EN_M (BIT(8))
#define TIMG_LACT_CPST_EN_V 0x1
#define TIMG_LACT_CPST_EN_S 8
/* TIMG_LACT_RTC_ONLY : R/W ;bitpos:[7] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_RTC_ONLY (BIT(7))
#define TIMG_LACT_RTC_ONLY_M (BIT(7))
#define TIMG_LACT_RTC_ONLY_V 0x1
#define TIMG_LACT_RTC_ONLY_S 7
#define TIMG_LACTRTC_REG(i) (REG_TIMG_BASE(i) + 0x0074)
/* TIMG_LACT_RTC_STEP_LEN : R/W ;bitpos:[31:6] ;default: 26'h0 ; */
/*description: */
#define TIMG_LACT_RTC_STEP_LEN 0x03FFFFFF
#define TIMG_LACT_RTC_STEP_LEN_M ((TIMG_LACT_RTC_STEP_LEN_V)<<(TIMG_LACT_RTC_STEP_LEN_S))
#define TIMG_LACT_RTC_STEP_LEN_V 0x3FFFFFF
#define TIMG_LACT_RTC_STEP_LEN_S 6
#define TIMG_LACTLO_REG(i) (REG_TIMG_BASE(i) + 0x0078)
/* TIMG_LACT_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_LO 0xFFFFFFFF
#define TIMG_LACT_LO_M ((TIMG_LACT_LO_V)<<(TIMG_LACT_LO_S))
#define TIMG_LACT_LO_V 0xFFFFFFFF
#define TIMG_LACT_LO_S 0
#define TIMG_LACTHI_REG(i) (REG_TIMG_BASE(i) + 0x007c)
/* TIMG_LACT_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_HI 0xFFFFFFFF
#define TIMG_LACT_HI_M ((TIMG_LACT_HI_V)<<(TIMG_LACT_HI_S))
#define TIMG_LACT_HI_V 0xFFFFFFFF
#define TIMG_LACT_HI_S 0
#define TIMG_LACTUPDATE_REG(i) (REG_TIMG_BASE(i) + 0x0080)
/* TIMG_LACT_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_UPDATE 0xFFFFFFFF
#define TIMG_LACT_UPDATE_M ((TIMG_LACT_UPDATE_V)<<(TIMG_LACT_UPDATE_S))
#define TIMG_LACT_UPDATE_V 0xFFFFFFFF
#define TIMG_LACT_UPDATE_S 0
#define TIMG_LACTALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0084)
/* TIMG_LACT_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_ALARM_LO 0xFFFFFFFF
#define TIMG_LACT_ALARM_LO_M ((TIMG_LACT_ALARM_LO_V)<<(TIMG_LACT_ALARM_LO_S))
#define TIMG_LACT_ALARM_LO_V 0xFFFFFFFF
#define TIMG_LACT_ALARM_LO_S 0
#define TIMG_LACTALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0088)
/* TIMG_LACT_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_ALARM_HI 0xFFFFFFFF
#define TIMG_LACT_ALARM_HI_M ((TIMG_LACT_ALARM_HI_V)<<(TIMG_LACT_ALARM_HI_S))
#define TIMG_LACT_ALARM_HI_V 0xFFFFFFFF
#define TIMG_LACT_ALARM_HI_S 0
#define TIMG_LACTLOADLO_REG(i) (REG_TIMG_BASE(i) + 0x008c)
/* TIMG_LACT_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_LOAD_LO 0xFFFFFFFF
#define TIMG_LACT_LOAD_LO_M ((TIMG_LACT_LOAD_LO_V)<<(TIMG_LACT_LOAD_LO_S))
#define TIMG_LACT_LOAD_LO_V 0xFFFFFFFF
#define TIMG_LACT_LOAD_LO_S 0
#define TIMG_LACTLOADHI_REG(i) (REG_TIMG_BASE(i) + 0x0090)
/* TIMG_LACT_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_LOAD_HI 0xFFFFFFFF
#define TIMG_LACT_LOAD_HI_M ((TIMG_LACT_LOAD_HI_V)<<(TIMG_LACT_LOAD_HI_S))
#define TIMG_LACT_LOAD_HI_V 0xFFFFFFFF
#define TIMG_LACT_LOAD_HI_S 0
#define TIMG_LACTLOAD_REG(i) (REG_TIMG_BASE(i) + 0x0094)
/* TIMG_LACT_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_LOAD 0xFFFFFFFF
#define TIMG_LACT_LOAD_M ((TIMG_LACT_LOAD_V)<<(TIMG_LACT_LOAD_S))
#define TIMG_LACT_LOAD_V 0xFFFFFFFF
#define TIMG_LACT_LOAD_S 0
#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0098)
/* TIMG_LACT_INT_ENA : R/W ;bitpos:[3] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_INT_ENA (BIT(3))
#define TIMG_LACT_INT_ENA_M (BIT(3))
#define TIMG_LACT_INT_ENA_V 0x1
#define TIMG_LACT_INT_ENA_S 3
/* TIMG_WDT_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: Interrupt when an interrupt stage timeout*/
#define TIMG_WDT_INT_ENA (BIT(2))
#define TIMG_WDT_INT_ENA_M (BIT(2))
#define TIMG_WDT_INT_ENA_V 0x1
#define TIMG_WDT_INT_ENA_S 2
/* TIMG_T1_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */
/*description: interrupt when timer1 alarm*/
#define TIMG_T1_INT_ENA (BIT(1))
#define TIMG_T1_INT_ENA_M (BIT(1))
#define TIMG_T1_INT_ENA_V 0x1
#define TIMG_T1_INT_ENA_S 1
/* TIMG_T0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: interrupt when timer0 alarm*/
#define TIMG_T0_INT_ENA (BIT(0))
#define TIMG_T0_INT_ENA_M (BIT(0))
#define TIMG_T0_INT_ENA_V 0x1
#define TIMG_T0_INT_ENA_S 0
#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x009c)
/* TIMG_LACT_INT_RAW : RO ;bitpos:[3] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_INT_RAW (BIT(3))
#define TIMG_LACT_INT_RAW_M (BIT(3))
#define TIMG_LACT_INT_RAW_V 0x1
#define TIMG_LACT_INT_RAW_S 3
/* TIMG_WDT_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */
/*description: Interrupt when an interrupt stage timeout*/
#define TIMG_WDT_INT_RAW (BIT(2))
#define TIMG_WDT_INT_RAW_M (BIT(2))
#define TIMG_WDT_INT_RAW_V 0x1
#define TIMG_WDT_INT_RAW_S 2
/* TIMG_T1_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */
/*description: interrupt when timer1 alarm*/
#define TIMG_T1_INT_RAW (BIT(1))
#define TIMG_T1_INT_RAW_M (BIT(1))
#define TIMG_T1_INT_RAW_V 0x1
#define TIMG_T1_INT_RAW_S 1
/* TIMG_T0_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */
/*description: interrupt when timer0 alarm*/
#define TIMG_T0_INT_RAW (BIT(0))
#define TIMG_T0_INT_RAW_M (BIT(0))
#define TIMG_T0_INT_RAW_V 0x1
#define TIMG_T0_INT_RAW_S 0
#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x00a0)
/* TIMG_LACT_INT_ST : RO ;bitpos:[3] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_INT_ST (BIT(3))
#define TIMG_LACT_INT_ST_M (BIT(3))
#define TIMG_LACT_INT_ST_V 0x1
#define TIMG_LACT_INT_ST_S 3
/* TIMG_WDT_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */
/*description: Interrupt when an interrupt stage timeout*/
#define TIMG_WDT_INT_ST (BIT(2))
#define TIMG_WDT_INT_ST_M (BIT(2))
#define TIMG_WDT_INT_ST_V 0x1
#define TIMG_WDT_INT_ST_S 2
/* TIMG_T1_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */
/*description: interrupt when timer1 alarm*/
#define TIMG_T1_INT_ST (BIT(1))
#define TIMG_T1_INT_ST_M (BIT(1))
#define TIMG_T1_INT_ST_V 0x1
#define TIMG_T1_INT_ST_S 1
/* TIMG_T0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */
/*description: interrupt when timer0 alarm*/
#define TIMG_T0_INT_ST (BIT(0))
#define TIMG_T0_INT_ST_M (BIT(0))
#define TIMG_T0_INT_ST_V 0x1
#define TIMG_T0_INT_ST_S 0
#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x00a4)
/* TIMG_LACT_INT_CLR : WO ;bitpos:[3] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_INT_CLR (BIT(3))
#define TIMG_LACT_INT_CLR_M (BIT(3))
#define TIMG_LACT_INT_CLR_V 0x1
#define TIMG_LACT_INT_CLR_S 3
/* TIMG_WDT_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */
/*description: Interrupt when an interrupt stage timeout*/
#define TIMG_WDT_INT_CLR (BIT(2))
#define TIMG_WDT_INT_CLR_M (BIT(2))
#define TIMG_WDT_INT_CLR_V 0x1
#define TIMG_WDT_INT_CLR_S 2
/* TIMG_T1_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */
/*description: interrupt when timer1 alarm*/
#define TIMG_T1_INT_CLR (BIT(1))
#define TIMG_T1_INT_CLR_M (BIT(1))
#define TIMG_T1_INT_CLR_V 0x1
#define TIMG_T1_INT_CLR_S 1
/* TIMG_T0_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */
/*description: interrupt when timer0 alarm*/
#define TIMG_T0_INT_CLR (BIT(0))
#define TIMG_T0_INT_CLR_M (BIT(0))
#define TIMG_T0_INT_CLR_V 0x1
#define TIMG_T0_INT_CLR_S 0
#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0x00f8)
/* TIMG_NTIMERS_DATE : R/W ;bitpos:[27:0] ;default: 28'h1604290 ; */
/*description: Version of this regfile*/
#define TIMG_NTIMERS_DATE 0x0FFFFFFF
#define TIMG_NTIMERS_DATE_M ((TIMG_NTIMERS_DATE_V)<<(TIMG_NTIMERS_DATE_S))
#define TIMG_NTIMERS_DATE_V 0xFFFFFFF
#define TIMG_NTIMERS_DATE_S 0
#define TIMGCLK_REG(i) (REG_TIMG_BASE(i) + 0x00fc)
/* TIMG_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: Force clock enable for this regfile*/
#define TIMG_CLK_EN (BIT(31))
#define TIMG_CLK_EN_M (BIT(31))
#define TIMG_CLK_EN_V 0x1
#define TIMG_CLK_EN_S 31
#endif /*__TIMG_REG_H__ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_TIMERS_REG_H_
#define _SOC_TIMER_REG_H_
#include "soc.h"
#define T0CONFIG(i) (DR_REG_TIMERS_BASE(i) + 0x0000)
#define TIMERS_T0_EN (BIT(31))
#define TIMERS_T0_EN_S 31
#define TIMERS_T0_INCREASE (BIT(30))
#define TIMERS_T0_INCREASE_S 30
#define TIMERS_T0_AUTORELOAD (BIT(29))
#define TIMERS_T0_AUTORELOAD_S 29
#define TIMERS_T0_DIVIDER 0x0000FFFF
#define TIMERS_T0_DIVIDER_S 13
#define TIMERS_T0_EDGE_INT_EN (BIT(12))
#define TIMERS_T0_EDGE_INT_EN_S 12
#define TIMERS_T0_LEVEL_INT_EN (BIT(11))
#define TIMERS_T0_LEVEL_INT_EN_S 11
#define TIMERS_T0_ALARM_EN (BIT(10))
#define TIMERS_T0_ALARM_EN_S 10
#define T0LO(i) (DR_REG_TIMERS_BASE(i) + 0x0004)
#define TIMERS_T0_LO 0xFFFFFFFF
#define TIMERS_T0_LO_S 0
#define T0HI(i) (DR_REG_TIMERS_BASE(i) + 0x0008)
#define TIMERS_T0_HI 0xFFFFFFFF
#define TIMERS_T0_HI_S 0
#define T0UPDATE(i) (DR_REG_TIMERS_BASE(i) + 0x000c)
#define TIMERS_T0_UPDATE 0xFFFFFFFF
#define TIMERS_T0_UPDATE_S 0
#define T0ALARMLO(i) (DR_REG_TIMERS_BASE(i) + 0x0010)
#define TIMERS_T0_ALARM_LO 0xFFFFFFFF
#define TIMERS_T0_ALARM_LO_S 0
#define T0ALARMHI(i) (DR_REG_TIMERS_BASE(i) + 0x0014)
#define TIMERS_T0_ALARM_HI 0xFFFFFFFF
#define TIMERS_T0_ALARM_HI_S 0
#define T0LOADLO(i) (DR_REG_TIMERS_BASE(i) + 0x0018)
#define TIMERS_T0_LOAD_LO 0xFFFFFFFF
#define TIMERS_T0_LOAD_LO_S 0
#define T0LOADHI(i) (DR_REG_TIMERS_BASE(i) + 0x001c)
#define TIMERS_T0_LOAD_HI 0xFFFFFFFF
#define TIMERS_T0_LOAD_HI_S 0
#define T0LOAD(i) (DR_REG_TIMERS_BASE(i) + 0x0020)
#define TIMERS_T0_LOAD 0xFFFFFFFF
#define TIMERS_T0_LOAD_S 0
#define T1CONFIG(i) (DR_REG_TIMERS_BASE(i) + 0x0024)
#define TIMERS_T1_EN (BIT(31))
#define TIMERS_T1_EN_S 31
#define TIMERS_T1_INCREASE (BIT(30))
#define TIMERS_T1_INCREASE_S 30
#define TIMERS_T1_AUTORELOAD (BIT(29))
#define TIMERS_T1_AUTORELOAD_S 29
#define TIMERS_T1_DIVIDER 0x0000FFFF
#define TIMERS_T1_DIVIDER_S 13
#define TIMERS_T1_EDGE_INT_EN (BIT(12))
#define TIMERS_T1_EDGE_INT_EN_S 12
#define TIMERS_T1_LEVEL_INT_EN (BIT(11))
#define TIMERS_T1_LEVEL_INT_EN_S 11
#define TIMERS_T1_ALARM_EN (BIT(10))
#define TIMERS_T1_ALARM_EN_S 10
#define T1LO(i) (DR_REG_TIMERS_BASE(i) + 0x0028)
#define TIMERS_T1_LO 0xFFFFFFFF
#define TIMERS_T1_LO_S 0
#define T1HI(i) (DR_REG_TIMERS_BASE(i) + 0x002c)
#define TIMERS_T1_HI 0xFFFFFFFF
#define TIMERS_T1_HI_S 0
#define T1UPDATE(i) (DR_REG_TIMERS_BASE(i) + 0x0030)
#define TIMERS_T1_UPDATE 0xFFFFFFFF
#define TIMERS_T1_UPDATE_S 0
#define T1ALARMLO(i) (DR_REG_TIMERS_BASE(i) + 0x0034)
#define TIMERS_T1_ALARM_LO 0xFFFFFFFF
#define TIMERS_T1_ALARM_LO_S 0
#define T1ALARMHI(i) (DR_REG_TIMERS_BASE(i) + 0x0038)
#define TIMERS_T1_ALARM_HI 0xFFFFFFFF
#define TIMERS_T1_ALARM_HI_S 0
#define T1LOADLO(i) (DR_REG_TIMERS_BASE(i) + 0x003c)
#define TIMERS_T1_LOAD_LO 0xFFFFFFFF
#define TIMERS_T1_LOAD_LO_S 0
#define T1LOADHI(i) (DR_REG_TIMERS_BASE(i) + 0x0040)
#define TIMERS_T1_LOAD_HI 0xFFFFFFFF
#define TIMERS_T1_LOAD_HI_S 0
#define T1LOAD(i) (DR_REG_TIMERS_BASE(i) + 0x0044)
#define TIMERS_T1_LOAD 0xFFFFFFFF
#define TIMERS_T1_LOAD_S 0
#define WDTCONFIG0(i) (DR_REG_TIMERS_BASE(i) + 0x0048)
#define TIMERS_WDT_EN (BIT(31))
#define TIMERS_WDT_EN_S 31
#define TIMERS_WDT_STG0 0x00000003
#define TIMERS_WDT_STG0_S 29
#define TIMERS_WDT_STG1 0x00000003
#define TIMERS_WDT_STG1_S 27
#define TIMERS_WDT_STG2 0x00000003
#define TIMERS_WDT_STG2_S 25
#define TIMERS_WDT_STG3 0x00000003
#define TIMERS_WDT_STG3_S 23
#define TIMERS_WDT_EDGE_INT_EN (BIT(22))
#define TIMERS_WDT_EDGE_INT_EN_S 22
#define TIMERS_WDT_LEVEL_INT_EN (BIT(21))
#define TIMERS_WDT_LEVEL_INT_EN_S 21
#define TIMERS_WDT_CPU_RESET_LENGTH 0x00000007
#define TIMERS_WDT_CPU_RESET_LENGTH_S 18
#define TIMERS_WDT_SYS_RESET_LENGTH 0x00000007
#define TIMERS_WDT_SYS_RESET_LENGTH_S 15
#define TIMERS_WDT_FLASHBOOT_MOD_EN (BIT(14))
#define TIMERS_WDT_FLASHBOOT_MOD_EN_S 14
#define WDTCONFIG1(i) (DR_REG_TIMERS_BASE(i) + 0x004c)
#define TIMERS_WDT_CLK_PRESCALE 0x0000FFFF
#define TIMERS_WDT_CLK_PRESCALE_S 16
#define WDTCONFIG2(i) (DR_REG_TIMERS_BASE(i) + 0x0050)
#define TIMERS_WDT_STG0_HOLD 0xFFFFFFFF
#define TIMERS_WDT_STG0_HOLD_S 0
#define WDTCONFIG3(i) (DR_REG_TIMERS_BASE(i) + 0x0054)
#define TIMERS_WDT_STG1_HOLD 0xFFFFFFFF
#define TIMERS_WDT_STG1_HOLD_S 0
#define WDTCONFIG4(i) (DR_REG_TIMERS_BASE(i) + 0x0058)
#define TIMERS_WDT_STG2_HOLD 0xFFFFFFFF
#define TIMERS_WDT_STG2_HOLD_S 0
#define WDTCONFIG5(i) (DR_REG_TIMERS_BASE(i) + 0x005c)
#define TIMERS_WDT_STG3_HOLD 0xFFFFFFFF
#define TIMERS_WDT_STG3_HOLD_S 0
#define WDTFEED(i) (DR_REG_TIMERS_BASE(i) + 0x0060)
#define TIMERS_WDT_FEED 0xFFFFFFFF
#define TIMERS_WDT_FEED_S 0
#define WDTWPROTECT(i) (DR_REG_TIMERS_BASE(i) + 0x0064)
#define TIMERS_WDT_WKEY 0xFFFFFFFF
#define TIMERS_WDT_WKEY_S 0
#define RTCCALICFG(i) (DR_REG_TIMERS_BASE(i) + 0x0068)
#define TIMERS_RTC_CALI_START (BIT(31))
#define TIMERS_RTC_CALI_START_S 31
#define TIMERS_RTC_CALI_MAX 0x00007FFF
#define TIMERS_RTC_CALI_MAX_S 16
#define TIMERS_RTC_CALI_RDY (BIT(15))
#define TIMERS_RTC_CALI_RDY_S 15
#define TIMERS_RTC_CALI_CLK_SEL 0x00000003
#define TIMERS_RTC_CALI_CLK_SEL_S 13
#define TIMERS_RTC_CALI_START_CYCLING (BIT(12))
#define TIMERS_RTC_CALI_START_CYCLING_S 12
#define RTCCALICFG1(i) (DR_REG_TIMERS_BASE(i) + 0x006c)
#define TIMERS_RTC_CALI_VALUE 0x01FFFFFF
#define TIMERS_RTC_CALI_VALUE_S 7
#define LACTCONFIG(i) (DR_REG_TIMERS_BASE(i) + 0x0070)
#define TIMERS_LACT_EN (BIT(31))
#define TIMERS_LACT_EN_S 31
#define TIMERS_LACT_INCREASE (BIT(30))
#define TIMERS_LACT_INCREASE_S 30
#define TIMERS_LACT_AUTORELOAD (BIT(29))
#define TIMERS_LACT_AUTORELOAD_S 29
#define TIMERS_LACT_DIVIDER 0x0000FFFF
#define TIMERS_LACT_DIVIDER_S 13
#define TIMERS_LACT_EDGE_INT_EN (BIT(12))
#define TIMERS_LACT_EDGE_INT_EN_S 12
#define TIMERS_LACT_LEVEL_INT_EN (BIT(11))
#define TIMERS_LACT_LEVEL_INT_EN_S 11
#define TIMERS_LACT_ALARM_EN (BIT(10))
#define TIMERS_LACT_ALARM_EN_S 10
#define TIMERS_LACT_LAC_EN (BIT(9))
#define TIMERS_LACT_LAC_EN_S 9
#define TIMERS_LACT_CPST_EN (BIT(8))
#define TIMERS_LACT_CPST_EN_S 8
#define TIMERS_LACT_RTC_ONLY (BIT(7))
#define TIMERS_LACT_RTC_ONLY_S 7
#define LACTRTC(i) (DR_REG_TIMERS_BASE(i) + 0x0074)
#define TIMERS_LACT_RTC_STEP_LEN 0x03FFFFFF
#define TIMERS_LACT_RTC_STEP_LEN_S 6
#define LACTLO(i) (DR_REG_TIMERS_BASE(i) + 0x0078)
#define TIMERS_LACT_LO 0xFFFFFFFF
#define TIMERS_LACT_LO_S 0
#define LACTHI(i) (DR_REG_TIMERS_BASE(i) + 0x007c)
#define TIMERS_LACT_HI 0xFFFFFFFF
#define TIMERS_LACT_HI_S 0
#define LACTUPDATE(i) (DR_REG_TIMERS_BASE(i) + 0x0080)
#define TIMERS_LACT_UPDATE 0xFFFFFFFF
#define TIMERS_LACT_UPDATE_S 0
#define LACTALARMLO(i) (DR_REG_TIMERS_BASE(i) + 0x0084)
#define TIMERS_LACT_ALARM_LO 0xFFFFFFFF
#define TIMERS_LACT_ALARM_LO_S 0
#define LACTALARMHI(i) (DR_REG_TIMERS_BASE(i) + 0x0088)
#define TIMERS_LACT_ALARM_HI 0xFFFFFFFF
#define TIMERS_LACT_ALARM_HI_S 0
#define LACTLOADLO(i) (DR_REG_TIMERS_BASE(i) + 0x008c)
#define TIMERS_LACT_LOAD_LO 0xFFFFFFFF
#define TIMERS_LACT_LOAD_LO_S 0
#define LACTLOADHI(i) (DR_REG_TIMERS_BASE(i) + 0x0090)
#define TIMERS_LACT_LOAD_HI 0xFFFFFFFF
#define TIMERS_LACT_LOAD_HI_S 0
#define LACTLOAD(i) (DR_REG_TIMERS_BASE(i) + 0x0094)
#define TIMERS_LACT_LOAD 0xFFFFFFFF
#define TIMERS_LACT_LOAD_S 0
#define INT_ENA_TIMERS(i) (DR_REG_TIMERS_BASE(i) + 0x0098)
#define TIMERS_LACT_INT_ENA (BIT(3))
#define TIMERS_LACT_INT_ENA_S 3
#define TIMERS_WDT_INT_ENA (BIT(2))
#define TIMERS_WDT_INT_ENA_S 2
#define TIMERS_T1_INT_ENA (BIT(1))
#define TIMERS_T1_INT_ENA_S 1
#define TIMERS_T0_INT_ENA (BIT(0))
#define TIMERS_T0_INT_ENA_S 0
#define INT_RAW_TIMERS(i) (DR_REG_TIMERS_BASE(i) + 0x009c)
#define TIMERS_LACT_INT_RAW (BIT(3))
#define TIMERS_LACT_INT_RAW_S 3
#define TIMERS_WDT_INT_RAW (BIT(2))
#define TIMERS_WDT_INT_RAW_S 2
#define TIMERS_T1_INT_RAW (BIT(1))
#define TIMERS_T1_INT_RAW_S 1
#define TIMERS_T0_INT_RAW (BIT(0))
#define TIMERS_T0_INT_RAW_S 0
#define INT_ST_TIMERS(i) (DR_REG_TIMERS_BASE(i) + 0x00a0)
#define TIMERS_LACT_INT_ST (BIT(3))
#define TIMERS_LACT_INT_ST_S 3
#define TIMERS_WDT_INT_ST (BIT(2))
#define TIMERS_WDT_INT_ST_S 2
#define TIMERS_T1_INT_ST (BIT(1))
#define TIMERS_T1_INT_ST_S 1
#define TIMERS_T0_INT_ST (BIT(0))
#define TIMERS_T0_INT_ST_S 0
#define INT_CLR_TIMERS(i) (DR_REG_TIMERS_BASE(i) + 0x00a4)
#define TIMERS_LACT_INT_CLR (BIT(3))
#define TIMERS_LACT_INT_CLR_S 3
#define TIMERS_WDT_INT_CLR (BIT(2))
#define TIMERS_WDT_INT_CLR_S 2
#define TIMERS_T1_INT_CLR (BIT(1))
#define TIMERS_T1_INT_CLR_S 1
#define TIMERS_T0_INT_CLR (BIT(0))
#define TIMERS_T0_INT_CLR_S 0
#define NTIMERS_DATE(i) (DR_REG_TIMERS_BASE(i) + 0x00f8)
#define TIMERS_NTIMERS_DATE 0x0FFFFFFF
#define TIMERS_NTIMERS_DATE_S 0
#define TIMERS_NTIMERS_DATE_VERSION 0x1604290
#define REGCLK(i) (DR_REG_TIMERS_BASE(i) + 0x00fc)
#define TIMERS_CLK_EN (BIT(31))
#define TIMERS_CLK_EN_S 31
#endif /* _SOC_TIMER_REG_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_UHCI0_REG_H_
#define _SOC_UHCI0_REG_H_
#include "soc.h"
#define UHCI0_CONF0 ( DR_REG_UHCI0_BASE + 0x0)
#define UHCI0_UART_RX_BRK_EOF_EN (BIT(22))
#define UHCI0_CLK_EN (BIT(21))
#define UHCI0_ENCODE_CRC_EN (BIT(20))
#define UHCI0_LEN_EOF_EN (BIT(19))
#define UHCI0_UART_IDLE_EOF_EN (BIT(18))
#define UHCI0_CRC_REC_EN (BIT(17))
#define UHCI0_HEAD_EN (BIT(16))
#define UHCI0_SEPER_EN (BIT(15))
#define UHCI0_MEM_TRANS_EN (BIT(14))
#define UHCI0_RX_DATA_BURST_EN (BIT(13))
#define UHCI0_TXDSCR_BURST_EN (BIT(12))
#define UHCI0_RXDSCR_BURST_EN (BIT(11))
#define UHCI0_UART1_CE (BIT(10))
#define UHCI0_UART0_CE (BIT(9))
#define UHCI0_TO_EOF_MODE (BIT(8))
#define UHCI0_RX_NO_RESTART_CLR (BIT(7))
#define UHCI0_RX_AUTO_WRBACK (BIT(6))
#define UHCI0_RX_LOOP_TEST (BIT(5))
#define UHCI0_TX_LOOP_TEST (BIT(4))
#define UHCI0_AHBM_RST (BIT(3))
#define UHCI0_AHBM_FIFO_RST (BIT(2))
#define UHCI0_RX_RST (BIT(1))
#define UHCI0_TX_RST (BIT(0))
#define UHCI0_INT_RAW ( DR_REG_UHCI0_BASE + 0x4)
#define UHCI0_UHCI_SEND_A_Q_INT_RAW (BIT(15))
#define UHCI0_UHCI_SEND_S_Q_INT_RAW (BIT(14))
#define UHCI0_UHCI_TO_TOTAL_EOF_INT_RAW (BIT(13))
#define UHCI0_UHCI_RXLINK_EOF_ERR_INT_RAW (BIT(12))
#define UHCI0_UHCI_TX_DSCR_EMPTY_INT_RAW (BIT(11))
#define UHCI0_UHCI_RX_DSCR_ERR_INT_RAW (BIT(10))
#define UHCI0_UHCI_TX_DSCR_ERR_INT_RAW (BIT(9))
#define UHCI0_UHCI_TO_EOF_INT_RAW (BIT(8))
#define UHCI0_UHCI_RX_DONE_INT_RAW (BIT(7))
#define UHCI0_UHCI_FROM_ERR_EOF_INT_RAW (BIT(6))
#define UHCI0_UHCI_FROM_SUC_EOF_INT_RAW (BIT(5))
#define UHCI0_UHCI_TX_DONE_INT_RAW (BIT(4))
#define UHCI0_UHCI_TX_HUNG_INT_RAW (BIT(3))
#define UHCI0_UHCI_RX_HUNG_INT_RAW (BIT(2))
#define UHCI0_UHCI_TX_START_INT_RAW (BIT(1))
#define UHCI0_UHCI_RX_START_INT_RAW (BIT(0))
#define UHCI0_INT_ST ( DR_REG_UHCI0_BASE + 0x8)
#define UHCI0_UHCI_SEND_A_Q_INT_ST (BIT(15))
#define UHCI0_UHCI_SEND_S_Q_INT_ST (BIT(14))
#define UHCI0_UHCI_TO_TOTAL_EOF_INT_ST (BIT(13))
#define UHCI0_UHCI_RXLINK_EOF_ERR_INT_ST (BIT(12))
#define UHCI0_UHCI_TX_DSCR_EMPTY_INT_ST (BIT(11))
#define UHCI0_UHCI_RX_DSCR_ERR_INT_ST (BIT(10))
#define UHCI0_UHCI_TX_DSCR_ERR_INT_ST (BIT(9))
#define UHCI0_UHCI_TO_EOF_INT_ST (BIT(8))
#define UHCI0_UHCI_RX_DONE_INT_ST (BIT(7))
#define UHCI0_UHCI_FROM_ERR_EOF_INT_ST (BIT(6))
#define UHCI0_UHCI_FROM_SUC_EOF_INT_ST (BIT(5))
#define UHCI0_UHCI_TX_DONE_INT_ST (BIT(4))
#define UHCI0_UHCI_TX_HUNG_INT_ST (BIT(3))
#define UHCI0_UHCI_RX_HUNG_INT_ST (BIT(2))
#define UHCI0_UHCI_TX_START_INT_ST (BIT(1))
#define UHCI0_UHCI_RX_START_INT_ST (BIT(0))
#define UHCI0_INT_ENA ( DR_REG_UHCI0_BASE + 0xC)
#define UHCI0_UHCI_SEND_A_Q_INT_ENA (BIT(15))
#define UHCI0_UHCI_SEND_S_Q_INT_ENA (BIT(14))
#define UHCI0_UHCI_TO_TOTAL_EOF_INT_ENA (BIT(13))
#define UHCI0_UHCI_RXLINK_EOF_ERR_INT_ENA (BIT(12))
#define UHCI0_UHCI_TX_DSCR_EMPTY_INT_ENA (BIT(11))
#define UHCI0_UHCI_RX_DSCR_ERR_INT_ENA (BIT(10))
#define UHCI0_UHCI_TX_DSCR_ERR_INT_ENA (BIT(9))
#define UHCI0_UHCI_TO_EOF_INT_ENA (BIT(8))
#define UHCI0_UHCI_RX_DONE_INT_ENA (BIT(7))
#define UHCI0_UHCI_FROM_ERR_EOF_INT_ENA (BIT(6))
#define UHCI0_UHCI_FROM_SUC_EOF_INT_ENA (BIT(5))
#define UHCI0_UHCI_TX_DONE_INT_ENA (BIT(4))
#define UHCI0_UHCI_TX_HUNG_INT_ENA (BIT(3))
#define UHCI0_UHCI_RX_HUNG_INT_ENA (BIT(2))
#define UHCI0_UHCI_TX_START_INT_ENA (BIT(1))
#define UHCI0_UHCI_RX_START_INT_ENA (BIT(0))
#define UHCI0_INT_CLR ( DR_REG_UHCI0_BASE + 0x10)
#define UHCI0_SEND_A_REG_Q_INT_CLR (BIT(15))
#define UHCI0_SEND_S_REG_Q_INT_CLR (BIT(14))
#define UHCI0_TO_TOTAL_EOF_INT_CLR (BIT(13))
#define UHCI0_RXLINK_EOF_ERR_INT_CLR (BIT(12))
#define UHCI0_TX_DSCR_EMPTY_INT_CLR (BIT(11))
#define UHCI0_RX_DSCR_ERR_INT_CLR (BIT(10))
#define UHCI0_TX_DSCR_ERR_INT_CLR (BIT(9))
#define UHCI0_TO_EOF_INT_CLR (BIT(8))
#define UHCI0_RX_DONE_INT_CLR (BIT(7))
#define UHCI0_FROM_ERR_EOF_INT_CLR (BIT(6))
#define UHCI0_FROM_SUC_EOF_INT_CLR (BIT(5))
#define UHCI0_TX_DONE_INT_CLR (BIT(4))
#define UHCI0_TX_HUNG_INT_CLR (BIT(3))
#define UHCI0_RX_HUNG_INT_CLR (BIT(2))
#define UHCI0_TX_START_INT_CLR (BIT(1))
#define UHCI0_RX_START_INT_CLR (BIT(0))
#define UHCI0_RX_STATUS ( DR_REG_UHCI0_BASE + 0x14)
#define UHCI0_RX_EMPTY (BIT(1))
#define UHCI0_RX_FULL (BIT(0))
#define UHCI0_RXFIFO_PUSH ( DR_REG_UHCI0_BASE + 0x18)
#define UHCI0_RXFIFO_PUSH_EN (BIT(16))
#define UHCI0_RXFIFO_WDATA 0x000001FF
#define UHCI0_RXFIFO_WDATA_S 0
#define UHCI0_TX_STATUS ( DR_REG_UHCI0_BASE + 0x1C)
#define UHCI0_UHCI_RX_ERR_CAUSE 0x00000007
#define UHCI0_UHCI_RX_ERR_CAUSE_S 4
#define UHCI0_TX_EMPTY (BIT(1))
#define UHCI0_TX_FULL (BIT(0))
#define UHCI0_TX_POP ( DR_REG_UHCI0_BASE + 0x20)
#define UHCI0_TXFIFO_POP (BIT(16))
#define UHCI0_TXFIFO_RDATA 0x00000FFF
#define UHCI0_TXFIFO_RDATA_S 0
#define UHCI0_RX_LINK ( DR_REG_UHCI0_BASE + 0x24)
#define UHCI0_UHCI_RXLINK_PARK (BIT(31))
#define UHCI0_RXLINK_RESTART (BIT(30))
#define UHCI0_RXLINK_START (BIT(29))
#define UHCI0_RXLINK_STOP (BIT(28))
#define UHCI0_RXLINK_ADDR 0x000FFFFF
#define UHCI0_RXLINK_ADDR_S 0
#define UHCI0_TX_LINK ( DR_REG_UHCI0_BASE + 0x28)
#define UHCI0_UHCI_TXLINK_PARK (BIT(31))
#define UHCI0_TXLINK_RESTART (BIT(30))
#define UHCI0_TXLINK_START (BIT(29))
#define UHCI0_TXLINK_STOP (BIT(28))
#define UHCI0_TXLINK_AUTO_RET (BIT(20))
#define UHCI0_TXLINK_ADDR 0x000FFFFF
#define UHCI0_TXLINK_ADDR_S 0
#define UHCI0_CONF1 ( DR_REG_UHCI0_BASE + 0x2C)
#define UHCI0_SW_START (BIT(8))
#define UHCI0_WAIT_SW_START (BIT(7))
#define UHCI0_CHECK_OWNER (BIT(6))
#define UHCI0_TX_ACK_NUM_RE (BIT(5))
#define UHCI0_TX_CHECK_SUM_RE (BIT(4))
#define UHCI0_SAVE_HEAD (BIT(3))
#define UHCI0_CRC_DISABLE (BIT(2))
#define UHCI0_CHECK_SEQ_EN (BIT(1))
#define UHCI0_CHECK_SUM_EN (BIT(0))
#define UHCI0_STATE0 ( DR_REG_UHCI0_BASE + 0x30)
#define UHCI0_UHCI_STATE0 0xFFFFFFFF
#define UHCI0_UHCI_STATE0_S 0
#define UHCI0_STATE1 ( DR_REG_UHCI0_BASE + 0x34)
#define UHCI0_UHCI_STATE1 0xFFFFFFFF
#define UHCI0_UHCI_STATE1_S 0
#define UHCI0_RX_EOF_DES_ADDR ( DR_REG_UHCI0_BASE + 0x38)
#define UHCI0_TO_EOF_DES_ADDR 0xFFFFFFFF
#define UHCI0_TO_EOF_DES_ADDR_S 0
#define UHCI0_TX_SUC_EOF_DES_ADDR ( DR_REG_UHCI0_BASE + 0x3C)
#define UHCI0_FROM_SUC_EOF_DES_ADDR 0xFFFFFFFF
#define UHCI0_FROM_SUC_EOF_DES_ADDR_S 0
#define UHCI0_TX_ERR_EOF_DES_ADDR ( DR_REG_UHCI0_BASE + 0x40)
#define UHCI0_FROM_ERR_EOF_DES_ADDR 0xFFFFFFFF
#define UHCI0_FROM_ERR_EOF_DES_ADDR_S 0
#define UHCI0_RX_EOF_BFR_DES_ADDR ( DR_REG_UHCI0_BASE + 0x44)
#define UHCI0_TO_EOF_BFR_DES_ADDR 0xFFFFFFFF
#define UHCI0_TO_EOF_BFR_DES_ADDR_S 0
#define UHCI0_AHB_TEST ( DR_REG_UHCI0_BASE + 0x48)
#define UHCI0_AHB_TESTADDR 0x00000003
#define UHCI0_AHB_TESTADDR_S 4
#define UHCI0_AHB_TESTMODE 0x00000007
#define UHCI0_AHB_TESTMODE_S 0
#define UHCI0_TX_DSCR ( DR_REG_UHCI0_BASE + 0x4C)
#define UHCI0_TXLINK_DSCR 0xFFFFFFFF
#define UHCI0_TXLINK_DSCR_S 0
#define UHCI0_TX_DSCR_BF0 ( DR_REG_UHCI0_BASE + 0x50)
#define UHCI0_TXLINK_DSCR_BF0 0xFFFFFFFF
#define UHCI0_TXLINK_DSCR_BF0_S 0
#define UHCI0_TX_DSCR_BF1 ( DR_REG_UHCI0_BASE + 0x54)
#define UHCI0_TXLINK_DSCR_BF1 0xFFFFFFFF
#define UHCI0_TXLINK_DSCR_BF1_S 0
#define UHCI0_RX_DSCR ( DR_REG_UHCI0_BASE + 0x58)
#define UHCI0_RXLINK_DSCR 0xFFFFFFFF
#define UHCI0_RXLINK_DSCR_S 0
#define UHCI0_RX_DSCR_BF0 ( DR_REG_UHCI0_BASE + 0x5C)
#define UHCI0_RXLINK_DSCR_BF0 0xFFFFFFFF
#define UHCI0_RXLINK_DSCR_BF0_S 0
#define UHCI0_RX_DSCR_BF1 ( DR_REG_UHCI0_BASE + 0x60)
#define UHCI0_RXLINK_DSCR_BF1 0xFFFFFFFF
#define UHCI0_RXLINK_DSCR_BF1_S 0
#define UHCI0_ESCAPE_CONF ( DR_REG_UHCI0_BASE + 0x64)
#define UHCI0_RX_13_ESC_EN (BIT(7))
#define UHCI0_RX_11_ESC_EN (BIT(6))
#define UHCI0_RX_DB_ESC_EN (BIT(5))
#define UHCI0_RX_C0_ESC_EN (BIT(4))
#define UHCI0_TX_13_ESC_EN (BIT(3))
#define UHCI0_TX_11_ESC_EN (BIT(2))
#define UHCI0_TX_DB_ESC_EN (BIT(1))
#define UHCI0_TX_C0_ESC_EN (BIT(0))
#define UHCI0_HUNG_CONF ( DR_REG_UHCI0_BASE + 0x68)
#define UHCI0_RXFIFO_TIMEOUT_ENA (BIT(23))
#define UHCI0_RXFIFO_TIMEOUT_SHIFT 0x00000007
#define UHCI0_RXFIFO_TIMEOUT_SHIFT_S 20
#define UHCI0_RXFIFO_TIMEOUT 0x000000FF
#define UHCI0_RXFIFO_TIMEOUT_S 12
#define UHCI0_TXFIFO_TIMEOUT_ENA (BIT(11))
#define UHCI0_TXFIFO_TIMEOUT_SHIFT 0x00000007
#define UHCI0_TXFIFO_TIMEOUT_SHIFT_S 8
#define UHCI0_TXFIFO_TIMEOUT 0x000000FF
#define UHCI0_TXFIFO_TIMEOUT_S 0
#define UHCI0_ACK_NUM ( DR_REG_UHCI0_BASE + 0x6C)
#define UHCI0_RX_HEAD ( DR_REG_UHCI0_BASE + 0x70)
#define UHCI0_UHCI_RX_HEAD 0xFFFFFFFF
#define UHCI0_UHCI_RX_HEAD_S 0
#define UHCI0_QUICK_SENT ( DR_REG_UHCI0_BASE + 0x74)
#define UHCI0_ALWAYS_SEND_EN (BIT(7))
#define UHCI0_ALWAYS_SEND_NUM 0x00000007
#define UHCI0_ALWAYS_SEND_NUM_S 4
#define UHCI0_SINGLE_SEND_EN (BIT(3))
#define UHCI0_SINGLE_SEND_NUM 0x00000007
#define UHCI0_SINGLE_SEND_NUM_S 0
#define UHCI0_REG_Q0_WORD0 ( DR_REG_UHCI0_BASE + 0x78)
#define UHCI0_SEND_Q0_WORD0 0xFFFFFFFF
#define UHCI0_SEND_Q0_WORD0_S 0
#define UHCI0_REG_Q0_WORD1 ( DR_REG_UHCI0_BASE + 0x7C)
#define UHCI0_SEND_Q0_WORD1 0xFFFFFFFF
#define UHCI0_SEND_Q0_WORD1_S 0
#define UHCI0_REG_Q1_WORD0 ( DR_REG_UHCI0_BASE + 0x80)
#define UHCI0_SEND_Q1_WORD0 0xFFFFFFFF
#define UHCI0_SEND_Q1_WORD0_S 0
#define UHCI0_REG_Q1_WORD1 ( DR_REG_UHCI0_BASE + 0x84)
#define UHCI0_SEND_Q1_WORD1 0xFFFFFFFF
#define UHCI0_SEND_Q1_WORD1_S 0
#define UHCI0_REG_Q2_WORD0 ( DR_REG_UHCI0_BASE + 0x88)
#define UHCI0_SEND_Q2_WORD0 0xFFFFFFFF
#define UHCI0_SEND_Q2_WORD0_S 0
#define UHCI0_REG_Q2_WORD1 ( DR_REG_UHCI0_BASE + 0x8C)
#define UHCI0_SEND_Q2_WORD1 0xFFFFFFFF
#define UHCI0_SEND_Q2_WORD1_S 0
#define UHCI0_REG_Q3_WORD0 ( DR_REG_UHCI0_BASE + 0x90)
#define UHCI0_SEND_Q3_WORD0 0xFFFFFFFF
#define UHCI0_SEND_Q3_WORD0_S 0
#define UHCI0_REG_Q3_WORD1 ( DR_REG_UHCI0_BASE + 0x94)
#define UHCI0_SEND_Q3_WORD1 0xFFFFFFFF
#define UHCI0_SEND_Q3_WORD1_S 0
#define UHCI0_REG_Q4_WORD0 ( DR_REG_UHCI0_BASE + 0x98)
#define UHCI0_SEND_Q4_WORD0 0xFFFFFFFF
#define UHCI0_SEND_Q4_WORD0_S 0
#define UHCI0_REG_Q4_WORD1 ( DR_REG_UHCI0_BASE + 0x9C)
#define UHCI0_SEND_Q4_WORD1 0xFFFFFFFF
#define UHCI0_SEND_Q4_WORD1_S 0
#define UHCI0_REG_Q5_WORD0 ( DR_REG_UHCI0_BASE + 0xA0)
#define UHCI0_SEND_Q5_WORD0 0xFFFFFFFF
#define UHCI0_SEND_Q5_WORD0_S 0
#define UHCI0_REG_Q5_WORD1 ( DR_REG_UHCI0_BASE + 0xA4)
#define UHCI0_SEND_Q5_WORD1 0xFFFFFFFF
#define UHCI0_SEND_Q5_WORD1_S 0
#define UHCI0_REG_Q6_WORD0 ( DR_REG_UHCI0_BASE + 0xA8)
#define UHCI0_SEND_Q6_WORD0 0xFFFFFFFF
#define UHCI0_SEND_Q6_WORD0_S 0
#define UHCI0_REG_Q6_WORD1 ( DR_REG_UHCI0_BASE + 0xAC)
#define UHCI0_SEND_Q6_WORD1 0xFFFFFFFF
#define UHCI0_SEND_Q6_WORD1_S 0
#define UHCI0_ESC_CONF0 ( DR_REG_UHCI0_BASE + 0xB0)
#define UHCI0_SEPER_ESC_CHAR1 0x000000FF
#define UHCI0_SEPER_ESC_CHAR1_S 16
#define UHCI0_SEPER_ESC_CHAR0 0x000000FF
#define UHCI0_SEPER_ESC_CHAR0_S 8
#define UHCI0_SEPER_CHAR 0x000000FF
#define UHCI0_SEPER_CHAR_S 0
#define UHCI0_ESC_CONF1 ( DR_REG_UHCI0_BASE + 0xB4)
#define UHCI0_ESC_SEQ0_CHAR1 0x000000FF
#define UHCI0_ESC_SEQ0_CHAR1_S 16
#define UHCI0_ESC_SEQ0_CHAR0 0x000000FF
#define UHCI0_ESC_SEQ0_CHAR0_S 8
#define UHCI0_ESC_SEQ0 0x000000FF
#define UHCI0_ESC_SEQ0_S 0
#define UHCI0_ESC_CONF2 ( DR_REG_UHCI0_BASE + 0xB8)
#define UHCI0_ESC_SEQ1_CHAR1 0x000000FF
#define UHCI0_ESC_SEQ1_CHAR1_S 16
#define UHCI0_ESC_SEQ1_CHAR0 0x000000FF
#define UHCI0_ESC_SEQ1_CHAR0_S 8
#define UHCI0_ESC_SEQ1 0x000000FF
#define UHCI0_ESC_SEQ1_S 0
#define UHCI0_ESC_CONF3 ( DR_REG_UHCI0_BASE + 0xBC)
#define UHCI0_ESC_SEQ2_CHAR1 0x000000FF
#define UHCI0_ESC_SEQ2_CHAR1_S 16
#define UHCI0_ESC_SEQ2_CHAR0 0x000000FF
#define UHCI0_ESC_SEQ2_CHAR0_S 8
#define UHCI0_ESC_SEQ2 0x000000FF
#define UHCI0_ESC_SEQ2_S 0
#define UHCI0_PKT_THRES ( DR_REG_UHCI0_BASE + 0xC0)
#define UHCI0_PKT_THRS 0x00001FFF
#define UHCI0_PKT_THRS_S 0
#define UHCI0_DATA ( DR_REG_UHCI0_BASE + 0xFC)
#define UHCI0_UHCI_DATA 0xFFFFFFFF
#define UHCI0_UHCI_DATA_S 0
#endif /* _SOC_UHCI0_REG_H_ */

1260
components/esp32/include/soc/uhci_reg.h Normal file
View file

File diff suppressed because it is too large Load diff

2
components/freertos/gdbstub.c
View file

@ -21,7 +21,7 @@
//ToDo: Clean up includes and sync to real rtos
#include "rom/ets_sys.h"
#include "soc/uart_register.h"
#include "soc/uart_reg.h"
#include "soc/io_mux_reg.h"
#include "gdbstub.h"

18
components/freertos/panic.c
View file

@ -21,7 +21,7 @@
#include "freertos/task.h"
#include "freertos/xtensa_api.h"
#include "soc/uart_register.h"
#include "soc/uart_reg.h"
#include "soc/io_mux_reg.h"
#include "soc/dport_reg.h"
#include "soc/rtc_cntl_reg.h"
@ -105,16 +105,16 @@ void commonErrorHandler(XtExcFrame *frame);
static void haltOtherCore() {
if (xPortGetCoreID()==0) {
//Kill app cpu
CLEAR_PERI_REG_MASK(RTC_OPTIONS0, RTC_CNTL_SW_STALL_APPCPU_C1<<RTC_CNTL_SW_STALL_APPCPU_C1_S);
SET_PERI_REG_MASK(RTC_OPTIONS0, 0x21<<RTC_CNTL_SW_STALL_APPCPU_C1_S);
CLEAR_PERI_REG_MASK(RTC_SW_CPU_STALL, RTC_CNTL_SW_STALL_APPCPU_C0<<RTC_CNTL_SW_STALL_APPCPU_C0_S);
SET_PERI_REG_MASK(RTC_SW_CPU_STALL, 2<<RTC_CNTL_SW_STALL_APPCPU_C0_S);
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_APPCPU_C1<<RTC_CNTL_SW_STALL_APPCPU_C1_S);
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, 0x21<<RTC_CNTL_SW_STALL_APPCPU_C1_S);
CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_APPCPU_C0<<RTC_CNTL_SW_STALL_APPCPU_C0_S);
SET_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, 2<<RTC_CNTL_SW_STALL_APPCPU_C0_S);
} else {
//Kill pro cpu
CLEAR_PERI_REG_MASK(RTC_OPTIONS0, RTC_CNTL_SW_STALL_PROCPU_C1<<RTC_CNTL_SW_STALL_PROCPU_C1_S);
SET_PERI_REG_MASK(RTC_OPTIONS0, 0x21<<RTC_CNTL_SW_STALL_PROCPU_C1_S);
CLEAR_PERI_REG_MASK(RTC_SW_CPU_STALL, RTC_CNTL_SW_STALL_PROCPU_C0<<RTC_CNTL_SW_STALL_PROCPU_C0_S);
SET_PERI_REG_MASK(RTC_SW_CPU_STALL, 2<<RTC_CNTL_SW_STALL_PROCPU_C0_S);
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_PROCPU_C1<<RTC_CNTL_SW_STALL_PROCPU_C1_S);
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, 0x21<<RTC_CNTL_SW_STALL_PROCPU_C1_S);
CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_PROCPU_C0<<RTC_CNTL_SW_STALL_PROCPU_C0_S);
SET_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, 2<<RTC_CNTL_SW_STALL_PROCPU_C0_S);
}
}

20
components/spi_flash/esp_spi_flash.c
View file

@ -245,17 +245,17 @@ static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t* saved_st
{
uint32_t ret = 0;
if (cpuid == 0) {
ret |= GET_PERI_REG_BITS2(PRO_CACHE_CTRL1_REG, cache_mask, 0);
while (GET_PERI_REG_BITS2(PRO_DCACHE_DBUG_REG0, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) {
ret |= GET_PERI_REG_BITS2(DPORT_PRO_CACHE_CTRL1_REG, cache_mask, 0);
while (GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) {
;
}
SET_PERI_REG_BITS(PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S);
SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S);
} else {
ret |= GET_PERI_REG_BITS2(APP_CACHE_CTRL1_REG, cache_mask, 0);
while (GET_PERI_REG_BITS2(APP_DCACHE_DBUG_REG0, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1) {
ret |= GET_PERI_REG_BITS2(DPORT_APP_CACHE_CTRL1_REG, cache_mask, 0);
while (GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1) {
;
}
SET_PERI_REG_BITS(APP_CACHE_CTRL_REG, 1, 0, DPORT_APP_CACHE_ENABLE_S);
SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 0, DPORT_APP_CACHE_ENABLE_S);
}
*saved_state = ret;
}
@ -263,10 +263,10 @@ static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t* saved_st
static void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state)
{
if (cpuid == 0) {
SET_PERI_REG_BITS(PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S);
SET_PERI_REG_BITS(PRO_CACHE_CTRL1_REG, cache_mask, saved_state, 0);
SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S);
SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL1_REG, cache_mask, saved_state, 0);
} else {
SET_PERI_REG_BITS(APP_CACHE_CTRL_REG, 1, 1, DPORT_APP_CACHE_ENABLE_S);
SET_PERI_REG_BITS(APP_CACHE_CTRL1_REG, cache_mask, saved_state, 0);
SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 1, DPORT_APP_CACHE_ENABLE_S);
SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL1_REG, cache_mask, saved_state, 0);
}
}