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OVMS3-idf/components/soc/esp32/include/soc/soc.h

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soc: allow REG_SET_FIELD to be used with single-bit fields
2017-04-18 04:09:19 +00:00
// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
Initial public version
2016-08-17 15:08:22 +00:00
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
soc: allow REG_SET_FIELD to be used with single-bit fields
2017-04-18 04:09:19 +00:00
//
Initial public version
2016-08-17 15:08:22 +00:00
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ESP32_SOC_H_
#define _ESP32_SOC_H_
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#ifndef __ASSEMBLER__
Initial public version
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#include <stdint.h>
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
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#include "esp_assert.h"
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#endif
Initial public version
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//Register Bits{{
#define BIT31 0x80000000
#define BIT30 0x40000000
#define BIT29 0x20000000
#define BIT28 0x10000000
#define BIT27 0x08000000
#define BIT26 0x04000000
#define BIT25 0x02000000
#define BIT24 0x01000000
#define BIT23 0x00800000
#define BIT22 0x00400000
#define BIT21 0x00200000
#define BIT20 0x00100000
#define BIT19 0x00080000
#define BIT18 0x00040000
#define BIT17 0x00020000
#define BIT16 0x00010000
#define BIT15 0x00008000
#define BIT14 0x00004000
#define BIT13 0x00002000
#define BIT12 0x00001000
#define BIT11 0x00000800
#define BIT10 0x00000400
#define BIT9 0x00000200
#define BIT8 0x00000100
#define BIT7 0x00000080
#define BIT6 0x00000040
#define BIT5 0x00000020
#define BIT4 0x00000010
#define BIT3 0x00000008
#define BIT2 0x00000004
#define BIT1 0x00000002
#define BIT0 0x00000001
//}}
Only modify headers in soc/ . Pass compiling under esp-idf-tests/merge_soc_tmp/merge_for_soc_headers branch.(only change some names of register and INUM).
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#define PRO_CPU_NUM (0)
#define APP_CPU_NUM (1)
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
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/* Overall memory map */
#define SOC_IROM_LOW 0x400D0000
#define SOC_IROM_HIGH 0x40400000
#define SOC_DROM_LOW 0x3F400000
#define SOC_DROM_HIGH 0x3F800000
#define SOC_RTC_IRAM_LOW 0x400C0000
#define SOC_RTC_IRAM_HIGH 0x400C2000
#define SOC_RTC_DATA_LOW 0x50000000
#define SOC_RTC_DATA_HIGH 0x50002000
Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet.
2017-07-20 08:26:35 +00:00
#define SOC_EXTRAM_DATA_LOW 0x3F800000
#define SOC_EXTRAM_DATA_HIGH 0x3FC00000
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
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#define DR_REG_DPORT_BASE 0x3ff00000
esp32 hwcrypto: Use AES registers directly
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#define DR_REG_AES_BASE 0x3ff01000
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
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#define DR_REG_RSA_BASE 0x3ff02000
#define DR_REG_SHA_BASE 0x3ff03000
esp32: add protection for DPORT registers of RSA
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#define DR_REG_DPORT_END 0x3ff03FFC
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
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#define DR_REG_UART_BASE 0x3ff40000
#define DR_REG_SPI1_BASE 0x3ff42000
#define DR_REG_SPI0_BASE 0x3ff43000
#define DR_REG_GPIO_BASE 0x3ff44000
#define DR_REG_GPIO_SD_BASE 0x3ff44f00
#define DR_REG_FE2_BASE 0x3ff45000
#define DR_REG_FE_BASE 0x3ff46000
#define DR_REG_FRC_TIMER_BASE 0x3ff47000
#define DR_REG_RTCCNTL_BASE 0x3ff48000
#define DR_REG_RTCIO_BASE 0x3ff48400
#define DR_REG_SENS_BASE 0x3ff48800
#define DR_REG_IO_MUX_BASE 0x3ff49000
#define DR_REG_RTCMEM0_BASE 0x3ff61000
#define DR_REG_RTCMEM1_BASE 0x3ff62000
#define DR_REG_RTCMEM2_BASE 0x3ff63000
#define DR_REG_SYSCON_BASE 0x3ff66000
#define DR_REG_HINF_BASE 0x3ff4B000
#define DR_REG_UHCI1_BASE 0x3ff4C000
#define DR_REG_I2S_BASE 0x3ff4F000
#define DR_REG_UART1_BASE 0x3ff50000
#define DR_REG_BT_BASE 0x3ff51000
#define DR_REG_I2C_EXT_BASE 0x3ff53000
#define DR_REG_UHCI0_BASE 0x3ff54000
#define DR_REG_SLCHOST_BASE 0x3ff55000
#define DR_REG_RMT_BASE 0x3ff56000
#define DR_REG_PCNT_BASE 0x3ff57000
#define DR_REG_SLC_BASE 0x3ff58000
#define DR_REG_LEDC_BASE 0x3ff59000
#define DR_REG_EFUSE_BASE 0x3ff5A000
#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000
#define DR_REG_NRX_BASE 0x3ff5CC00
#define DR_REG_BB_BASE 0x3ff5D000
#define DR_REG_PWM_BASE 0x3ff5E000
#define DR_REG_TIMERGROUP0_BASE 0x3ff5F000
#define DR_REG_TIMERGROUP1_BASE 0x3ff60000
#define DR_REG_SPI2_BASE 0x3ff64000
#define DR_REG_SPI3_BASE 0x3ff65000
#define DR_REG_APB_CTRL_BASE 0x3ff66000
#define DR_REG_I2C1_EXT_BASE 0x3ff67000
#define DR_REG_SDMMC_BASE 0x3ff68000
#define DR_REG_EMAC_BASE 0x3ff69000
#define DR_REG_PWM1_BASE 0x3ff6C000
#define DR_REG_I2S1_BASE 0x3ff6D000
#define DR_REG_UART2_BASE 0x3ff6E000
#define DR_REG_PWM2_BASE 0x3ff6F000
#define DR_REG_PWM3_BASE 0x3ff70000
Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet.
2017-07-20 08:26:35 +00:00
#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
Initial public version
2016-08-17 15:08:22 +00:00
//Registers Operation {{
#define ETS_UNCACHED_ADDR(addr) (addr)
#define ETS_CACHED_ADDR(addr) (addr)
esp32: make soc header compatible with assembler
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#ifndef __ASSEMBLER__
Initial public version
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#define BIT(nr) (1UL << (nr))
esp32: make soc header compatible with assembler
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#else
#define BIT(nr) (1 << (nr))
add detection of invalid cache access - fix level 4 interrupt vectors to produce correct backtrace - initialize invalid cache access interrupt on startup - handle invalid cache access in panic handler
2017-03-09 12:50:39 +00:00
#endif
Initial public version
2016-08-17 15:08:22 +00:00
add detection of invalid cache access - fix level 4 interrupt vectors to produce correct backtrace - initialize invalid cache access interrupt on startup - handle invalid cache access in panic handler
2017-03-09 12:50:39 +00:00
#ifndef __ASSEMBLER__
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
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#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END)
#if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_FREERTOS_UNICORE ) && defined( ESP_PLATFORM )
#define ASSERT_IF_DPORT_REG(_r, OP) TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP));
#else
#define ASSERT_IF_DPORT_REG(_r, OP)
#endif
add comments to register read/write operations
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//write value to register
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
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#define REG_WRITE(_r, _v) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_WRITE); \
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
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(*(volatile uint32_t *)(_r)) = (_v); \
})
add comments to register read/write operations
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//read value from register
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
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#define REG_READ(_r) ({ \
ASSERT_IF_DPORT_REG((_r), REG_READ); \
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(*(volatile uint32_t *)(_r)); \
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
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})
Initial public version
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add comments to register read/write operations
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//get bit or get bits from register
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define REG_GET_BIT(_r, _b) ({ \
ASSERT_IF_DPORT_REG((_r), REG_GET_BIT); \
(*(volatile uint32_t*)(_r) & (_b)); \
})
add comments to register read/write operations
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//set bit or set bits to register
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
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#define REG_SET_BIT(_r, _b) ({ \
ASSERT_IF_DPORT_REG((_r), REG_SET_BIT); \
(*(volatile uint32_t*)(_r) |= (_b)); \
})
add comments to register read/write operations
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//clear bit or clear bits of register
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
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#define REG_CLR_BIT(_r, _b) ({ \
ASSERT_IF_DPORT_REG((_r), REG_CLR_BIT); \
(*(volatile uint32_t*)(_r) &= ~(_b)); \
})
add comments to register read/write operations
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//set bits of register controlled by mask
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define REG_SET_BITS(_r, _b, _m) ({ \
ASSERT_IF_DPORT_REG((_r), REG_SET_BITS); \
(*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))); \
})
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
Flash encryption: Support enabling flash encryption in bootloader, app support * App access functions are all flash encryption-aware * Documentation for flash encryption * Partition read/write is flash aware * New encrypted write function
2016-11-11 06:00:34 +00:00
//get field from register, uses field _S & _V to determine mask
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define REG_GET_FIELD(_r, _f) ({ \
ASSERT_IF_DPORT_REG((_r), REG_GET_FIELD); \
((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \
})
add comments to register read/write operations
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soc: allow REG_SET_FIELD to be used with single-bit fields
2017-04-18 04:09:19 +00:00
//set field of a register from variable, uses field _S & _V to determine mask
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define REG_SET_FIELD(_r, _f, _v) ({ \
ASSERT_IF_DPORT_REG((_r), REG_SET_FIELD); \
(REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))); \
})
add comments to register read/write operations
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//get field value from a variable, used when _f is not left shifted by _f##_S
Initial public version
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#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
add comments to register read/write operations
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//get field value from a variable, used when _f is left shifted by _f##_S
Initial public version
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#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
add comments to register read/write operations
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//set field value to a variable, used when _f is not left shifted by _f##_S
Initial public version
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#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
add comments to register read/write operations
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//set field value to a variable, used when _f is left shifted by _f##_S
Initial public version
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#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
add comments to register read/write operations
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//generate a value from a field value, used when _f is not left shifted by _f##_S
Initial public version
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#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
add comments to register read/write operations
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//generate a value from a field value, used when _f is left shifted by _f##_S
#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
Initial public version
2016-08-17 15:08:22 +00:00
add comments to register read/write operations
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//read value from register
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define READ_PERI_REG(addr) ({ \
ASSERT_IF_DPORT_REG((addr), READ_PERI_REG); \
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \
})
add comments to register read/write operations
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//write value to register
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define WRITE_PERI_REG(addr, val) ({ \
ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG); \
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \
})
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//clear bits of register controlled by mask
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define CLEAR_PERI_REG_MASK(reg, mask) ({ \
ASSERT_IF_DPORT_REG((reg), CLEAR_PERI_REG_MASK); \
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \
})
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//set bits of register controlled by mask
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define SET_PERI_REG_MASK(reg, mask) ({ \
ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_MASK); \
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \
})
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//get bits of register controlled by mask
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define GET_PERI_REG_MASK(reg, mask) ({ \
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK); \
(READ_PERI_REG(reg) & (mask)); \
})
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//get bits of register controlled by highest bit and lowest bit
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS); \
((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \
})
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//set bits of register controlled by mask and shift
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({ \
ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_BITS); \
(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )); \
})
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//get field of register
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS2); \
((READ_PERI_REG(reg)>>(shift))&(mask)); \
})
Initial public version
2016-08-17 15:08:22 +00:00
add detection of invalid cache access - fix level 4 interrupt vectors to produce correct backtrace - initialize invalid cache access interrupt on startup - handle invalid cache access in panic handler
2017-03-09 12:50:39 +00:00
#endif /* !__ASSEMBLER__ */
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
//}}
add detection of invalid cache access - fix level 4 interrupt vectors to produce correct backtrace - initialize invalid cache access interrupt on startup - handle invalid cache access in panic handler
2017-03-09 12:50:39 +00:00
Initial public version
2016-08-17 15:08:22 +00:00
//Periheral Clock {{
Add API for random number generator
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#define APB_CLK_FREQ_ROM ( 26*1000000 )
Initial public version
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#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define CPU_CLK_FREQ APB_CLK_FREQ
Add API for random number generator
2016-11-21 14:59:46 +00:00
#define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz
Initial public version
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#define UART_CLK_FREQ APB_CLK_FREQ
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
#define WDT_CLK_FREQ APB_CLK_FREQ
Initial public version
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#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16
#define SPI_CLK_DIV 4
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
#define TICKS_PER_US_ROM 26 // CPU is 80MHz
Initial public version
2016-08-17 15:08:22 +00:00
//}}
heap: Add new multi_heap heap implementation to replace FreeRTOS-based tagged heaps
2017-04-28 04:08:58 +00:00
/* Overall memory map */
feat(log): add new function to log buffer with level and hex dump.
2017-08-21 14:03:53 +00:00
#define SOC_DROM_LOW 0x3F400000
#define SOC_DROM_HIGH 0x3F800000
heap: Add new multi_heap heap implementation to replace FreeRTOS-based tagged heaps
2017-04-28 04:08:58 +00:00
#define SOC_IROM_LOW 0x400D0000
#define SOC_IROM_HIGH 0x40400000
#define SOC_IRAM_LOW 0x40080000
#define SOC_IRAM_HIGH 0x400A0000
#define SOC_RTC_IRAM_LOW 0x400C0000
#define SOC_RTC_IRAM_HIGH 0x400C2000
#define SOC_RTC_DATA_LOW 0x50000000
#define SOC_RTC_DATA_HIGH 0x50002000
heap: Refactor heap regions/capabilities out of FreeRTOS Remove tagged heap API, rename caps_xxx to heap_caps_xxx Also includes additional heap_caps_xxx inspection functions.
2017-05-03 08:03:28 +00:00
//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
#define SOC_DIRAM_IRAM_LOW 0x400A0000
#define SOC_DIRAM_IRAM_HIGH 0x400BFFFC
#define SOC_DIRAM_DRAM_LOW 0x3FFE0000
#define SOC_DIRAM_DRAM_HIGH 0x3FFFFFFC
soc: Move esp_ptr_dma_capable() function to soc_memory_layout.h
2017-05-05 04:16:02 +00:00
// Region of memory accessible via DMA. See esp_ptr_dma_capable().
#define SOC_DMA_LOW 0x3FFAE000
#define SOC_DMA_HIGH 0x40000000
Add logic to make external RAM usable with malloc()
2017-09-22 08:02:39 +00:00
// Region of memory that is byte-accessible. See esp_ptr_byte_accessible().
feat(log): add new function to log buffer with level and hex dump.
2017-08-21 14:03:53 +00:00
#define SOC_BYTE_ACCESSIBLE_LOW 0x3FFAE000
#define SOC_BYTE_ACCESSIBLE_HIGH 0x40000000
Add logic to make external RAM usable with malloc()
2017-09-22 08:02:39 +00:00
//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs (excluding RTC data region, that's checked separately.) See esp_ptr_internal().
#define SOC_MEM_INTERNAL_LOW 0x3F400000
#define SOC_MEM_INTERNAL_HIGH 0x400C2000
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
//Interrupt hardware source table
//This table is decided by hardware, don't touch this.
#define ETS_WIFI_MAC_INTR_SOURCE 0/**< interrupt of WiFi MAC, level*/
#define ETS_WIFI_MAC_NMI_SOURCE 1/**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
#define ETS_WIFI_BB_INTR_SOURCE 2/**< interrupt of WiFi BB, level, we can do some calibartion*/
#define ETS_BT_MAC_INTR_SOURCE 3/**< will be cancelled*/
#define ETS_BT_BB_INTR_SOURCE 4/**< interrupt of BT BB, level*/
#define ETS_BT_BB_NMI_SOURCE 5/**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
#define ETS_RWBT_INTR_SOURCE 6/**< interrupt of RWBT, level*/
#define ETS_RWBLE_INTR_SOURCE 7/**< interrupt of RWBLE, level*/
#define ETS_RWBT_NMI_SOURCE 8/**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
#define ETS_RWBLE_NMI_SOURCE 9/**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
#define ETS_SLC0_INTR_SOURCE 10/**< interrupt of SLC0, level*/
#define ETS_SLC1_INTR_SOURCE 11/**< interrupt of SLC1, level*/
#define ETS_UHCI0_INTR_SOURCE 12/**< interrupt of UHCI0, level*/
#define ETS_UHCI1_INTR_SOURCE 13/**< interrupt of UHCI1, level*/
#define ETS_TG0_T0_LEVEL_INTR_SOURCE 14/**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/
#define ETS_TG0_T1_LEVEL_INTR_SOURCE 15/**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/
#define ETS_TG0_WDT_LEVEL_INTR_SOURCE 16/**< interrupt of TIMER_GROUP0, WATCHDOG, level*/
#define ETS_TG0_LACT_LEVEL_INTR_SOURCE 17/**< interrupt of TIMER_GROUP0, LACT, level*/
#define ETS_TG1_T0_LEVEL_INTR_SOURCE 18/**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/
#define ETS_TG1_T1_LEVEL_INTR_SOURCE 19/**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/
#define ETS_TG1_WDT_LEVEL_INTR_SOURCE 20/**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
#define ETS_TG1_LACT_LEVEL_INTR_SOURCE 21/**< interrupt of TIMER_GROUP1, LACT, level*/
#define ETS_GPIO_INTR_SOURCE 22/**< interrupt of GPIO, level*/
#define ETS_GPIO_NMI_SOURCE 23/**< interrupt of GPIO, NMI*/
Merge branch 'master' into feature/btdm_bluedroid 1.update esptool submodule 2.new esp32 lib and new phy lib 3.new bt lib 4.soc.h add comment
2016-11-01 09:53:59 +00:00
#define ETS_FROM_CPU_INTR0_SOURCE 24/**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
#define ETS_FROM_CPU_INTR1_SOURCE 25/**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
component/esp32 : fix dualcore bug 1. When dual core cpu run access DPORT register, must do protection. 2. If access DPORT register, must use DPORT_REG_READ/DPORT_REG_WRITE and DPORT_XXX register operation macro.
2017-05-08 12:03:04 +00:00
#define ETS_FROM_CPU_INTR2_SOURCE 26/**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
#define ETS_FROM_CPU_INTR3_SOURCE 27/**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
#define ETS_SPI0_INTR_SOURCE 28/**< interrupt of SPI0, level, SPI0 is for Cache Access, do not use this*/
#define ETS_SPI1_INTR_SOURCE 29/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
#define ETS_SPI2_INTR_SOURCE 30/**< interrupt of SPI2, level*/
#define ETS_SPI3_INTR_SOURCE 31/**< interrupt of SPI3, level*/
#define ETS_I2S0_INTR_SOURCE 32/**< interrupt of I2S0, level*/
#define ETS_I2S1_INTR_SOURCE 33/**< interrupt of I2S1, level*/
#define ETS_UART0_INTR_SOURCE 34/**< interrupt of UART0, level*/
#define ETS_UART1_INTR_SOURCE 35/**< interrupt of UART1, level*/
#define ETS_UART2_INTR_SOURCE 36/**< interrupt of UART2, level*/
#define ETS_SDIO_HOST_INTR_SOURCE 37/**< interrupt of SD/SDIO/MMC HOST, level*/
#define ETS_ETH_MAC_INTR_SOURCE 38/**< interrupt of ethernet mac, level*/
#define ETS_PWM0_INTR_SOURCE 39/**< interrupt of PWM0, level, Reserved*/
#define ETS_PWM1_INTR_SOURCE 40/**< interrupt of PWM1, level, Reserved*/
#define ETS_PWM2_INTR_SOURCE 41/**< interrupt of PWM2, level*/
#define ETS_PWM3_INTR_SOURCE 42/**< interruot of PWM3, level*/
#define ETS_LEDC_INTR_SOURCE 43/**< interrupt of LED PWM, level*/
#define ETS_EFUSE_INTR_SOURCE 44/**< interrupt of efuse, level, not likely to use*/
#define ETS_CAN_INTR_SOURCE 45/**< interrupt of can, level*/
#define ETS_RTC_CORE_INTR_SOURCE 46/**< interrupt of rtc core, level, include rtc watchdog*/
#define ETS_RMT_INTR_SOURCE 47/**< interrupt of remote controller, level*/
#define ETS_PCNT_INTR_SOURCE 48/**< interrupt of pluse count, level*/
#define ETS_I2C_EXT0_INTR_SOURCE 49/**< interrupt of I2C controller1, level*/
#define ETS_I2C_EXT1_INTR_SOURCE 50/**< interrupt of I2C controller0, level*/
#define ETS_RSA_INTR_SOURCE 51/**< interrupt of RSA accelerator, level*/
#define ETS_SPI1_DMA_INTR_SOURCE 52/**< interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this*/
#define ETS_SPI2_DMA_INTR_SOURCE 53/**< interrupt of SPI2 DMA, level*/
#define ETS_SPI3_DMA_INTR_SOURCE 54/**< interrupt of SPI3 DMA, level*/
#define ETS_WDT_INTR_SOURCE 55/**< will be cancelled*/
#define ETS_TIMER1_INTR_SOURCE 56/**< will be cancelled*/
#define ETS_TIMER2_INTR_SOURCE 57/**< will be cancelled*/
#define ETS_TG0_T0_EDGE_INTR_SOURCE 58/**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/
#define ETS_TG0_T1_EDGE_INTR_SOURCE 59/**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/
#define ETS_TG0_WDT_EDGE_INTR_SOURCE 60/**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/
#define ETS_TG0_LACT_EDGE_INTR_SOURCE 61/**< interrupt of TIMER_GROUP0, LACT, EDGE*/
#define ETS_TG1_T0_EDGE_INTR_SOURCE 62/**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/
#define ETS_TG1_T1_EDGE_INTR_SOURCE 63/**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/
#define ETS_TG1_WDT_EDGE_INTR_SOURCE 64/**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/
#define ETS_TG1_LACT_EDGE_INTR_SOURCE 65/**< interrupt of TIMER_GROUP0, LACT, EDGE*/
#define ETS_MMU_IA_INTR_SOURCE 66/**< interrupt of MMU Invalid Access, LEVEL*/
#define ETS_MPU_IA_INTR_SOURCE 67/**< interrupt of MPU Invalid Access, LEVEL*/
#define ETS_CACHE_IA_INTR_SOURCE 68/**< interrupt of Cache Invalied Access, LEVEL*/
Initial public version
2016-08-17 15:08:22 +00:00
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
//interrupt cpu using table, Please see the core-isa.h
/*************************************************************************************************************
* Intr num Level Type PRO CPU usage APP CPU uasge
* 0 1 extern level WMAC Reserved
component/bt : change VHCI interrupt type to software interrupt(int no 7)
2017-04-28 09:17:39 +00:00
* 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA
Mark some interrupts that are now allocated dynamically as free, add int handle param documentation, add local ints test
2016-12-08 04:38:22 +00:00
* 2 1 extern level
* 3 1 extern level
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
* 4 1 extern level WBB
component/bt : change VHCI interrupt type to software interrupt(int no 7)
2017-04-28 09:17:39 +00:00
* 5 1 extern level BT/BLE Controller BT/BLE Controller
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
component/bt : change VHCI interrupt type to software interrupt(int no 7)
2017-04-28 09:17:39 +00:00
* 7 1 software BT/BLE VHCI BT/BLE VHCI
* 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX)
Mark some interrupts that are now allocated dynamically as free, add int handle param documentation, add local ints test
2016-12-08 04:38:22 +00:00
* 9 1 extern level
soc: release interrupts which are not reserved by timers any more
2017-08-21 14:29:50 +00:00
* 10 1 extern edge
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
* 11 3 profiling
* 12 1 extern level
* 13 1 extern level
* 14 7 nmi Reserved Reserved
* 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3)
* 16 5 timer
* 17 1 extern level
* 18 1 extern level
* 19 2 extern level
* 20 2 extern level
* 21 2 extern level
soc: release interrupts which are not reserved by timers any more
2017-08-21 14:29:50 +00:00
* 22 3 extern edge
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
* 23 3 extern level
newlib: implement time syscalls
2016-11-02 09:17:28 +00:00
* 24 4 extern level TG1_WDT
add detection of invalid cache access - fix level 4 interrupt vectors to produce correct backtrace - initialize invalid cache access interrupt on startup - handle invalid cache access in panic handler
2017-03-09 12:50:39 +00:00
* 25 4 extern level CACHEERR
Merge panic and dport high level interrupt code to both use int level 4
2017-05-26 09:41:18 +00:00
* 26 5 extern level
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
* 27 3 extern level Reserved Reserved
Merge panic and dport high level interrupt code to both use int level 4
2017-05-26 09:41:18 +00:00
* 28 4 extern edge DPORT ACCESS DPORT ACCESS
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
* 29 3 software Reserved Reserved
* 30 4 extern edge Reserved Reserved
Merge panic and dport high level interrupt code to both use int level 4
2017-05-26 09:41:18 +00:00
* 31 5 extern level
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
*************************************************************************************************************
*/
Initial public version
2016-08-17 15:08:22 +00:00
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
//CPU0 Interrupt number reserved, not touch this.
#define ETS_WMAC_INUM 0
#define ETS_BT_HOST_INUM 1
#define ETS_WBB_INUM 4
#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
newlib: implement time syscalls
2016-11-02 09:17:28 +00:00
#define ETS_FRC1_INUM 22
#define ETS_T1_WDT_INUM 24
add detection of invalid cache access - fix level 4 interrupt vectors to produce correct backtrace - initialize invalid cache access interrupt on startup - handle invalid cache access in panic handler
2017-03-09 12:50:39 +00:00
#define ETS_CACHEERR_INUM 25
Merge panic and dport high level interrupt code to both use int level 4
2017-05-26 09:41:18 +00:00
#define ETS_DPORT_INUM 28
Initial public version
2016-08-17 15:08:22 +00:00
newlib: implement time syscalls
2016-11-02 09:17:28 +00:00
//CPU0 Interrupt number used in ROM, should be cancelled in SDK
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
#define ETS_SLC_INUM 1
#define ETS_UART0_INUM 5
#define ETS_UART1_INUM 5
Only modify headers in soc/ . Pass compiling under esp-idf-tests/merge_soc_tmp/merge_for_soc_headers branch.(only change some names of register and INUM).
2016-09-13 15:02:03 +00:00
//Other interrupt number should be managed by the user
Initial public version
2016-08-17 15:08:22 +00:00
component/bt : fix interrupt number conflict 1. the typical problem is when push keyboard on serial tool, the bluetooth may stop.
2017-06-15 09:20:25 +00:00
//Invalid interrupt for number interrupt matrix
#define ETS_INVALID_INUM 6
Initial public version
2016-08-17 15:08:22 +00:00
#endif /* _ESP32_SOC_H_ */
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