Commit graph

780 commits

Author SHA1 Message Date
Jeroen Domburg 0faa881470 Add fundamental newlib routines (memcpy etc) to IRAM 2017-05-16 14:12:07 +08:00
Jeroen Domburg 68ef6723bb Fix lib picking, revert non-workaround libs to whatever is in master to hopefully make later merging easier. 2017-05-16 14:12:07 +08:00
Jeroen Domburg 3b07fcebb6 Fix rebase artifacts 2017-05-16 14:12:06 +08:00
Jeroen Domburg 363e595c60 Do not forget to add files 2017-05-16 14:12:06 +08:00
Jeroen Domburg 4918907257 Add psram workaround newlib versions, add some documentation 2017-05-16 14:12:04 +08:00
Jeroen Domburg afd10b982b Recompiled newlib to make memmove use the workaround 2017-05-16 14:11:01 +08:00
Jeroen Domburg 754f574aab Rebasing to latest master 2017-05-16 14:10:59 +08:00
Jeroen Domburg c46d7e60b0 Also add cache mode choice to menuconfig 2017-05-16 13:14:32 +08:00
Jeroen Domburg 4fd173c8c3 Add option for memory barriers everywhere 2017-05-16 13:14:32 +08:00
Jeroen Domburg 58e8763874 Move debug exception vector to vector_defaults.S 2017-05-16 13:14:32 +08:00
Jeroen Domburg 202a5db2d2 Rework high interrupt code to be able to link to external handlers; add psram test that swarms cpu with interrupts 2017-05-16 13:14:30 +08:00
Jeroen Domburg b63921a99c Add option to enable compiler psram workaround. Needs custom crosstool. 2017-05-16 13:13:01 +08:00
Jeroen Domburg d970307120 Change default mode to low/high for dualcore 2017-05-16 13:13:01 +08:00
Jeroen Domburg bbb1820501 Do not mark SPI ram as DMA-capable 2017-05-16 13:13:01 +08:00
Jeroen Domburg c09ba35d3b Fix int level 4 panics to give a correct backtrace. Add cache invalid access interrupt to panic handler reasons and wire it up to panic(). Fix issue where cache was re-enabled for pro cpu and pro cpu continuing execution while cache was still disabled on app cpu. 2017-05-16 13:13:01 +08:00
Jeroen Domburg c9a7d21068 Fix intlvl 4 stuff to give a correct backtrace; add cache invalid access to intlvl4 2017-05-16 13:13:01 +08:00
Jeroen Domburg e954277d7b Fix up tests for stack not in psram on flash, add small testcase 2017-05-16 13:12:59 +08:00
Jeroen Domburg 6e992cc6cc Get rid of superfluous printf 2017-05-16 13:11:59 +08:00
Jeroen Domburg 671787a966 After rebasing, it was found out that flushing the cache drops the writeback-pending psram cache lines on the ground. We now evict these by reading 64/128K of memory before flushing the cache. Also fixes a snafu in psram cache mode (inverted hi/lo and even/odd selectors) as well as an option to not let the heap allocator touch the psram. 2017-05-16 13:11:59 +08:00
Wangjialin 8af42554ba remove unused codes in psram driver 2017-05-16 13:11:58 +08:00
Wangjialin 34d9cf4f00 update psram driver:
1. fix init error after system restart
2. use MACROs for GPIO definition and psram id.
3. format the code
2017-05-16 13:11:58 +08:00
Jeroen Domburg 39d9882be9 More MR comment fixes 2017-05-16 13:11:58 +08:00
Jeroen Domburg da1ef5da03 Maybe I should try to compile before commit/push... 2017-05-16 13:11:58 +08:00
Jeroen Domburg 84b728e7fd Some fixes to MR comments 2017-05-16 13:11:58 +08:00
Jeroen Domburg b3a526536c Fix warnings for test 2017-05-16 13:11:58 +08:00
Jeroen Domburg fe3082fa98 Do not declare test_spiram when option is disabled 2017-05-16 13:11:58 +08:00
Jeroen Domburg 0049b918b4 Fix psram silicon bug test; clean up Kconfig mess, clean out psram unused functions warnings 2017-05-16 13:11:56 +08:00
Jeroen Domburg c6d01c2bd2 Fix dualcore PSRAM. 2017-05-16 13:11:30 +08:00
Jeroen Domburg c9a2463f3b Add Doom psram test, fix free_heap_size/minimum_ever_heap_size calls to also understand combinations of caps, add psram support to allocator. At the moment, psram only works for the first core because of some funny business in the MMU of the 2nd core. 2017-05-16 13:10:52 +08:00
Jeroen Domburg 10402186bc Add internal memory capability to heap alloc, add some PSRAM tests 2017-05-16 13:09:50 +08:00
Jeroen Domburg 15012589a5 Psram driver cleanup: remove DMA and test functions, tabs to spaces, add copyright header 2017-05-16 13:08:31 +08:00
Wangjialin 0a88301fce update psram example files
1. update psram code
2. add missing files
3. add psram example
4. add mmu and psram init
2017-05-16 13:08:28 +08:00
Jiang Jiang Jian 1e0710f1b2 Merge branch 'bugfix/bt_acl_tx' into 'master'
components/bt: update libbtdm.a with a bugfix for an assertion failure when ACL-…

…U transmission is resumed

See merge request !755
2017-05-12 18:23:20 +08:00
Jiang Jiang Jian a6608648db Merge branch 'driver_merge_tmp/mcpwm' into 'master'
feature: Motor Control PWM(mcpwm) driver and examples



See merge request !698
2017-05-12 18:21:38 +08:00
Jiang Jiang Jian bb25ac91f4 Merge branch 'bugfix/dualcore' into 'master'
component/soc: fix register access protection missing

- fix dport register access protection missing
- add rom function protect
- add normal register function check

See merge request !747
2017-05-12 18:19:31 +08:00
wangmengyang 23965694b1 components/bt: update libbtdm.a with a bugfix for an assertion failure when ACL-U transmission is resumed 2017-05-12 17:53:25 +08:00
Kewal M Shah 2008f4d88c feature: add Motor Control PWM(mcpwm) driver
1. Name change from chopper to carrier, block diagram update, minor changes to example codes
2. mcpwm_reg.h changed, brought uniformity in comments, worked on suggestions, duty to accept float. Some name changes!
3. Minor readme changes and Indetation
4. Minor change:  move mcpwm_reg.h and mcpwm_struct.h to new path
5. Minor change: addition of BLDC example code and Readme
6. Name changed from epwm to mcpwm
7. Improve the reg name in mcpwm_struct.h
8. Name change chopper>carrier, deadband>deadtime
2017-05-12 15:47:59 +08:00
Tian Hao 377a1f5ea1 component/esp32 : do more fix of dualcore bug
1. the cache API in romcode will access DPORT register, so protect it.
2. fix STALL spelling.
3. check dport access by non-dport access function
2017-05-12 15:41:51 +08:00
Liu Zhi Fu dc78c55f61 esp32: update wifi lib to enlarge wifi task stack size
1. Enlarge wifi task stack size by 512Bytes to fix potential stack overflow issue
2. Modify wifi hmac tx queue size from 12 to 32 because we already limit the buffer number in ebuf
   management module
2017-05-12 09:36:41 +08:00
Ivan Grokhotkov 15a6145961 Merge branch 'feature/get_chip_ver' into 'master'
add API to get chip info

This change adds an API to get chip info, such as chip model, enabled capabilities, size of embedded flash, silicon revision.

Hello_world example is modified to print out the information about the chip. The example is also simplified by moving all code into the main task.

Ref TW12031.

See merge request !549
2017-05-11 12:05:55 +08:00
Ivan Grokhotkov 67b08c20ec Merge branch 'bugfix/update_wifi_lib_for_some_bugs' into 'master'
esp32: update wifi lib for some bugfix

1. Fix wifi ebuf free twice issue
2. Fix wifi internal assert issue
3. Fix a bug in esp_wifi_stop
4. Fix wifi crash issue
5. Fix wifi run out of memory when 10 udp connection stability test

See merge request !745
2017-05-11 12:02:50 +08:00
Ivan Grokhotkov c742f7d860 Merge branch 'feature/base_mac_address' into 'master'
Optimize configuration of base MAC address

Application developer can call APIs to configure base MAC address
instead of using menuconfig.

See merge request !744
2017-05-11 12:01:51 +08:00
Liu Zhi Fu 4235b4c13e esp32: update wifi lib for some bugfix
1. Fix wifi ebuf free twice issue
2. Fix wifi internal assert issue
3. Fix a bug in esp_wifi_stop
4. Fix wifi crash issue
5. Fix 10 UDP connection test out of memory issue
2017-05-11 11:30:08 +08:00
Jiang Jiang Jian c518325385 Merge branch 'bugfix/dualcore_dport' into 'master'
component/esp32 : fix dualcore bug

1. When dual core cpu run access DPORT register, must do protection.
2. If access DPORT register, must use DPORT_REG_READ/DPORT_REG_WRITE and DPORT_XXX register operation macro.

See merge request !742
2017-05-10 11:27:01 +08:00
XiaXiaotian b22067a8f0 Optimize configuration of base MAC address
Application developer can call APIs to configure base MAC address
    instead of using menuconfig.
2017-05-10 10:15:07 +08:00
Tian Hao 26a3cb93c7 component/soc : move dport access header files to soc
1. move dport access header files to soc
2. reduce dport register write protection. Only protect read operation
2017-05-09 18:06:00 +08:00
Tian Hao f7e8856520 component/esp32 : fix dualcore bug
1. When dual core cpu run access DPORT register, must do protection.
2. If access DPORT register, must use DPORT_REG_READ/DPORT_REG_WRITE and DPORT_XXX register operation macro.
2017-05-08 21:53:43 +08:00
Jeroen Domburg a41ac2d21d Merge branch 'bugfix/spi_example' into 'master'
SPI: Various fixes (examples, mem leak, arg check)

- Fix SPI master example to use DMA-capable memory for display initialization. Fixes https://github.com/espressif/esp-idf/issues/551
- SPI master: Do not leak DMA descriptor pointer array on free
- SPI Master/Slave: Check if DMA'ed buffers actually live in DMA-capable memory



See merge request !735
2017-05-08 17:28:55 +08:00
Ivan Grokhotkov 2260c714e7 add esp_chip_info API 2017-05-05 17:28:30 +08:00
Jiang Jiang Jian a7847dbec9 Merge branch 'bugfix/bt_sniff_mode' into 'master'
component/bt: fix some bugs related to bluetooth sniff mode in controller

1. fix some bugs in bluetooth sniff mode in controller
2. export some symbols to esp32.rom.ld including functions and global variables in ROM code
3. update libbtdm.a which includes "IRAM_ATTR" addition or removal for some functions

See merge request !729
2017-05-05 16:27:37 +08:00