Fix dualcore PSRAM.
This commit is contained in:
Jeroen Domburg
parent
c9a2463f3b
commit
c6d01c2bd2
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@ -94,6 +94,13 @@ extern volatile int port_xSchedulerRunning[2];
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static const char* TAG = "cpu_start";
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#if CONFIG_FREERTOS_UNICORE
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#define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
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#else
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#define PSRAM_MODE PSRAM_VADDR_MODE_EVENODD
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#endif
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/*
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* We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
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* and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
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@ -136,11 +143,23 @@ void IRAM_ATTR call_start_cpu0()
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memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start));
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}
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#if CONFIG_MEMMAP_SPIRAM_ENABLE
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if ( psram_enable(PSRAM_CACHE_F40M_S40M, PSRAM_MODE) != ESP_OK) {
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ESP_EARLY_LOGE(TAG, "PSRAM enabled but initialization failed. Bailing out.");
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abort();
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}
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#endif
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ESP_EARLY_LOGI(TAG, "Pro cpu up.");
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#if !CONFIG_FREERTOS_UNICORE
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ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
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//Flush and enable icache for APP CPU
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CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1);
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cache_sram_mmu_set( 1, 0, 0x3f800000, 0, 32, 128 );
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Cache_Flush(1);
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Cache_Read_Enable(1);
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@ -152,6 +171,7 @@ void IRAM_ATTR call_start_cpu0()
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DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
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ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
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while (!app_cpu_started) {
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ets_delay_us(100);
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}
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@ -263,6 +283,8 @@ void start_cpu0_default(void)
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vTaskStartScheduler();
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}
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#if !CONFIG_FREERTOS_UNICORE
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void start_cpu1_default(void)
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{
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@ -270,10 +270,6 @@ void heap_alloc_caps_init() {
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#endif
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#if CONFIG_MEMMAP_SPIRAM_ENABLE
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if ( psram_enable(PSRAM_CACHE_F40M_S40M) != ESP_OK) {
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ESP_EARLY_LOGE(TAG, "PSRAM enabled but initialization failed. Bailing out.");
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abort();
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}
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#if CONFIG_MEMMAP_SPIRAM_TEST
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if (!test_spiram(4*1024*1024)) abort();
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#endif
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@ -10,6 +10,12 @@ typedef enum {
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PSRAM_CACHE_MAX,
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} psram_cache_mode_t;
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esp_err_t psram_enable(psram_cache_mode_t mode);
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typedef enum {
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PSRAM_VADDR_MODE_NORMAL=0,
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PSRAM_VADDR_MODE_LOWHIGH,
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PSRAM_VADDR_MODE_EVENODD,
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} psram_vaddr_mode_t;
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esp_err_t psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode);
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#endif
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@ -71,7 +71,7 @@ typedef struct {
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uint32_t dummyBitLen;
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} psram_cmd_t;
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static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode);
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static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode);
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static void psram_clear_spi_fifo(psram_spi_num_t spiNum)
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@ -642,7 +642,7 @@ void IRAM_ATTR psram_spi_init(psram_spi_num_t spiNum,psram_cache_mode_t mode)
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//psram gpio init , different working frequency we have different solutions
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esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode) //psram init
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esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode) //psram init
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{
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WRITE_PERI_REG(GPIO_ENABLE_W1TC_REG,BIT16|BIT17);//DISALBE OUPUT FOR IO16/17
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@ -713,12 +713,12 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode) //psram init
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return ESP_FAIL;
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}
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psram_enable_qio_mode(PSRAM_SPI_1);
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psram_cache_init(mode);
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psram_cache_init(mode, vaddrmode);
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return ESP_OK;
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}
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//register initialization for sram cache params and r/w commands
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static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode)
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static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode)
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{
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CLEAR_PERI_REG_MASK(SPI_CLOCK_REG(0),SPI_CLK_EQU_SYSCLK_M);
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SET_PERI_REG_BITS(SPI_CLOCK_REG(0),SPI_CLKDIV_PRE_V,0,SPI_CLKDIV_PRE_S);
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@ -781,8 +781,24 @@ static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode)
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SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38, write command value,(0x00 for delay)
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break;
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}
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CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL1_REG , DPORT_PRO_CACHE_MASK_DRAM1);//use Dram1 to visit ext sram.
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CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG , DPORT_PRO_DRAM_HL|DPORT_PRO_DRAM_SPLIT);
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CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG , DPORT_APP_DRAM_HL|DPORT_APP_DRAM_SPLIT);
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if (vaddrmode == PSRAM_VADDR_MODE_LOWHIGH) {
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SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG , DPORT_PRO_DRAM_SPLIT);
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SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG , DPORT_APP_DRAM_SPLIT);
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} else if (vaddrmode == PSRAM_VADDR_MODE_EVENODD) {
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SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG , DPORT_PRO_DRAM_HL);
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SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG , DPORT_APP_DRAM_HL);
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}
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CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL1_REG , DPORT_PRO_CACHE_MASK_DRAM1|DPORT_PRO_CACHE_MASK_OPSDRAM);//use Dram1 to visit ext sram.
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SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CMMU_SRAM_PAGE_MODE, 0, DPORT_PRO_CMMU_SRAM_PAGE_MODE_S); //cache page mode : 1 -->16k 4 -->2k 0-->32k,(accord with the settings in cache_sram_mmu_set)
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CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG , DPORT_APP_CACHE_MASK_DRAM1|DPORT_APP_CACHE_MASK_OPSDRAM);//use Dram1 to visit ext sram.
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SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CMMU_SRAM_PAGE_MODE, 0, DPORT_APP_CMMU_SRAM_PAGE_MODE_S); //cache page mode : 1 -->16k 4 -->2k 0-->32k,(accord with the settings in cache_sram_mmu_set)
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CLEAR_PERI_REG_MASK(SPI_PIN_REG(0), SPI_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
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}
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@ -117,6 +117,11 @@ CONFIG_BASE_MAC_STORED_DEFAULT_EFUSE=y
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# CONFIG_TWO_MAC_ADDRESS_FROM_EFUSE is not set
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CONFIG_FOUR_MAC_ADDRESS_FROM_EFUSE=y
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CONFIG_NUMBER_OF_MAC_ADDRESS_GENERATED_FROM_EFUSE=4
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CONFIG_MEMMAP_SPIRAM_ENABLE=y
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CONFIG_MEMMAP_SPIRAM_TYPE_ESPPSRAM32=y
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CONFIG_MEMMAP_SPIRAM_TEST=y
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CONFIG_MEMMAP_SPIRAM_ENABLE_MALLOC=y
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CONFIG_MEMMAP_SPIRAM_ALLOC_LIMIT_INTERNAL=1024
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CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32
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CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2048
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CONFIG_MAIN_TASK_STACK_SIZE=4096
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@ -130,9 +135,9 @@ CONFIG_CONSOLE_UART_BAUDRATE=115200
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CONFIG_ULP_COPROC_ENABLED=y
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CONFIG_ULP_COPROC_RESERVE_MEM=512
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# CONFIG_ESP32_PANIC_PRINT_HALT is not set
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CONFIG_ESP32_PANIC_PRINT_REBOOT=y
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# CONFIG_ESP32_PANIC_PRINT_REBOOT is not set
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# CONFIG_ESP32_PANIC_SILENT_REBOOT is not set
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# CONFIG_ESP32_PANIC_GDBSTUB is not set
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CONFIG_ESP32_PANIC_GDBSTUB=y
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CONFIG_ESP32_DEBUG_OCDAWARE=y
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CONFIG_INT_WDT=y
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CONFIG_INT_WDT_TIMEOUT_MS=300
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