update psram driver:
1. fix init error after system restart 2. use MACROs for GPIO definition and psram id. 3. format the code
This commit is contained in:
Wangjialin
Jeroen Domburg
parent
39d9882be9
commit
34d9cf4f00
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@ -28,6 +28,7 @@
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#include "rom/spi_flash.h"
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#include "esp_err.h"
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#include "rom/cache.h"
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#include "driver/gpio.h"
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//Commands for PSRAM chip
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#define PSRAM_READ 0x03
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@ -42,6 +43,13 @@
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#define PSRAM_SET_BURST_LEN 0xC0
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#define PSRAM_DEVICE_ID 0x9F
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#define PSRAM_MFG_ID_M 0xff
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#define PSRAM_MFG_ID_S 8
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#define PSRAM_MFG_ID_ESPRESSIF 0x5d
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#define PSRAM_CLK_IO 17
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#define PSRAM_CS_IO 16
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typedef enum {
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PSRAM_SPI_1 = 0x1,
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PSRAM_SPI_2,
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@ -52,7 +60,7 @@ typedef enum {
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static psram_cache_mode_t s_psram_mode = PSRAM_CACHE_MAX;
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//For now, we only use F40M + S40M, and we don't have to go through gpio matrix
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#define GPIO_MATRIX_FOR_40M 0
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#define DISABLE_GPIO_MATRIX_FOR_40M 1
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static int extra_dummy = 0;
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typedef enum {
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@ -74,200 +82,229 @@ typedef struct {
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static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode);
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static void psram_clear_spi_fifo(psram_spi_num_t spiNum)
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static void psram_clear_spi_fifo(psram_spi_num_t spi_num)
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{
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int i;
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for(i=0;i<16;i++){
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WRITE_PERI_REG(SPI_W0_REG(spiNum)+i*4,0);
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for (i = 0; i < 16; i++) {
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WRITE_PERI_REG(SPI_W0_REG(spi_num)+i*4, 0);
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}
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}
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//set basic SPI write mode
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static void psram_set_basic_write_mode(psram_spi_num_t spiNum)
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static void psram_set_basic_write_mode(psram_spi_num_t spi_num)
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{
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spiNum),SPI_FWRITE_QIO);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spiNum),SPI_FWRITE_DIO);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spiNum),SPI_FWRITE_QUAD);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spiNum),SPI_FWRITE_DUAL);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_QIO);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_DIO);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_QUAD);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_DUAL);
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}
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//set QPI write mode
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static void psram_set_qio_write_mode(psram_spi_num_t spiNum)
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static void psram_set_qio_write_mode(psram_spi_num_t spi_num)
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{
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SET_PERI_REG_MASK(SPI_USER_REG(spiNum),SPI_FWRITE_QIO);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spiNum),SPI_FWRITE_DIO);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spiNum),SPI_FWRITE_QUAD);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spiNum),SPI_FWRITE_DUAL);
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SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_QIO);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_DIO);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_QUAD);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_DUAL);
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}
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//set QPI read mode
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static void psram_set_qio_read_mode(psram_spi_num_t spiNum)
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static void psram_set_qio_read_mode(psram_spi_num_t spi_num)
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{
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SET_PERI_REG_MASK(SPI_CTRL_REG(spiNum),SPI_FREAD_QIO);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spiNum),SPI_FREAD_QUAD);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spiNum),SPI_FREAD_DUAL);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spiNum),SPI_FREAD_DIO);
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SET_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_QIO);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_QUAD);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_DUAL);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_DIO);
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}
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//set SPI read mode
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static void psram_set_basic_read_mode(psram_spi_num_t spiNum)
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static void psram_set_basic_read_mode(psram_spi_num_t spi_num)
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{
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spiNum),SPI_FREAD_QIO);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spiNum),SPI_FREAD_QUAD);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spiNum),SPI_FREAD_DUAL);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spiNum),SPI_FREAD_DIO);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_QIO);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_QUAD);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_DUAL);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_DIO);
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}
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//start sending and wait for finishing
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static IRAM_ATTR void psram_cmd_start(psram_spi_num_t spiNum, psram_cmd_mode_t cmd_mode)
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static IRAM_ATTR void psram_cmd_start(psram_spi_num_t spi_num, psram_cmd_mode_t cmd_mode)
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{
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//get cs1
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CLEAR_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS1_DIS_M);
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SET_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS0_DIS_M);
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uint32_t wr_mode_backup = (READ_PERI_REG(SPI_USER_REG(spiNum)) >> SPI_FWRITE_DUAL_S) & 0xf;
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uint32_t rd_mode_backup = READ_PERI_REG(SPI_CTRL_REG(spiNum)) & (SPI_FREAD_DIO_M|SPI_FREAD_DUAL_M|SPI_FREAD_QUAD_M|SPI_FREAD_QIO_M);
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if(cmd_mode == PSRAM_CMD_SPI) {
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psram_set_basic_write_mode(spiNum);
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psram_set_basic_read_mode(spiNum);
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uint32_t wr_mode_backup = (READ_PERI_REG(SPI_USER_REG(spi_num)) >> SPI_FWRITE_DUAL_S) & 0xf;
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uint32_t rd_mode_backup = READ_PERI_REG(SPI_CTRL_REG(spi_num)) & (SPI_FREAD_DIO_M | SPI_FREAD_DUAL_M | SPI_FREAD_QUAD_M | SPI_FREAD_QIO_M);
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if (cmd_mode == PSRAM_CMD_SPI) {
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psram_set_basic_write_mode(spi_num);
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psram_set_basic_read_mode(spi_num);
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} else if (cmd_mode == PSRAM_CMD_QPI) {
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psram_set_qio_write_mode(spiNum);
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psram_set_qio_read_mode(spiNum);
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psram_set_qio_write_mode(spi_num);
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psram_set_qio_read_mode(spi_num);
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}
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//WAIT SPI0 IDLE
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//READ THREE TIMES TO MAKE SURE?
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while( READ_PERI_REG(SPI_EXT2_REG(0))!= 0);
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while( READ_PERI_REG(SPI_EXT2_REG(0))!= 0);
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while( READ_PERI_REG(SPI_EXT2_REG(0))!= 0);
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while( READ_PERI_REG(SPI_EXT2_REG(0)) != 0);
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while( READ_PERI_REG(SPI_EXT2_REG(0)) != 0);
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while( READ_PERI_REG(SPI_EXT2_REG(0)) != 0);
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SET_PERI_REG_MASK( DPORT_HOST_INF_SEL_REG, 1<<14);
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// Start send data
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SET_PERI_REG_MASK(SPI_CMD_REG(spiNum), SPI_USR);
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while ((READ_PERI_REG(SPI_CMD_REG(spiNum))&SPI_USR));
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SET_PERI_REG_MASK(SPI_CMD_REG(spi_num), SPI_USR);
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while ((READ_PERI_REG(SPI_CMD_REG(spi_num)) & SPI_USR));
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CLEAR_PERI_REG_MASK( DPORT_HOST_INF_SEL_REG, 1<<14);
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CLEAR_PERI_REG_MASK(DPORT_HOST_INF_SEL_REG, 1 << 14);
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//recover spi mode
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SET_PERI_REG_BITS(SPI_USER_REG(spiNum), 0xf, wr_mode_backup, SPI_FWRITE_DUAL_S);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spiNum), (SPI_FREAD_DIO_M|SPI_FREAD_DUAL_M|SPI_FREAD_QUAD_M|SPI_FREAD_QIO_M));
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SET_PERI_REG_MASK(SPI_CTRL_REG(spiNum), rd_mode_backup);
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SET_PERI_REG_BITS(SPI_USER_REG(spi_num), 0xf, wr_mode_backup, SPI_FWRITE_DUAL_S);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), (SPI_FREAD_DIO_M|SPI_FREAD_DUAL_M|SPI_FREAD_QUAD_M|SPI_FREAD_QIO_M));
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SET_PERI_REG_MASK(SPI_CTRL_REG(spi_num), rd_mode_backup);
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//return cs to cs0
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SET_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1),SPI_CS1_DIS_M);
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SET_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS1_DIS_M);
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CLEAR_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1),SPI_CS0_DIS_M);
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}
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//start sending cmd/addr and receving data
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static void IRAM_ATTR psram_recv_start(psram_spi_num_t spiNum,uint32_t* pRxData,uint16_t rxByteLen, psram_cmd_mode_t cmd_mode)
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static void IRAM_ATTR psram_recv_start(psram_spi_num_t spi_num, uint32_t* pRxData, uint16_t rxByteLen,
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psram_cmd_mode_t cmd_mode)
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{
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//get cs1
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CLEAR_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS1_DIS_M);
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SET_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS0_DIS_M);
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uint32_t cmd_mode_backup = (READ_PERI_REG(SPI_USER_REG(spiNum)) >> SPI_FWRITE_DUAL_S) & 0xf;
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uint32_t rd_mode_backup = READ_PERI_REG(SPI_CTRL_REG(spiNum)) & (SPI_FREAD_DIO_M|SPI_FREAD_DUAL_M|SPI_FREAD_QUAD_M|SPI_FREAD_QIO_M);
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if(cmd_mode == PSRAM_CMD_SPI) {
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psram_set_basic_write_mode(spiNum);
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psram_set_basic_read_mode(spiNum);
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uint32_t cmd_mode_backup = (READ_PERI_REG(SPI_USER_REG(spi_num)) >> SPI_FWRITE_DUAL_S) & 0xf;
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uint32_t rd_mode_backup = READ_PERI_REG(SPI_CTRL_REG(spi_num)) & (SPI_FREAD_DIO_M | SPI_FREAD_DUAL_M | SPI_FREAD_QUAD_M | SPI_FREAD_QIO_M);
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if (cmd_mode == PSRAM_CMD_SPI) {
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psram_set_basic_write_mode(spi_num);
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psram_set_basic_read_mode(spi_num);
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} else if (cmd_mode == PSRAM_CMD_QPI) {
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psram_set_qio_write_mode(spiNum);
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psram_set_qio_read_mode(spiNum);
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psram_set_qio_write_mode(spi_num);
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psram_set_qio_read_mode(spi_num);
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}
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//WAIT SPI0 IDLE
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//READ THREE TIMES TO MAKE SURE?
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while( READ_PERI_REG(SPI_EXT2_REG(0))!= 0);
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while( READ_PERI_REG(SPI_EXT2_REG(0))!= 0);
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while( READ_PERI_REG(SPI_EXT2_REG(0))!= 0);
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SET_PERI_REG_MASK( DPORT_HOST_INF_SEL_REG, 1<<14);
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while ( READ_PERI_REG(SPI_EXT2_REG(0)) != 0);
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while ( READ_PERI_REG(SPI_EXT2_REG(0)) != 0);
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while ( READ_PERI_REG(SPI_EXT2_REG(0)) != 0);
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SET_PERI_REG_MASK(DPORT_HOST_INF_SEL_REG, 1 << 14);
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// Start send data
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SET_PERI_REG_MASK(SPI_CMD_REG(spiNum), SPI_USR);
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while ((READ_PERI_REG(SPI_CMD_REG(spiNum))&SPI_USR));
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CLEAR_PERI_REG_MASK( DPORT_HOST_INF_SEL_REG, 1<<14);
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SET_PERI_REG_MASK(SPI_CMD_REG(spi_num), SPI_USR);
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while ((READ_PERI_REG(SPI_CMD_REG(spi_num)) & SPI_USR));
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CLEAR_PERI_REG_MASK(DPORT_HOST_INF_SEL_REG, 1 << 14);
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//recover spi mode
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SET_PERI_REG_BITS(SPI_USER_REG(spiNum), SPI_FWRITE_DUAL_M, cmd_mode_backup, SPI_FWRITE_DUAL_S);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spiNum), (SPI_FREAD_DIO_M|SPI_FREAD_DUAL_M|SPI_FREAD_QUAD_M|SPI_FREAD_QIO_M));
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SET_PERI_REG_MASK(SPI_CTRL_REG(spiNum), rd_mode_backup);
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SET_PERI_REG_BITS(SPI_USER_REG(spi_num), SPI_FWRITE_DUAL_M, cmd_mode_backup, SPI_FWRITE_DUAL_S);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), (SPI_FREAD_DIO_M|SPI_FREAD_DUAL_M|SPI_FREAD_QUAD_M|SPI_FREAD_QIO_M));
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SET_PERI_REG_MASK(SPI_CTRL_REG(spi_num), rd_mode_backup);
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//return cs to cs0
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SET_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1),SPI_CS1_DIS_M);
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CLEAR_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1),SPI_CS0_DIS_M);
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SET_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS1_DIS_M);
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CLEAR_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS0_DIS_M);
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int idx = 0;
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// Read data out
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do {
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*pRxData++ = READ_PERI_REG(SPI_W0_REG(spiNum) + (idx << 2));
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*pRxData++ = READ_PERI_REG(SPI_W0_REG(spi_num) + (idx << 2));
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} while (++idx < ((rxByteLen / 4) + ((rxByteLen % 4) ? 1 : 0)));
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}
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//setup spi command/addr/data/dummy in user mode
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static int psram_cmd_config(psram_spi_num_t spiNum, psram_cmd_t* pInData)
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static int psram_cmd_config(psram_spi_num_t spi_num, psram_cmd_t* pInData)
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{
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while (READ_PERI_REG(SPI_CMD_REG(spiNum))&SPI_USR);
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while (READ_PERI_REG(SPI_CMD_REG(spi_num)) & SPI_USR);
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// Set command by user.
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if (pInData->cmdBitLen != 0) {
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// Max command length 16 bits.
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SET_PERI_REG_BITS(SPI_USER2_REG(spiNum), SPI_USR_COMMAND_BITLEN,pInData->cmdBitLen-1, SPI_USR_COMMAND_BITLEN_S);
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SET_PERI_REG_BITS(SPI_USER2_REG(spi_num), SPI_USR_COMMAND_BITLEN, pInData->cmdBitLen - 1,
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SPI_USR_COMMAND_BITLEN_S);
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// Enable command
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SET_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_USR_COMMAND);
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SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_COMMAND);
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// Load command,bit15-0 is cmd value.
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SET_PERI_REG_BITS(SPI_USER2_REG(spiNum), SPI_USR_COMMAND_VALUE, pInData->cmd, SPI_USR_COMMAND_VALUE_S);
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SET_PERI_REG_BITS(SPI_USER2_REG(spi_num), SPI_USR_COMMAND_VALUE, pInData->cmd, SPI_USR_COMMAND_VALUE_S);
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} else {
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_USR_COMMAND);
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SET_PERI_REG_BITS(SPI_USER2_REG(spiNum), SPI_USR_COMMAND_BITLEN,0, SPI_USR_COMMAND_BITLEN_S);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_COMMAND);
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SET_PERI_REG_BITS(SPI_USER2_REG(spi_num), SPI_USR_COMMAND_BITLEN, 0, SPI_USR_COMMAND_BITLEN_S);
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}
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// Set Address by user.
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if (pInData->addrBitLen != 0) {
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SET_PERI_REG_BITS(SPI_USER1_REG(spiNum), SPI_USR_ADDR_BITLEN,(pInData->addrBitLen- 1), SPI_USR_ADDR_BITLEN_S);
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SET_PERI_REG_BITS(SPI_USER1_REG(spi_num), SPI_USR_ADDR_BITLEN, (pInData->addrBitLen - 1), SPI_USR_ADDR_BITLEN_S);
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// Enable address
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SET_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_USR_ADDR);
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SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_ADDR);
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// Set address
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//SET_PERI_REG_BITS(SPI_ADDR_REG(spiNum), SPI_USR_ADDR_VALUE, *pInData->addr, SPI_USR_ADDR_VALUE_S);
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WRITE_PERI_REG(SPI_ADDR_REG(spiNum), *pInData->addr);
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//SET_PERI_REG_BITS(SPI_ADDR_REG(spi_num), SPI_USR_ADDR_VALUE, *pInData->addr, SPI_USR_ADDR_VALUE_S);
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WRITE_PERI_REG(SPI_ADDR_REG(spi_num), *pInData->addr);
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} else {
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_USR_ADDR);
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SET_PERI_REG_BITS(SPI_USER1_REG(spiNum), SPI_USR_ADDR_BITLEN,0, SPI_USR_ADDR_BITLEN_S);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_ADDR);
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SET_PERI_REG_BITS(SPI_USER1_REG(spi_num), SPI_USR_ADDR_BITLEN, 0, SPI_USR_ADDR_BITLEN_S);
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}
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// Set data by user.
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uint32_t* pTxVal = pInData->txData;
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if ( pInData->txDataBitLen != 0 ) {
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uint32_t* p_tx_val = pInData->txData;
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if (pInData->txDataBitLen != 0) {
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// Enable MOSI
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SET_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_USR_MOSI);
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SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MOSI);
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// Load send buffer
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int len = (pInData->txDataBitLen + 31) / 32;
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if(pTxVal != NULL) {
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memcpy((void*)SPI_W0_REG(spiNum), pTxVal, len*4);
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if (p_tx_val != NULL) {
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memcpy((void*)SPI_W0_REG(spi_num), p_tx_val, len * 4);
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}
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// Set data send buffer length.Max data length 64 bytes.
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SET_PERI_REG_BITS(SPI_MOSI_DLEN_REG(spiNum), SPI_USR_MOSI_DBITLEN, (pInData->txDataBitLen - 1), SPI_USR_MOSI_DBITLEN_S);
|
||||
SET_PERI_REG_BITS(SPI_MOSI_DLEN_REG(spi_num), SPI_USR_MOSI_DBITLEN, (pInData->txDataBitLen - 1),
|
||||
SPI_USR_MOSI_DBITLEN_S);
|
||||
} else {
|
||||
CLEAR_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_USR_MOSI);
|
||||
SET_PERI_REG_BITS(SPI_MOSI_DLEN_REG(spiNum), SPI_USR_MOSI_DBITLEN,0, SPI_USR_MOSI_DBITLEN_S);
|
||||
CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MOSI);
|
||||
SET_PERI_REG_BITS(SPI_MOSI_DLEN_REG(spi_num), SPI_USR_MOSI_DBITLEN, 0, SPI_USR_MOSI_DBITLEN_S);
|
||||
}
|
||||
// Set rx data by user.
|
||||
if ( pInData->rxDataBitLen != 0 ) {
|
||||
if (pInData->rxDataBitLen != 0) {
|
||||
// Enable MOSI
|
||||
SET_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_USR_MISO);
|
||||
SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MISO);
|
||||
// Set data send buffer length.Max data length 64 bytes.
|
||||
SET_PERI_REG_BITS(SPI_MISO_DLEN_REG(spiNum), SPI_USR_MISO_DBITLEN, (pInData->rxDataBitLen -1 ), SPI_USR_MISO_DBITLEN_S);
|
||||
SET_PERI_REG_BITS(SPI_MISO_DLEN_REG(spi_num), SPI_USR_MISO_DBITLEN, (pInData->rxDataBitLen - 1),
|
||||
SPI_USR_MISO_DBITLEN_S);
|
||||
} else {
|
||||
CLEAR_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_USR_MISO);
|
||||
SET_PERI_REG_BITS(SPI_MISO_DLEN_REG(spiNum), SPI_USR_MISO_DBITLEN, 0, SPI_USR_MISO_DBITLEN_S);
|
||||
CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MISO);
|
||||
SET_PERI_REG_BITS(SPI_MISO_DLEN_REG(spi_num), SPI_USR_MISO_DBITLEN, 0, SPI_USR_MISO_DBITLEN_S);
|
||||
}
|
||||
if( pInData->dummyBitLen != 0 ){
|
||||
SET_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1),SPI_USR_DUMMY); // dummy en
|
||||
SET_PERI_REG_BITS(SPI_USER1_REG(PSRAM_SPI_1),SPI_USR_DUMMY_CYCLELEN_V,pInData->dummyBitLen-1,SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
|
||||
if (pInData->dummyBitLen != 0) {
|
||||
SET_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_USR_DUMMY); // dummy en
|
||||
SET_PERI_REG_BITS(SPI_USER1_REG(PSRAM_SPI_1), SPI_USR_DUMMY_CYCLELEN_V, pInData->dummyBitLen - 1,
|
||||
SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
|
||||
} else {
|
||||
CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1),SPI_USR_DUMMY); // dummy en
|
||||
SET_PERI_REG_BITS(SPI_USER1_REG(PSRAM_SPI_1),SPI_USR_DUMMY_CYCLELEN_V,0,SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
|
||||
CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_USR_DUMMY); // dummy en
|
||||
SET_PERI_REG_BITS(SPI_USER1_REG(PSRAM_SPI_1), SPI_USR_DUMMY_CYCLELEN_V, 0, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
//exit QPI mode(set back to SPI mode)
|
||||
static void psram_disable_qio_mode(psram_spi_num_t spi_num)
|
||||
{
|
||||
psram_cmd_t ps_cmd;
|
||||
uint32_t cmd_exit_qpi;
|
||||
switch (s_psram_mode) {
|
||||
case PSRAM_CACHE_F80M_S80M:
|
||||
cmd_exit_qpi = PSRAM_EXIT_QMODE;
|
||||
ps_cmd.txDataBitLen = 8;
|
||||
break;
|
||||
case PSRAM_CACHE_F80M_S40M:
|
||||
case PSRAM_CACHE_F40M_S40M:
|
||||
default:
|
||||
cmd_exit_qpi = PSRAM_EXIT_QMODE << 8;
|
||||
ps_cmd.txDataBitLen = 16;
|
||||
break;
|
||||
}
|
||||
ps_cmd.txData = &cmd_exit_qpi;
|
||||
ps_cmd.cmd = 0;
|
||||
ps_cmd.cmdBitLen = 0;
|
||||
ps_cmd.addr = 0;
|
||||
ps_cmd.addrBitLen = 0;
|
||||
ps_cmd.rxData = NULL;
|
||||
ps_cmd.rxDataBitLen = 0;
|
||||
ps_cmd.dummyBitLen = 0;
|
||||
psram_cmd_config(spi_num, &ps_cmd);
|
||||
psram_cmd_start(spi_num, PSRAM_CMD_QPI);
|
||||
}
|
||||
|
||||
//The following helper functions aren't used in this code right now, but may be useful for other SPI RAM chips.
|
||||
#if 0
|
||||
|
|
@ -297,12 +334,12 @@ static void psram_dma_cmd_write_config(uint32_t dst, uint32_t len, uint32_t dumm
|
|||
psram_cmd_config(PSRAM_SPI_1, &ps_cmd);
|
||||
}
|
||||
|
||||
static void psram_dma_qio_read_config(psram_spi_num_t spiNum, uint32_t src, uint32_t len)
|
||||
static void psram_dma_qio_read_config(psram_spi_num_t spi_num, uint32_t src, uint32_t len)
|
||||
{
|
||||
uint32_t addr = (PSRAM_FAST_READ_QUAD <<24) | src;
|
||||
uint32_t addr = (PSRAM_FAST_READ_QUAD << 24) | src;
|
||||
uint32_t dummy_bits = 0;
|
||||
psram_cmd_t ps_cmd;
|
||||
switch(s_psram_mode){
|
||||
switch(s_psram_mode) {
|
||||
case PSRAM_CACHE_F80M_S80M:
|
||||
dummy_bits = 6+extra_dummy;
|
||||
ps_cmd.cmdBitLen = 0;
|
||||
|
|
@ -322,17 +359,16 @@ static void psram_dma_qio_read_config(psram_spi_num_t spiNum, uint32_t src, uint
|
|||
ps_cmd.rxDataBitLen = len*8 ;
|
||||
ps_cmd.rxData = NULL;
|
||||
ps_cmd.dummyBitLen = dummy_bits;
|
||||
psram_cmd_config(spiNum,&ps_cmd);
|
||||
// psram_clear_spi_fifo(spiNum);
|
||||
psram_cmd_config(spi_num,&ps_cmd);
|
||||
}
|
||||
|
||||
//switch psram burst length(32 bytes or 1024 bytes)
|
||||
//datasheet says it should be 1024 bytes by default
|
||||
//but they sent us a correction doc and told us it is 32 bytes for these samples
|
||||
static void psram_set_burst_length(psram_spi_num_t spiNum)
|
||||
static void psram_set_burst_length(psram_spi_num_t spi_num)
|
||||
{
|
||||
psram_cmd_t ps_cmd;
|
||||
switch(s_psram_mode){
|
||||
switch (s_psram_mode) {
|
||||
case PSRAM_CACHE_F80M_S80M:
|
||||
ps_cmd.cmd = 0xC0;
|
||||
ps_cmd.cmdBitLen = 8;
|
||||
|
|
@ -351,13 +387,13 @@ static void psram_set_burst_length(psram_spi_num_t spiNum)
|
|||
ps_cmd.rxData = NULL;
|
||||
ps_cmd.rxDataBitLen = 0;
|
||||
ps_cmd.dummyBitLen = 0;
|
||||
psram_cmd_config(spiNum, &ps_cmd);
|
||||
psram_cmd_start(spiNum, PSRAM_CMD_QPI);
|
||||
psram_cmd_config(spi_num, &ps_cmd);
|
||||
psram_cmd_start(spi_num, PSRAM_CMD_QPI);
|
||||
}
|
||||
|
||||
//send reset command to psram(right now,we only send this command in QPI mode)
|
||||
//seems not working
|
||||
static void psram_reset_mode(psram_spi_num_t spiNum)
|
||||
static void psram_reset_mode(psram_spi_num_t spi_num)
|
||||
{
|
||||
psram_cmd_t ps_cmd;
|
||||
uint32_t cmd_rst = 0x99066;
|
||||
|
|
@ -370,44 +406,14 @@ static void psram_reset_mode(psram_spi_num_t spiNum)
|
|||
ps_cmd.rxData = NULL;
|
||||
ps_cmd.rxDataBitLen = 0;
|
||||
ps_cmd.dummyBitLen = 0;
|
||||
psram_cmd_config(spiNum, &ps_cmd);
|
||||
psram_cmd_start(spiNum, PSRAM_CMD_QPI);
|
||||
}
|
||||
|
||||
//exit QPI mode(set back to SPI mode)
|
||||
static void psram_disable_qio_mode(psram_spi_num_t spiNum)
|
||||
{
|
||||
psram_cmd_t ps_cmd;
|
||||
uint32_t cmd_exit_qpi;
|
||||
switch(s_psram_mode){
|
||||
case PSRAM_CACHE_F80M_S80M:
|
||||
cmd_exit_qpi = PSRAM_EXIT_QMODE;
|
||||
ps_cmd.txDataBitLen = 8;
|
||||
break;
|
||||
case PSRAM_CACHE_F80M_S40M:
|
||||
case PSRAM_CACHE_F40M_S40M:
|
||||
default:
|
||||
cmd_exit_qpi = PSRAM_EXIT_QMODE<<8;
|
||||
ps_cmd.txDataBitLen = 16;
|
||||
break;
|
||||
}
|
||||
ps_cmd.txData = &cmd_exit_qpi;
|
||||
ps_cmd.cmd = 0;
|
||||
ps_cmd.cmdBitLen = 0;
|
||||
ps_cmd.addr = 0;
|
||||
ps_cmd.addrBitLen = 0;
|
||||
ps_cmd.rxData = NULL;
|
||||
ps_cmd.rxDataBitLen = 0;
|
||||
ps_cmd.dummyBitLen = 0;
|
||||
psram_cmd_config(spiNum, &ps_cmd);
|
||||
psram_cmd_start(spiNum, PSRAM_CMD_QPI);
|
||||
psram_cmd_config(spi_num, &ps_cmd);
|
||||
psram_cmd_start(spi_num, PSRAM_CMD_QPI);
|
||||
}
|
||||
|
||||
static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode)
|
||||
{
|
||||
gpio_matrix_out(6, SPICLK_OUT_IDX, 0, 0);
|
||||
gpio_matrix_out(11, SPICS0_OUT_IDX, 0, 0);
|
||||
|
||||
gpio_matrix_out(7, SPIQ_OUT_IDX, 0, 0);
|
||||
gpio_matrix_in(7,SPIQ_IN_IDX, 0);
|
||||
gpio_matrix_out(8, SPID_OUT_IDX, 0, 0);
|
||||
|
|
@ -416,7 +422,6 @@ static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode)
|
|||
gpio_matrix_in(10, SPIWP_IN_IDX, 0);
|
||||
gpio_matrix_out(9, SPIHD_OUT_IDX, 0, 0);
|
||||
gpio_matrix_in(9, SPIHD_IN_IDX, 0);
|
||||
|
||||
switch(mode){
|
||||
case PSRAM_CACHE_F80M_S80M:
|
||||
case PSRAM_CACHE_F80M_S40M:
|
||||
|
|
@ -452,94 +457,93 @@ static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode)
|
|||
//read psram id
|
||||
static void psram_read_id(uint32_t* dev_id)
|
||||
{
|
||||
psram_spi_num_t spiNum = PSRAM_SPI_1;
|
||||
uint32_t addr = (PSRAM_DEVICE_ID <<24) | 0;
|
||||
psram_spi_num_t spi_num = PSRAM_SPI_1;
|
||||
psram_disable_qio_mode(spi_num);
|
||||
uint32_t addr = (PSRAM_DEVICE_ID << 24) | 0;
|
||||
uint32_t dummy_bits = 0;
|
||||
psram_cmd_t ps_cmd;
|
||||
switch(s_psram_mode){
|
||||
switch (s_psram_mode) {
|
||||
case PSRAM_CACHE_F80M_S80M:
|
||||
dummy_bits = 0+extra_dummy;
|
||||
dummy_bits = 0 + extra_dummy;
|
||||
ps_cmd.cmdBitLen = 0;
|
||||
break;
|
||||
case PSRAM_CACHE_F80M_S40M:
|
||||
case PSRAM_CACHE_F40M_S40M:
|
||||
default:
|
||||
dummy_bits = 0+extra_dummy;
|
||||
ps_cmd.cmdBitLen = 2; //this two bits is used for delay one byte in qio mode
|
||||
dummy_bits = 0 + extra_dummy;
|
||||
ps_cmd.cmdBitLen = 2; //this two bits is used to delay 2 clock cycle
|
||||
break;
|
||||
}
|
||||
ps_cmd.cmd = 0;
|
||||
ps_cmd.addr = &addr;
|
||||
ps_cmd.addrBitLen = 4*8;
|
||||
ps_cmd.addrBitLen = 4 * 8;
|
||||
ps_cmd.txDataBitLen = 0;
|
||||
ps_cmd.txData = NULL;
|
||||
ps_cmd.rxDataBitLen = 4*8 ;
|
||||
ps_cmd.rxDataBitLen = 4 * 8;
|
||||
ps_cmd.rxData = dev_id;
|
||||
ps_cmd.dummyBitLen = dummy_bits;
|
||||
psram_cmd_config(spiNum,&ps_cmd);
|
||||
psram_clear_spi_fifo(spiNum);
|
||||
psram_recv_start(spiNum,ps_cmd.rxData,ps_cmd.rxDataBitLen/8, PSRAM_CMD_SPI);
|
||||
psram_cmd_config(spi_num, &ps_cmd);
|
||||
psram_clear_spi_fifo(spi_num);
|
||||
psram_recv_start(spi_num, ps_cmd.rxData, ps_cmd.rxDataBitLen / 8, PSRAM_CMD_SPI);
|
||||
}
|
||||
|
||||
|
||||
//enter QPI mode
|
||||
static void IRAM_ATTR psram_enable_qio_mode(psram_spi_num_t spiNum)
|
||||
static esp_err_t IRAM_ATTR psram_enable_qio_mode(psram_spi_num_t spi_num)
|
||||
{
|
||||
psram_cmd_t ps_cmd;
|
||||
switch(s_psram_mode){
|
||||
uint32_t addr = (PSRAM_ENTER_QMODE << 24) | 0;
|
||||
switch (s_psram_mode) {
|
||||
case PSRAM_CACHE_F80M_S80M:
|
||||
ps_cmd.cmd = PSRAM_ENTER_QMODE;
|
||||
ps_cmd.cmdBitLen = 8;
|
||||
ps_cmd.cmdBitLen = 0;
|
||||
break;
|
||||
case PSRAM_CACHE_F80M_S40M:
|
||||
case PSRAM_CACHE_F40M_S40M:
|
||||
default:
|
||||
ps_cmd.cmd = 0x400d;
|
||||
ps_cmd.cmdBitLen = 10;
|
||||
ps_cmd.cmdBitLen = 2;
|
||||
break;
|
||||
}
|
||||
ps_cmd.addr = 0;
|
||||
ps_cmd.addrBitLen = 0;
|
||||
ps_cmd.cmd = 0;
|
||||
ps_cmd.addr = &addr;
|
||||
ps_cmd.addrBitLen = 8;
|
||||
ps_cmd.txData = NULL;
|
||||
ps_cmd.txDataBitLen = 0;
|
||||
ps_cmd.rxData = NULL;
|
||||
ps_cmd.rxDataBitLen = 0;
|
||||
ps_cmd.dummyBitLen = 0;
|
||||
psram_cmd_config(spiNum, &ps_cmd);
|
||||
psram_cmd_start(spiNum, PSRAM_CMD_SPI);
|
||||
psram_cmd_config(spi_num, &ps_cmd);
|
||||
psram_cmd_start(spi_num, PSRAM_CMD_SPI);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
|
||||
|
||||
//spi param init for psram
|
||||
void IRAM_ATTR psram_spi_init(psram_spi_num_t spiNum,psram_cache_mode_t mode)
|
||||
void IRAM_ATTR psram_spi_init(psram_spi_num_t spi_num, psram_cache_mode_t mode)
|
||||
{
|
||||
uint8_t i, k;
|
||||
CLEAR_PERI_REG_MASK(SPI_SLAVE_REG(spiNum), SPI_TRANS_DONE << 5);
|
||||
SET_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_CS_SETUP);
|
||||
CLEAR_PERI_REG_MASK(SPI_SLAVE_REG(spi_num), SPI_TRANS_DONE << 5);
|
||||
SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_CS_SETUP);
|
||||
// SPI_CPOL & SPI_CPHA
|
||||
CLEAR_PERI_REG_MASK(SPI_PIN_REG(spiNum), SPI_CK_IDLE_EDGE);
|
||||
CLEAR_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_CK_OUT_EDGE);
|
||||
CLEAR_PERI_REG_MASK(SPI_PIN_REG(spi_num), SPI_CK_IDLE_EDGE);
|
||||
CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_CK_OUT_EDGE);
|
||||
// SPI bit order
|
||||
CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spiNum), SPI_WR_BIT_ORDER);
|
||||
CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spiNum), SPI_RD_BIT_ORDER);
|
||||
CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_WR_BIT_ORDER);
|
||||
CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_RD_BIT_ORDER);
|
||||
// SPI bit order
|
||||
CLEAR_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_DOUTDIN);
|
||||
CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_DOUTDIN);
|
||||
// May be not must to do.
|
||||
WRITE_PERI_REG(SPI_USER1_REG(spiNum), 0);
|
||||
WRITE_PERI_REG(SPI_USER1_REG(spi_num), 0);
|
||||
// SPI mode type
|
||||
CLEAR_PERI_REG_MASK(SPI_SLAVE_REG(spiNum), SPI_SLAVE_MODE);
|
||||
switch(mode){
|
||||
CLEAR_PERI_REG_MASK(SPI_SLAVE_REG(spi_num), SPI_SLAVE_MODE);
|
||||
switch (mode) {
|
||||
case PSRAM_CACHE_F80M_S80M:
|
||||
WRITE_PERI_REG(SPI_CLOCK_REG(spiNum), SPI_CLK_EQU_SYSCLK); // 80Mhz speed
|
||||
WRITE_PERI_REG(SPI_CLOCK_REG(spi_num), SPI_CLK_EQU_SYSCLK); // 80Mhz speed
|
||||
break;
|
||||
case PSRAM_CACHE_F80M_S40M:
|
||||
case PSRAM_CACHE_F40M_S40M:
|
||||
default:
|
||||
i = (2 / 40) ? (2 / 40) : 1;
|
||||
k = 2 / i;
|
||||
CLEAR_PERI_REG_MASK(SPI_CLOCK_REG(spiNum), SPI_CLK_EQU_SYSCLK);
|
||||
WRITE_PERI_REG(SPI_CLOCK_REG(spiNum),
|
||||
CLEAR_PERI_REG_MASK(SPI_CLOCK_REG(spi_num), SPI_CLK_EQU_SYSCLK);
|
||||
WRITE_PERI_REG(SPI_CLOCK_REG(spi_num),
|
||||
(((i - 1) & SPI_CLKDIV_PRE) << SPI_CLKDIV_PRE_S) |
|
||||
(((k - 1) & SPI_CLKCNT_N) << SPI_CLKCNT_N_S) |
|
||||
((((k + 1) / 2 - 1) & SPI_CLKCNT_H) << SPI_CLKCNT_H_S) |
|
||||
|
|
@ -547,47 +551,43 @@ void IRAM_ATTR psram_spi_init(psram_spi_num_t spiNum,psram_cache_mode_t mode)
|
|||
break;
|
||||
}
|
||||
// Enable MOSI
|
||||
SET_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_CS_SETUP | SPI_CS_HOLD | SPI_USR_MOSI);
|
||||
memset((void*)SPI_W0_REG(spiNum), 0, 16*4);
|
||||
SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_CS_SETUP | SPI_CS_HOLD | SPI_USR_MOSI);
|
||||
memset((void*)SPI_W0_REG(spi_num), 0, 16 * 4);
|
||||
}
|
||||
|
||||
|
||||
//psram gpio init , different working frequency we have different solutions
|
||||
esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode) //psram init
|
||||
{
|
||||
WRITE_PERI_REG(GPIO_ENABLE_W1TC_REG,BIT16|BIT17);//DISABLE OUPUT FOR IO16/17
|
||||
|
||||
assert(mode==PSRAM_CACHE_F40M_S40M && "we don't support any other mode for now.");
|
||||
|
||||
WRITE_PERI_REG(GPIO_ENABLE_W1TC_REG, BIT(PSRAM_CLK_IO) | BIT(PSRAM_CS_IO)); //DISABLE OUPUT FOR IO16/17
|
||||
assert(mode == PSRAM_CACHE_F40M_S40M && "we don't support any other mode for now.");
|
||||
s_psram_mode = mode;
|
||||
|
||||
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,BIT16);//DPORT_SPI_CLK_EN
|
||||
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,BIT16);//DPORT_SPI_RST
|
||||
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,BIT1);//DPORT_SPI_CLK_EN_1
|
||||
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,BIT1);//DPORT_SPI_RST_1
|
||||
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,BIT6);//DPORT_SPI_CLK_EN_2
|
||||
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,BIT6);//DPORT_SPI_RST_2
|
||||
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN);
|
||||
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST);
|
||||
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_1);
|
||||
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST_1);
|
||||
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_2);
|
||||
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST_2);
|
||||
|
||||
WRITE_PERI_REG( SPI_EXT3_REG(0), 0x1);
|
||||
CLEAR_PERI_REG_MASK( SPI_USER_REG(PSRAM_SPI_1), SPI_USR_PREP_HOLD_M);
|
||||
WRITE_PERI_REG(SPI_EXT3_REG(0), 0x1);
|
||||
CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_USR_PREP_HOLD_M);
|
||||
|
||||
|
||||
switch(mode){
|
||||
switch (mode) {
|
||||
case PSRAM_CACHE_F80M_S80M:
|
||||
psram_spi_init(PSRAM_SPI_1, mode);
|
||||
extra_dummy = 2;
|
||||
CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_CS_HOLD);
|
||||
gpio_matrix_out(16, SPICS1_OUT_IDX, 0, 0);
|
||||
gpio_matrix_out(17, VSPICLK_OUT_IDX, 0, 0);
|
||||
gpio_matrix_out(PSRAM_CS_IO, SPICS1_OUT_IDX, 0, 0);
|
||||
gpio_matrix_out(PSRAM_CLK_IO, VSPICLK_OUT_IDX, 0, 0);
|
||||
//use spi3 clock,but use spi1 data/cs wires
|
||||
WRITE_PERI_REG(SPI_ADDR_REG(PSRAM_SPI_3), 32<<24);
|
||||
WRITE_PERI_REG(SPI_CLOCK_REG(PSRAM_SPI_3),SPI_CLK_EQU_SYSCLK_M);//SET 80M AND CLEAR OTHERS
|
||||
SET_PERI_REG_MASK(SPI_CMD_REG(PSRAM_SPI_3),SPI_FLASH_READ_M);
|
||||
WRITE_PERI_REG(SPI_ADDR_REG(PSRAM_SPI_3), 32 << 24);
|
||||
WRITE_PERI_REG(SPI_CLOCK_REG(PSRAM_SPI_3), SPI_CLK_EQU_SYSCLK_M); //SET 80M AND CLEAR OTHERS
|
||||
SET_PERI_REG_MASK(SPI_CMD_REG(PSRAM_SPI_3), SPI_FLASH_READ_M);
|
||||
uint32_t spi_status;
|
||||
while(1){
|
||||
while (1) {
|
||||
spi_status = READ_PERI_REG(SPI_EXT2_REG(PSRAM_SPI_3));
|
||||
if(spi_status != 0 && spi_status != 1){
|
||||
CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,BIT16);//DPORT_SPI_CLK_EN
|
||||
if (spi_status != 0 && spi_status != 1) {
|
||||
CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, BIT(PSRAM_CS_IO)); //DPORT_SPI_CLK_EN
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -595,34 +595,31 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
|
|||
case PSRAM_CACHE_F80M_S40M:
|
||||
case PSRAM_CACHE_F40M_S40M:
|
||||
default:
|
||||
#if GPIO_MATRIX_FOR_40M
|
||||
extra_dummy = 1;
|
||||
#else
|
||||
#if DISABLE_GPIO_MATRIX_FOR_40M
|
||||
extra_dummy = 0;
|
||||
#else
|
||||
extra_dummy = 1;
|
||||
#endif
|
||||
psram_spi_init(PSRAM_SPI_1, mode);
|
||||
CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_CS_HOLD);
|
||||
gpio_matrix_out(16, SPICS1_OUT_IDX, 0, 0);
|
||||
gpio_matrix_in(6,SIG_IN_FUNC224_IDX,0);
|
||||
gpio_matrix_out(20,SIG_IN_FUNC224_IDX,0,0);
|
||||
gpio_matrix_in(20,SIG_IN_FUNC225_IDX,0);
|
||||
gpio_matrix_out(17,SIG_IN_FUNC225_IDX,0,0);
|
||||
gpio_matrix_out(PSRAM_CS_IO, SPICS1_OUT_IDX, 0, 0);
|
||||
gpio_matrix_in(6, SIG_IN_FUNC224_IDX, 0);
|
||||
gpio_matrix_out(20, SIG_IN_FUNC224_IDX, 0, 0);
|
||||
gpio_matrix_in(20, SIG_IN_FUNC225_IDX, 0);
|
||||
gpio_matrix_out(PSRAM_CLK_IO, SIG_IN_FUNC225_IDX, 0, 0);
|
||||
break;
|
||||
}
|
||||
CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1),SPI_CS_SETUP_M);
|
||||
CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_CS_SETUP_M);
|
||||
|
||||
#if GPIO_MATRIX_FOR_40M
|
||||
#if (!DISABLE_GPIO_MATRIX_FOR_40M)
|
||||
psram_gpio_config(mode);
|
||||
#endif
|
||||
|
||||
|
||||
WRITE_PERI_REG(GPIO_ENABLE_W1TS_REG,BIT16|BIT17);//GPIO_Pin_16 | GPIO_Pin_17
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO16_U,2);
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO17_U,2);
|
||||
|
||||
WRITE_PERI_REG(GPIO_ENABLE_W1TS_REG, BIT(PSRAM_CS_IO)| BIT(PSRAM_CLK_IO));
|
||||
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[PSRAM_CS_IO], 2);
|
||||
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[PSRAM_CLK_IO], 2);
|
||||
uint32_t id;
|
||||
psram_read_id(&id);
|
||||
if(((id >> 8) & 0xff )!= 0x5d) {
|
||||
if (((id >> PSRAM_MFG_ID_S) & PSRAM_MFG_ID_M) != PSRAM_MFG_ID_ESPRESSIF) {
|
||||
return ESP_FAIL;
|
||||
}
|
||||
psram_enable_qio_mode(PSRAM_SPI_1);
|
||||
|
|
@ -633,85 +630,87 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
|
|||
//register initialization for sram cache params and r/w commands
|
||||
static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode)
|
||||
{
|
||||
CLEAR_PERI_REG_MASK(SPI_CLOCK_REG(0),SPI_CLK_EQU_SYSCLK_M);
|
||||
SET_PERI_REG_BITS(SPI_CLOCK_REG(0),SPI_CLKDIV_PRE_V,0,SPI_CLKDIV_PRE_S);
|
||||
SET_PERI_REG_BITS(SPI_CLOCK_REG(0),SPI_CLKCNT_N,1,SPI_CLKCNT_N_S);
|
||||
SET_PERI_REG_BITS(SPI_CLOCK_REG(0),SPI_CLKCNT_H,0,SPI_CLKCNT_H_S);
|
||||
SET_PERI_REG_BITS(SPI_CLOCK_REG(0),SPI_CLKCNT_L,1,SPI_CLKCNT_L_S);
|
||||
CLEAR_PERI_REG_MASK(SPI_CLOCK_REG(0), SPI_CLK_EQU_SYSCLK_M);
|
||||
SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKDIV_PRE_V, 0, SPI_CLKDIV_PRE_S);
|
||||
SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_N, 1, SPI_CLKCNT_N_S);
|
||||
SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_H, 0, SPI_CLKCNT_H_S);
|
||||
SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_L, 1, SPI_CLKCNT_L_S);
|
||||
|
||||
switch(psram_cache_mode){
|
||||
switch (psram_cache_mode) {
|
||||
case PSRAM_CACHE_F80M_S80M:
|
||||
CLEAR_PERI_REG_MASK(SPI_DATE_REG(0),BIT(31));//flash 1 div clk,80+40;
|
||||
CLEAR_PERI_REG_MASK(SPI_DATE_REG(0),BIT(30));//pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0. FLASH DIV 2+SRAM DIV4
|
||||
WRITE_PERI_REG(SPI_CLOCK_REG(0),SPI_CLK_EQU_SYSCLK_M);//SET 1DIV CLOCK AND RESET OTHER PARAMS
|
||||
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0),SPI_USR_RD_SRAM_DUMMY_M);//enable cache read dummy
|
||||
SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0),SPI_SRAM_DUMMY_CYCLELEN_V,3+extra_dummy,SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy
|
||||
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0),SPI_CACHE_SRAM_USR_RCMD_M);//enable user mode for cache read command
|
||||
CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(31)); //flash 1 div clk,80+40;
|
||||
CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(30)); //pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0. FLASH DIV 2+SRAM DIV4
|
||||
WRITE_PERI_REG(SPI_CLOCK_REG(0), SPI_CLK_EQU_SYSCLK_M); //SET 1DIV CLOCK AND RESET OTHER PARAMS
|
||||
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_RD_SRAM_DUMMY_M); //enable cache read dummy
|
||||
SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_DUMMY_CYCLELEN_V, 3 + extra_dummy,
|
||||
SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy
|
||||
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_CACHE_SRAM_USR_RCMD_M); //enable user mode for cache read command
|
||||
break;
|
||||
case PSRAM_CACHE_F80M_S40M:
|
||||
SET_PERI_REG_MASK(SPI_DATE_REG(0),BIT(31));//flash 1 div clk
|
||||
CLEAR_PERI_REG_MASK(SPI_DATE_REG(0),BIT(30));//pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0.
|
||||
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0),SPI_USR_RD_SRAM_DUMMY_M);//enable cache read dummy
|
||||
SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0),SPI_SRAM_DUMMY_CYCLELEN_V,3+extra_dummy,SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy
|
||||
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0),SPI_CACHE_SRAM_USR_RCMD_M);//enable user mode for cache read command
|
||||
SET_PERI_REG_MASK(SPI_DATE_REG(0), BIT(31)); //flash 1 div clk
|
||||
CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(30)); //pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0.
|
||||
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_RD_SRAM_DUMMY_M); //enable cache read dummy
|
||||
SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_DUMMY_CYCLELEN_V, 3 + extra_dummy,
|
||||
SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy
|
||||
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_CACHE_SRAM_USR_RCMD_M); //enable user mode for cache read command
|
||||
break;
|
||||
case PSRAM_CACHE_F40M_S40M:
|
||||
default:
|
||||
CLEAR_PERI_REG_MASK(SPI_DATE_REG(0),BIT(31));//flash 1 div clk
|
||||
CLEAR_PERI_REG_MASK(SPI_DATE_REG(0),BIT(30));//pre clk div
|
||||
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0),SPI_USR_RD_SRAM_DUMMY_M);//enable cache read dummy
|
||||
SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0),SPI_SRAM_DUMMY_CYCLELEN_V,3+extra_dummy,SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy
|
||||
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0),SPI_CACHE_SRAM_USR_RCMD_M);//enable user mode for cache read command
|
||||
CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(31)); //flash 1 div clk
|
||||
CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(30)); //pre clk div
|
||||
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_RD_SRAM_DUMMY_M); //enable cache read dummy
|
||||
SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_DUMMY_CYCLELEN_V, 3 + extra_dummy,
|
||||
SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy
|
||||
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_CACHE_SRAM_USR_RCMD_M); //enable user mode for cache read command
|
||||
break;
|
||||
}
|
||||
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0),SPI_CACHE_SRAM_USR_WCMD_M); // cache write command enable
|
||||
SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0),SPI_SRAM_ADDR_BITLEN_V,23,SPI_SRAM_ADDR_BITLEN_S);//write address for cache command.
|
||||
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0),SPI_USR_SRAM_QIO_M);//enable qio mode for cache command
|
||||
CLEAR_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0),SPI_USR_SRAM_DIO_M);//disable dio mode for cache command
|
||||
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_CACHE_SRAM_USR_WCMD_M); // cache write command enable
|
||||
SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_ADDR_BITLEN_V, 23, SPI_SRAM_ADDR_BITLEN_S); //write address for cache command.
|
||||
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_SRAM_QIO_M); //enable qio mode for cache command
|
||||
CLEAR_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_SRAM_DIO_M); //disable dio mode for cache command
|
||||
|
||||
//config sram cache r/w command
|
||||
switch(psram_cache_mode) {
|
||||
switch (psram_cache_mode) {
|
||||
case PSRAM_CACHE_F80M_S80M: //in this mode , no delay is needed
|
||||
SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_BITLEN, 7,
|
||||
SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S);
|
||||
SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S);
|
||||
SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_VALUE, 0x38,
|
||||
SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38
|
||||
SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38
|
||||
SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7,
|
||||
SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S);
|
||||
SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S);
|
||||
SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V, 0x0b,
|
||||
SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0x0b
|
||||
SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0x0b
|
||||
break;
|
||||
case PSRAM_CACHE_F80M_S40M: //is sram is @40M, need 2 cycles of delay
|
||||
case PSRAM_CACHE_F40M_S40M:
|
||||
default:
|
||||
default:
|
||||
SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 15,
|
||||
SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S); //read command length, 2 bytes(1byte for delay),sending in qio mode in cache
|
||||
SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S); //read command length, 2 bytes(1byte for delay),sending in qio mode in cache
|
||||
SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V, 0x0b00,
|
||||
SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0x0b, read command value,(0x00 for delay,0x0b for cmd)
|
||||
SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0x0b, read command value,(0x00 for delay,0x0b for cmd)
|
||||
SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_BITLEN, 15,
|
||||
SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S); //write command length,2 bytes(1byte for delay,send in qio mode in cache)
|
||||
SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S); //write command length,2 bytes(1byte for delay,send in qio mode in cache)
|
||||
SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_VALUE, 0x3800,
|
||||
SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38, write command value,(0x00 for delay)
|
||||
SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38, write command value,(0x00 for delay)
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG , DPORT_PRO_DRAM_HL|DPORT_PRO_DRAM_SPLIT);
|
||||
CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG , DPORT_APP_DRAM_HL|DPORT_APP_DRAM_SPLIT);
|
||||
CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL|DPORT_PRO_DRAM_SPLIT);
|
||||
CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL|DPORT_APP_DRAM_SPLIT);
|
||||
if (vaddrmode == PSRAM_VADDR_MODE_LOWHIGH) {
|
||||
SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG , DPORT_PRO_DRAM_SPLIT);
|
||||
SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG , DPORT_APP_DRAM_SPLIT);
|
||||
SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_SPLIT);
|
||||
SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_SPLIT);
|
||||
} else if (vaddrmode == PSRAM_VADDR_MODE_EVENODD) {
|
||||
SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG , DPORT_PRO_DRAM_HL);
|
||||
SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG , DPORT_APP_DRAM_HL);
|
||||
SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL);
|
||||
SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL);
|
||||
}
|
||||
|
||||
CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL1_REG , DPORT_PRO_CACHE_MASK_DRAM1|DPORT_PRO_CACHE_MASK_OPSDRAM);//use Dram1 to visit ext sram.
|
||||
SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CMMU_SRAM_PAGE_MODE, 0, DPORT_PRO_CMMU_SRAM_PAGE_MODE_S); //cache page mode : 1 -->16k 4 -->2k 0-->32k,(accord with the settings in cache_sram_mmu_set)
|
||||
|
||||
CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG , DPORT_APP_CACHE_MASK_DRAM1|DPORT_APP_CACHE_MASK_OPSDRAM);//use Dram1 to visit ext sram.
|
||||
SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CMMU_SRAM_PAGE_MODE, 0, DPORT_APP_CMMU_SRAM_PAGE_MODE_S); //cache page mode : 1 -->16k 4 -->2k 0-->32k,(accord with the settings in cache_sram_mmu_set)
|
||||
|
||||
CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DRAM1|DPORT_PRO_CACHE_MASK_OPSDRAM); //use Dram1 to visit ext sram.
|
||||
//cache page mode : 1 -->16k 4 -->2k 0-->32k,(accord with the settings in cache_sram_mmu_set)
|
||||
SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CMMU_SRAM_PAGE_MODE, 0, DPORT_PRO_CMMU_SRAM_PAGE_MODE_S);
|
||||
CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1|DPORT_APP_CACHE_MASK_OPSDRAM); //use Dram1 to visit ext sram.
|
||||
//cache page mode : 1 -->16k 4 -->2k 0-->32k,(accord with the settings in cache_sram_mmu_set)
|
||||
SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CMMU_SRAM_PAGE_MODE, 0, DPORT_APP_CMMU_SRAM_PAGE_MODE_S);
|
||||
CLEAR_PERI_REG_MASK(SPI_PIN_REG(0), SPI_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
|
||||
}
|
||||
|
||||
|
|
|
|||
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