- In SPI mode, the card will respond to the initial SDIO reset (done
using CMD52) with “invalid command” error. Handle this correctly.
- sdmmc_card_init had a hack where GO_IDLE_STATE (CMD0) command was
sent twice. Add explanation why this is done, and don’t expect
correct response from the card on first CMD0.
- improve logs printed at debug level by adding CMD index
- Add SDIO support at protocol layer (probing, data transfer, interrupts)
- Add SDIO interrupts support in SDMMC host
- Add test (communicate with ESP32 in SDIO download mode)
Existing code assumed that response timeout is not followed by CMD_DONE,
which was not true, in fact. Host datasheet states that CMD_DONE is sent
after an RTO.
All the commands which do not have a response must have their flags set
accordingly. Therefore the host will not send RTO interrupt if response
is not expected. It is a bug in the code logic if it happens otherwise.
SDMMC host suffers from an issue that it outputs data near the rising
edge of the card clock, which is the edge used by the card to sample
data. If sampling time constraint is not satisfied, card may read data
after the transition.
The phases of output/input data can, in fact, be adjusted. However this
adjustment happens in the clock generation block outside of the host.
So the maximum phase change which can be created this way is equal to
half of the host clock period. So if the host clock is set to the lowest
possible frequency (for the given card frequency), then the phase offset
(and hence the hold time) will be the highest. This change modifies the
logic used to determine clock dividers accordingly.
sdmmc host: set correct dout phase and print correct frequency
SET_BUS_WIDTH is not a data transfer command. Extensive search in the
host datasheet and SD card spec did not reveal the origin of this hack
or 'feature'. Further testing showed that removing this does not lead to
regressions.
Fixes exceptions LoadProhibited, when rmt tries read variable p_rmt on RX END which can be 0.
It happens after esp_reset() (OTA) and the rmt is not probably stopped by it.
In other words the routine rmt_driver_isr_default was called before second rx channel was registered.
scenario:
register tx channel
register rx channel
reboot
register tx channel
-> exception (because rx channel is accessed)
Merges https://github.com/espressif/esp-idf/pull/1671
SDSPI driver optimized polling of the response tokens by requesting
two extra bytes on top of the block size (512) and CRC (2), and
checking whether these bytes contained the data response token or
not. In case the token was there, further polling would not need to
happen, thereby reducing latency between two consecutive blocks
transferred. However this caused compatibility issues when these two
extra bytes were sent after reading the final block. When
STOP_TRANSMISSION command was sent, these extra two bytes were
treated as part of the command, causing an invalid command error.
This fixes the logic by only requesting extra two bytes if the block
being read is not the final block. In addition to that, more strict
error checking is implemented for command response tokens.
On most microcontrollers I have worked with one can retrieve the
current state of output GPIO pins. On ESP32 this is not the case
if the pad is not explictly configured to route this information into
the port by configuring it as input or i/o.
Thus add a warning to the API documentation of gpio_get_level().
Merges https://github.com/espressif/esp-idf/pull/1740
The TRM describes IOMUX registers are IO_MUX_x_REG for x in GPIO0-39.
Until now ESP-IDF describes them as PERIPHS_IO_MUX_(pinname)_U
This commit adds additional IOMUX register names which match the ones used in the TRM.
Reported from github: https://github.com/espressif/esp-idf/issues/1236
All the touch channels are enabled by default in hardware. This would interfere other RTC function on Touch IOs.
Disable touch function in touch_pad_init().
requirement from github(https://github.com/espressif/esp-idf/issues/805): to provide the position in the buffer of the pattern detected.
requirement from AT application: in AT app, when no hardware flow control is enabled, in some situation the rx buffer might be full, and the terminator “+++” might be lost, we can use pattern detect interrupt to avoid missing the terminator. When pattern detect interrupt happens, it will not send a data event at the same time.
1. Add API to get position of detected pattern in rx buffer
2. Modify UART event example
3. Add comments for uart_flush, add alias API uart_flush_input to clear the rx buffer
4. Modify the way rx_buffered_len is calculated
A couple of typos referencing tx_ring_buf when rx_ring_buf, slv_tx_mux
instead of slv_rx_mux.
Also, I2C_ENTER_CRITICAL()/I2C_EXIT_CRITICAL() usage was not consistent.
Only some of the _set_ functions had them. Most of the _get_ function
had them? It is my understanding that they should be wrapped around
writes, not reads? (I think we still need the lock for reading pairs of consistent values)
Also, the ticks_to_wait timeout handling in i2c_master_cmd_begin() would
not handle integer rollover correctly.
Merges https://github.com/espressif/esp-idf/pull/1180
Previously SDSPI host driver would rely on retry count when waiting for
the card to read or write data. This caused different timeout times
depending on CPU frequency and card clock frequency. In practice, card
performance does not depend on these two factors.
This change uses timeout_ms field of sdmmc_command_t introduced
previously for SDMMC host.
Fixes https://esp32.com/viewtopic.php?f=2&t=3440&p=16037 and similar
issues related to SDSPI timeouts.
Reported from github:
https://github.com/espressif/esp-idf/issues/1312https://github.com/espressif/esp-idf/issues/1193
Issues:
1. We used to use event group in the driver, which would cause:
a. longer operation time since the event group are based on FreeRTOS timer.
b. Operation fails if the timer queue is not long enough.
2. There might be some issue with event group, we will still try to provide a small test code in other branch.
modification:
1. use queue instead of event-bit for internal commands
2. use queue overwrite for cmd_done event
1. All the registers of touch sensor 8 and 9 are mismatched except the ‘dac’ field in touch register of RTC IO
2. To swap the index for sensor 8 and 9 in APIs.
Reported from github:
https://github.com/espressif/esp-idf/issues/1219https://github.com/espressif/esp-idf/issues/1202
After providing a simple code to digital team, they confirmed that this is a hardware bug.
Root cause:
The fifo reset signal is incorrectly connected
If we want to reset tx fifo of UART2, we have to set txfifo_rst bit of both UART1 and UART2
If we want to reset rx fifo of UART2, we have to set rxfifo_rst bit of both UART1 and UART2
Workaround:
we don't use fifo rst bit in driver.
Documentation:
Digital team would update TRM and give more explanation about this issue.
1. move settings of WIFI_CLK_EN_REG for bluetooth into controller init/deinit APIs
2. modify the bit mask used in phy_rf init/deinit to use WIFI-BT shared bits
append adc support and api
- esp_err_t adc2_config_width(adc_bits_width_t width_bit);
- esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten);
- int adc2_get_voltage(adc2_channel_t channel);
Reported from:
https://github.com/espressif/esp-idf/issues/703https://github.com/espressif/esp-idf/issues/917
In uart driver we didn't change the default value of tx idle num, so there would be a delay after tx FIFO is empty.
1. Add API to set tx idle interval before next data transmission. (The UART hardware can add an interval after tx FIFO is empty).
2. Set default tx idle interval to zero.
3. Add hardware disable in uart driver delete function.
Reported from different sources from github or bbs:
https://github.com/espressif/esp-idf/issues/680https://github.com/espressif/esp-idf/issues/922
We tested reading several sensor or other I2C slave devices, if the power and SDA/SCL wires are in proper condition, everything works find with reading the slave.
If we remove the power supply for the slave during I2C is reading, or directly connect SDA or SCL to ground, this would cause the I2C FSM get stuck in wrong state, all we can do is the reset the I2C hardware in this case.
After this commit, no matter whether the power supply of I2C slave is removed or SDA / SCL are shorted to ground, the driver can recover from wrong state.
We are not sure whether this the save issue with the reported one yet, but to make the driver more robust.
Further information:
1. For I2C master mode, we have tested different situations, e.g., to short the SDA/SCL directly to GND/VCC, to short the SDA to SCL, to un-plug the slave device, to power off the slave device. Under all of those situations, this version of driver can recover and keep working.
2. Some slave device will die by accident and keep the SDA in low level, in this case, master should send several clock to make the slave release the bus.
3. Slave mode of ESP32 might also get in wrong state that held the SDA low, in this case, master device could send a stop signal to make esp32 slave release the bus.
Modifications:
1. Disable I2C_MASTER_TRAN_COMP interrupt to void extra interrupt.
2. Disable un-used timeout interrupt for slave.
3. Add bus reset if error detected for master mode.
4. Add bus clear if SDA level is low when error detected.
5. Modify the argument type of i2c_set_pin.
6. add API to set timeout value
7. add parameter check for timing APIs
Previously the timeout was set to the same value (1000ms) for all kinds
of commands. In some cases, such as with slow cards, write commands
failed to complete in time.
This change makes command timeouts configurable via sdmmc_host_t
structure, and also makes default timeouts different for ordinary
commands and write commands.
Closes https://github.com/espressif/esp-idf/issues/1093
Ref TW15774.
using apll_param to setup APLL
new apll calculation method, much faster
validate freq calculation
Ensure that the i2s frequency is greater than the hardware limit
Add description of how to calculate apll clock, support apll for other 16-bits audio, check rev0 chip
correct space
1. Support built-in ADC for I2S.
2. Modify code of ADC, made no change to the original APIs.
3. Add APIs in I2S:
esp_err_t i2s_set_adc_mode(adc_unit_t adc_unit, adc1_channel_t adc_channel);
4. Add I2S ADC/DAC example code.
5. add old-fashion definition to make it more compatible
6. replase spi_flash_ APIs with esp_partition_ APIs
7. add example of generating audio table from wav
8. change example sound
Added component containg API that is able to correct raw ADC readings
into a voltage in mV. Also provided a helper function that combines
the process of getting the raw ADC1 reading then converting it to a
voltage in mV. In doing so, the adc1_get_voltage() function of the ADC
driver has been deprecated. Instead there is now adc1_get_raw to obtain
the raw ADC1 reading, and adc1_to_voltage() that gets the raw reading
and converts all in one function. Functions using the deprecated
adc1_get_voltage() have also been updated to use adc1_get_raw().
Conversion is based on ADC characteristics. The characteristics are based
on the ADC's v_ref, herefore the appropriate structure and functions have
been provided to obtain the ADC characteristics.
The existing ADC driver has also been modified by adding a function to
route the internal ADC reference voltage to a GPIO allowing users to measure
it manually.
Relevant documentation has also been updated
1. add sens_struct.h
2. add definition of RTCCNTL and RTCIO
3. modify touch pad examples
4. update example code.
5. add comments add option in menuconfig
6. fix issue that pad index 8 and 9 are mismatched
7. add touch_pad_read_filtered() api to get value filtered by iir filter
8. modify touch pad isr func
9. Make the items in perihperal.ld in the sequence of address
10. delete Kconfig for touch pad
11. add touchpad filter APIs to adjust the filter
12. add touch_pad into index.rst
13. add touch_pad in Doxyfile
14. add touch_pad.rst
By default SD cards are initialized in default speed (DS) mode. Enabling
HS mode requires SWITCH_FUNC command to be sent twice: first time to
query if the card supports switching to HS mode, second time to perform
the switch.
This change implements SWITCH_FUNC command and adds the procedure to
switch to HS mode.
‘make_hw_cmd’ function checks opcodes in a few cases. Comparing opcode
does not tell the whole story, because for some SD commands there is are
APP commands with the same opcodes. This change introduces a flag which
indicates whether the next command is going to be an APP command.
The check for APP_SET_BUS_WIDTH command is updated to use this flag.
This fixes a bug with an unexpected STOP_TRANSMISSION command sent after
SWITCH_FUNC command, which has opcode 6, same as APP_SET_BUS_WIDTH.
MMC_RSP_BITS helper function had a hack that it flipped word order in
the response, assuming that response size is 4 words. This hack does not
work for responses which are not 4 words long (such as the SWITCH_FUNC
response, which is 64 words long).
This change removes the hack and the matching word order reversal code
in sdmmc driver.
1. Rename api from rmt_get_ringbuf_handler to rmt_get_ringbuf_handle (Github Issue #274)
2. doxygen param rename
3. change API rmt_wait_tx_done to specify maximum waiting time
4.Change return type of rmt_wait_tx_done API from bool to esp_err_t
5. update doc
The address field should be placed at the highest bits of address and slv_wr_status registers. Instead of breaking the address into two parts and fill in each register, move the address to the highest bits and write to the registers respectively.
Breaking change: if you fill-in the SPI address filed in a previous version in some way and it works correctly, you still have to rewrite the address, in a more intuitive way.
force rxlength=length and mosi=1 and inlink.start=1 on in full-duplex mode.
set rxlength > length is forbidden in full-duplex mode.
TW#12609, TW#14240, https://www.esp32.com/viewtopic.php?f=13&t=2519
SDMMC hardware treats all buffers as aligned, and ignores 2 LSBs of
addresses written into DMA descriptors. Previously SDMMC host driver
assumed that data buffers passed from SDDMC command layer would be
aligned. However alignment checks were never implemented in the command
layer, as were the checks that the buffer coming from the application
would be in DMA capable memory. Most of the time this was indeed true.
However in some cases FATFS library can pass buffers offset by 2 bytes
from word boundary. “DMA capable” restriction may be broken if pSRAM
support is used.
This change adds buffer checks to the SDMMC host driver (alignment and
DMA capability), so that the host layer will error out for incompatible
buffers. In SDMMC command layer, a check is added to read and write
functions. If an incompatible buffer is passed from the application, new
buffer (512 bytes size) is allocated, and the transfer is performed
using {READ,WRITE}_SINGLE_BLOCK commands.
SD SPI mode driver
This MR adds functionality to support SD cards connected via SPI interface.
Additionally, two bugs are fixed:
- Definition of `SPI_TRANS_MODE_DIOQIO_ADDR` in spi_master driver
- SD card probing frequency was 4000kHz instead of 400kHz as required by the standard
See merge request !727
gpio_matrix_out function will set output enable for GPIO, seems in gpio_matrix_out there will be a short moment that the chip will output GPIO level.
So we can set GPIO as high before gpio_matrix_out function.
Previously the first call to rmt_driver_uninstall() would remove the interrupt handler,
even if other channels still had the driver installed.
Adds an OS-level lock to control concurrent registration/deregistration of channels.
1. Name change from chopper to carrier, block diagram update, minor changes to example codes
2. mcpwm_reg.h changed, brought uniformity in comments, worked on suggestions, duty to accept float. Some name changes!
3. Minor readme changes and Indetation
4. Minor change: move mcpwm_reg.h and mcpwm_struct.h to new path
5. Minor change: addition of BLDC example code and Readme
6. Name changed from epwm to mcpwm
7. Improve the reg name in mcpwm_struct.h
8. Name change chopper>carrier, deadband>deadtime
component/esp32 : fix dualcore bug
1. When dual core cpu run access DPORT register, must do protection.
2. If access DPORT register, must use DPORT_REG_READ/DPORT_REG_WRITE and DPORT_XXX register operation macro.
See merge request !742
1. When dual core cpu run access DPORT register, must do protection.
2. If access DPORT register, must use DPORT_REG_READ/DPORT_REG_WRITE and DPORT_XXX register operation macro.
I2S driver - fixed support for 24 and 32-bits, fixed tx/rx at the same time
- Modify sample can test with 24, 32-bits audio
- Add i2s sample README
- simply i2s_push function
- change sample rates, bits per sample, channel on fly
See merge request !483
Add support 24, 32 bits
@jxmao optimize i2s_zero_buffer
@jxmao correct config support slave mode
@jxmao correct setup pin support tx/rx at the same time
Enhance pin power
@jxmao add dynamic change number of channels
remove nvs_init
remove start log and enhance power pin setup
using enum for i2s_channel and i2s_bits_per_sample, return ESP_ERR_INVALID_ARG when check params
validate i2s_bits_per_sample and channel
check tx & rx buffer before fill zero
remove checking channel as @jxmao suggest
limit dma buffer
modify i2s pin back to gpio mux before configure gpio matrix, resolve github issue #512
Add support 24, 32 bits
reduce push function
Modify sample can test with 24, 32-bits
Add i2s sample README
Fixed i2s_set_clk got reset sometime
can changes bit-wide while running
Fix sample rate calculation for DAC mode from @jeroen
modify example can change bits per sample every 5 seconds
cleanup
add comment for bytes_per_sample
update as @angus suggestions
Add i2s_set_clk api
I2S driver bug fixed as following log:
@jxmao optimize i2s_zero_buffer
@jxmao correct config support slave mode
@jxmao correct setup pin support tx/rx at the same time
Enhance pin power
@jxmao add dynamic change number of channels
remove nvs_init
remove start log and enhance power pin setup
using enum for i2s_channel and i2s_bits_per_sample, return ESP_ERR_INVALID_ARG when check params
validate i2s_bits_per_sample and channel
check tx & rx buffer before fill zero
remove checking channel as @jxmao suggest
limit dma buffer
modify i2s pin back to gpio mux before configure gpio matrix, resolve github issue #512
limit dma buffer to 4092
change gpio_matrix_*_check to inline function, remove some comments and rename test_i2s function to setup_triangle_sine_waves
for change commit title
sdmmc: handle card removal when CD is not used
When SD card is removed during transaction, SDMMC peripheral can report
a range of errors, such as timeouts, CRC errors, start/end bit errors.
Under normal conditions (card is inserted), SDMMC peripheral also generates
command done or data done interrupts. When the card is removed, such
interrupts may not be always generated.
This change fixes handling of timeout interrupts and SBE interrupts.
It also adds a one second timeout into the event processing loop. This
timeout allows applications to recover in cases when the SDMMC peripheral
doesn’t generate command/data done event on card removal.
Fixes TW11592.
See merge request !678
SPI transfer length is bits, not bytes, so the error should indicate bits. Also, there are separate lengths for rx and
tx (confusingly named rxlength and length... if rxlength is 0, length is used). The code checks the tx length for the
rx, so it never validates rxlength.
Originally contributed as part of #511https://github.com/espressif/esp-idf/pull/511
When SD card is removed during transaction, SDMMC peripheral can report
a range of errors, such as timeouts, CRC errors, start/end bit errors.
Under normal conditions (card is inserted), SDMMC peripheral also generates
command done or data done interrupts. When the card is removed, such
interrupts may not be always generated.
This change fixes handling of timeout interrupts and SBE interrupts.
It also adds a one second timeout into the event processing loop. This
timeout allows applications to recover in cases when the SDMMC peripheral
doesn’t generate command/data done event on card removal.
To enable tx empty interrupt each time the tx ringbuffer get filled, so that tx function will not block if tx data length is larger than tx ringbuffer size.
Reported from customer of Audio team.
modify touch pad read function
The touch pad read function taks too much time within spin lock waiting for the "done bit". (about 7.6ms as we tested)
So we try to use a mutex on the touch read function and any other functions might change the "done bit".
See merge request !543
This issue is reported from https://github.com/espressif/esp-idf/issues/304.
We found that when we operate the hw command registers in I2C struct, sometimes the behaviour would be different in DEBUG/RELEASE optimisation level:
The code looks like this:
I2C[i2c_num]->command[p_i2c->cmd_idx].byte_num -= 0;
In DEBUG configuration:
I2C[i2c_num]->command[p_i2c->cmd_idx].byte_num -= 0;
400f3ab0: 3388 l32i.n a8, a3, 12
400f3ab2: 14c882 addi a8, a8, 20
400f3ab5: a08840 addx4 a8, a8, a4
400f3ab8: 0020c0 memw
400f3abb: 2898 l32i.n a9, a8, 8
400f3abd: 0020c0 memw
400f3ac0: 28b8 l32i.n a11, a8, 8
400f3ac2: 74a090 extui a10, a9, 0, 8
400f3ac5: 00af92 movi a9, 0xffffff00
400f3ac8: 109b90 and a9, a11, a9
400f3acb: 2099a0 or a9, a9, a10
400f3ace: 0020c0 memw
400f3ad1: 2899 s32i.n a9, a8, 8
In RELEASE configuration:
I2C[i2c_num]->command[p_i2c->cmd_idx].byte_num -= 0;
400f2ba2: 580572 l8ui a7, a5, 88
400f2ba5: 747070 extui a7, a7, 0, 8
400f2ba8: 0020c0 memw
400f2bab: 584572 s8i a7, a5, 88
Looks like the compiler will make it a 8bit operation after optimisation.
But the register value changes from 0x901 to 0x101.
After this 8-bit optimisation, the 11th bit changed from 1 to zero, which caused this error.
We are still trying to find out why that happens, because there might be some risk when operating the register struct.
This is a workaround to avoid "-=" operation on I2C register struct fields.
1. Add low speed channels for LEDC module.
2. Improve fade object allocate mechanism.
3. Improve ledc example, add 2 low speed channels in example.
4. Remove debug code
5. Improve the register bit field name of slow clock.
The touch pad read function taks too much time within spin lock waiting for the "done bit". (about 7.6ms as we tested)
So we try to use a mutex on the touch read function and any other functions might change the "done bit".
1. add fading functions.
2. clear up ledc.c and ledc.h
3. update api doc.
4. add ledc example
5. edit ledc.rst and add readme for example code.
6. add s_ prefix for static global values.
7. add mutex for fade functions
8. minor changes according to the comments.
2. update example comments and other minor changes
3. rename API: i2c_cmd_link_create/i2c_cmd_link_delete (+4 squashed commits)
Squashed commits:
[2e0ac3e] 1. coding style: add one space after condition key words.
2. modify i2c.h, use gpio_num_t instead of int, improve comments of return values
3. add i2c index in index.rst
4. add readme for i2c example
[4991d92] update i2c.doc
[88b672e] driver: i2c
1. add mux and spin lock to run in a thread-safe way.
2. modify example code
[4eb15fe] driver: i2c code
1. add i2c master code
2. add i2c slave code
3. add i2c example code
4. add DRAM_ATTR for I2C array
bugfix: uart event mismatch
Fix bug of uart frame error and parity error interrupt mismatch in driver code, which will cause the corresponding interrupt can not be cleared correctly, and will finally cause a interrupt watch dog.
See merge request !335
GPIO driver: add per-pin interrupt handlers
1. add ISR handler apis so that users of different layers can hook their own isr handler on different GPIO.
Audio project has different software layers, they need different gpio isr handler for layer instead of processing all GPIO interrupts in one handler.
If this kind of calling a handler from isr is not proper, please kindly point out.
2. add gpio example code.
3. update gpio doc.
See merge request !345
