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bugfix(uart): set default tx idle num

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Reported from:
https://github.com/espressif/esp-idf/issues/703
https://github.com/espressif/esp-idf/issues/917
In uart driver we didn't change the default value of tx idle num, so there would be a delay after tx FIFO is empty.

1. Add API to set tx idle interval before next data transmission. (The UART hardware can add an interval after tx FIFO is empty).
2. Set default tx idle interval to zero.
3. Add hardware disable in uart driver delete function.
This commit is contained in:
Wangjialin 2017-10-18 12:04:59 +08:00
parent 2c95a77cf9
commit 303b9f60db
2 changed files with 35 additions and 0 deletions
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13
components/driver/include/driver/uart.h
View file

@ -460,6 +460,19 @@ esp_err_t uart_set_rts(uart_port_t uart_num, int level);
*/
esp_err_t uart_set_dtr(uart_port_t uart_num, int level);
/**
* @brief Set UART idle interval after tx FIFO is empty
*
* @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param idle_num idle interval after tx FIFO is empty(unit: the time it takes to send one bit
* under current baudrate)
*
* @return
* - ESP_OK Success
* - ESP_FAIL Parameter error
*/
esp_err_t uart_set_tx_idle_num(uart_port_t uart_num, uint16_t idle_num);
/**
* @brief Set UART configuration parameters.
*

22
components/driver/uart.c
View file

@ -43,6 +43,7 @@ static const char* UART_TAG = "uart";
#define UART_EMPTY_THRESH_DEFAULT (10)
#define UART_FULL_THRESH_DEFAULT (120)
#define UART_TOUT_THRESH_DEFAULT (10)
#define UART_TX_IDLE_NUM_DEFAULT (0)
#define UART_ENTER_CRITICAL_ISR(mux) portENTER_CRITICAL_ISR(mux)
#define UART_EXIT_CRITICAL_ISR(mux) portEXIT_CRITICAL_ISR(mux)
#define UART_ENTER_CRITICAL(mux) portENTER_CRITICAL(mux)
@ -469,6 +470,17 @@ esp_err_t uart_set_dtr(uart_port_t uart_num, int level)
return ESP_OK;
}
esp_err_t uart_set_tx_idle_num(uart_port_t uart_num, uint16_t idle_num)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
UART_CHECK((idle_num <= UART_TX_IDLE_NUM_V), "uart idle num error", ESP_FAIL);
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
UART[uart_num]->idle_conf.tx_idle_num = idle_num;
UART_EXIT_CRITICAL(&uart_spinlock[uart_num]);
return ESP_OK;
}
esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_config)
{
esp_err_t r;
@ -492,6 +504,8 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
r = uart_set_baudrate(uart_num, uart_config->baud_rate);
if (r != ESP_OK) return r;
r = uart_set_tx_idle_num(uart_num, UART_TX_IDLE_NUM_DEFAULT);
if (r != ESP_OK) return r;
r = uart_set_stop_bits(uart_num, uart_config->stop_bits);
return r;
}
@ -1125,5 +1139,13 @@ esp_err_t uart_driver_delete(uart_port_t uart_num)
free(p_uart_obj[uart_num]);
p_uart_obj[uart_num] = NULL;
if(uart_num == UART_NUM_0) {
periph_module_disable(PERIPH_UART0_MODULE);
} else if(uart_num == UART_NUM_1) {
periph_module_disable(PERIPH_UART1_MODULE);
} else if(uart_num == UART_NUM_2) {
periph_module_disable(PERIPH_UART2_MODULE);
}
return ESP_OK;
}