SDMMC host suffers from an issue that it outputs data near the rising
edge of the card clock, which is the edge used by the card to sample
data. If sampling time constraint is not satisfied, card may read data
after the transition.
The phases of output/input data can, in fact, be adjusted. However this
adjustment happens in the clock generation block outside of the host.
So the maximum phase change which can be created this way is equal to
half of the host clock period. So if the host clock is set to the lowest
possible frequency (for the given card frequency), then the phase offset
(and hence the hold time) will be the highest. This change modifies the
logic used to determine clock dividers accordingly.
sdmmc host: set correct dout phase and print correct frequency
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