When using CPP and C combination this particular file threw error on linking.
Merges https://github.com/espressif/esp-idf/pull/1249
(Amended to add INC_FREERTOS_H guard, comment on #endif)
1. Usage of this module required applications to include additional
files. What files to include is not very intuitive. Instead, it is
better for the header file itself to include other files as required.
2. Even though it may seem logical, it is better to explicitly mention
that an item needs to be "Returned" after a Receive
Signed-off-by: Piyush Shah <piyush@espressif.com>
It was observed that if the ring buffer size provided by application
is not a multiple of 4, some checks were failing (as read_ptr and write_ptr
could shoot beyond the ring buffer boundary), thereby causing asserts.
Simply wrapping around the pointers for such cases fixes the issue.
Moreover, because of the logic for maintaining 4-byte boundary,
it was also possible that a wrap-around occurred for some data,
even when the actual size remaining was sufficient for it.
Eg. Buffer available: 34, data size: 34, 4-byte aligned size: 36
Since the logic compares against 36, it writes 34 bytes and does a
wraparound. But since all 34 bytes are already written, there is
nothing to write after wrapping. It is better to just re-set the
write pointer to the dtart of ring buffer in such cases.
Tested send/receive for various arbitrary sizes of data and for
arbitrary sizes of ring buffer.
Alternative Solutions:
1) Allow only sizes which are multiples of 4, and return error otherwise.
Appropriate code and documentation change would be required
2) Allow arbitrary sizes, but internally add upto 3 bytes to make
the total size a multiple of 4
Signed-off-by: Piyush Shah <piyush@espressif.com>
disabled
The misssing stubs get pulled in from the toolchain's libstdc++ also
causing to pull in defined stubs. This results in redefinition of
symbols. Fixing it by simply adding the missing stubs when exceptions
are disabled.
Signed-off-by: Amey Inamdar <amey.inamdar@gmail.com>
This defines the OpenSSL X509_CHECK_FLAG_...s and the set/clear
accessors. Since none of them are supported, the set / clear
accessor currently always does nothing and returns error.
This call is often part of the generic openssl user code to
set up certificate verification. This patch allows it to
compile for ESP32 and decide at runtime what to do about
unsupported flags.
Merges https://github.com/espressif/esp-idf/pull/980
This lets the user code set the mbedtls hostname using the standard OpenSSL
X509_VERIFY_PARAM_set1_host() API semantics.
The API takes an X509_VERIFY_PARAM pointer. We use the fact that is
a composed member of the SSL struct to derive the SSL pointer.
The X509_VERIFY_PARAM_set1_host() is unusual in that it can accept a
NUL terminated C string as usual, or a nonterminated pointer + length.
This implementation converts the latter to the former if given, before
using it.
This is enough for user code to get the openssl wrapper to make
mbedtls confirm the CN on the peer cert belongs to the hostname used
to reach it, by doing, eg
X509_VERIFY_PARAM_set1_host(SSL_get0_param(myssl), myhostname, 0);
Merges https://github.com/espressif/esp-idf/pull/980
This adds the standard OpenSSL api to get a pointer to the SSL struct's
X509_VERIFY_PARAM. We need this for the OpenSSL api to set the peer
hostname introduced in the next patch.
Part of https://github.com/espressif/esp-idf/pull/980
These functions were discarded but not provided in ROM.
Generated from commit 8ad0aa7d6 in newlib script repo. Didn't rebuild most of libc/libc_nano,
only appended the missing object files to the existing archives (should save some git churn).
In the queue registry test, start_sem is given twice to let both tasks
start the test. Each task takes start_sem, does some work, gives done_sem,
and goes on to wait for start_sem again.
It may happen that one task can grab start_sem, add queues to the
registry, give done_sem, then grab start_sem again, delete the queues
from the registry, and give done_sem again. At this point, main test
task takes done_sem twice and proceeds to verify that queues have been
added to the registry. But in fact, the first task has already deleted
its queues from the registry, and the second one might not have added
the queues yet. This causes test to fail.
This changes the test to use separate start semaphores for each task,
to avoid the race condition.
1. All the registers of touch sensor 8 and 9 are mismatched except the ‘dac’ field in touch register of RTC IO
2. To swap the index for sensor 8 and 9 in APIs.
This commit makes the configQUEUE_REGISTRY_SIZE and
configGENERATE_RUN_TIME_STATS configurable in menuconfig.
- configQUEUE_REGISTRY_SIZE can now be set in menuconfig.
- The functions vQueueAddToRegistry() and vQueueUnregisterQueue() were made
SMP compatbile
- pcQueueGetName() was backported from FreeRTOS v9.0.0
- Added test case for Queue Registry functions
- configGENERATE_RUN_TIME_STATS can now be enabled in menuconfig. CCOUNT or
esp_timer can be selected as the FreeRTOS run time clock in menuconfig as
well, although CCOUNT will overflow quickly.
- Run time stats collection (in vTaskSwitchContext) and generation (in
uxTaskGetSystemState) have been made SMP compatible. Therefore
vTaskGetRunTimeStats() now displays the run time usage of each task as a
percentage of total runtime of both CPUs
Squash
- Remove ASCII-only configuration, CP437 is used instead
- Add dynamic code page configuration
See components/fatfs/src/00history.txt for FATFS changelog.
Reported from github:
https://github.com/espressif/esp-idf/issues/1219https://github.com/espressif/esp-idf/issues/1202
After providing a simple code to digital team, they confirmed that this is a hardware bug.
Root cause:
The fifo reset signal is incorrectly connected
If we want to reset tx fifo of UART2, we have to set txfifo_rst bit of both UART1 and UART2
If we want to reset rx fifo of UART2, we have to set rxfifo_rst bit of both UART1 and UART2
Workaround:
we don't use fifo rst bit in driver.
Documentation:
Digital team would update TRM and give more explanation about this issue.
1. use esp_timer instead of FreeRTOS timer to implement osi_alarm in bluedroid
2. Remove two APIs: osi_alarm_now() and osi_alarm_time_diff() and modify the hci layer logic that use them
3. Implement osi_alarm_get_remaining_ms()
4. Move the definition of struct alarm_t in source file "alarm.c"
5. Add definition of module error code
To achieve reliable operation with GD flash at 80MHz, need to raise
core voltage.
This causes the following current consumption increase:
At 80MHz: from 29mA to 33mA
At 160MHz: from 41mA to 47mA
Test conditions: 2 cores running code from IRAM, remaining peripherals
clock gated.
Earlier recursive mutex was being used for this but since
SCOMPARE1 is already being saved/restored during context
switch, atomic compare and set can be used for this.
Signed-off-by: Mahavir Jain <mahavir@espressif.com>
Test cases were added for the following functions
- xTaskNotify(), xTaskNotifyGive(), xTaskNotifyFromISR(), vTaskNotifyGiveFromISR(),
- xTaskNotifyWait(), ulTaskNotifyTake()
- vTaskDelayUntil()
The following function was made smp compatible and tested as well
- eTaskGetState()
Old behavior assumes message compressed when any of 2 most significant bits are set,
But in fact Message compressed only when both those bits are set to 1.
Also maximal label length should be 63 bytes.
Renamed the internal rc to __err_rc to avoid clashes with local variables.
This code would not do the expected thing with the original ESP_ERROR_CHECK macro:
esp_err_t my_func(esp_err_t x)
{
assert(x == 23);
}
esp_err_t rc = 23; //some value that is important fo the user
ESP_ERROR_CHECK(my_func(rc));
The macro will expand to:
esp_err_t rc = (my_func(rc));
And the code will assert, as my_func will receive a random value - whatever is in the internal macro rc temp variable. This is due to the C weirdness of allowing this code:
int x = x; //x has a random value.
Pointer tcpip_api_call *m should be converted to pppapi_msg* instead of pppapi_msg_msg*
in pppapi_do_ppp_set_default(), pppapi_do_ppp_free() and so on.
It solve this issue https://github.com/espressif/esp-idf/pull/1028
so there is no need to patch ip4.c because now netif_defauilt is setted correctly.
Also it prevents memory corruption when pppapi_free() is called.
This commit reverts the revert on the new task watchdog API. It also
fixes the following bug which caused the reversion.
- sdkconfig TASK_WDT_TIMEOUT_S has been reverted from the unit of ms back to the
unit of seconds. Fixes bug where projects using the new API without rebuilding sdkconfig
would cause the old default value of 5 to be interpreted in ms.
This commit also adds the following features to the task watchdog
- Updated idle hook registration to be compatible with dual core hooks
- Updated dual core hooks to support deregistration for cpu
- Legacy mode has been removed and esp_task_wdt_feed() is now replaced by
esp_task_wdt_reset(). esp_task_wdt_feed() is deprecated
- Idle hooks to reset are now registered/deregistered when the idle tasks are
added/deleted from the Task Watchdog instead of at Task Watchdog init/deinit
- Updated example
1. V366, fix a problem which initialize current can reach 800mA.
2. V365, fix a problem for pll_cap tracking in Coexist (BT & WIFI)
mode. The problem will make Coexist (BT & WIFI) WIFI AP mode TX
Fail in high temperature(>70).
3. V364, fix a bug of BT and Wifi coexist (hung in function of
force_wifi_mode())
component/bt: Fix the bug of master don't send pair request to the slave when the sec_act set to the value of ESP_BLE_SEC_ENCRYPT.
See merge request !1376
1. move settings of WIFI_CLK_EN_REG for bluetooth into controller init/deinit APIs
2. modify the bit mask used in phy_rf init/deinit to use WIFI-BT shared bits
This commit updates various test cases throughout esp-idf such that
the values used for timer divider pass the assertions in the timer component.
Timer divider values must be between 2 to 65536
Previously esp_restart would stall the other CPU before enabling RTC_WDT.
If the other CPU was executing an s32c1i instruction, the lock signal
from CPU to the arbiter would still be held after CPU was stalled. If
the CPU running esp_restart would then try to access the same locked
memory pool, it would be stuck, because lock signal would never be
released.
With this change, esp_restart resets the other CPU before stalling it.
Ideally, we would want to reset the CPU and keep it in reset, but the
hardware doesn't have such feature for PRO_CPU (it is possible to hold
APP_CPU in reset using DPORT register). Given that ROM code will not use
s32c1i in the first few hundred cycles, doing reset and then stall seems
to be safe.
In addition to than, RTC_WDT initialization is moved to the beginning of
the function, to prevent possible lock-up if CPU stalling still has any
issue.
1. Make sure that 8MD256 clock used to estimate XTAL frequency is enabled
before trying to use rtc_clk_cal_ratio.
This fixes "Bogus XTAL frequency: 0 MHz" warnings after software reset.
2. Don't call rtc_clk_xtal_freq_estimate if XTAL frequency is already
known. This reduces startup time after deep sleep or software reset.
3. Compare known XTAL frequency and estimated one before printing a
warning. This fixes "Possibly invalid CONFIG_ESP32_XTAL_FREQ setting
(40MHz). Detected 40 MHz." warnings.
Previous implementation waited for 20us after setting
RTC_CNTL_SOC_CLK_SEL_XTL register, using ets_delay_us, assuming that
the CPU was running at XTAL frequency. In reality, clock switch happened
on the next RTC_SLOW_CLK cycle, and CPU could be running at the previous
frequency (for example, 240 MHz) until then.
ets_delay_us would wait for 20 us * 40 cycles per us = 800 CPU cycles
(assuming 40 MHz XTAL; even less with a 26 MHz XTAL).
But if CPU was running at 240 MHz, 800 cycles would pass in just 3.3us,
while SLOW_CLK cycle could happen as much as 1/150kHz = 6.7us after
RTC_CNTL_SOC_CLK_SEL_XTL was set. So the software would not actually wait
long enough for the clock switch to happen, and would disable the PLL
while CPU was still clocked from PLL, leading to a halt.
This implementation uses rtc_clk_wait_for_slow_cycle() function to wait
until the clock switch, removing the need to wait for a fixed number of
CPU cycles.
Some RTC features are synchronized to RTC_SLOW_CLK, so sometimes
software needs to wait for the next slow clock cycle.
This function implements waiting using Timer Group clock calibration
feature.
append adc support and api
- esp_err_t adc2_config_width(adc_bits_width_t width_bit);
- esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten);
- int adc2_get_voltage(adc2_channel_t channel);
The mutex is common across all the threads. It needn't be held across
the init_routine() call as long as the 'once' behaviour is guaranteed
Saw a deadlock case, where init_routine of one thread was waiting for
the completion of init_routine in another thread.
t2: wait for command
t1: pthread_once:
lock once_mux
init_routine:
inform thread t2
wait for signal from t2
t2: received command
pthread_once
lock once_mux (already held by t1)
---- Deadlock ----
Reported from:
https://github.com/espressif/esp-idf/issues/703https://github.com/espressif/esp-idf/issues/917
In uart driver we didn't change the default value of tx idle num, so there would be a delay after tx FIFO is empty.
1. Add API to set tx idle interval before next data transmission. (The UART hardware can add an interval after tx FIFO is empty).
2. Set default tx idle interval to zero.
3. Add hardware disable in uart driver delete function.
1. add sw interrupt cause osi to controller.
2. modify the kconfig to improve the option view.
3. add option of the cpu core which bluedroid run.
4. add option of the cpu core which bluetooth controller run.
Previously ioctl was declared as a macro in lwip/sockets.h.
Disabling LWIP_POSIX_SOCKETS_IO_NAMES removed that declaration.
This adds sys/ioctl.h file and the missing declaration.
Also adds missing includes in vfs.c.
Reported from different sources from github or bbs:
https://github.com/espressif/esp-idf/issues/680https://github.com/espressif/esp-idf/issues/922
We tested reading several sensor or other I2C slave devices, if the power and SDA/SCL wires are in proper condition, everything works find with reading the slave.
If we remove the power supply for the slave during I2C is reading, or directly connect SDA or SCL to ground, this would cause the I2C FSM get stuck in wrong state, all we can do is the reset the I2C hardware in this case.
After this commit, no matter whether the power supply of I2C slave is removed or SDA / SCL are shorted to ground, the driver can recover from wrong state.
We are not sure whether this the save issue with the reported one yet, but to make the driver more robust.
Further information:
1. For I2C master mode, we have tested different situations, e.g., to short the SDA/SCL directly to GND/VCC, to short the SDA to SCL, to un-plug the slave device, to power off the slave device. Under all of those situations, this version of driver can recover and keep working.
2. Some slave device will die by accident and keep the SDA in low level, in this case, master should send several clock to make the slave release the bus.
3. Slave mode of ESP32 might also get in wrong state that held the SDA low, in this case, master device could send a stop signal to make esp32 slave release the bus.
Modifications:
1. Disable I2C_MASTER_TRAN_COMP interrupt to void extra interrupt.
2. Disable un-used timeout interrupt for slave.
3. Add bus reset if error detected for master mode.
4. Add bus clear if SDA level is low when error detected.
5. Modify the argument type of i2c_set_pin.
6. add API to set timeout value
7. add parameter check for timing APIs
This commit makes configUSE_TRACE_FACILITY and
configUSE_STATS_FORMATTING_FUNCTIONS configurable in kconfig. Test cases fro the
functions enabled by the two configurations above have also been added.
Test cases for the following functions have been added...
- uxTaskGetSystemState()
- uxTaskGetTaskNumber()
- vTaskSetTaskNumber()
- xEventGroupClearBitsFromISR()
- xEventGroupSetBitsFromISR()
- uxEventGroupGetNumber()
- uxQueueGetQueueNumber()
- vQueueSetQueueNumber()
- ucQueueGetQueueType()
Test cases for the following functions were not required...
- prvListTaskWithinSingleList()
- prvWriteNameToBuffer()
- vTaskList()
Internal byte accessible memory starts with Internal ROM 1 at 0x3FF90000.
Region of RTC fast memory starting at 0x3FF80000 is not used in IDF as
it is mapped to PRO CPU only.
During a call to multi_heap_malloc(), if both these conditions were true:
- That heap only has one block large enough for the allocation
(this is always the case if the heap is unfragmented).
- Another allocation is simultaneously occurring in the same heap.
... multi_heap_malloc() could incorrectly return NULL.
This caused IDF heap_caps_malloc() and malloc() to also fail, particularly
often if only one or two heaps had space for the allocation (otherwise
heap_caps_malloc() fails over to the next heap).
1. Fix WiFi timer enable twice issue
2. Fix a softAP compatibility issue
3. Fix ebuf alloc counter issue
4. remove nvs_flash_init() in esp_wifi_init()
5. Fix scan only find few APs after set bssid
6. Fix can not connect to hidden SoftAP
7. Remove group key entry before connecting ot AP
- _FS_TINY: disables per-file caches
- _FS_TIMEOUT: locking timeout for concurrent access
- _FS_LOCK: prevents operations which are not allowed on open files
Also sets _MAX_SS based on sector size configured for wear_levelling.
This reduces memory usage of FATFS if wear_levelling is using 512 byte
sectors.
Moves the ets_timer_arm() / ets_timer_disarm() code paths to RAM
Overhead is 740 bytes of IRAM, 0 bytes DRAM
(For comparison: If all of esp_timer.c is moved to RAM, overhead is 1068 bytes IRAM and 480 bytes DRAM.)
Allows fcntl() implementation in vfs to be used.
Closes https://github.com/espressif/esp-idf/issues/1070
Note this is different to the other libc file-related syscalls, as there is no
reent structure involved.
Some frameworks based on ESP-IDF need to be able to decide whether to
initialize SPI RAM after the application has started. This change splits
out part of esp_spiram_init which manipulate cache MMU into a separate
function. Applications can disable cache, call esp_spiram_init_cache,
re-enable cache, and then call esp_spiram_init.
Disabling and re-enabling the cache can be achieved using functions
provided in esp_spi_flash.h.
This commit fixes bugs with the dual core changes to freeRTOS tick and idle hooks.
Interrupt watchdog now registers tick hooks to both cores.
API for cross core tick and idle hook registration were also added
Do some refactor to socket ping:
1. Add ping_deinit to kill ping thread
2. Apply configuration set by esp_ping_set_target to socket ping
3. Limit only one ping thread
Previously the timeout was set to the same value (1000ms) for all kinds
of commands. In some cases, such as with slow cards, write commands
failed to complete in time.
This change makes command timeouts configurable via sdmmc_host_t
structure, and also makes default timeouts different for ordinary
commands and write commands.
Closes https://github.com/espressif/esp-idf/issues/1093
Ref TW15774.
