psram: improve clock signal generation, increase drive strength
Also check the chip type when initializing.
This commit is contained in:
Wangjialin
Ivan Grokhotkov
parent
d034bc9ca0
commit
cea7dfbe90
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@ -22,6 +22,7 @@
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_types.h"
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#include "esp_log.h"
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#include "spiram_psram.h"
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#include "rom/ets_sys.h"
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#include "rom/spi_flash.h"
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@ -30,6 +31,7 @@
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#include "soc/io_mux_reg.h"
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#include "soc/dport_reg.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/efuse_reg.h"
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#include "driver/gpio.h"
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#include "driver/spi_common.h"
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@ -71,6 +73,8 @@
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#define PSRAM_SPIWP_IO 10
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#define PSRAM_SPIHD_IO 9
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#define PSRAM_INTERNAL_IO_28 28
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#define PSRAM_INTERNAL_IO_29 29
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#define PSRAM_IO_MATRIX_DUMMY_40M 1
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#define PSRAM_IO_MATRIX_DUMMY_80M 2
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@ -84,7 +88,7 @@
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#define SPI_CACHE_DUMMY SPI0_R_FAST_DUMMY_CYCLELEN //dout 7
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#endif
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static const char* TAG = "psram";
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typedef enum {
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PSRAM_SPI_1 = 0x1,
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PSRAM_SPI_2,
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@ -418,7 +422,6 @@ void IRAM_ATTR psram_spi_init(psram_spi_num_t spi_num, psram_cache_mode_t mode)
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static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode)
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{
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gpio_matrix_out(FLASH_CLK_IO, SPICLK_OUT_IDX, 0, 0);
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gpio_matrix_out(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
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gpio_matrix_out(PSRAM_SPIQ_IO, SPIQ_OUT_IDX, 0, 0);
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gpio_matrix_in(PSRAM_SPIQ_IO, SPIQ_IN_IDX, 0);
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@ -434,16 +437,25 @@ static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode)
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extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M;
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g_rom_spiflash_dummy_len_plus[1] = PSRAM_IO_MATRIX_DUMMY_40M;
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SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, SPI_CACHE_DUMMY + PSRAM_IO_MATRIX_DUMMY_80M, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
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//set drive ability for clock
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, 3, FUN_DRV_S);
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SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[PSRAM_CLK_IO], FUN_DRV, 2, FUN_DRV_S);
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break;
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case PSRAM_CACHE_F80M_S80M:
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extra_dummy = PSRAM_IO_MATRIX_DUMMY_80M;
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g_rom_spiflash_dummy_len_plus[1] = PSRAM_IO_MATRIX_DUMMY_80M;
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SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, SPI_CACHE_DUMMY + PSRAM_IO_MATRIX_DUMMY_80M, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
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//set drive ability for clock
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, 3, FUN_DRV_S);
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SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[PSRAM_CLK_IO], FUN_DRV, 3, FUN_DRV_S);
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break;
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case PSRAM_CACHE_F40M_S40M:
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extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M;
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g_rom_spiflash_dummy_len_plus[1] = PSRAM_IO_MATRIX_DUMMY_40M;
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SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, SPI_CACHE_DUMMY + PSRAM_IO_MATRIX_DUMMY_40M, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
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//set drive ability for clock
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, 2, FUN_DRV_S);
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SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[PSRAM_CLK_IO], FUN_DRV, 2, FUN_DRV_S);
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break;
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default:
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break;
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@ -451,17 +463,31 @@ static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode)
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SET_PERI_REG_MASK(SPI_USER_REG(0), SPI_USR_DUMMY); // dummy en
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//select pin function gpio
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, 2);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, 2);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA2_U, 2);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA3_U, 2);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, 2);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, 2);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO);
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//flash clock signal should come from IO MUX.
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
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}
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//psram gpio init , different working frequency we have different solutions
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esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode) //psram init
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{
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uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
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uint32_t pkg_ver = chip_ver & 0x7;
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if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) {
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ESP_EARLY_LOGE(TAG, "ESP32D2WD do not support psram yet");
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return ESP_FAIL;
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} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) {
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ESP_EARLY_LOGE(TAG, "ESP32PICOD2 do not support psram yet");
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return ESP_FAIL;
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} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) {
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ESP_EARLY_LOGE(TAG, "ESP32PICOD4 do not support psram yet");
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return ESP_FAIL;
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}
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/* note: If the third mode(80Mhz+80Mhz) is enabled, VSPI port will be occupied by the system,
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Application code should never touch VSPI hardware in this case. We try to stop applications
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from doing this using the drivers by claiming the port for ourselves*/
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@ -515,20 +541,20 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
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We do this by routing it signal to signal 224/225, which are used as a loopback; the extra run through
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the GPIO matrix causes the delay. We use GPIO20 (which is not in any package but has pad logic in
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silicon) as a temporary pad for this. So the signal path is:
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GPIO6(SPI CLK) --> signal224(in then out) --> internal GPIO20 --> signal225(in then out) --> GPIO17(PSRAM CLK)
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SPI CLK --> GPIO28 --> signal224(in then out) --> internal GPIO29 --> signal225(in then out) --> GPIO17(PSRAM CLK)
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*/
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gpio_matrix_in(FLASH_CLK_IO, SIG_IN_FUNC224_IDX, 0);
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gpio_matrix_out(20, SIG_IN_FUNC224_IDX, 0, 0);
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gpio_matrix_in(20, SIG_IN_FUNC225_IDX, 0);
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gpio_matrix_out(PSRAM_INTERNAL_IO_28, SPICLK_OUT_IDX, 0, 0);
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gpio_matrix_in(PSRAM_INTERNAL_IO_28, SIG_IN_FUNC224_IDX, 0);
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gpio_matrix_out(PSRAM_INTERNAL_IO_29, SIG_IN_FUNC224_IDX, 0, 0);
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gpio_matrix_in(PSRAM_INTERNAL_IO_29, SIG_IN_FUNC225_IDX, 0);
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gpio_matrix_out(PSRAM_CLK_IO, SIG_IN_FUNC225_IDX, 0, 0);
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break;
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}
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CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_CS_SETUP_M);
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psram_gpio_config(mode);
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WRITE_PERI_REG(GPIO_ENABLE_W1TS_REG, BIT(PSRAM_CS_IO)| BIT(PSRAM_CLK_IO));
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[PSRAM_CS_IO], 2);
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[PSRAM_CLK_IO], 2);
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[PSRAM_CS_IO], PIN_FUNC_GPIO);
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[PSRAM_CLK_IO], PIN_FUNC_GPIO);
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uint32_t id;
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psram_read_id(&id);
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if (((id >> PSRAM_MFG_ID_S) & PSRAM_MFG_ID_M) != PSRAM_MFG_ID_V) {
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