This fixes errors logged on the console: sdmmc_req:
handle_idle_state_events unhandled: 00000004 00000000
The issue happens if "data done" event occurs before "command done".
State machine code did not check *which* event occurred in
SENDING_CMD state, and went to IDLE or SENDING_DATA state on any
non-error event. In this case, we can't process "data done" event
until command has completed. This change introduces "unhandled event"
mask, which is carried over from one run of process_events to the
other. This allows waiting for the "command done" event to complete,
and then process "data done" event.
Ref TW17126.
CMD53 in byte mode supports transfers of any number of bytes between 1
and 512. This change removes limitation that the number of bytes must
be divisible by 4. Host quirk, that such transfers must be split into
two commands (one for the aligned part and the other one for
unaligned) is taken into account.
1. Fix the duty fade check issue reported from https://github.com/espressif/esp-idf/issues/1914
2. Fix the duty overflow issue when duty_scale is set to 1.
3. Fix the duty fade error when a fade operation is under way. We must configure a new duty setting after the previous fade operation has finished due to hardware limit.
4. Add thread-safe version APIs to set duty and fade.
5. Correct the duty range in driver.
It has been observed that, if external SPIRAM is enabled, then under
certain scenarios (e.g. internal memory being too much fragmented),
I2S tx/rx descriptors can land in external SPIRAM and hence resulting
in failure in DMA. Adding explicit capability to allocate in only DMA
capable memory.
Signed-off-by: Mahavir Jain <mahavir@espressif.com>
Command response tokens can be delayed from the original command by 1
to 8 bytes. In 4a2489b9, handling for delayed tokens was added for
normal (no data) commands, and data read commands. This adds handling
for delayed commands for data write commands.
Previous version of the code only connected CD and WP to the
peripheral, in fact the hardware does not use the values of these
signals automatically. This adds code to read CD and WP values when
command is executed and return errors if card is not present, or
write command is executed when WP signal is active.
- In SPI mode, the card will respond to the initial SDIO reset (done
using CMD52) with “invalid command” error. Handle this correctly.
- sdmmc_card_init had a hack where GO_IDLE_STATE (CMD0) command was
sent twice. Add explanation why this is done, and don’t expect
correct response from the card on first CMD0.
- improve logs printed at debug level by adding CMD index
- Add SDIO support at protocol layer (probing, data transfer, interrupts)
- Add SDIO interrupts support in SDMMC host
- Add test (communicate with ESP32 in SDIO download mode)
Existing code assumed that response timeout is not followed by CMD_DONE,
which was not true, in fact. Host datasheet states that CMD_DONE is sent
after an RTO.
All the commands which do not have a response must have their flags set
accordingly. Therefore the host will not send RTO interrupt if response
is not expected. It is a bug in the code logic if it happens otherwise.
SDMMC host suffers from an issue that it outputs data near the rising
edge of the card clock, which is the edge used by the card to sample
data. If sampling time constraint is not satisfied, card may read data
after the transition.
The phases of output/input data can, in fact, be adjusted. However this
adjustment happens in the clock generation block outside of the host.
So the maximum phase change which can be created this way is equal to
half of the host clock period. So if the host clock is set to the lowest
possible frequency (for the given card frequency), then the phase offset
(and hence the hold time) will be the highest. This change modifies the
logic used to determine clock dividers accordingly.
sdmmc host: set correct dout phase and print correct frequency
SET_BUS_WIDTH is not a data transfer command. Extensive search in the
host datasheet and SD card spec did not reveal the origin of this hack
or 'feature'. Further testing showed that removing this does not lead to
regressions.
Fixes exceptions LoadProhibited, when rmt tries read variable p_rmt on RX END which can be 0.
It happens after esp_reset() (OTA) and the rmt is not probably stopped by it.
In other words the routine rmt_driver_isr_default was called before second rx channel was registered.
scenario:
register tx channel
register rx channel
reboot
register tx channel
-> exception (because rx channel is accessed)
Merges https://github.com/espressif/esp-idf/pull/1671
SDSPI driver optimized polling of the response tokens by requesting
two extra bytes on top of the block size (512) and CRC (2), and
checking whether these bytes contained the data response token or
not. In case the token was there, further polling would not need to
happen, thereby reducing latency between two consecutive blocks
transferred. However this caused compatibility issues when these two
extra bytes were sent after reading the final block. When
STOP_TRANSMISSION command was sent, these extra two bytes were
treated as part of the command, causing an invalid command error.
This fixes the logic by only requesting extra two bytes if the block
being read is not the final block. In addition to that, more strict
error checking is implemented for command response tokens.
On most microcontrollers I have worked with one can retrieve the
current state of output GPIO pins. On ESP32 this is not the case
if the pad is not explictly configured to route this information into
the port by configuring it as input or i/o.
Thus add a warning to the API documentation of gpio_get_level().
Merges https://github.com/espressif/esp-idf/pull/1740
The TRM describes IOMUX registers are IO_MUX_x_REG for x in GPIO0-39.
Until now ESP-IDF describes them as PERIPHS_IO_MUX_(pinname)_U
This commit adds additional IOMUX register names which match the ones used in the TRM.
