It has been observed that, if external SPIRAM is enabled, then under
certain scenarios (e.g. internal memory being too much fragmented),
I2S tx/rx descriptors can land in external SPIRAM and hence resulting
in failure in DMA. Adding explicit capability to allocate in only DMA
capable memory.
Signed-off-by: Mahavir Jain <mahavir@espressif.com>
* Philosophical: "explicit is better than implicit".
* Practical: Allows useful errors if invalid directories given in components as the defaults aren't
always used. Also trims the -I path from a number of components that have no actual include
directory.
* Simplifies knowing which components will be header-only and which won't
Command response tokens can be delayed from the original command by 1
to 8 bytes. In 4a2489b9, handling for delayed tokens was added for
normal (no data) commands, and data read commands. This adds handling
for delayed commands for data write commands.
Previous version of the code only connected CD and WP to the
peripheral, in fact the hardware does not use the values of these
signals automatically. This adds code to read CD and WP values when
command is executed and return errors if card is not present, or
write command is executed when WP signal is active.
- In SPI mode, the card will respond to the initial SDIO reset (done
using CMD52) with “invalid command” error. Handle this correctly.
- sdmmc_card_init had a hack where GO_IDLE_STATE (CMD0) command was
sent twice. Add explanation why this is done, and don’t expect
correct response from the card on first CMD0.
- improve logs printed at debug level by adding CMD index
- Add SDIO support at protocol layer (probing, data transfer, interrupts)
- Add SDIO interrupts support in SDMMC host
- Add test (communicate with ESP32 in SDIO download mode)
Existing code assumed that response timeout is not followed by CMD_DONE,
which was not true, in fact. Host datasheet states that CMD_DONE is sent
after an RTO.
All the commands which do not have a response must have their flags set
accordingly. Therefore the host will not send RTO interrupt if response
is not expected. It is a bug in the code logic if it happens otherwise.
SDMMC host suffers from an issue that it outputs data near the rising
edge of the card clock, which is the edge used by the card to sample
data. If sampling time constraint is not satisfied, card may read data
after the transition.
The phases of output/input data can, in fact, be adjusted. However this
adjustment happens in the clock generation block outside of the host.
So the maximum phase change which can be created this way is equal to
half of the host clock period. So if the host clock is set to the lowest
possible frequency (for the given card frequency), then the phase offset
(and hence the hold time) will be the highest. This change modifies the
logic used to determine clock dividers accordingly.
sdmmc host: set correct dout phase and print correct frequency
SET_BUS_WIDTH is not a data transfer command. Extensive search in the
host datasheet and SD card spec did not reveal the origin of this hack
or 'feature'. Further testing showed that removing this does not lead to
regressions.
Fixes exceptions LoadProhibited, when rmt tries read variable p_rmt on RX END which can be 0.
It happens after esp_reset() (OTA) and the rmt is not probably stopped by it.
In other words the routine rmt_driver_isr_default was called before second rx channel was registered.
scenario:
register tx channel
register rx channel
reboot
register tx channel
-> exception (because rx channel is accessed)
Merges https://github.com/espressif/esp-idf/pull/1671
SDSPI driver optimized polling of the response tokens by requesting
two extra bytes on top of the block size (512) and CRC (2), and
checking whether these bytes contained the data response token or
not. In case the token was there, further polling would not need to
happen, thereby reducing latency between two consecutive blocks
transferred. However this caused compatibility issues when these two
extra bytes were sent after reading the final block. When
STOP_TRANSMISSION command was sent, these extra two bytes were
treated as part of the command, causing an invalid command error.
This fixes the logic by only requesting extra two bytes if the block
being read is not the final block. In addition to that, more strict
error checking is implemented for command response tokens.
On most microcontrollers I have worked with one can retrieve the
current state of output GPIO pins. On ESP32 this is not the case
if the pad is not explictly configured to route this information into
the port by configuring it as input or i/o.
Thus add a warning to the API documentation of gpio_get_level().
Merges https://github.com/espressif/esp-idf/pull/1740
The TRM describes IOMUX registers are IO_MUX_x_REG for x in GPIO0-39.
Until now ESP-IDF describes them as PERIPHS_IO_MUX_(pinname)_U
This commit adds additional IOMUX register names which match the ones used in the TRM.
Reported from github: https://github.com/espressif/esp-idf/issues/1236
All the touch channels are enabled by default in hardware. This would interfere other RTC function on Touch IOs.
Disable touch function in touch_pad_init().
requirement from github(https://github.com/espressif/esp-idf/issues/805): to provide the position in the buffer of the pattern detected.
requirement from AT application: in AT app, when no hardware flow control is enabled, in some situation the rx buffer might be full, and the terminator “+++” might be lost, we can use pattern detect interrupt to avoid missing the terminator. When pattern detect interrupt happens, it will not send a data event at the same time.
1. Add API to get position of detected pattern in rx buffer
2. Modify UART event example
3. Add comments for uart_flush, add alias API uart_flush_input to clear the rx buffer
4. Modify the way rx_buffered_len is calculated
A couple of typos referencing tx_ring_buf when rx_ring_buf, slv_tx_mux
instead of slv_rx_mux.
Also, I2C_ENTER_CRITICAL()/I2C_EXIT_CRITICAL() usage was not consistent.
Only some of the _set_ functions had them. Most of the _get_ function
had them? It is my understanding that they should be wrapped around
writes, not reads? (I think we still need the lock for reading pairs of consistent values)
Also, the ticks_to_wait timeout handling in i2c_master_cmd_begin() would
not handle integer rollover correctly.
Merges https://github.com/espressif/esp-idf/pull/1180
Previously SDSPI host driver would rely on retry count when waiting for
the card to read or write data. This caused different timeout times
depending on CPU frequency and card clock frequency. In practice, card
performance does not depend on these two factors.
This change uses timeout_ms field of sdmmc_command_t introduced
previously for SDMMC host.
Fixes https://esp32.com/viewtopic.php?f=2&t=3440&p=16037 and similar
issues related to SDSPI timeouts.
Reported from github:
https://github.com/espressif/esp-idf/issues/1312https://github.com/espressif/esp-idf/issues/1193
Issues:
1. We used to use event group in the driver, which would cause:
a. longer operation time since the event group are based on FreeRTOS timer.
b. Operation fails if the timer queue is not long enough.
2. There might be some issue with event group, we will still try to provide a small test code in other branch.
modification:
1. use queue instead of event-bit for internal commands
2. use queue overwrite for cmd_done event
1. All the registers of touch sensor 8 and 9 are mismatched except the ‘dac’ field in touch register of RTC IO
2. To swap the index for sensor 8 and 9 in APIs.
Reported from github:
https://github.com/espressif/esp-idf/issues/1219https://github.com/espressif/esp-idf/issues/1202
After providing a simple code to digital team, they confirmed that this is a hardware bug.
Root cause:
The fifo reset signal is incorrectly connected
If we want to reset tx fifo of UART2, we have to set txfifo_rst bit of both UART1 and UART2
If we want to reset rx fifo of UART2, we have to set rxfifo_rst bit of both UART1 and UART2
Workaround:
we don't use fifo rst bit in driver.
Documentation:
Digital team would update TRM and give more explanation about this issue.
1. move settings of WIFI_CLK_EN_REG for bluetooth into controller init/deinit APIs
2. modify the bit mask used in phy_rf init/deinit to use WIFI-BT shared bits
append adc support and api
- esp_err_t adc2_config_width(adc_bits_width_t width_bit);
- esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten);
- int adc2_get_voltage(adc2_channel_t channel);
Reported from:
https://github.com/espressif/esp-idf/issues/703https://github.com/espressif/esp-idf/issues/917
In uart driver we didn't change the default value of tx idle num, so there would be a delay after tx FIFO is empty.
1. Add API to set tx idle interval before next data transmission. (The UART hardware can add an interval after tx FIFO is empty).
2. Set default tx idle interval to zero.
3. Add hardware disable in uart driver delete function.
Reported from different sources from github or bbs:
https://github.com/espressif/esp-idf/issues/680https://github.com/espressif/esp-idf/issues/922
We tested reading several sensor or other I2C slave devices, if the power and SDA/SCL wires are in proper condition, everything works find with reading the slave.
If we remove the power supply for the slave during I2C is reading, or directly connect SDA or SCL to ground, this would cause the I2C FSM get stuck in wrong state, all we can do is the reset the I2C hardware in this case.
After this commit, no matter whether the power supply of I2C slave is removed or SDA / SCL are shorted to ground, the driver can recover from wrong state.
We are not sure whether this the save issue with the reported one yet, but to make the driver more robust.
Further information:
1. For I2C master mode, we have tested different situations, e.g., to short the SDA/SCL directly to GND/VCC, to short the SDA to SCL, to un-plug the slave device, to power off the slave device. Under all of those situations, this version of driver can recover and keep working.
2. Some slave device will die by accident and keep the SDA in low level, in this case, master should send several clock to make the slave release the bus.
3. Slave mode of ESP32 might also get in wrong state that held the SDA low, in this case, master device could send a stop signal to make esp32 slave release the bus.
Modifications:
1. Disable I2C_MASTER_TRAN_COMP interrupt to void extra interrupt.
2. Disable un-used timeout interrupt for slave.
3. Add bus reset if error detected for master mode.
4. Add bus clear if SDA level is low when error detected.
5. Modify the argument type of i2c_set_pin.
6. add API to set timeout value
7. add parameter check for timing APIs
