Commit graph

281 commits

Author SHA1 Message Date
Michael (XIAO Xufeng)
9d98111652 Merge branch 'bugfix/spi_bus_lock_missing_semphrstatic' into 'master'
spi: fix config break and reduce overhead of the bus lock on SPI1

Closes IDFGH-3017

See merge request espressif/esp-idf!8221
2020-04-27 12:57:19 +08:00
Angus Gratton
bb0a95b17c spi_flash s2: Fix encrypted writes when legacy implementation disabled
ROM function didn't use correct Addr bitlen if legacy was disabled on ESP32-S2
2020-04-24 12:43:47 -03:00
Angus Gratton
dbdce93d23 spi_flash: Use per-chip flash_ops files for legacy API
Looks like when ESP32-S2 Beta support was merged, the separate files
were dropped by accident.
2020-04-24 12:43:47 -03:00
Michael (XIAO Xufeng)
7ec4d64b80 spi: Update documents about the bus lock and how to use SPI Master on SPI1 bus 2020-04-23 12:27:25 +08:00
michael
fdf983e0c4 spi: fix config break and reduce overhead of the bus lock on SPI1
The SPI bus lock on SPI1 introduces two side effects:

1. The device lock for the main flash requires the
`CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION` to be selected, however this
option is disabled by default in earlier IDF versions. Some developers
may find their project cannot be built by their old sdkconfig files.

2. Usually we don't need the lock on the SPI1 bus, due to it's
restrictions. However the overhead still exists in this case, the IRAM
cost for static version of semaphore functions, and the time cost when
getting and releasing the lock.

This commit:

1. Add a CONFIG_SPI_FLASH_BYPASS_MAIN_LOCK option, which will forbid the
space cost, as well as the initialization of the main bus lock.

2. When the option is not selected, the bus lock is used, the
`CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION` will be selected explicitly.

3. Revert default value of `CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION`
to `n`.

introduced in 49a48644e4.

Closes https://github.com/espressif/esp-idf/issues/5046
2020-04-22 16:06:13 +08:00
Michael (XIAO Xufeng)
9d9d22c920 esp_flash: deprecate the cs_id member, which is no longer used.
We used to manually specify the CS id. However after the SPI bus lock is
introduced, the lock is responsible to assign the CS lines and provide
the CS id. The esp_flash driver now depends on the ID assigned by the
SPI bus lock, the configuration field is deprecated.
2020-04-17 18:15:33 +08:00
Michael (XIAO Xufeng)
5404e3d434 esp_flash: fix cache exception when CS pin is through IOMUX 2020-04-17 18:15:33 +08:00
Michael (XIAO Xufeng)
11501dbaa9 esp_flash: fix the cleanup when add device fails 2020-04-17 18:15:32 +08:00
Michael (XIAO Xufeng)
dc26065a72 esp_flash: fix the regression of non-quad mode by default chip driver
The issue is introduced in 571864e8ae. The
esp_flash API tries to clear the QE bit when the flash is not working in
quad modes.

However this introduces a regression, compared to earlier versions and
the legacy API. When the chip is not detected, the generic chip driver
is used, which cannot 100% handle the QE bit properly for all flash
vendors. There may be some flash chips (e.g. MXIC) that can be used in
dual modes by legacy API, but output wrong data when the esp_flash API
clears the QE bit in a wrong way.

This commit reverts the QE force clearing behavior, so that it's safer
for the generic chip driver to work under dual modes.
2020-04-17 18:15:31 +08:00
Michael (XIAO Xufeng)
61ce037fc1 Merge branch 'feat/esp_flash_support_mxic' into 'master'
esp_flash: support MXIC flash chips

See merge request espressif/esp-idf!8037
2020-04-03 16:04:49 +08:00
Angus Gratton
d76bf19ffd docs: Explain custom partition types/subtypes in more detail
Including how to use with C++ (closes https://github.com/espressif/esp-idf/pull/1832)
2020-04-02 10:00:17 +11:00
Michael (XIAO Xufeng)
3b429766bc esp_flash: support MXIC flash chips
The default chip driver (chip_generic) use command 01H + 2 bytes to
clear the QE bit. However this will accidently change the configuration
register value of the MXIC chip.

MXIC chip driver is added to fix that.
2020-04-01 20:54:23 +08:00
Michael (XIAO Xufeng)
49a48644e4 spi: allow using esp_flash and spi_master driver on the same bus 2020-03-26 22:08:26 +08:00
Renz Bagaporo
3d0967a58a test: declare requirements and include dirs private 2020-03-23 10:58:50 +08:00
michael
3b1fa7b8f0 spi_flash: add caps for dummy output control 2020-03-11 16:13:39 +00:00
Jiang Jiang Jian
b7a14c47e6 Merge branch 'bugfix/customer_baidu_psram_stack_backtrace' into 'master'
added psram stack check in backtrace

See merge request espressif/esp-idf!7834
2020-03-06 11:35:54 +08:00
Li Shuai
c796e14964 added psram stack check in backtrace 2020-03-03 11:52:29 +08:00
Angus Gratton
95f7b1985b spi_flash: Remove 16KB free internal heap limit for esp_flash_read() into PSRAM
Allocation of the temporary internal buffer will now repeat until a small enough buffer can be
allocated, and only fail if less than a 256 byte block of internal RAM is free.

Adds unit test for the same, and generic test utility for creating memory pressure.
2020-03-03 00:17:27 +00:00
Angus Gratton
fb340940d3 spi_flash: Fix over-allocation and OOM crash when reading from SPI flash to PSRAM buffers
Previously would try allocate buffer of minimum size 16KB not maximum size 16KB, causing
out of memory errors for any large reads, or if less than 16KB contiguous free heap.

Also, if using legacy API and internal allocation failed then implementation would abort()
instead of returning the error to the caller.

Added test for using large buffers in PSRAM.

Closes https://github.com/espressif/esp-idf/issues/4769

Also reported on forum: https://esp32.com/viewtopic.php?f=13&t=14304&p=55972
2020-03-03 00:17:27 +00:00
michael
7a3f21636f spi_flash: fix the reading issue using the ROM functions in the ROM 2020-02-26 11:12:09 +08:00
michael
f8fae4c80c spi_flash: resume unit tests for ESP32-S2 2020-02-26 11:12:08 +08:00
michael
2529eda907 ci: disable failed cases for s2 temporarily 2020-02-15 18:28:25 +08:00
Renz Christian Bagaporo
1f2e2fe8af soc: separate abstraction, description and implementation 2020-02-11 14:30:42 +05:00
Ivan Grokhotkov
4bfd0b961b Merge branch 'fix/spi_on_esp32s2' into 'master'
spi: support esp32s2

See merge request espressif/esp-idf!7432
2020-02-09 19:45:16 +08:00
Wangjialin
aaf119e930 flash(esp32s2): fix setting address field in spi user mode. 2020-02-07 16:10:51 +01:00
Michael (XIAO Xufeng)
7026087dc0 spi: support esp32s2 2020-01-26 17:24:12 +08:00
morris
e30cd361a8 global: rename esp32s2beta to esp32s2 2020-01-22 12:14:38 +08:00
morris
2422c52851 global: hello world on real esp32-s2 2020-01-16 17:43:59 +08:00
Wangjialin
d4e5980823 flash: fix 80Mhz for new spi flash driver on esp32s2 2020-01-16 17:43:59 +08:00
duyi
30a525aeb1 update cache config 2020-01-16 17:41:31 +08:00
morris
1c2cc5430e global: bring up esp32s2(not beta) 2020-01-16 17:41:31 +08:00
Renz Christian Bagaporo
fb1dec37d8 spi_flash: reenable mmap tests on esp32s2beta 2020-01-10 16:17:01 +11:00
michael
4220752aed ut: Move tests back from "esp32" subfolder
DISABLED_FOR_TARGETS macros are used

Partly revert "ci: disable unavailable tests for esp32s2beta"

This partly reverts commit 76a3a5fb48.

Partly revert "ci: disable UTs for esp32s2beta without runners"

This partly reverts commit eb158e9a22.

Partly revert "fix unit test and examples for s2beta"

This partly reverts commit 9baa7826be.

Partly revert "efuse: Add support for esp32s2beta"

This partly reverts commit db84ba868c.
2020-01-06 17:13:53 +08:00
Angus Gratton
5139934767 bootloader_common: Fix esp_partition_get_sha256(), add unit tests
Regression in 438d513a95

Reported here: https://esp32.com/viewtopic.php?f=13&t=13250&p=52460
2019-12-30 13:47:47 +11:00
Michael (XIAO Xufeng)
2ffe0aca12 esp_flash: increase the timeout for block erase 2019-12-24 16:50:09 +08:00
Renz Christian Bagaporo
e6ad330018 ble_mesh_wifi_coexist example: Disable Wi-Fi RX IRAM optimisation
Otherwise IRAM usage is too high in this example.
2019-11-28 09:20:00 +08:00
chenjianqiang
9f9da9ec96 feat(timer): refator timer group driver
1. add hal and low-level layer for timer group
2. add callback functions to handle interrupt
3. add timer deinit function
4. add timer spinlock take function
2019-11-21 14:14:19 +08:00
Ivan Grokhotkov
a74988ae3b Merge branch 'bugfix/cpp_extern' into 'master'
Add extern C header guards to some files

Closes IDFGH-2025 and IDFGH-2093

See merge request espressif/esp-idf!6611
2019-11-19 19:01:29 +08:00
wanglei
5e55ffc95a fix dummy issue in spi mem and make some spiflash api called from idf 2019-11-15 15:59:07 +00:00
wanglei
8bea8dacbc esp32s2beta: fix some macro and add flash wrap size condition 2019-11-15 15:59:07 +00:00
Gabriel Durante
5f0d257240 Added Cpp compatibility for components/spi_flash/include/esp_flash_spi_init.h
Merges https://github.com/espressif/esp-idf/pull/4260
2019-11-05 14:52:57 +01:00
Michael (XIAO Xufeng)
2660cb82ae spi_flash: support to verify written encrypted data
Also add unit test for encrypted_read
2019-10-30 05:49:50 +00:00
Angus Gratton
36cd75d7ed spi_flash tests: Fix exclusion of new API tests in legacy mode 2019-10-28 18:58:05 +11:00
Angus Gratton
894a3b4771 spi_flash: Remove duplicate spi_flash_rom_patch in CMakeLists.txt 2019-10-28 18:58:05 +11:00
Angus Gratton
8675a818f9 Merge branch 'master' into feature/esp32s2beta_merge 2019-10-22 13:51:49 +11:00
Ivan Grokhotkov
c7d8ef52ca Merge branch 'fix/esp_flash_no_qe' into 'master'
esp_flash: fix the QE write issue in high freq, and support UT for external chips

Closes IDF-888

See merge request espressif/esp-idf!5736
2019-10-20 13:59:30 +08:00
Ajita Chavan
56f73d7720 flash_ops: fix spi_flash_read with source buffer not from internal memory and size < 16
Closes https://github.com/espressif/esp-idf/issues/4010
2019-10-19 14:56:43 +08:00
Angus Gratton
496ede9bcd Merge branch 'master' into feature/esp32s2beta_merge 2019-10-15 14:59:27 +11:00
Michael (XIAO Xufeng)
eb104aa16f esp_flash: fix the quad issue for some GD flash chips
The GD flash with product ID 40H, is already used in Wrover-nosufix modules.
2019-10-14 17:25:59 +08:00
Michael (XIAO Xufeng)
1e1d50376b esp_flash: add unit test for external flash and QE toggling
Tests for external flash chips used to controlled by macros, one bin for
one chip. And tests are done manually. This commit refactored the test
so that all 3 chips can all run in single test.
2019-10-14 17:25:58 +08:00