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Merge branch 'fix/spi_on_esp32s2' into 'master'

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spi: support esp32s2

See merge request espressif/esp-idf!7432
This commit is contained in:
Ivan Grokhotkov 2020-02-09 19:45:16 +08:00
parent e5cb972c3a 7026087dc0
commit 4bfd0b961b
16 changed files with 670 additions and 497 deletions
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20
components/driver/periph_ctrl.c
View file

@ -112,8 +112,6 @@ static uint32_t get_clk_en_mask(periph_module_t periph)
return DPORT_SPI2_CLK_EN;
case PERIPH_HSPI_MODULE:
return DPORT_SPI3_CLK_EN;
case PERIPH_VSPI_MODULE:
return DPORT_SPI4_CLK_EN;
case PERIPH_SPI2_DMA_MODULE:
return DPORT_SPI2_DMA_CLK_EN;
case PERIPH_SPI3_DMA_MODULE:
@ -216,8 +214,6 @@ static uint32_t get_rst_en_mask(periph_module_t periph, bool enable)
return DPORT_SPI2_RST;
case PERIPH_HSPI_MODULE:
return DPORT_SPI3_RST;
case PERIPH_VSPI_MODULE:
return DPORT_SPI4_RST;
case PERIPH_SPI2_DMA_MODULE:
return DPORT_SPI2_DMA_RST;
case PERIPH_SPI3_DMA_MODULE:
@ -293,13 +289,9 @@ static uint32_t get_clk_en_reg(periph_module_t periph)
#if CONFIG_IDF_TARGET_ESP32
if (periph == PERIPH_AES_MODULE || periph == PERIPH_SHA_MODULE || periph == PERIPH_RSA_MODULE) {
return DPORT_PERI_CLK_EN_REG;
}
#elif CONFIG_IDF_TARGET_ESP32S2
if(periph == PERIPH_SPI_SHARED_DMA_MODULE) {
return DPORT_PERIP_CLK_EN1_REG;
}
} else
#endif
else {
{
return is_wifi_clk_peripheral(periph) ? DPORT_WIFI_CLK_EN_REG : DPORT_PERIP_CLK_EN_REG;
}
}
@ -309,13 +301,9 @@ static uint32_t get_rst_en_reg(periph_module_t periph)
#if CONFIG_IDF_TARGET_ESP32
if (periph == PERIPH_AES_MODULE || periph == PERIPH_SHA_MODULE || periph == PERIPH_RSA_MODULE) {
return DPORT_PERI_RST_EN_REG;
}
#elif CONFIG_IDF_TARGET_ESP32S2
if(periph == PERIPH_SPI_SHARED_DMA_MODULE){
return DPORT_PERIP_CLK_EN1_REG;
}
} else
#endif
else {
{
return is_wifi_clk_peripheral(periph) ? DPORT_CORE_RST_EN_REG : DPORT_PERIP_RST_EN_REG;
}
}

3
components/driver/sdspi_host.c
View file

@ -109,7 +109,8 @@ static bool card_missing(int slot)
/// Check if slot number is within bounds
static bool is_valid_slot(int slot)
{
return slot == VSPI_HOST || slot == HSPI_HOST;
//SPI1 is not supported yet
return slot == SPI2_HOST || slot == SPI3_HOST;
}
static spi_device_handle_t spi_handle(int slot)

6
components/driver/spi_common.c
View file

@ -110,8 +110,6 @@ static inline uint32_t get_dma_periph(int dma_chan)
return PERIPH_SPI2_DMA_MODULE;
} else if (dma_chan==2) {
return PERIPH_SPI3_DMA_MODULE;
} else if (dma_chan==3) {
return PERIPH_SPI_SHARED_DMA_MODULE;
} else {
abort();
return -1;
@ -140,8 +138,6 @@ bool spicommon_dma_chan_claim (int dma_chan)
periph_module_enable(PERIPH_SPI2_DMA_MODULE);
} else if (dma_chan==2) {
periph_module_enable(PERIPH_SPI3_DMA_MODULE);
} else if (dma_chan==3) {
periph_module_enable(PERIPH_SPI_SHARED_DMA_MODULE);
}
#endif
portEXIT_CRITICAL(&spi_dma_spinlock);
@ -172,8 +168,6 @@ bool spicommon_dma_chan_free(int dma_chan)
periph_module_disable(PERIPH_SPI2_DMA_MODULE);
} else if (dma_chan==2) {
periph_module_disable(PERIPH_SPI3_DMA_MODULE);
} else if (dma_chan==3) {
periph_module_disable(PERIPH_SPI_SHARED_DMA_MODULE);
}
#endif
portEXIT_CRITICAL(&spi_dma_spinlock);

11
components/driver/spi_master.c
View file

@ -209,6 +209,11 @@ static const char *SPI_TAG = "spi_master";
static void spi_intr(void *arg);
static inline bool is_valid_host(spi_host_device_t host)
{
return host >= SPI1_HOST && host <= SPI3_HOST;
}
esp_err_t spi_bus_initialize(spi_host_device_t host, const spi_bus_config_t *bus_config, int dma_chan)
{
bool spi_chan_claimed, dma_chan_claimed;
@ -217,7 +222,7 @@ esp_err_t spi_bus_initialize(spi_host_device_t host, const spi_bus_config_t *bus
/* ToDo: remove this when we have flash operations cooperating with this */
SPI_CHECK(host!=SPI_HOST, "SPI1 is not supported", ESP_ERR_NOT_SUPPORTED);
SPI_CHECK(host>=SPI_HOST && host<=VSPI_HOST, "invalid host", ESP_ERR_INVALID_ARG);
SPI_CHECK(is_valid_host(host), "invalid host", ESP_ERR_INVALID_ARG);
#ifdef CONFIG_IDF_TARGET_ESP32
SPI_CHECK( dma_chan >= 0 && dma_chan <= 2, "invalid dma channel", ESP_ERR_INVALID_ARG );
#elif CONFIG_IDF_TARGET_ESP32S2
@ -321,7 +326,7 @@ cleanup:
esp_err_t spi_bus_free(spi_host_device_t host)
{
int x;
SPI_CHECK(host>=SPI_HOST && host<=VSPI_HOST, "invalid host", ESP_ERR_INVALID_ARG);
SPI_CHECK(is_valid_host(host), "invalid host", ESP_ERR_INVALID_ARG);
SPI_CHECK(spihost[host]!=NULL, "host not in use", ESP_ERR_INVALID_STATE);
for (x=0; x<NO_CS; x++) {
SPI_CHECK(atomic_load(&spihost[host]->device[x])==NULL, "not all CSses freed", ESP_ERR_INVALID_STATE);
@ -370,7 +375,7 @@ esp_err_t spi_bus_add_device(spi_host_device_t host, const spi_device_interface_
int freecs;
int duty_cycle;
SPI_CHECK(host>=SPI_HOST && host<=VSPI_HOST, "invalid host", ESP_ERR_INVALID_ARG);
SPI_CHECK(is_valid_host(host), "invalid host", ESP_ERR_INVALID_ARG);
SPI_CHECK(spihost[host]!=NULL, "host not initialized", ESP_ERR_INVALID_STATE);
SPI_CHECK(dev_config->spics_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(dev_config->spics_io_num), "spics pin invalid", ESP_ERR_INVALID_ARG);
SPI_CHECK(dev_config->clock_speed_hz > 0, "invalid sclk speed", ESP_ERR_INVALID_ARG);

2
components/driver/spi_slave.c
View file

@ -41,7 +41,7 @@ static const char *SPI_TAG = "spi_slave";
return (ret_val); \
}
#define VALID_HOST(x) (x>SPI_HOST && x<=VSPI_HOST)
#define VALID_HOST(x) (x > SPI1_HOST && x <= SPI3_HOST)
#ifdef CONFIG_SPI_SLAVE_ISR_IN_IRAM
#define SPI_SLAVE_ISR_ATTR IRAM_ATTR

8
components/driver/test/test_spi_master.c
View file

@ -752,7 +752,13 @@ void test_cmd_addr(spi_slave_task_context_t *slave_context, bool lsb_first)
vTaskDelay(50);
//prepare master tx data
int cmd_bits = (i+1)*2;
int addr_bits = 56-8*i;
int addr_bits =
#ifdef CONFIG_IDF_TARGET_ESP32
56-8*i;
#elif CONFIG_IDF_TARGET_ESP32S2
//ESP32S2 only supportes up to 32 bits address
28-4*i;
#endif
int round_up = (cmd_bits+addr_bits+7)/8*8;
addr_bits = round_up - cmd_bits;

118
components/soc/esp32s2/include/hal/spi_ll.h
View file

@ -97,22 +97,19 @@ static inline void spi_ll_master_init(spi_dev_t *hw)
*/
static inline void spi_ll_slave_init(spi_dev_t *hw)
{
//it's stupid, but if something goes wrong, try to uncomment it
//hw->slave.slave_mode = 1;
//Configure slave
hw->clock.val = 0;
hw->user.val = 0;
hw->ctrl.val = 0;
hw->user.doutdin = 1; //we only support full duplex
hw->user.sio = 0;
hw->user.tx_start_bit = 7;
hw->slave.slave_mode = 1;
hw->dma_conf.val |= SPI_LL_RST_MASK;
hw->dma_out_link.start = 0;
hw->dma_in_link.start = 0;
hw->dma_conf.val &= ~SPI_LL_RST_MASK;
hw->slave.sync_reset = 1;
hw->slave.sync_reset = 0;
hw->slave.soft_reset = 1;
hw->slave.soft_reset = 0;
//use all 64 bytes of the buffer
hw->user.usr_miso_highpart = 0;
hw->user.usr_mosi_highpart = 0;
@ -136,7 +133,7 @@ static inline void spi_ll_reset_dma(spi_dev_t *hw)
hw->dma_out_link.start = 0;
hw->dma_in_link.start = 0;
hw->dma_conf.val &= ~SPI_LL_RST_MASK;
hw->dma_conf.out_data_burst_en = 1;
hw->dma_conf.out_data_burst_en = 0;
hw->dma_conf.indscr_burst_en = 1;
hw->dma_conf.outdscr_burst_en = 1;
hw->dma_in_link.dma_rx_ena = 0;
@ -151,8 +148,6 @@ static inline void spi_ll_reset_dma(spi_dev_t *hw)
*/
static inline void spi_ll_rxdma_start(spi_dev_t *hw, lldesc_t *addr)
{
//if something breaks, uncomment this line
//hw->dma_in_link.restart = 1;
hw->dma_in_link.addr = (int) addr & 0xFFFFF;
hw->dma_in_link.start = 1;
}
@ -165,8 +160,6 @@ static inline void spi_ll_rxdma_start(spi_dev_t *hw, lldesc_t *addr)
*/
static inline void spi_ll_txdma_start(spi_dev_t *hw, lldesc_t *addr)
{
//if something breaks, uncomment this line
hw->dma_out_link.restart = 1;
hw->dma_out_link.addr = (int) addr & 0xFFFFF;
hw->dma_out_link.start = 1;
}
@ -249,7 +242,7 @@ static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw)
*/
static inline void spi_ll_disable_int(spi_dev_t *hw)
{
hw->slave.trans_inten = 0;
hw->slave.int_trans_done_en = 0;
}
/**
@ -280,7 +273,7 @@ static inline void spi_ll_set_int_stat(spi_dev_t *hw)
*/
static inline void spi_ll_enable_int(spi_dev_t *hw)
{
hw->slave.trans_inten = 1;
hw->slave.int_trans_done_en = 1;
}
/**
@ -295,17 +288,15 @@ static inline void spi_ll_slave_set_int_type(spi_dev_t *hw, spi_ll_slave_intr_ty
case SPI_LL_INT_TYPE_SEG:
hw->dma_int_ena.in_suc_eof = 1;
hw->dma_int_ena.out_total_eof = 1;
hw->slave.trans_inten = 0;
hw->slave.int_trans_done_en = 0;
break;
default:
hw->dma_int_ena.in_suc_eof = 0;
hw->dma_int_ena.out_total_eof = 0;
hw->slave.trans_inten = 1;
hw->slave.int_trans_done_en = 1;
}
}
/*------------------------------------------------------------------------------
* Configs: mode
*----------------------------------------------------------------------------*/
@ -383,28 +374,24 @@ static inline void spi_ll_slave_set_mode(spi_dev_t *hw, const int mode, bool dma
hw->misc.ck_idle_edge = 0;
hw->user.rsck_i_edge = 0;
hw->user.tsck_i_edge = 0;
hw->ctrl1.rsck_data_out = 0;
hw->ctrl1.clk_mode_13 = 0;
} else if (mode == 1) {
hw->misc.ck_idle_edge = 0;
hw->user.rsck_i_edge = 1;
hw->user.tsck_i_edge = 1;
hw->ctrl1.rsck_data_out = 0;
hw->ctrl1.clk_mode_13 = 1;
} else if (mode == 2) {
hw->misc.ck_idle_edge = 1;
hw->user.rsck_i_edge = 1;
hw->user.tsck_i_edge = 1;
hw->ctrl1.rsck_data_out = 0;
hw->ctrl1.clk_mode_13 = 0;
} else if (mode == 3) {
hw->misc.ck_idle_edge = 1;
hw->user.rsck_i_edge = 0;
hw->user.tsck_i_edge = 0;
hw->ctrl1.rsck_data_out = 0;
hw->ctrl1.clk_mode_13 = 1;
}
//hw->ctrl1.rsck_data_out = 1;
hw->ctrl1.rsck_data_out = 0;
}
/**
@ -439,31 +426,34 @@ static inline void spi_ll_set_sio_mode(spi_dev_t *hw, int sio_mode)
*/
static inline void spi_ll_master_set_io_mode(spi_dev_t *hw, spi_ll_io_mode_t io_mode)
{
hw->ctrl.val &= ~(SPI_FREAD_DUAL | SPI_FREAD_QUAD | SPI_FREAD_DIO | SPI_FREAD_QIO);
hw->user.val &= ~(SPI_FWRITE_DUAL | SPI_FWRITE_QUAD | SPI_FWRITE_DIO | SPI_FWRITE_QIO);
switch (io_mode) {
case SPI_LL_IO_MODE_DIO:
// hw->ctrl.fread_dio = 1;
// hw->user.fwrite_dio = 1;
break;
case SPI_LL_IO_MODE_DUAL:
hw->ctrl.fread_dual = 1;
hw->user.fwrite_dual = 1;
break;
case SPI_LL_IO_MODE_QIO:
// hw->ctrl.fread_qio = 1;
// hw->user.fwrite_qio = 1;
break;
case SPI_LL_IO_MODE_QUAD:
hw->ctrl.fread_quad = 1;
hw->user.fwrite_quad = 1;
break;
default:
break;
};
// if (io_mode != SPI_LL_IO_MODE_NORMAL) {
// hw->ctrl.fastrd_mode = 1;
// }
if (io_mode == SPI_LL_IO_MODE_DIO || io_mode == SPI_LL_IO_MODE_DUAL) {
hw->ctrl.fcmd_dual= (io_mode == SPI_LL_IO_MODE_DIO) ? 1 : 0;
hw->ctrl.faddr_dual= (io_mode == SPI_LL_IO_MODE_DIO) ? 1 : 0;
hw->ctrl.fread_dual=1;
hw->user.fwrite_dual=1;
hw->ctrl.fcmd_quad = 0;
hw->ctrl.faddr_quad = 0;
hw->ctrl.fread_quad = 0;
hw->user.fwrite_quad = 0;
} else if (io_mode == SPI_LL_IO_MODE_QIO || io_mode == SPI_LL_IO_MODE_QUAD) {
hw->ctrl.fcmd_quad = (io_mode == SPI_LL_IO_MODE_QIO) ? 1 : 0;
hw->ctrl.faddr_quad = (io_mode == SPI_LL_IO_MODE_QIO) ? 1 : 0;
hw->ctrl.fread_quad=1;
hw->user.fwrite_quad=1;
hw->ctrl.fcmd_dual = 0;
hw->ctrl.faddr_dual = 0;
hw->ctrl.fread_dual = 0;
hw->user.fwrite_dual = 0;
} else {
hw->ctrl.fcmd_dual = 0;
hw->ctrl.faddr_dual = 0;
hw->ctrl.fread_dual = 0;
hw->user.fwrite_dual = 0;
hw->ctrl.fcmd_quad = 0;
hw->ctrl.faddr_quad = 0;
hw->ctrl.fread_quad = 0;
hw->user.fwrite_quad = 0;
}
}
/**
@ -722,7 +712,7 @@ static inline void spi_ll_set_mosi_bitlen(spi_dev_t *hw, size_t bitlen)
*/
static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen)
{
hw->slv_wrbuf_dlen.bit_len = bitlen - 1;
spi_ll_set_miso_bitlen(hw, bitlen);
}
/**
@ -733,7 +723,7 @@ static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen)
*/
static inline void spi_ll_slave_set_tx_bitlen(spi_dev_t *hw, size_t bitlen)
{
hw->slv_rdbuf_dlen.bit_len = bitlen - 1;
spi_ll_set_miso_bitlen(hw, bitlen);
}
/**
@ -785,27 +775,13 @@ static inline void spi_ll_set_address(spi_dev_t *hw, uint64_t addr, int addrlen,
* addr[0] -> addr[7]
* So swap the byte order to let the LSB sent first.
*/
addr = HAL_SWAP64(addr);
if (addrlen > 32) {
//The slv_wr_status register bits are sent first, then
//bits in addr register is sent.
hw->slv_wr_status = addr >> 32;
hw->addr = addr;
} else {
//otherwise only addr register is sent
hw->addr = addr >> 32;
}
addr = HAL_SWAP32(addr);
//otherwise only addr register is sent
hw->addr = addr;
} else {
// shift the address to MSB of addr (and maybe slv_wr_status) register.
if (addrlen > 32) {
// output address will be sent from MSB to LSB of slv_wr_status register, then comes the MSB to
// LSB of addr register.
hw->addr = addr << (64 - addrlen);
hw->slv_wr_status = addr >> (addrlen - 32);
} else {
// output address will be sent from MSB to LSB of addr register
hw->addr = addr << (32 - addrlen);
}
// shift the address to MSB of addr register.
// output address will be sent from MSB to LSB of addr register
hw->addr = addr << (32 - addrlen);
}
}
@ -863,8 +839,8 @@ static inline void spi_ll_enable_mosi(spi_dev_t *hw, int enable)
*/
static inline void spi_ll_slave_reset(spi_dev_t *hw)
{
hw->slave.sync_reset = 1;
hw->slave.sync_reset = 0;
hw->slave.soft_reset = 1;
hw->slave.soft_reset = 0;
}
/**
@ -876,7 +852,7 @@ static inline void spi_ll_slave_reset(spi_dev_t *hw)
*/
static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw)
{
return hw->slv_rd_byte.slv_rdata_bit * 8;
return hw->slv_rd_byte.data_bytelen * 8;
}

2
components/soc/esp32s2/include/soc/periph_defs.h
View file

@ -45,10 +45,8 @@ typedef enum {
PERIPH_SPI_MODULE, //SPI1
PERIPH_FSPI_MODULE, //SPI2
PERIPH_HSPI_MODULE, //SPI3
PERIPH_VSPI_MODULE, //SPI4
PERIPH_SPI2_DMA_MODULE,
PERIPH_SPI3_DMA_MODULE,
PERIPH_SPI_SHARED_DMA_MODULE, //this DMA is shared by SPI1 and SPI4
PERIPH_SDMMC_MODULE,
PERIPH_SDIO_SLAVE_MODULE,
PERIPH_CAN_MODULE,

3
components/soc/esp32s2/include/soc/spi_caps.h
View file

@ -26,7 +26,7 @@
#define SPI_IOMUX_PIN_NUM_WP 28
//TODO: add the next slot
#define FSPI_FUNC_NUM 2
#define FSPI_FUNC_NUM 4
#define FSPI_IOMUX_PIN_NUM_HD 9
#define FSPI_IOMUX_PIN_NUM_CS 10
#define FSPI_IOMUX_PIN_NUM_MOSI 11
@ -43,6 +43,7 @@
#define SOC_SPI_SUPPORT_DDRCLK 1
#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
#define SOC_SPI_SUPPORT_CD_SIG 1
#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
// Peripheral supports DIO, DOUT, QIO, or QOUT
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_dev) (!((void*)spi_dev == (void*)&GPSPI3))

40
components/soc/esp32s2/include/soc/spi_pins.h
View file

@ -1,40 +0,0 @@
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SPI_PINS_H_
#define _SOC_SPI_PINS_H_
#define SPI_PERIPH_NUM 3
#define SPI_FUNC_NUM 2
#define SPI_IOMUX_PIN_NUM_HD 27
#define SPI_IOMUX_PIN_NUM_CS 29
#define SPI_IOMUX_PIN_NUM_MOSI 32
#define SPI_IOMUX_PIN_NUM_CLK 30
#define SPI_IOMUX_PIN_NUM_MISO 31
#define SPI_IOMUX_PIN_NUM_WP 28
//TODO: add the next slot
#define FSPI_FUNC_NUM 0
#define FSPI_IOMUX_PIN_NUM_HD 9
#define FSPI_IOMUX_PIN_NUM_CS 10
#define FSPI_IOMUX_PIN_NUM_MOSI 11
#define FSPI_IOMUX_PIN_NUM_CLK 12
#define FSPI_IOMUX_PIN_NUM_MISO 13
#define FSPI_IOMUX_PIN_NUM_WP 14
//TODO: add the next slot
//HSPI and VSPI have no iomux pins
#endif

472
components/soc/esp32s2/include/soc/spi_reg.h
View file

@ -19,7 +19,7 @@
extern "C" {
#endif
#include "soc.h"
#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (i - 2) * 0x1000)
#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (((i)>3) ? (((i-2)* 0x1000) + 0x10000) : ((i - 2)* 0x1000 )))
#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x000)
/* SPI_USR : R/W ;bitpos:[24] ;default: 1'b0 ; */
@ -29,7 +29,7 @@ extern "C" {
#define SPI_USR_M (BIT(24))
#define SPI_USR_V 0x1
#define SPI_USR_S 24
/* SPI_CONF_BITLEN : R/W ;bitpos:[22:0] ;default: 23'd104 ; */
/* SPI_CONF_BITLEN : R/W ;bitpos:[22:0] ;default: 23'd0 ; */
/*description: Define the spi_clk cycles of SPI_CONF state. Can be configured in CONF state.*/
#define SPI_CONF_BITLEN 0x007FFFFF
#define SPI_CONF_BITLEN_M ((SPI_CONF_BITLEN_V)<<(SPI_CONF_BITLEN_S))
@ -216,8 +216,8 @@ extern "C" {
#define SPI_CS_HOLD_TIME_M ((SPI_CS_HOLD_TIME_V)<<(SPI_CS_HOLD_TIME_S))
#define SPI_CS_HOLD_TIME_V 0x1FFF
#define SPI_CS_HOLD_TIME_S 13
/* SPI_CS_SETUP_TIME : R/W ;bitpos:[12:0] ;default: 13'h1 ; */
/*description: (cycles-1) of prepare phase by spi clock this bits are combined
/* SPI_CS_SETUP_TIME : R/W ;bitpos:[12:0] ;default: 13'h0 ; */
/*description: (cycles+1) of prepare phase by spi clock this bits are combined
with spi_cs_setup bit. Can be configured in CONF state.*/
#define SPI_CS_SETUP_TIME 0x00001FFF
#define SPI_CS_SETUP_TIME_M ((SPI_CS_SETUP_TIME_V)<<(SPI_CS_SETUP_TIME_S))
@ -430,14 +430,14 @@ extern "C" {
#define SPI_RSCK_I_EDGE_M (BIT(8))
#define SPI_RSCK_I_EDGE_V 0x1
#define SPI_RSCK_I_EDGE_S 8
/* SPI_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
/* SPI_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b1 ; */
/*description: spi cs is enable when spi is in prepare phase. 1: enable 0:
disable. Can be configured in CONF state.*/
#define SPI_CS_SETUP (BIT(7))
#define SPI_CS_SETUP_M (BIT(7))
#define SPI_CS_SETUP_V 0x1
#define SPI_CS_SETUP_S 7
/* SPI_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
/* SPI_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: spi cs keep low when spi is in done phase. 1: enable 0: disable.
Can be configured in CONF state.*/
#define SPI_CS_HOLD (BIT(6))
@ -451,6 +451,20 @@ extern "C" {
#define SPI_TSCK_I_EDGE_M (BIT(5))
#define SPI_TSCK_I_EDGE_V 0x1
#define SPI_TSCK_I_EDGE_S 5
/* SPI_OPI_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: Just for master mode. 1: spi controller is in OPI mode (all in
8-b-m). 0: others. Can be configured in CONF state.*/
#define SPI_OPI_MODE (BIT(4))
#define SPI_OPI_MODE_M (BIT(4))
#define SPI_OPI_MODE_V 0x1
#define SPI_OPI_MODE_S 4
/* SPI_QPI_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: Both for master mode and slave mode. 1: spi controller is in
QPI mode. 0: others. Can be configured in CONF state.*/
#define SPI_QPI_MODE (BIT(3))
#define SPI_QPI_MODE_M (BIT(3))
#define SPI_QPI_MODE_V 0x1
#define SPI_QPI_MODE_S 3
/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set the bit to enable full duplex communication. 1: enable 0:
disable. Can be configured in CONF state.*/
@ -508,23 +522,7 @@ extern "C" {
#define SPI_USR_MISO_DBITLEN_V 0x7FFFFF
#define SPI_USR_MISO_DBITLEN_S 0
#define SPI_SLV_WR_STATUS_REG(i) (REG_SPI_BASE(i) + 0x02C)
/* SPI_OPI_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: Just for master mode. 1: spi controller is in OPI mode (all in
8-b-m). 0: others. Can be configured in CONF state.*/
#define SPI_OPI_MODE (BIT(1))
#define SPI_OPI_MODE_M (BIT(1))
#define SPI_OPI_MODE_V 0x1
#define SPI_OPI_MODE_S 1
/* SPI_QPI_MODE : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Both for master mode and slave mode. 1: spi controller is in
QPI mode. 0: others. Can be configured in CONF state.*/
#define SPI_QPI_MODE (BIT(0))
#define SPI_QPI_MODE_M (BIT(0))
#define SPI_QPI_MODE_V 0x1
#define SPI_QPI_MODE_S 0
#define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x030)
#define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x02C)
/* SPI_QUAD_DIN_PIN_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: 1: spi quad input swap enable 0: spi quad input swap disable.
Can be configured in CONF state.*/
@ -592,8 +590,35 @@ extern "C" {
#define SPI_CD_DATA_SET_M (BIT(20))
#define SPI_CD_DATA_SET_V 0x1
#define SPI_CD_DATA_SET_S 20
/* SPI_CMD_DTR_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
/*description: 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode including
master 1/2/4/8-bm. Can be configured in CONF state.*/
#define SPI_CMD_DTR_EN (BIT(19))
#define SPI_CMD_DTR_EN_M (BIT(19))
#define SPI_CMD_DTR_EN_V 0x1
#define SPI_CMD_DTR_EN_S 19
/* SPI_ADDR_DTR_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
/*description: 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode including
master 1/2/4/8-bm. Can be configured in CONF state.*/
#define SPI_ADDR_DTR_EN (BIT(18))
#define SPI_ADDR_DTR_EN_M (BIT(18))
#define SPI_ADDR_DTR_EN_V 0x1
#define SPI_ADDR_DTR_EN_S 18
/* SPI_DATA_DTR_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR
mode including master 1/2/4/8-bm. Can be configured in CONF state.*/
#define SPI_DATA_DTR_EN (BIT(17))
#define SPI_DATA_DTR_EN_M (BIT(17))
#define SPI_DATA_DTR_EN_V 0x1
#define SPI_DATA_DTR_EN_S 17
/* SPI_CLK_DATA_DTR_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: 1: SPI master DTR mode is applied to SPI clk data and spi_dqs*/
#define SPI_CLK_DATA_DTR_EN (BIT(16))
#define SPI_CLK_DATA_DTR_EN_M (BIT(16))
#define SPI_CLK_DATA_DTR_EN_V 0x1
#define SPI_CLK_DATA_DTR_EN_S 16
/* SPI_MASTER_CS_POL : R/W ;bitpos:[12:7] ;default: 6'b0 ; */
/*description: In the master mode the bits are the polarity of spi cs line
/*description: In the master mode the bits are the polarity of spi cs line
the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/
#define SPI_MASTER_CS_POL 0x0000003F
#define SPI_MASTER_CS_POL_M ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S))
@ -647,7 +672,7 @@ extern "C" {
#define SPI_CS0_DIS_V 0x1
#define SPI_CS0_DIS_S 0
#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0x034)
#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0x030)
/* SPI_SOFT_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: Software reset enable reset the spi clock line cs line and data
lines. Can be configured in CONF state.*/
@ -656,8 +681,7 @@ extern "C" {
#define SPI_SOFT_RESET_V 0x1
#define SPI_SOFT_RESET_S 31
/* SPI_SLAVE_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: Set SPI work mode. 1: slave mode 0: master mode. Can be configured
in CONF state.*/
/*description: Set SPI work mode. 1: slave mode 0: master mode.*/
#define SPI_SLAVE_MODE (BIT(30))
#define SPI_SLAVE_MODE_M (BIT(30))
#define SPI_SLAVE_MODE_V 0x1
@ -732,7 +756,7 @@ extern "C" {
#define SPI_TRANS_DONE_V 0x1
#define SPI_TRANS_DONE_S 4
#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0x038)
#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0x034)
/* SPI_SLV_LAST_ADDR : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
/*description: In the slave mode it is the value of address.*/
#define SPI_SLV_LAST_ADDR 0x000000FF
@ -752,31 +776,40 @@ extern "C" {
#define SPI_SLV_WR_DMA_DONE_M (BIT(15))
#define SPI_SLV_WR_DMA_DONE_V 0x1
#define SPI_SLV_WR_DMA_DONE_S 15
/* SPI_SLV_CMD_ERR : R/W ;bitpos:[14] ;default: 1'b0 ; */
/* SPI_SLV_CMD_ERR : RO ;bitpos:[14] ;default: 1'b0 ; */
/*description: 1: The command value of the last SPI transfer is not supported
by SPI slave. 0: The command value is supported or no command value is received.*/
#define SPI_SLV_CMD_ERR (BIT(14))
#define SPI_SLV_CMD_ERR_M (BIT(14))
#define SPI_SLV_CMD_ERR_V 0x1
#define SPI_SLV_CMD_ERR_S 14
/* SPI_SLV_ADDR_ERR : R/W ;bitpos:[13] ;default: 1'b0 ; */
/* SPI_SLV_ADDR_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */
/*description: 1: The address value of the last SPI transfer is not supported
by SPI slave. 0: The address value is supported or no address value is received.*/
#define SPI_SLV_ADDR_ERR (BIT(13))
#define SPI_SLV_ADDR_ERR_M (BIT(13))
#define SPI_SLV_ADDR_ERR_V 0x1
#define SPI_SLV_ADDR_ERR_S 13
/* SPI_SLV_NO_QPI_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: 1: spi slave QPI mode is not supported. 0: spi slave QPI mode is supported.*/
#define SPI_SLV_NO_QPI_EN (BIT(12))
#define SPI_SLV_NO_QPI_EN_M (BIT(12))
#define SPI_SLV_NO_QPI_EN_V 0x1
#define SPI_SLV_NO_QPI_EN_S 12
/* SPI_SLV_CMD_ERR_CLR : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: 1: Clear spi_slv_cmd_err. 0: not valid. Can be changed by CONF_buf.*/
#define SPI_SLV_CMD_ERR_CLR (BIT(11))
#define SPI_SLV_CMD_ERR_CLR_M (BIT(11))
#define SPI_SLV_CMD_ERR_CLR_V 0x1
#define SPI_SLV_CMD_ERR_CLR_S 11
/* SPI_SLV_ADDR_ERR_CLR : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: 1: Clear spi_slv_addr_err. 0: not valid. Can be changed by CONF_buf.*/
#define SPI_SLV_ADDR_ERR_CLR (BIT(10))
#define SPI_SLV_ADDR_ERR_CLR_M (BIT(10))
#define SPI_SLV_ADDR_ERR_CLR_V 0x1
#define SPI_SLV_ADDR_ERR_CLR_S 10
#define SPI_SLAVE2_REG(i) (REG_SPI_BASE(i) + 0x03C)
/* SPI_SLV_RD_DMA_DONE : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: The interrupt raw bit for the completion of Rd-DMA operation
in the slave mode. Can not be changed by CONF_buf.*/
#define SPI_SLV_RD_DMA_DONE (BIT(8))
#define SPI_SLV_RD_DMA_DONE_M (BIT(8))
#define SPI_SLV_RD_DMA_DONE_V 0x1
#define SPI_SLV_RD_DMA_DONE_S 8
#define SPI_SLV_WRBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x040)
#define SPI_SLV_WRBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x038)
/* SPI_CONF_BASE_BITLEN : R/W ;bitpos:[31:25] ;default: 7'd108 ; */
/*description: The basic spi_clk cycles of CONF state. The real cycle length
of CONF state if spi_usr_conf is enabled is spi_conf_base_bitlen[6:0] + spi_conf_bitlen[23:0].*/
@ -792,7 +825,7 @@ extern "C" {
#define SPI_SLV_WR_BUF_DONE_V 0x1
#define SPI_SLV_WR_BUF_DONE_S 24
#define SPI_SLV_RDBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x044)
#define SPI_SLV_RDBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x03C)
/* SPI_SEG_MAGIC_ERR : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: 1: The recent magic value in CONF buffer is not right in master
DMA seg-trans mode. 0: others.*/
@ -815,19 +848,26 @@ extern "C" {
#define SPI_SLV_DMA_RD_BYTELEN_V 0xFFFFF
#define SPI_SLV_DMA_RD_BYTELEN_S 0
#define SPI_SLV_RD_BYTE_REG(i) (REG_SPI_BASE(i) + 0x048)
#define SPI_SLV_RD_BYTE_REG(i) (REG_SPI_BASE(i) + 0x040)
/* SPI_USR_CONF : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: 1: Enable the DMA CONF phase of current seg-trans operation
/*description: 1: Enable the DMA CONF phase of current seg-trans operation
which means seg-trans will start. 0: This is not seg-trans mode.*/
#define SPI_USR_CONF (BIT(31))
#define SPI_USR_CONF_M (BIT(31))
#define SPI_USR_CONF_V 0x1
#define SPI_USR_CONF_S 31
/* SPI_DMA_SEG_MAGIC_VALUE : R/W ;bitpos:[29:24] ;default: 6'd23 ; */
/* SPI_SLV_RD_DMA_DONE : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: The interrupt raw bit for the completion of Rd-DMA operation
in the slave mode. Can not be changed by CONF_buf.*/
#define SPI_SLV_RD_DMA_DONE (BIT(30))
#define SPI_SLV_RD_DMA_DONE_M (BIT(30))
#define SPI_SLV_RD_DMA_DONE_V 0x1
#define SPI_SLV_RD_DMA_DONE_S 30
/* SPI_DMA_SEG_MAGIC_VALUE : R/W ;bitpos:[27:24] ;default: 4'd10 ; */
/*description: The magic value of BM table in master DMA seg-trans.*/
#define SPI_DMA_SEG_MAGIC_VALUE 0x0000003F
#define SPI_DMA_SEG_MAGIC_VALUE 0x0000000F
#define SPI_DMA_SEG_MAGIC_VALUE_M ((SPI_DMA_SEG_MAGIC_VALUE_V)<<(SPI_DMA_SEG_MAGIC_VALUE_S))
#define SPI_DMA_SEG_MAGIC_VALUE_V 0x3F
#define SPI_DMA_SEG_MAGIC_VALUE_V 0xF
#define SPI_DMA_SEG_MAGIC_VALUE_S 24
/* SPI_SLV_WRBUF_BYTELEN_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
/*description: 1: spi_slv_data_bytelen stores data byte length of master-write-to-slave
@ -865,7 +905,7 @@ extern "C" {
#define SPI_SLV_DATA_BYTELEN_V 0xFFFFF
#define SPI_SLV_DATA_BYTELEN_S 0
#define SPI_FSM_REG(i) (REG_SPI_BASE(i) + 0x050)
#define SPI_FSM_REG(i) (REG_SPI_BASE(i) + 0x044)
/* SPI_MST_DMA_RD_BYTELEN : R/W ;bitpos:[31:12] ;default: 20'h0 ; */
/*description: Define the master DMA read byte length in non seg-trans or seg-trans
mode. Invalid when spi_rx_eof_en is 0. Can be configured in CONF state..*/
@ -881,7 +921,7 @@ extern "C" {
#define SPI_ST_V 0xF
#define SPI_ST_S 0
#define SPI_HOLD_REG(i) (REG_SPI_BASE(i) + 0x054)
#define SPI_HOLD_REG(i) (REG_SPI_BASE(i) + 0x048)
/* SPI_DMA_SEG_TRANS_DONE : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: 1: spi master DMA full-duplex/half-duplex seg-trans ends or
slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-trans is not ended or not occurred. Can not be changed by CONF_buf.*/
@ -918,27 +958,20 @@ extern "C" {
#define SPI_INT_HOLD_ENA_V 0x3
#define SPI_INT_HOLD_ENA_S 0
#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x058)
#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x04C)
/* SPI_DMA_SEG_TRANS_CLR : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: 1: End slave seg-trans which acts as 0x05 command. 2 or more
end seg-trans signals will induce error in DMA RX.*/
#define SPI_DMA_SEG_TRANS_CLR (BIT(28))
#define SPI_DMA_SEG_TRANS_CLR_M (BIT(28))
#define SPI_DMA_SEG_TRANS_CLR_V 0x1
#define SPI_DMA_SEG_TRANS_CLR_S 28
/* SPI_EXT_MEM_BK_SIZE : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
/*description: Select the external memory block size.*/
#define SPI_EXT_MEM_BK_SIZE 0x00000003
#define SPI_EXT_MEM_BK_SIZE_M ((SPI_EXT_MEM_BK_SIZE_V)<<(SPI_EXT_MEM_BK_SIZE_S))
#define SPI_EXT_MEM_BK_SIZE_V 0x3
#define SPI_EXT_MEM_BK_SIZE_S 26
/* SPI_DMA_OUTFIFO_EMPTY_ERR : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: 1:spi_dma_outfifo_empty and spi_pop_data_prep are valid which
means that there is no data to pop but pop is valid. 0: Others. Can not be changed by CONF_buf.*/
#define SPI_DMA_OUTFIFO_EMPTY_ERR (BIT(25))
#define SPI_DMA_OUTFIFO_EMPTY_ERR_M (BIT(25))
#define SPI_DMA_OUTFIFO_EMPTY_ERR_V 0x1
#define SPI_DMA_OUTFIFO_EMPTY_ERR_S 25
/* SPI_DMA_INFIFO_FULL_ERR : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: 1:spi_dma_infifo_full and spi_push_data_prep are valid which
means that DMA Rx buffer is full but push is valid. 0: Others. Can not be changed by CONF_buf.*/
#define SPI_DMA_INFIFO_FULL_ERR (BIT(24))
#define SPI_DMA_INFIFO_FULL_ERR_M (BIT(24))
#define SPI_DMA_INFIFO_FULL_ERR_V 0x1
#define SPI_DMA_INFIFO_FULL_ERR_S 24
/* SPI_DMA_OUTFIFO_EMPTY_CLR : R/W ;bitpos:[23] ;default: 1'b0 ; */
/*description: 1:Clear spi_dma_outfifo_empty_vld. 0: Do not control it.*/
#define SPI_DMA_OUTFIFO_EMPTY_CLR (BIT(23))
@ -1077,7 +1110,7 @@ extern "C" {
#define SPI_IN_RST_V 0x1
#define SPI_IN_RST_S 2
#define SPI_DMA_OUT_LINK_REG(i) (REG_SPI_BASE(i) + 0x05C)
#define SPI_DMA_OUT_LINK_REG(i) (REG_SPI_BASE(i) + 0x050)
/* SPI_DMA_TX_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: spi dma write data status bit.*/
#define SPI_DMA_TX_ENA (BIT(31))
@ -1109,7 +1142,7 @@ extern "C" {
#define SPI_OUTLINK_ADDR_V 0xFFFFF
#define SPI_OUTLINK_ADDR_S 0
#define SPI_DMA_IN_LINK_REG(i) (REG_SPI_BASE(i) + 0x060)
#define SPI_DMA_IN_LINK_REG(i) (REG_SPI_BASE(i) + 0x054)
/* SPI_DMA_RX_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: spi dma read data status bit.*/
#define SPI_DMA_RX_ENA (BIT(31))
@ -1148,7 +1181,49 @@ extern "C" {
#define SPI_INLINK_ADDR_V 0xFFFFF
#define SPI_INLINK_ADDR_S 0
#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x064)
#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x058)
/* SPI_SLV_CMDA_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: The enable bit for SPI slave CMDA interrupt.*/
#define SPI_SLV_CMDA_INT_ENA (BIT(15))
#define SPI_SLV_CMDA_INT_ENA_M (BIT(15))
#define SPI_SLV_CMDA_INT_ENA_V 0x1
#define SPI_SLV_CMDA_INT_ENA_S 15
/* SPI_SLV_CMD9_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: The enable bit for SPI slave CMD9 interrupt.*/
#define SPI_SLV_CMD9_INT_ENA (BIT(14))
#define SPI_SLV_CMD9_INT_ENA_M (BIT(14))
#define SPI_SLV_CMD9_INT_ENA_V 0x1
#define SPI_SLV_CMD9_INT_ENA_S 14
/* SPI_SLV_CMD8_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: The enable bit for SPI slave CMD8 interrupt.*/
#define SPI_SLV_CMD8_INT_ENA (BIT(13))
#define SPI_SLV_CMD8_INT_ENA_M (BIT(13))
#define SPI_SLV_CMD8_INT_ENA_V 0x1
#define SPI_SLV_CMD8_INT_ENA_S 13
/* SPI_SLV_CMD7_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: The enable bit for SPI slave CMD7 interrupt.*/
#define SPI_SLV_CMD7_INT_ENA (BIT(12))
#define SPI_SLV_CMD7_INT_ENA_M (BIT(12))
#define SPI_SLV_CMD7_INT_ENA_V 0x1
#define SPI_SLV_CMD7_INT_ENA_S 12
/* SPI_SLV_CMD6_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: The enable bit for SPI slave CMD6 interrupt.*/
#define SPI_SLV_CMD6_INT_ENA (BIT(11))
#define SPI_SLV_CMD6_INT_ENA_M (BIT(11))
#define SPI_SLV_CMD6_INT_ENA_V 0x1
#define SPI_SLV_CMD6_INT_ENA_S 11
/* SPI_OUTFIFO_EMPTY_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: The enable bit for outfifo empty error interrupt.*/
#define SPI_OUTFIFO_EMPTY_ERR_INT_ENA (BIT(10))
#define SPI_OUTFIFO_EMPTY_ERR_INT_ENA_M (BIT(10))
#define SPI_OUTFIFO_EMPTY_ERR_INT_ENA_V 0x1
#define SPI_OUTFIFO_EMPTY_ERR_INT_ENA_S 10
/* SPI_INFIFO_FULL_ERR_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: The enable bit for infifo full error interrupt.*/
#define SPI_INFIFO_FULL_ERR_INT_ENA (BIT(9))
#define SPI_INFIFO_FULL_ERR_INT_ENA_M (BIT(9))
#define SPI_INFIFO_FULL_ERR_INT_ENA_V 0x1
#define SPI_INFIFO_FULL_ERR_INT_ENA_S 9
/* SPI_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: The enable bit for sending all the packets to host done. Can
be configured in CONF state.*/
@ -1210,7 +1285,51 @@ extern "C" {
#define SPI_INLINK_DSCR_EMPTY_INT_ENA_V 0x1
#define SPI_INLINK_DSCR_EMPTY_INT_ENA_S 0
#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x068)
#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x05C)
/* SPI_SLV_CMDA_INT_RAW : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: The raw bit for SPI slave CMDA interrupt.*/
#define SPI_SLV_CMDA_INT_RAW (BIT(15))
#define SPI_SLV_CMDA_INT_RAW_M (BIT(15))
#define SPI_SLV_CMDA_INT_RAW_V 0x1
#define SPI_SLV_CMDA_INT_RAW_S 15
/* SPI_SLV_CMD9_INT_RAW : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: The raw bit for SPI slave CMD9 interrupt.*/
#define SPI_SLV_CMD9_INT_RAW (BIT(14))
#define SPI_SLV_CMD9_INT_RAW_M (BIT(14))
#define SPI_SLV_CMD9_INT_RAW_V 0x1
#define SPI_SLV_CMD9_INT_RAW_S 14
/* SPI_SLV_CMD8_INT_RAW : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: The raw bit for SPI slave CMD8 interrupt.*/
#define SPI_SLV_CMD8_INT_RAW (BIT(13))
#define SPI_SLV_CMD8_INT_RAW_M (BIT(13))
#define SPI_SLV_CMD8_INT_RAW_V 0x1
#define SPI_SLV_CMD8_INT_RAW_S 13
/* SPI_SLV_CMD7_INT_RAW : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: The raw bit for SPI slave CMD7 interrupt.*/
#define SPI_SLV_CMD7_INT_RAW (BIT(12))
#define SPI_SLV_CMD7_INT_RAW_M (BIT(12))
#define SPI_SLV_CMD7_INT_RAW_V 0x1
#define SPI_SLV_CMD7_INT_RAW_S 12
/* SPI_SLV_CMD6_INT_RAW : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: The raw bit for SPI slave CMD6 interrupt.*/
#define SPI_SLV_CMD6_INT_RAW (BIT(11))
#define SPI_SLV_CMD6_INT_RAW_M (BIT(11))
#define SPI_SLV_CMD6_INT_RAW_V 0x1
#define SPI_SLV_CMD6_INT_RAW_S 11
/* SPI_OUTFIFO_EMPTY_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: 1:spi_dma_outfifo_empty and spi_pop_data_prep are valid which
means that there is no data to pop but pop is valid. 0: Others. Can not be changed by CONF_buf.*/
#define SPI_OUTFIFO_EMPTY_ERR_INT_RAW (BIT(10))
#define SPI_OUTFIFO_EMPTY_ERR_INT_RAW_M (BIT(10))
#define SPI_OUTFIFO_EMPTY_ERR_INT_RAW_V 0x1
#define SPI_OUTFIFO_EMPTY_ERR_INT_RAW_S 10
/* SPI_INFIFO_FULL_ERR_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: 1:spi_dma_infifo_full and spi_push_data_prep are valid which
means that DMA Rx buffer is full but push is valid. 0: Others. Can not be changed by CONF_buf.*/
#define SPI_INFIFO_FULL_ERR_INT_RAW (BIT(9))
#define SPI_INFIFO_FULL_ERR_INT_RAW_M (BIT(9))
#define SPI_INFIFO_FULL_ERR_INT_RAW_V 0x1
#define SPI_INFIFO_FULL_ERR_INT_RAW_S 9
/* SPI_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: The raw bit for sending all the packets to host done. Can be
configured in CONF state.*/
@ -1271,7 +1390,49 @@ extern "C" {
#define SPI_INLINK_DSCR_EMPTY_INT_RAW_V 0x1
#define SPI_INLINK_DSCR_EMPTY_INT_RAW_S 0
#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x06C)
#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x060)
/* SPI_SLV_CMDA_INT_ST : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: The status bit for SPI slave CMDA interrupt.*/
#define SPI_SLV_CMDA_INT_ST (BIT(15))
#define SPI_SLV_CMDA_INT_ST_M (BIT(15))
#define SPI_SLV_CMDA_INT_ST_V 0x1
#define SPI_SLV_CMDA_INT_ST_S 15
/* SPI_SLV_CMD9_INT_ST : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: The status bit for SPI slave CMD9 interrupt.*/
#define SPI_SLV_CMD9_INT_ST (BIT(14))
#define SPI_SLV_CMD9_INT_ST_M (BIT(14))
#define SPI_SLV_CMD9_INT_ST_V 0x1
#define SPI_SLV_CMD9_INT_ST_S 14
/* SPI_SLV_CMD8_INT_ST : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: The status bit for SPI slave CMD8 interrupt.*/
#define SPI_SLV_CMD8_INT_ST (BIT(13))
#define SPI_SLV_CMD8_INT_ST_M (BIT(13))
#define SPI_SLV_CMD8_INT_ST_V 0x1
#define SPI_SLV_CMD8_INT_ST_S 13
/* SPI_SLV_CMD7_INT_ST : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: The status bit for SPI slave CMD7 interrupt.*/
#define SPI_SLV_CMD7_INT_ST (BIT(12))
#define SPI_SLV_CMD7_INT_ST_M (BIT(12))
#define SPI_SLV_CMD7_INT_ST_V 0x1
#define SPI_SLV_CMD7_INT_ST_S 12
/* SPI_SLV_CMD6_INT_ST : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: The status bit for SPI slave CMD6 interrupt.*/
#define SPI_SLV_CMD6_INT_ST (BIT(11))
#define SPI_SLV_CMD6_INT_ST_M (BIT(11))
#define SPI_SLV_CMD6_INT_ST_V 0x1
#define SPI_SLV_CMD6_INT_ST_S 11
/* SPI_OUTFIFO_EMPTY_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: The status bit for outfifo empty error.*/
#define SPI_OUTFIFO_EMPTY_ERR_INT_ST (BIT(10))
#define SPI_OUTFIFO_EMPTY_ERR_INT_ST_M (BIT(10))
#define SPI_OUTFIFO_EMPTY_ERR_INT_ST_V 0x1
#define SPI_OUTFIFO_EMPTY_ERR_INT_ST_S 10
/* SPI_INFIFO_FULL_ERR_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: The status bit for infifo full error.*/
#define SPI_INFIFO_FULL_ERR_INT_ST (BIT(9))
#define SPI_INFIFO_FULL_ERR_INT_ST_M (BIT(9))
#define SPI_INFIFO_FULL_ERR_INT_ST_V 0x1
#define SPI_INFIFO_FULL_ERR_INT_ST_S 9
/* SPI_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: The status bit for sending all the packets to host done.*/
#define SPI_OUT_TOTAL_EOF_INT_ST (BIT(8))
@ -1327,7 +1488,50 @@ extern "C" {
#define SPI_INLINK_DSCR_EMPTY_INT_ST_V 0x1
#define SPI_INLINK_DSCR_EMPTY_INT_ST_S 0
#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x070)
#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x064)
/* SPI_SLV_CMDA_INT_CLR : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: The clear bit for SPI slave CMDA interrupt.*/
#define SPI_SLV_CMDA_INT_CLR (BIT(15))
#define SPI_SLV_CMDA_INT_CLR_M (BIT(15))
#define SPI_SLV_CMDA_INT_CLR_V 0x1
#define SPI_SLV_CMDA_INT_CLR_S 15
/* SPI_SLV_CMD9_INT_CLR : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: The clear bit for SPI slave CMD9 interrupt.*/
#define SPI_SLV_CMD9_INT_CLR (BIT(14))
#define SPI_SLV_CMD9_INT_CLR_M (BIT(14))
#define SPI_SLV_CMD9_INT_CLR_V 0x1
#define SPI_SLV_CMD9_INT_CLR_S 14
/* SPI_SLV_CMD8_INT_CLR : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: The clear bit for SPI slave CMD8 interrupt.*/
#define SPI_SLV_CMD8_INT_CLR (BIT(13))
#define SPI_SLV_CMD8_INT_CLR_M (BIT(13))
#define SPI_SLV_CMD8_INT_CLR_V 0x1
#define SPI_SLV_CMD8_INT_CLR_S 13
/* SPI_SLV_CMD7_INT_CLR : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: The clear bit for SPI slave CMD7 interrupt.*/
#define SPI_SLV_CMD7_INT_CLR (BIT(12))
#define SPI_SLV_CMD7_INT_CLR_M (BIT(12))
#define SPI_SLV_CMD7_INT_CLR_V 0x1
#define SPI_SLV_CMD7_INT_CLR_S 12
/* SPI_SLV_CMD6_INT_CLR : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: The clear bit for SPI slave CMD6 interrupt.*/
#define SPI_SLV_CMD6_INT_CLR (BIT(11))
#define SPI_SLV_CMD6_INT_CLR_M (BIT(11))
#define SPI_SLV_CMD6_INT_CLR_V 0x1
#define SPI_SLV_CMD6_INT_CLR_S 11
/* SPI_OUTFIFO_EMPTY_ERR_INT_CLR : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: 1: Clear spi_dma_outfifo_empty_err signal. 0: not valid. Can
be changed by CONF_buf.*/
#define SPI_OUTFIFO_EMPTY_ERR_INT_CLR (BIT(10))
#define SPI_OUTFIFO_EMPTY_ERR_INT_CLR_M (BIT(10))
#define SPI_OUTFIFO_EMPTY_ERR_INT_CLR_V 0x1
#define SPI_OUTFIFO_EMPTY_ERR_INT_CLR_S 10
/* SPI_INFIFO_FULL_ERR_INT_CLR : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: 1: Clear spi_dma_infifo_full_err. 0: not valid. Can be changed by CONF_buf.*/
#define SPI_INFIFO_FULL_ERR_INT_CLR (BIT(9))
#define SPI_INFIFO_FULL_ERR_INT_CLR_M (BIT(9))
#define SPI_INFIFO_FULL_ERR_INT_CLR_V 0x1
#define SPI_INFIFO_FULL_ERR_INT_CLR_S 9
/* SPI_OUT_TOTAL_EOF_INT_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: The clear bit for sending all the packets to host done. Can be
configured in CONF state.*/
@ -1389,7 +1593,7 @@ extern "C" {
#define SPI_INLINK_DSCR_EMPTY_INT_CLR_V 0x1
#define SPI_INLINK_DSCR_EMPTY_INT_CLR_S 0
#define SPI_IN_ERR_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x074)
#define SPI_IN_ERR_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x068)
/* SPI_DMA_IN_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: The inlink descriptor address when spi dma produce receiving error.*/
#define SPI_DMA_IN_ERR_EOF_DES_ADDR 0xFFFFFFFF
@ -1397,7 +1601,7 @@ extern "C" {
#define SPI_DMA_IN_ERR_EOF_DES_ADDR_V 0xFFFFFFFF
#define SPI_DMA_IN_ERR_EOF_DES_ADDR_S 0
#define SPI_IN_SUC_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x078)
#define SPI_IN_SUC_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x06C)
/* SPI_DMA_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: The last inlink descriptor address when spi dma produce from_suc_eof.*/
#define SPI_DMA_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF
@ -1405,7 +1609,7 @@ extern "C" {
#define SPI_DMA_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF
#define SPI_DMA_IN_SUC_EOF_DES_ADDR_S 0
#define SPI_INLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x07C)
#define SPI_INLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x070)
/* SPI_DMA_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: The content of current in descriptor pointer.*/
#define SPI_DMA_INLINK_DSCR 0xFFFFFFFF
@ -1413,7 +1617,7 @@ extern "C" {
#define SPI_DMA_INLINK_DSCR_V 0xFFFFFFFF
#define SPI_DMA_INLINK_DSCR_S 0
#define SPI_INLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x080)
#define SPI_INLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x074)
/* SPI_DMA_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: The content of next in descriptor pointer.*/
#define SPI_DMA_INLINK_DSCR_BF0 0xFFFFFFFF
@ -1421,7 +1625,7 @@ extern "C" {
#define SPI_DMA_INLINK_DSCR_BF0_V 0xFFFFFFFF
#define SPI_DMA_INLINK_DSCR_BF0_S 0
#define SPI_INLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x084)
#define SPI_INLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x078)
/* SPI_DMA_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: The content of current in descriptor data buffer pointer.*/
#define SPI_DMA_INLINK_DSCR_BF1 0xFFFFFFFF
@ -1429,7 +1633,7 @@ extern "C" {
#define SPI_DMA_INLINK_DSCR_BF1_V 0xFFFFFFFF
#define SPI_DMA_INLINK_DSCR_BF1_S 0
#define SPI_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x088)
#define SPI_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x07C)
/* SPI_DMA_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: The address of buffer relative to the outlink descriptor that produce eof.*/
#define SPI_DMA_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF
@ -1437,7 +1641,7 @@ extern "C" {
#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF
#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_S 0
#define SPI_OUT_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x08C)
#define SPI_OUT_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x080)
/* SPI_DMA_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: The last outlink descriptor address when spi dma produce to_eof.*/
#define SPI_DMA_OUT_EOF_DES_ADDR 0xFFFFFFFF
@ -1445,7 +1649,7 @@ extern "C" {
#define SPI_DMA_OUT_EOF_DES_ADDR_V 0xFFFFFFFF
#define SPI_DMA_OUT_EOF_DES_ADDR_S 0
#define SPI_OUTLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x090)
#define SPI_OUTLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x084)
/* SPI_DMA_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: The content of current out descriptor pointer.*/
#define SPI_DMA_OUTLINK_DSCR 0xFFFFFFFF
@ -1453,7 +1657,7 @@ extern "C" {
#define SPI_DMA_OUTLINK_DSCR_V 0xFFFFFFFF
#define SPI_DMA_OUTLINK_DSCR_S 0
#define SPI_OUTLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x094)
#define SPI_OUTLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x088)
/* SPI_DMA_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: The content of next out descriptor pointer.*/
#define SPI_DMA_OUTLINK_DSCR_BF0 0xFFFFFFFF
@ -1461,7 +1665,7 @@ extern "C" {
#define SPI_DMA_OUTLINK_DSCR_BF0_V 0xFFFFFFFF
#define SPI_DMA_OUTLINK_DSCR_BF0_S 0
#define SPI_OUTLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x098)
#define SPI_OUTLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x08C)
/* SPI_DMA_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: The content of current out descriptor data buffer pointer.*/
#define SPI_DMA_OUTLINK_DSCR_BF1 0xFFFFFFFF
@ -1469,7 +1673,7 @@ extern "C" {
#define SPI_DMA_OUTLINK_DSCR_BF1_V 0xFFFFFFFF
#define SPI_DMA_OUTLINK_DSCR_BF1_S 0
#define SPI_DMA_OUTSTATUS_REG(i) (REG_SPI_BASE(i) + 0x09C)
#define SPI_DMA_OUTSTATUS_REG(i) (REG_SPI_BASE(i) + 0x090)
/* SPI_DMA_OUTFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */
/*description: SPI dma outfifo is empty.*/
#define SPI_DMA_OUTFIFO_EMPTY (BIT(31))
@ -1507,7 +1711,7 @@ extern "C" {
#define SPI_DMA_OUTDSCR_ADDR_V 0x3FFFF
#define SPI_DMA_OUTDSCR_ADDR_S 0
#define SPI_DMA_INSTATUS_REG(i) (REG_SPI_BASE(i) + 0x0A0)
#define SPI_DMA_INSTATUS_REG(i) (REG_SPI_BASE(i) + 0x094)
/* SPI_DMA_INFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */
/*description: SPI dma infifo is empty.*/
#define SPI_DMA_INFIFO_EMPTY (BIT(31))
@ -1545,7 +1749,7 @@ extern "C" {
#define SPI_DMA_INDSCR_ADDR_V 0x3FFFF
#define SPI_DMA_INDSCR_ADDR_S 0
#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x0A4)
#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x098)
/* SPI_BUF0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer*/
#define SPI_BUF0 0xFFFFFFFF
@ -1553,7 +1757,7 @@ extern "C" {
#define SPI_BUF0_V 0xFFFFFFFF
#define SPI_BUF0_S 0
#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x0A8)
#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x09C)
/* SPI_BUF1 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer*/
#define SPI_BUF1 0xFFFFFFFF
@ -1561,7 +1765,7 @@ extern "C" {
#define SPI_BUF1_V 0xFFFFFFFF
#define SPI_BUF1_S 0
#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0x0AC)
#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0x0A0)
/* SPI_BUF2 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer*/
#define SPI_BUF2 0xFFFFFFFF
@ -1569,7 +1773,7 @@ extern "C" {
#define SPI_BUF2_V 0xFFFFFFFF
#define SPI_BUF2_S 0
#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0x0B0)
#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0x0A4)
/* SPI_BUF3 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer*/
#define SPI_BUF3 0xFFFFFFFF
@ -1577,7 +1781,7 @@ extern "C" {
#define SPI_BUF3_V 0xFFFFFFFF
#define SPI_BUF3_S 0
#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0x0B4)
#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0x0A8)
/* SPI_BUF4 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer*/
#define SPI_BUF4 0xFFFFFFFF
@ -1585,7 +1789,7 @@ extern "C" {
#define SPI_BUF4_V 0xFFFFFFFF
#define SPI_BUF4_S 0
#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0x0B8)
#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0x0AC)
/* SPI_BUF5 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer*/
#define SPI_BUF5 0xFFFFFFFF
@ -1593,7 +1797,7 @@ extern "C" {
#define SPI_BUF5_V 0xFFFFFFFF
#define SPI_BUF5_S 0
#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0x0BC)
#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0x0B0)
/* SPI_BUF6 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer*/
#define SPI_BUF6 0xFFFFFFFF
@ -1601,7 +1805,7 @@ extern "C" {
#define SPI_BUF6_V 0xFFFFFFFF
#define SPI_BUF6_S 0
#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0x0C0)
#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0x0B4)
/* SPI_BUF7 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer*/
#define SPI_BUF7 0xFFFFFFFF
@ -1609,7 +1813,7 @@ extern "C" {
#define SPI_BUF7_V 0xFFFFFFFF
#define SPI_BUF7_S 0
#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0x0C4)
#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0x0B8)
/* SPI_BUF8 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer*/
#define SPI_BUF8 0xFFFFFFFF
@ -1617,7 +1821,7 @@ extern "C" {
#define SPI_BUF8_V 0xFFFFFFFF
#define SPI_BUF8_S 0
#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0x0C8)
#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0x0BC)
/* SPI_BUF9 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer*/
#define SPI_BUF9 0xFFFFFFFF
@ -1625,7 +1829,7 @@ extern "C" {
#define SPI_BUF9_V 0xFFFFFFFF
#define SPI_BUF9_S 0
#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0x0CC)
#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0x0C0)
/* SPI_BUF10 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer*/
#define SPI_BUF10 0xFFFFFFFF
@ -1633,7 +1837,7 @@ extern "C" {
#define SPI_BUF10_V 0xFFFFFFFF
#define SPI_BUF10_S 0
#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0x0D0)
#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0x0C4)
/* SPI_BUF11 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer*/
#define SPI_BUF11 0xFFFFFFFF
@ -1641,7 +1845,7 @@ extern "C" {
#define SPI_BUF11_V 0xFFFFFFFF
#define SPI_BUF11_S 0
#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0x0D4)
#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0x0C8)
/* SPI_BUF12 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer*/
#define SPI_BUF12 0xFFFFFFFF
@ -1649,7 +1853,7 @@ extern "C" {
#define SPI_BUF12_V 0xFFFFFFFF
#define SPI_BUF12_S 0
#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0x0D8)
#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0x0CC)
/* SPI_BUF13 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer*/
#define SPI_BUF13 0xFFFFFFFF
@ -1657,7 +1861,7 @@ extern "C" {
#define SPI_BUF13_V 0xFFFFFFFF
#define SPI_BUF13_S 0
#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0x0DC)
#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0x0D0)
/* SPI_BUF14 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer*/
#define SPI_BUF14 0xFFFFFFFF
@ -1665,7 +1869,7 @@ extern "C" {
#define SPI_BUF14_V 0xFFFFFFFF
#define SPI_BUF14_S 0
#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0x0E0)
#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0x0D4)
/* SPI_BUF15 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer*/
#define SPI_BUF15 0xFFFFFFFF
@ -1673,7 +1877,7 @@ extern "C" {
#define SPI_BUF15_V 0xFFFFFFFF
#define SPI_BUF15_S 0
#define SPI_W16_REG(i) (REG_SPI_BASE(i) + 0x0E4)
#define SPI_W16_REG(i) (REG_SPI_BASE(i) + 0x0D8)
/* SPI_BUF16 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer*/
#define SPI_BUF16 0xFFFFFFFF
@ -1681,7 +1885,7 @@ extern "C" {
#define SPI_BUF16_V 0xFFFFFFFF
#define SPI_BUF16_S 0
#define SPI_W17_REG(i) (REG_SPI_BASE(i) + 0x0E8)
#define SPI_W17_REG(i) (REG_SPI_BASE(i) + 0x0DC)
/* SPI_BUF17 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer*/
#define SPI_BUF17 0xFFFFFFFF
@ -1689,7 +1893,7 @@ extern "C" {
#define SPI_BUF17_V 0xFFFFFFFF
#define SPI_BUF17_S 0
#define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x0EC)
#define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x0E0)
/* SPI_TIMING_CLK_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: 1:enable hclk in spi_timing.v. 0: disable it. Can be configured in CONF state.*/
#define SPI_TIMING_CLK_ENA (BIT(24))
@ -1753,7 +1957,7 @@ extern "C" {
#define SPI_DIN0_MODE_V 0x7
#define SPI_DIN0_MODE_S 0
#define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x0F0)
#define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x0E4)
/* SPI_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
/*description: the input signals are delayed by system clock cycles 0: delayed
by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
@ -1811,7 +2015,7 @@ extern "C" {
#define SPI_DIN0_NUM_V 0x3
#define SPI_DIN0_NUM_S 0
#define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x0F4)
#define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x0E8)
/* SPI_DOUT7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
/*description: the output signals are delayed by system clock cycles 0: output
without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/
@ -1869,7 +2073,7 @@ extern "C" {
#define SPI_DOUT0_MODE_V 0x7
#define SPI_DOUT0_MODE_S 0
#define SPI_DOUT_NUM_REG(i) (REG_SPI_BASE(i) + 0x0F8)
#define SPI_DOUT_NUM_REG(i) (REG_SPI_BASE(i) + 0x0EC)
/* SPI_DOUT7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
/*description: the output signals are delayed by system clock cycles 0: delayed
by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
@ -1927,14 +2131,14 @@ extern "C" {
#define SPI_DOUT0_NUM_V 0x3
#define SPI_DOUT0_NUM_S 0
#define SPI_LCD_CTRL_REG(i) (REG_SPI_BASE(i) + 0x0FC)
/* SPI_LCD_SRGB_MODE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
#define SPI_LCD_CTRL_REG(i) (REG_SPI_BASE(i) + 0x0F0)
/* SPI_LCD_MODE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: 1: Enable LCD mode output vsync hsync de. 0: Disable. Can be
configured in CONF state.*/
#define SPI_LCD_SRGB_MODE_EN (BIT(31))
#define SPI_LCD_SRGB_MODE_EN_M (BIT(31))
#define SPI_LCD_SRGB_MODE_EN_V 0x1
#define SPI_LCD_SRGB_MODE_EN_S 31
#define SPI_LCD_MODE_EN (BIT(31))
#define SPI_LCD_MODE_EN_M (BIT(31))
#define SPI_LCD_MODE_EN_V 0x1
#define SPI_LCD_MODE_EN_S 31
/* SPI_LCD_VT_HEIGHT : R/W ;bitpos:[30:21] ;default: 10'd0 ; */
/*description: It is the vertical total height of a frame. Can be configured in CONF state.*/
#define SPI_LCD_VT_HEIGHT 0x000003FF
@ -1955,7 +2159,7 @@ extern "C" {
#define SPI_LCD_HB_FRONT_V 0x7FF
#define SPI_LCD_HB_FRONT_S 0
#define SPI_LCD_CTRL1_REG(i) (REG_SPI_BASE(i) + 0x0100)
#define SPI_LCD_CTRL1_REG(i) (REG_SPI_BASE(i) + 0x0F4)
/* SPI_LCD_HT_WIDTH : R/W ;bitpos:[31:20] ;default: 12'd0 ; */
/*description: It is the horizontal total width of a frame. Can be configured in CONF state.*/
#define SPI_LCD_HT_WIDTH 0x00000FFF
@ -1976,49 +2180,55 @@ extern "C" {
#define SPI_LCD_VB_FRONT_V 0xFF
#define SPI_LCD_VB_FRONT_S 0
#define SPI_LCD_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x0104)
#define SPI_LCD_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x0F8)
/* SPI_LCD_HSYNC_POSITION : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
/*description: It is the position of spi_hsync_out active pulse in a line. Can
be configured in CONF state.*/
/*description: It is the position of spi_hsync active pulse in a line. Can be
configured in CONF state.*/
#define SPI_LCD_HSYNC_POSITION 0x000000FF
#define SPI_LCD_HSYNC_POSITION_M ((SPI_LCD_HSYNC_POSITION_V)<<(SPI_LCD_HSYNC_POSITION_S))
#define SPI_LCD_HSYNC_POSITION_V 0xFF
#define SPI_LCD_HSYNC_POSITION_S 24
/* SPI_HSYNC_IDLE_POL : R/W ;bitpos:[23] ;default: 1'd0 ; */
/*description: It is the idle value of spi_hsync_out. Can be configured in CONF state.*/
/*description: It is the idle value of spi_hsync. Can be configured in CONF state.*/
#define SPI_HSYNC_IDLE_POL (BIT(23))
#define SPI_HSYNC_IDLE_POL_M (BIT(23))
#define SPI_HSYNC_IDLE_POL_V 0x1
#define SPI_HSYNC_IDLE_POL_S 23
/* SPI_LCD_HSYNC_WIDTH : R/W ;bitpos:[22:16] ;default: 7'd0 ; */
/*description: It is the position of spi_hsync_out active pulse in a line. Can
be configured in CONF state.*/
/* SPI_LCD_HSYNC_WIDTH : R/W ;bitpos:[22:16] ;default: 7'd1 ; */
/*description: It is the position of spi_hsync active pulse in a line. Can be
configured in CONF state.*/
#define SPI_LCD_HSYNC_WIDTH 0x0000007F
#define SPI_LCD_HSYNC_WIDTH_M ((SPI_LCD_HSYNC_WIDTH_V)<<(SPI_LCD_HSYNC_WIDTH_S))
#define SPI_LCD_HSYNC_WIDTH_V 0x7F
#define SPI_LCD_HSYNC_WIDTH_S 16
/* SPI_LCD_VSYNC_POSITION : R/W ;bitpos:[15:8] ;default: 8'd0 ; */
/*description: It is the position of spi_vsync_out active pulse in a line. Can
be configured in CONF state.*/
#define SPI_LCD_VSYNC_POSITION 0x000000FF
#define SPI_LCD_VSYNC_POSITION_M ((SPI_LCD_VSYNC_POSITION_V)<<(SPI_LCD_VSYNC_POSITION_S))
#define SPI_LCD_VSYNC_POSITION_V 0xFF
#define SPI_LCD_VSYNC_POSITION_S 8
/* SPI_VSYNC_IDLE_POL : R/W ;bitpos:[7] ;default: 1'd0 ; */
/*description: It is the idle value of spi_vsync_out. Can be configured in CONF state.*/
/*description: It is the idle value of spi_vsync. Can be configured in CONF state.*/
#define SPI_VSYNC_IDLE_POL (BIT(7))
#define SPI_VSYNC_IDLE_POL_M (BIT(7))
#define SPI_VSYNC_IDLE_POL_V 0x1
#define SPI_VSYNC_IDLE_POL_S 7
/* SPI_LCD_VSYNC_WIDTH : R/W ;bitpos:[6:0] ;default: 7'd0 ; */
/*description: It is the position of spi_vsync_out active pulse in a line. Can
be configured in CONF state.*/
/* SPI_LCD_VSYNC_WIDTH : R/W ;bitpos:[6:0] ;default: 7'd1 ; */
/*description: It is the position of spi_vsync active pulse in a line. Can be
configured in CONF state.*/
#define SPI_LCD_VSYNC_WIDTH 0x0000007F
#define SPI_LCD_VSYNC_WIDTH_M ((SPI_LCD_VSYNC_WIDTH_V)<<(SPI_LCD_VSYNC_WIDTH_S))
#define SPI_LCD_VSYNC_WIDTH_V 0x7F
#define SPI_LCD_VSYNC_WIDTH_S 0
#define SPI_LCD_D_MODE_REG(i) (REG_SPI_BASE(i) + 0x108)
#define SPI_LCD_D_MODE_REG(i) (REG_SPI_BASE(i) + 0x0FC)
/* SPI_HS_BLANK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: 1: The pulse of spi_hsync is out in vertical blanking lines in
seg-trans or one trans. 0: spi_hsync pulse is valid only in active region lines in seg-trans.*/
#define SPI_HS_BLANK_EN (BIT(16))
#define SPI_HS_BLANK_EN_M (BIT(16))
#define SPI_HS_BLANK_EN_V 0x1
#define SPI_HS_BLANK_EN_S 16
/* SPI_DE_IDLE_POL : R/W ;bitpos:[15] ;default: 1'd0 ; */
/*description: It is the idle value of spi_de.*/
#define SPI_DE_IDLE_POL (BIT(15))
#define SPI_DE_IDLE_POL_M (BIT(15))
#define SPI_DE_IDLE_POL_V 0x1
#define SPI_DE_IDLE_POL_S 15
/* SPI_D_VSYNC_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
/*description: the output spi_vsync is delayed by system clock cycles 0: output
without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/
@ -2055,7 +2265,7 @@ extern "C" {
#define SPI_D_DQS_MODE_V 0x7
#define SPI_D_DQS_MODE_S 0
#define SPI_LCD_D_NUM_REG(i) (REG_SPI_BASE(i) + 0x10C)
#define SPI_LCD_D_NUM_REG(i) (REG_SPI_BASE(i) + 0x100)
/* SPI_D_VSYNC_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
/*description: the output spi_vsync is delayed by system clock cycles 0: delayed
by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
@ -2093,7 +2303,7 @@ extern "C" {
#define SPI_D_DQS_NUM_S 0
#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0x3FC)
/* SPI_DATE : RW ;bitpos:[27:0] ;default: 28'h1902200 ; */
/* SPI_DATE : RW ;bitpos:[27:0] ;default: 28'h1907240 ; */
/*description: SPI register version.*/
#define SPI_DATE 0x0FFFFFFF
#define SPI_DATE_M ((SPI_DATE_V)<<(SPI_DATE_S))

465
components/soc/esp32s2/include/soc/spi_struct.h
View file

@ -20,187 +20,196 @@ extern "C" {
typedef volatile struct {
union {
struct {
uint32_t conf_bitlen:23; /*Define the spi_clk cycles of SPI_CONF state.*/
uint32_t conf_bitlen:23; /*Define the spi_clk cycles of SPI_CONF state. Can be configured in CONF state.*/
uint32_t reserved23: 1; /*reserved*/
uint32_t usr: 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/
uint32_t reserved25: 7; /*reserved*/
};
uint32_t val;
} cmd;
uint32_t addr; /*[31:8]:address to slave [7:0]:Reserved.*/
uint32_t addr; /*[31:8]:address to slave [7:0]:Reserved. Can be configured in CONF state.*/
union {
struct {
uint32_t reserved0: 2; /*reserved*/
uint32_t ext_hold_en: 1; /*Set the bit to hold spi. The bit is combined with spi_usr_prep_hold spi_usr_cmd_hold spi_usr_addr_hold spi_usr_dummy_hold spi_usr_din_hold spi_usr_dout_hold and spi_usr_hold_pol.*/
uint32_t dummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/
uint32_t ext_hold_en: 1; /*Set the bit to hold spi. The bit is combined with spi_usr_prep_hold spi_usr_cmd_hold spi_usr_addr_hold spi_usr_dummy_hold spi_usr_din_hold spi_usr_dout_hold and spi_usr_hold_pol. Can be configured in CONF state.*/
uint32_t dummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.*/
uint32_t reserved4: 1; /*reserved*/
uint32_t faddr_dual: 1; /*Apply 2 signals during addr phase 1:enable 0: disable*/
uint32_t faddr_quad: 1; /*Apply 4 signals during addr phase 1:enable 0: disable*/
uint32_t faddr_oct: 1; /*Apply 8 signals during addr phase 1:enable 0: disable*/
uint32_t fcmd_dual: 1; /*Apply 2 signals during command phase 1:enable 0: disable*/
uint32_t fcmd_quad: 1; /*Apply 4 signals during command phase 1:enable 0: disable*/
uint32_t fcmd_oct: 1; /*Apply 8 signals during command phase 1:enable 0: disable*/
uint32_t faddr_dual: 1; /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t faddr_quad: 1; /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t faddr_oct: 1; /*Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t fcmd_dual: 1; /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t fcmd_quad: 1; /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t fcmd_oct: 1; /*Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t reserved11: 3; /*reserved*/
uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/
uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
uint32_t fread_oct: 1; /*In the read operations read-data phase apply 8 signals. 1: enable 0: disable.*/
uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t fread_oct: 1; /*In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t reserved17: 1; /*reserved*/
uint32_t q_pol: 1; /*The bit is used to set MISO line polarity 1: high 0 low*/
uint32_t d_pol: 1; /*The bit is used to set MOSI line polarity 1: high 0 low*/
uint32_t q_pol: 1; /*The bit is used to set MISO line polarity 1: high 0 low. Can be configured in CONF state.*/
uint32_t d_pol: 1; /*The bit is used to set MOSI line polarity 1: high 0 low. Can be configured in CONF state.*/
uint32_t reserved20: 1; /*reserved*/
uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/
uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low. Can be configured in CONF state.*/
uint32_t reserved22: 3; /*reserved*/
uint32_t rd_bit_order: 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first*/
uint32_t wr_bit_order: 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/
uint32_t rd_bit_order: 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/
uint32_t wr_bit_order: 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/
uint32_t reserved27: 5; /*reserved*/
};
uint32_t val;
} ctrl;
union {
struct {
uint32_t clk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
uint32_t clk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/
uint32_t clk_mode_13: 1; /*{CPOL CPHA} 1: support spi clk mode 1 and 3 first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2 first edge output data B[1]/B[6].*/
uint32_t rsck_data_out: 1; /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge*/
uint32_t w16_17_wr_ena: 1; /*1:reg_buf[16] [17] can be written 0:reg_buf[16] [17] can not be written.*/
uint32_t w16_17_wr_ena: 1; /*1:reg_buf[16] [17] can be written 0:reg_buf[16] [17] can not be written. Can be configured in CONF state.*/
uint32_t reserved5: 9; /*reserved*/
uint32_t cs_hold_delay: 6; /*SPI cs signal is delayed by spi clock cycles.*/
uint32_t cs_hold_delay: 6; /*SPI cs signal is delayed by spi clock cycles. Can be configured in CONF state.*/
uint32_t reserved20: 12; /*reserved*/
};
uint32_t val;
} ctrl1;
union {
struct {
uint32_t cs_setup_time:13; /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit.*/
uint32_t cs_hold_time: 13; /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.*/
uint32_t cs_delay_mode: 3; /*spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/
uint32_t cs_delay_num: 2; /*spi_cs signal is delayed by system clock cycles*/
uint32_t cs_setup_time:13; /*(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.*/
uint32_t cs_hold_time: 13; /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.*/
uint32_t cs_delay_mode: 3; /*spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle. Can be configured in CONF state.*/
uint32_t cs_delay_num: 2; /*spi_cs signal is delayed by system clock cycles. Can be configured in CONF state.*/
uint32_t reserved31: 1; /*reserved*/
};
uint32_t val;
} ctrl2;
union {
struct {
uint32_t clkcnt_l: 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0.*/
uint32_t clkcnt_h: 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0.*/
uint32_t clkcnt_n: 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/
uint32_t clkdiv_pre: 13; /*In the master mode it is pre-divider of spi_clk.*/
uint32_t clk_equ_sysclk: 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock.*/
uint32_t clkcnt_l: 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.*/
uint32_t clkcnt_h: 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/
uint32_t clkcnt_n: 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/
uint32_t clkdiv_pre: 13; /*In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.*/
uint32_t clk_equ_sysclk: 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/
};
uint32_t val;
} clock;
union {
struct {
uint32_t doutdin: 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable.*/
uint32_t tx_start_bit: 3; /*It determines the start time of tx output data. It can be used for timing adjustment in MISO slave mode.*/
uint32_t reserved4: 1; /*reserved*/
uint32_t doutdin: 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t reserved1: 2; /*reserved*/
uint32_t qpi_mode: 1; /*Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.*/
uint32_t opi_mode: 1; /*Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state.*/
uint32_t tsck_i_edge: 1; /*In the slave mode this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/
uint32_t cs_hold: 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable.*/
uint32_t cs_setup: 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/
uint32_t cs_hold: 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t cs_setup: 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t rsck_i_edge: 1; /*In the slave mode this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/
uint32_t ck_out_edge: 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/
uint32_t rd_byte_order: 1; /*In read-data (MISO) phase 1: big-endian 0: little_endian*/
uint32_t wr_byte_order: 1; /*In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/
uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals*/
uint32_t fwrite_quad: 1; /*In the write operations read-data phase apply 4 signals*/
uint32_t fwrite_oct: 1; /*In the write operations read-data phase apply 8 signals*/
uint32_t usr_conf_nxt: 1; /*1: Enable the DMA CONF phase of next seg-trans operation which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode.*/
uint32_t sio: 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable.*/
uint32_t usr_hold_pol: 1; /*It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/
uint32_t usr_dout_hold: 1; /*spi is hold at data out state the bit are combined with spi_usr_hold_pol bit.*/
uint32_t usr_din_hold: 1; /*spi is hold at data in state the bit are combined with spi_usr_hold_pol bit.*/
uint32_t usr_dummy_hold: 1; /*spi is hold at dummy state the bit are combined with spi_usr_hold_pol bit.*/
uint32_t usr_addr_hold: 1; /*spi is hold at address state the bit are combined with spi_usr_hold_pol bit.*/
uint32_t usr_cmd_hold: 1; /*spi is hold at command state the bit are combined with spi_usr_hold_pol bit.*/
uint32_t usr_prep_hold: 1; /*spi is hold at prepare state the bit are combined with spi_usr_hold_pol bit.*/
uint32_t usr_miso_highpart: 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/
uint32_t usr_mosi_highpart: 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/
uint32_t usr_dummy_idle: 1; /*spi clock is disable in dummy phase when the bit is enable.*/
uint32_t usr_mosi: 1; /*This bit enable the write-data phase of an operation.*/
uint32_t usr_miso: 1; /*This bit enable the read-data phase of an operation.*/
uint32_t usr_dummy: 1; /*This bit enable the dummy phase of an operation.*/
uint32_t usr_addr: 1; /*This bit enable the address phase of an operation.*/
uint32_t usr_command: 1; /*This bit enable the command phase of an operation.*/
uint32_t ck_out_edge: 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.*/
uint32_t rd_byte_order: 1; /*In read-data (MISO) phase 1: big-endian 0: little_endian. Can be configured in CONF state.*/
uint32_t wr_byte_order: 1; /*In command address write-data (MOSI) phases 1: big-endian 0: litte_endian. Can be configured in CONF state.*/
uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals. Can be configured in CONF state.*/
uint32_t fwrite_quad: 1; /*In the write operations read-data phase apply 4 signals. Can be configured in CONF state.*/
uint32_t fwrite_oct: 1; /*In the write operations read-data phase apply 8 signals. Can be configured in CONF state.*/
uint32_t usr_conf_nxt: 1; /*1: Enable the DMA CONF phase of next seg-trans operation which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/
uint32_t sio: 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t usr_hold_pol: 1; /*It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low. Can be configured in CONF state.*/
uint32_t usr_dout_hold: 1; /*spi is hold at data out state the bit are combined with spi_usr_hold_pol bit. Can be configured in CONF state.*/
uint32_t usr_din_hold: 1; /*spi is hold at data in state the bit are combined with spi_usr_hold_pol bit. Can be configured in CONF state.*/
uint32_t usr_dummy_hold: 1; /*spi is hold at dummy state the bit are combined with spi_usr_hold_pol bit. Can be configured in CONF state.*/
uint32_t usr_addr_hold: 1; /*spi is hold at address state the bit are combined with spi_usr_hold_pol bit. Can be configured in CONF state.*/
uint32_t usr_cmd_hold: 1; /*spi is hold at command state the bit are combined with spi_usr_hold_pol bit. Can be configured in CONF state.*/
uint32_t usr_prep_hold: 1; /*spi is hold at prepare state the bit are combined with spi_usr_hold_pol bit. Can be configured in CONF state.*/
uint32_t usr_miso_highpart: 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t usr_mosi_highpart: 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t usr_dummy_idle: 1; /*spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.*/
uint32_t usr_mosi: 1; /*This bit enable the write-data phase of an operation. Can be configured in CONF state.*/
uint32_t usr_miso: 1; /*This bit enable the read-data phase of an operation. Can be configured in CONF state.*/
uint32_t usr_dummy: 1; /*This bit enable the dummy phase of an operation. Can be configured in CONF state.*/
uint32_t usr_addr: 1; /*This bit enable the address phase of an operation. Can be configured in CONF state.*/
uint32_t usr_command: 1; /*This bit enable the command phase of an operation. Can be configured in CONF state.*/
};
uint32_t val;
} user;
union {
struct {
uint32_t usr_dummy_cyclelen: 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
uint32_t usr_dummy_cyclelen: 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.*/
uint32_t reserved8: 19; /*reserved*/
uint32_t usr_addr_bitlen: 5; /*The length in bits of address phase. The register value shall be (bit_num-1).*/
uint32_t usr_addr_bitlen: 5; /*The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
};
uint32_t val;
} user1;
union {
struct {
uint32_t usr_command_value: 16; /*The value of command.*/
uint32_t usr_command_value: 16; /*The value of command. Can be configured in CONF state.*/
uint32_t reserved16: 12; /*reserved*/
uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/
uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
};
uint32_t val;
} user2;
union {
struct {
uint32_t usr_mosi_bit_len:23; /*The length in bits of write-data. The register value shall be (bit_num-1).*/
uint32_t usr_mosi_bit_len:23; /*The length in bits of write-data. The register value shall be (bit_num-1). Can be configured in CONF state.*/
uint32_t reserved23: 9; /*reserved*/
};
uint32_t val;
} mosi_dlen;
union {
struct {
uint32_t usr_miso_bit_len:23; /*The length in bits of read-data. The register value shall be (bit_num-1).*/
uint32_t usr_miso_bit_len:23; /*The length in bits of read-data. The register value shall be (bit_num-1). Can be configured in CONF state.*/
uint32_t reserved23: 9; /*reserved*/
};
uint32_t val;
} miso_dlen;
uint32_t slv_wr_status; /*In the master mode this register are the higher 32bits in the 64 bits address condition.*/
union {
struct {
uint32_t cs0_dis: 1; /*SPI CS0 pin enable 1: disable CS0 0: spi_cs0 signal is from/to CS0 pin*/
uint32_t cs1_dis: 1; /*SPI CS1 pin enable 1: disable CS1 0: spi_cs1 signal is from/to CS1 pin*/
uint32_t cs2_dis: 1; /*SPI CS2 pin enable 1: disable CS2 0: spi_cs2 signal is from/to CS2 pin*/
uint32_t cs0_dis: 1; /*SPI CS0 pin enable 1: disable CS0 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.*/
uint32_t cs1_dis: 1; /*SPI CS1 pin enable 1: disable CS1 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.*/
uint32_t cs2_dis: 1; /*SPI CS2 pin enable 1: disable CS2 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.*/
uint32_t cs3_dis: 1; /*reserved*/
uint32_t cs4_dis: 1; /*SPI CS4 pin enable 1: disable CS4 0: spi_cs4 signal is from/to CS4 pin*/
uint32_t cs5_dis: 1; /*SPI CS5 pin enable 1: disable CS5 0: spi_cs5 signal is from/to CS5 pin*/
uint32_t ck_dis: 1; /*1: spi clk out disable 0: spi clk out enable*/
uint32_t master_cs_pol: 6; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol.*/
uint32_t reserved13: 7; /*reserved*/
uint32_t cd_data_set: 1; /*1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DOUT or SPI_DIN state. 0: spi_cd = spi_cd_idle_edge.*/
uint32_t cd_dummy_set: 1; /*1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DUMMY state. 0: spi_cd = spi_cd_idle_edge.*/
uint32_t cd_addr_set: 1; /*1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_SEND_ADDR state. 0: spi_cd = spi_cd_idle_edge.*/
uint32_t slave_cs_pol: 1; /*spi slave input cs polarity select. 1: inv 0: not change*/
uint32_t dqs_idle_edge: 1; /*The default value of spi_dqs.*/
uint32_t cd_cmd_set: 1; /*1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_SEND_CMD state. 0: spi_cd = spi_cd_idle_edge.*/
uint32_t cd_idle_edge: 1; /*The default value of spi_cd.*/
uint32_t cs4_dis: 1; /*SPI CS4 pin enable 1: disable CS4 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.*/
uint32_t cs5_dis: 1; /*SPI CS5 pin enable 1: disable CS5 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.*/
uint32_t ck_dis: 1; /*1: spi clk out disable 0: spi clk out enable. Can be configured in CONF state.*/
uint32_t master_cs_pol: 6; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/
uint32_t reserved13: 3; /*reserved*/
uint32_t clk_data_dtr_en: 1; /*1: SPI master DTR mode is applied to SPI clk data and spi_dqs*/
uint32_t data_dtr_en: 1; /*1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode including master 1/2/4/8-bm. Can be configured in CONF state.*/
uint32_t addr_dtr_en: 1; /*1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode including master 1/2/4/8-bm. Can be configured in CONF state.*/
uint32_t cmd_dtr_en: 1; /*1: SPI clk and data of SPI_SEND_CMD state are in DTR mode including master 1/2/4/8-bm. Can be configured in CONF state.*/
uint32_t cd_data_set: 1; /*1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DOUT or SPI_DIN state. 0: spi_cd = spi_cd_idle_edge. Can be configured in CONF state.*/
uint32_t cd_dummy_set: 1; /*1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DUMMY state. 0: spi_cd = spi_cd_idle_edge. Can be configured in CONF state.*/
uint32_t cd_addr_set: 1; /*1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_SEND_ADDR state. 0: spi_cd = spi_cd_idle_edge. Can be configured in CONF state.*/
uint32_t slave_cs_pol: 1; /*spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.*/
uint32_t dqs_idle_edge: 1; /*The default value of spi_dqs. Can be configured in CONF state.*/
uint32_t cd_cmd_set: 1; /*1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_SEND_CMD state. 0: spi_cd = spi_cd_idle_edge. Can be configured in CONF state.*/
uint32_t cd_idle_edge: 1; /*The default value of spi_cd. Can be configured in CONF state.*/
uint32_t reserved27: 2; /*reserved*/
uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/
uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set.*/
uint32_t quad_din_pin_swap: 1; /*1: spi quad input swap enable 0: spi quad input swap disable*/
uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.*/
uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/
uint32_t quad_din_pin_swap: 1; /*1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state.*/
};
uint32_t val;
} misc;
union {
struct {
uint32_t reserved0: 4; /*reserved*/
uint32_t trans_done: 1; /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.*/
uint32_t rd_buf_inten: 1; /*The interrupt enable bit for the completion of read-buffer operation in the slave mode.*/
uint32_t wr_buf_inten: 1; /*The interrupt enable bit for the completion of write-buffer operation in the slave mode.*/
uint32_t rd_dma_inten: 1; /*The interrupt enable bit for the completion of read-status operation in the slave mode.*/
uint32_t wr_dma_inten: 1; /*The interrupt enable bit for the completion of write-status operation in the slave mode.*/
uint32_t trans_inten: 1; /*The interrupt enable bit for the completion of any operation in both the master mode and the slave mode.*/
uint32_t reserved10:13; /*reserved*/
uint32_t trans_cnt: 4; /*The operations counter in both the master mode and the slave mode.*/
uint32_t reserved27: 1; /*reserved*/
uint32_t reserved28: 1; /*reserved*/
uint32_t reserved29: 1; /*reserved*/
uint32_t slave_mode: 1; /*Set SPI work mode. 1: slave mode 0: master mode.*/
uint32_t sync_reset: 1; /*Software reset enable reset the spi clock line cs line and data lines.*/
uint32_t reserved0: 4; /*reserved*/
uint32_t trans_done: 1; /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode. Can not be changed by CONF_buf.*/
uint32_t int_rd_buf_done_en: 1; /*spi_slv_rd_buf Interrupt enable. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t int_wr_buf_done_en: 1; /*spi_slv_wr_buf Interrupt enable. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t int_rd_dma_done_en: 1; /*spi_slv_rd_dma Interrupt enable. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t int_wr_dma_done_en: 1; /*spi_slv_wr_dma Interrupt enable. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t int_trans_done_en: 1; /*spi_trans_done Interrupt enable. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t int_dma_seg_trans_en: 1; /*spi_dma_seg_trans_done Interrupt enable. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t seg_magic_err_int_en: 1; /*1: Enable seg magic value error interrupt. 0: Others. Can be configured in CONF state.*/
uint32_t reserved12: 11; /*reserved*/
uint32_t trans_cnt: 4; /*The operations counter in both the master mode and the slave mode.*/
uint32_t reserved27: 1; /*reserved*/
uint32_t reserved28: 1; /*reserved*/
uint32_t trans_done_auto_clr_en: 1; /*spi_trans_done auto clear enable clear it 3 apb cycles after the pos edge of spi_trans_done. 0:disable. 1: enable. Can be configured in CONF state.*/
uint32_t slave_mode: 1; /*Set SPI work mode. 1: slave mode 0: master mode.*/
uint32_t soft_reset: 1; /*Software reset enable reset the spi clock line cs line and data lines. Can be configured in CONF state.*/
};
uint32_t val;
} slave;
union {
struct {
uint32_t reserved0: 13; /*reserved*/
uint32_t reserved0: 10; /*reserved*/
uint32_t addr_err_clr: 1; /*1: Clear spi_slv_addr_err. 0: not valid. Can be changed by CONF_buf.*/
uint32_t cmd_err_clr: 1; /*1: Clear spi_slv_cmd_err. 0: not valid. Can be changed by CONF_buf.*/
uint32_t no_qpi_en: 1; /*1: spi slave QPI mode is not supported. 0: spi slave QPI mode is supported.*/
uint32_t addr_err: 1; /*1: The address value of the last SPI transfer is not supported by SPI slave. 0: The address value is supported or no address value is received.*/
uint32_t cmd_err: 1; /*1: The command value of the last SPI transfer is not supported by SPI slave. 0: The command value is supported or no command value is received.*/
uint32_t wr_dma_done: 1; /*The interrupt raw bit for the completion of dma write operation in the slave mode. Can not be changed by CONF_buf.*/
@ -211,50 +220,50 @@ typedef volatile struct {
} slave1;
union {
struct {
uint32_t reserved0: 8;
uint32_t rd_dma_done: 1; /*The interrupt raw bit for the completion of Rd-DMA operation in the slave mode. Can not be changed by CONF_buf.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
} slave2;
union {
struct {
uint32_t bit_len: 24; /*In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1).*/
uint32_t wr_buf_done: 1; /*The interrupt raw bit for the completion of write-buffer operation in the slave mode.*/
uint32_t reserved25: 7; /*reserved*/
uint32_t reserved0: 24; /*reserved*/
uint32_t wr_buf_done: 1; /*The interrupt raw bit for the completion of write-buffer operation in the slave mode. Can not be changed by CONF_buf.*/
uint32_t conf_base_bitlen: 7; /*The basic spi_clk cycles of CONF state. The real cycle length of CONF state if spi_usr_conf is enabled is spi_conf_base_bitlen[6:0] + spi_conf_bitlen[23:0].*/
};
uint32_t val;
} slv_wrbuf_dlen;
union {
struct {
uint32_t bit_len: 24; /*In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1).*/
uint32_t rd_buf_done: 1; /*The interrupt raw bit for the completion of read-buffer operation in the slave mode.*/
uint32_t reserved25: 7; /*reserved*/
uint32_t dma_rd_bytelen: 20; /*In the slave mode it is the length in bytes for read operations. The register value shall be byte_num.*/
uint32_t reserved20: 4; /*reserved*/
uint32_t rd_buf_done: 1; /*The interrupt raw bit for the completion of read-buffer operation in the slave mode. Can not be changed by CONF_buf.*/
uint32_t seg_magic_err: 1; /*1: The recent magic value in CONF buffer is not right in master DMA seg-trans mode. 0: others.*/
uint32_t reserved26: 6; /*reserved*/
};
uint32_t val;
} slv_rdbuf_dlen;
union {
struct {
uint32_t slv_rdata_bit:24; /*In the slave mode it is the byte number of read data.*/
uint32_t reserved24: 8; /*reserved*/
uint32_t data_bytelen: 20; /*The full-duplex or half-duplex data byte length of the last SPI transfer in slave mode. In half-duplex mode this value is controlled by bits [23:20].*/
uint32_t rddma_bytelen_en: 1; /*1: spi_slv_data_bytelen stores data byte length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others*/
uint32_t wrdma_bytelen_en: 1; /*1: spi_slv_data_bytelen stores data byte length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others*/
uint32_t rdbuf_bytelen_en: 1; /*1: spi_slv_data_bytelen stores data byte length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others*/
uint32_t wrbuf_bytelen_en: 1; /*1: spi_slv_data_bytelen stores data byte length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others*/
uint32_t dma_seg_magic_value: 4; /*The magic value of BM table in master DMA seg-trans.*/
uint32_t reserved28: 2; /*reserved*/
uint32_t rd_dma_done: 1; /*The interrupt raw bit for the completion of Rd-DMA operation in the slave mode. Can not be changed by CONF_buf.*/
uint32_t usr_conf: 1; /*1: Enable the DMA CONF phase of current seg-trans operation which means seg-trans will start. 0: This is not seg-trans mode.*/
};
uint32_t val;
} slv_rd_byte;
uint32_t reserved_4c;
union {
struct {
uint32_t st: 4; /*The status of spi state machine. 0: idle state 1: preparation state 2: send command state 3: send data state 4: red data state 5:write data state 6: wait state 7: done state.*/
uint32_t reserved4: 8; /*reserved*/
uint32_t mst_dma_rd_bytelen:20; /*Define the master DMA read byte length in non seg-trans or seg-trans mode. Invalid when spi_rx_eof_en is 0.*/
uint32_t mst_dma_rd_bytelen:20; /*Define the master DMA read byte length in non seg-trans or seg-trans mode. Invalid when spi_rx_eof_en is 0. Can be configured in CONF state..*/
};
uint32_t val;
} fsm;
union {
struct {
uint32_t int_hold_ena: 2; /*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at idle phase 2: hold at prepare phase.*/
uint32_t hold_val: 1; /*spi hold output value which should be used with spi_hold_out_en.*/
uint32_t hold_out_en: 1; /*Enable set spi output hold value to spi_hold_reg. It can be used to hold spi state machine with spi_ext_hold_en and other usr hold signals.*/
uint32_t hold_out_time: 3; /*set the hold cycles of output spi_hold signal when spi_hold_out_en is enable.*/
uint32_t int_hold_ena: 2; /*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at idle phase 2: hold at prepare phase. Can be configured in CONF state.*/
uint32_t hold_val: 1; /*spi hold output value which should be used with spi_hold_out_en. Can be configured in CONF state.*/
uint32_t hold_out_en: 1; /*Enable set spi output hold value to spi_hold_reg. It can be used to hold spi state machine with spi_ext_hold_en and other usr hold signals. Can be configured in CONF state.*/
uint32_t hold_out_time: 3; /*set the hold cycles of output spi_hold signal when spi_hold_out_en is enable. Can be configured in CONF state.*/
uint32_t dma_seg_trans_done: 1; /*1: spi master DMA full-duplex/half-duplex seg-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-trans is not ended or not occurred. Can not be changed by CONF_buf.*/
uint32_t reserved8: 24; /*reserved*/
};
@ -285,10 +294,10 @@ typedef volatile struct {
uint32_t rx_eof_en: 1; /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/
uint32_t infifo_full_clr: 1; /*1:Clear spi_dma_infifo_full_vld. 0: Do not control it.*/
uint32_t outfifo_empty_clr: 1; /*1:Clear spi_dma_outfifo_empty_vld. 0: Do not control it.*/
uint32_t infifo_full_err: 1; /*1:spi_dma_infifo_full and spi_push_data_prep are valid which means that DMA Rx buffer is full but push is valid. 0: Others. Can not be changed by CONF_buf.*/
uint32_t outfifo_empty_err: 1; /*1:spi_dma_outfifo_empty and spi_pop_data_prep are valid which means that there is no data to pop but pop is valid. 0: Others. Can not be changed by CONF_buf.*/
uint32_t reserved24: 2; /*reserved*/
uint32_t ext_mem_bk_size: 2; /*Select the external memory block size.*/
uint32_t reserved28: 4; /*reserved*/
uint32_t dma_seg_trans_clr: 1; /*1: End slave seg-trans which acts as 0x05 command. 2 or more end seg-trans signals will induce error in DMA RX.*/
uint32_t reserved29: 3; /*reserved*/
};
uint32_t val;
} dma_conf;
@ -317,31 +326,45 @@ typedef volatile struct {
} dma_in_link;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The enable bit for lack of enough inlink descriptors.*/
uint32_t outlink_dscr_error: 1; /*The enable bit for outlink descriptor error.*/
uint32_t inlink_dscr_error: 1; /*The enable bit for inlink descriptor error.*/
uint32_t in_done: 1; /*The enable bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The enable bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The enable bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The enable bit for completing usage of a outlink descriptor .*/
uint32_t out_eof: 1; /*The enable bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The enable bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
uint32_t inlink_dscr_empty: 1; /*The enable bit for lack of enough inlink descriptors. Can be configured in CONF state.*/
uint32_t outlink_dscr_error: 1; /*The enable bit for outlink descriptor error. Can be configured in CONF state.*/
uint32_t inlink_dscr_error: 1; /*The enable bit for inlink descriptor error. Can be configured in CONF state.*/
uint32_t in_done: 1; /*The enable bit for completing usage of a inlink descriptor. Can be configured in CONF state.*/
uint32_t in_err_eof: 1; /*The enable bit for receiving error. Can be configured in CONF state.*/
uint32_t in_suc_eof: 1; /*The enable bit for completing receiving all the packets from host. Can be configured in CONF state.*/
uint32_t out_done: 1; /*The enable bit for completing usage of a outlink descriptor . Can be configured in CONF state.*/
uint32_t out_eof: 1; /*The enable bit for sending a packet to host done. Can be configured in CONF state.*/
uint32_t out_total_eof: 1; /*The enable bit for sending all the packets to host done. Can be configured in CONF state.*/
uint32_t infifo_full_err: 1; /*The enable bit for infifo full error interrupt.*/
uint32_t outfifo_empty_err: 1; /*The enable bit for outfifo empty error interrupt.*/
uint32_t cmd6: 1; /*The enable bit for SPI slave CMD6 interrupt.*/
uint32_t cmd7: 1; /*The enable bit for SPI slave CMD7 interrupt.*/
uint32_t cmd8: 1; /*The enable bit for SPI slave CMD8 interrupt.*/
uint32_t cmd9: 1; /*The enable bit for SPI slave CMD9 interrupt.*/
uint32_t cmda: 1; /*The enable bit for SPI slave CMDA interrupt.*/
uint32_t reserved16: 16; /*reserved*/
};
uint32_t val;
} dma_int_ena;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The raw bit for lack of enough inlink descriptors.*/
uint32_t outlink_dscr_error: 1; /*The raw bit for outlink descriptor error.*/
uint32_t inlink_dscr_error: 1; /*The raw bit for inlink descriptor error.*/
uint32_t in_done: 1; /*The raw bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The raw bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The raw bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The raw bit for completing usage of a outlink descriptor.*/
uint32_t out_eof: 1; /*The raw bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The raw bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
uint32_t inlink_dscr_empty: 1; /*The raw bit for lack of enough inlink descriptors. Can be configured in CONF state.*/
uint32_t outlink_dscr_error: 1; /*The raw bit for outlink descriptor error. Can be configured in CONF state.*/
uint32_t inlink_dscr_error: 1; /*The raw bit for inlink descriptor error. Can be configured in CONF state.*/
uint32_t in_done: 1; /*The raw bit for completing usage of a inlink descriptor. Can be configured in CONF state.*/
uint32_t in_err_eof: 1; /*The raw bit for receiving error. Can be configured in CONF state.*/
uint32_t in_suc_eof: 1; /*The raw bit for completing receiving all the packets from host. Can be configured in CONF state.*/
uint32_t out_done: 1; /*The raw bit for completing usage of a outlink descriptor. Can be configured in CONF state.*/
uint32_t out_eof: 1; /*The raw bit for sending a packet to host done. Can be configured in CONF state.*/
uint32_t out_total_eof: 1; /*The raw bit for sending all the packets to host done. Can be configured in CONF state.*/
uint32_t infifo_full_err: 1; /*1:spi_dma_infifo_full and spi_push_data_prep are valid which means that DMA Rx buffer is full but push is valid. 0: Others. Can not be changed by CONF_buf.*/
uint32_t outfifo_empty_err: 1; /*1:spi_dma_outfifo_empty and spi_pop_data_prep are valid which means that there is no data to pop but pop is valid. 0: Others. Can not be changed by CONF_buf.*/
uint32_t cmd6: 1; /*The raw bit for SPI slave CMD6 interrupt.*/
uint32_t cmd7: 1; /*The raw bit for SPI slave CMD7 interrupt.*/
uint32_t cmd8: 1; /*The raw bit for SPI slave CMD8 interrupt.*/
uint32_t cmd9: 1; /*The raw bit for SPI slave CMD9 interrupt.*/
uint32_t cmda: 1; /*The raw bit for SPI slave CMDA interrupt.*/
uint32_t reserved16: 16; /*reserved*/
};
uint32_t val;
} dma_int_raw;
@ -356,22 +379,36 @@ typedef volatile struct {
uint32_t out_done: 1; /*The status bit for completing usage of a outlink descriptor.*/
uint32_t out_eof: 1; /*The status bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The status bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
uint32_t infifo_full_err: 1; /*The status bit for infifo full error.*/
uint32_t outfifo_empty_err: 1; /*The status bit for outfifo empty error.*/
uint32_t cmd6: 1; /*The status bit for SPI slave CMD6 interrupt.*/
uint32_t cmd7: 1; /*The status bit for SPI slave CMD7 interrupt.*/
uint32_t cmd8: 1; /*The status bit for SPI slave CMD8 interrupt.*/
uint32_t cmd9: 1; /*The status bit for SPI slave CMD9 interrupt.*/
uint32_t cmda: 1; /*The status bit for SPI slave CMDA interrupt.*/
uint32_t reserved16: 16; /*reserved*/
};
uint32_t val;
} dma_int_st;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The clear bit for lack of enough inlink descriptors.*/
uint32_t outlink_dscr_error: 1; /*The clear bit for outlink descriptor error.*/
uint32_t inlink_dscr_error: 1; /*The clear bit for inlink descriptor error.*/
uint32_t in_done: 1; /*The clear bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The clear bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The clear bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The clear bit for completing usage of a outlink descriptor.*/
uint32_t out_eof: 1; /*The clear bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The clear bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
uint32_t inlink_dscr_empty: 1; /*The clear bit for lack of enough inlink descriptors. Can be configured in CONF state.*/
uint32_t outlink_dscr_error: 1; /*The clear bit for outlink descriptor error. Can be configured in CONF state.*/
uint32_t inlink_dscr_error: 1; /*The clear bit for inlink descriptor error. Can be configured in CONF state.*/
uint32_t in_done: 1; /*The clear bit for completing usage of a inlink descriptor. Can be configured in CONF state.*/
uint32_t in_err_eof: 1; /*The clear bit for receiving error. Can be configured in CONF state.*/
uint32_t in_suc_eof: 1; /*The clear bit for completing receiving all the packets from host. Can be configured in CONF state.*/
uint32_t out_done: 1; /*The clear bit for completing usage of a outlink descriptor. Can be configured in CONF state.*/
uint32_t out_eof: 1; /*The clear bit for sending a packet to host done. Can be configured in CONF state.*/
uint32_t out_total_eof: 1; /*The clear bit for sending all the packets to host done. Can be configured in CONF state.*/
uint32_t infifo_full_err: 1; /*1: Clear spi_dma_infifo_full_err. 0: not valid. Can be changed by CONF_buf.*/
uint32_t outfifo_empty_err: 1; /*1: Clear spi_dma_outfifo_empty_err signal. 0: not valid. Can be changed by CONF_buf.*/
uint32_t cmd6: 1; /*The clear bit for SPI slave CMD6 interrupt.*/
uint32_t cmd7: 1; /*The clear bit for SPI slave CMD7 interrupt.*/
uint32_t cmd8: 1; /*The clear bit for SPI slave CMD8 interrupt.*/
uint32_t cmd9: 1; /*The clear bit for SPI slave CMD9 interrupt.*/
uint32_t cmda: 1; /*The clear bit for SPI slave CMDA interrupt.*/
uint32_t reserved16: 16; /*reserved*/
};
uint32_t val;
} dma_int_clr;
@ -410,111 +447,116 @@ typedef volatile struct {
uint32_t data_buf[18]; /*data buffer*/
union {
struct {
uint32_t din0_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din1_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din2_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din3_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din4_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din5_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din6_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din7_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t timing_clk_ena: 1; /*1:enable hclk in spi_timing.v. 0: disable it.*/
uint32_t din0_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din1_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din2_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din3_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din4_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din5_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din6_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din7_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t timing_clk_ena: 1; /*1:enable hclk in spi_timing.v. 0: disable it. Can be configured in CONF state.*/
uint32_t reserved25: 7; /*reserved*/
};
uint32_t val;
} din_mode;
union {
struct {
uint32_t din0_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din1_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din2_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din3_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din4_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din5_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din6_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din7_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din0_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t din1_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t din2_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t din3_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t din4_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t din5_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t din6_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t din7_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t reserved16:16; /*reserved*/
};
uint32_t val;
} din_num;
union {
struct {
uint32_t dout0_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout1_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout2_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout3_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout4_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout5_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout6_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout7_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout0_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/
uint32_t dout1_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/
uint32_t dout2_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/
uint32_t dout3_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/
uint32_t dout4_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/
uint32_t dout5_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/
uint32_t dout6_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/
uint32_t dout7_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
} dout_mode;
union {
struct {
uint32_t dout0_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout1_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout2_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout3_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout4_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout5_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout6_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout7_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout0_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t dout1_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t dout2_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t dout3_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t dout4_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t dout5_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t dout6_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t dout7_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t reserved16:16; /*reserved*/
};
uint32_t val;
} dout_num;
union {
struct {
uint32_t lcd_hb_front: 11; /*It is the horizontal blank front porch of a frame.*/
uint32_t lcd_va_height: 10; /*It is the vertical active height of a frame.*/
uint32_t lcd_vt_height: 10; /*It is the vertical total height of a frame.*/
uint32_t lcd_srgb_mode_en: 1; /*1: Enable LCD mode output vsync hsync de. 0: Disable.*/
uint32_t lcd_hb_front: 11; /*It is the horizontal blank front porch of a frame. Can be configured in CONF state.*/
uint32_t lcd_va_height:10; /*It is the vertical active height of a frame. Can be configured in CONF state.*/
uint32_t lcd_vt_height:10; /*It is the vertical total height of a frame. Can be configured in CONF state.*/
uint32_t lcd_mode_en: 1; /*1: Enable LCD mode output vsync hsync de. 0: Disable. Can be configured in CONF state.*/
};
uint32_t val;
} lcd_ctrl;
union {
struct {
uint32_t lcd_vb_front: 8; /*It is the vertical blank front porch of a frame.*/
uint32_t lcd_ha_width:12; /*It is the horizontal active width of a frame.*/
uint32_t lcd_ht_width:12; /*It is the horizontal total width of a frame.*/
uint32_t lcd_vb_front: 8; /*It is the vertical blank front porch of a frame. Can be configured in CONF state.*/
uint32_t lcd_ha_width:12; /*It is the horizontal active width of a frame. Can be configured in CONF state.*/
uint32_t lcd_ht_width:12; /*It is the horizontal total width of a frame. Can be configured in CONF state.*/
};
uint32_t val;
} lcd_ctrl1;
union {
struct {
uint32_t lcd_vsync_width: 7; /*It is the position of spi_vsync_out active pulse in a line.*/
uint32_t vsync_idle_pol: 1; /*It is the idle value of spi_vsync_out.*/
uint32_t lcd_vsync_position: 8; /*It is the position of spi_vsync_out active pulse in a line.*/
uint32_t lcd_hsync_width: 7; /*It is the position of spi_hsync_out active pulse in a line.*/
uint32_t hsync_idle_pol: 1; /*It is the idle value of spi_hsync_out.*/
uint32_t lcd_hsync_position: 8; /*It is the position of spi_hsync_out active pulse in a line.*/
uint32_t lcd_vsync_width: 7; /*It is the position of spi_vsync active pulse in a line. Can be configured in CONF state.*/
uint32_t vsync_idle_pol: 1; /*It is the idle value of spi_vsync. Can be configured in CONF state.*/
uint32_t reserved8: 8; /*reserved*/
uint32_t lcd_hsync_width: 7; /*It is the position of spi_hsync active pulse in a line. Can be configured in CONF state.*/
uint32_t hsync_idle_pol: 1; /*It is the idle value of spi_hsync. Can be configured in CONF state.*/
uint32_t lcd_hsync_position: 8; /*It is the position of spi_hsync active pulse in a line. Can be configured in CONF state.*/
};
uint32_t val;
} lcd_ctrl2;
union {
struct {
uint32_t d_dqs_mode: 3; /*the output spi_dqs is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t d_cd_mode: 3; /*the output spi_cd is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t d_de_mode: 3; /*the output spi_de is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t d_hsync_mode: 3; /*the output spi_hsync is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t d_vsync_mode: 3; /*the output spi_vsync is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t reserved15: 17; /*reserved*/
uint32_t d_dqs_mode: 3; /*the output spi_dqs is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/
uint32_t d_cd_mode: 3; /*the output spi_cd is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/
uint32_t d_de_mode: 3; /*the output spi_de is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/
uint32_t d_hsync_mode: 3; /*the output spi_hsync is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/
uint32_t d_vsync_mode: 3; /*the output spi_vsync is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/
uint32_t de_idle_pol: 1; /*It is the idle value of spi_de.*/
uint32_t hs_blank_en: 1; /*1: The pulse of spi_hsync is out in vertical blanking lines in seg-trans or one trans. 0: spi_hsync pulse is valid only in active region lines in seg-trans.*/
uint32_t reserved17: 15; /*reserved*/
};
uint32_t val;
} lcd_d_mode;
union {
struct {
uint32_t d_dqs_num: 2; /*the output spi_dqs is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t d_cd_num: 2; /*the output spi_cd is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t d_de_num: 2; /*the output spi_de is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t d_hsync_num: 2; /*the output spi_hsync is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t d_vsync_num: 2; /*the output spi_vsync is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t d_dqs_num: 2; /*the output spi_dqs is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t d_cd_num: 2; /*the output spi_cd is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t d_de_num: 2; /*the output spi_de is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t d_hsync_num: 2; /*the output spi_hsync is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t d_vsync_num: 2; /*the output spi_vsync is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t reserved10: 22; /*reserved*/
};
uint32_t val;
} lcd_d_num;
uint32_t reserved_104;
uint32_t reserved_108;
uint32_t reserved_10c;
uint32_t reserved_110;
uint32_t reserved_114;
uint32_t reserved_118;
@ -713,7 +755,6 @@ typedef volatile struct {
extern spi_dev_t GPSPI2; //FSPI
extern spi_dev_t GPSPI3; //HSPI
_Static_assert(sizeof(spi_dev_t)==0x400, "***invalid spi");

7
components/soc/esp32s2/spi_periph.c
View file

@ -20,7 +20,7 @@
*/
const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
{
.spiclk_out = SPICLK_OUT_IDX,
.spiclk_out = SPICLK_OUT_MUX_IDX,
.spiclk_in = 0,/* SPI clock is not an input signal*/
.spid_out = SPID_OUT_IDX,
.spiq_out = SPIQ_OUT_IDX,
@ -39,13 +39,12 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
.spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
.spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
.irq = ETS_SPI1_INTR_SOURCE,
//TODO: SPI1 do not have DMA
/*.irq_dma = ETS_SPI1_DMA_INTR_SOURCE,*/
.irq_dma = -1,
.module = PERIPH_SPI_MODULE,
.hw = (spi_dev_t *) &SPIMEM1,
.func = SPI_FUNC_NUM,
}, {
.spiclk_out = FSPICLK_OUT_IDX,
.spiclk_out = FSPICLK_OUT_MUX_IDX,
.spiclk_in = FSPICLK_IN_IDX,
.spid_out = FSPID_OUT_IDX,
.spiq_out = FSPIQ_OUT_IDX,

1
components/soc/include/hal/spi_types.h
View file

@ -38,5 +38,4 @@ typedef enum {
#define SPI_HOST SPI1_HOST
#define FSPI_HOST SPI2_HOST
#define HSPI_HOST SPI3_HOST
#define VSPI_HOST SPI4_HOST
#endif

2
components/soc/include/soc/spi_periph.h
View file

@ -59,9 +59,7 @@ typedef struct {
const uint8_t spics_out[3]; // /CS GPIO output mux signals
const uint8_t spics_in;
const uint8_t spidqs_out;
const uint8_t spidqs_in;
const uint8_t spicd_out;
const uint8_t spicd_in;
const uint8_t spiclk_iomux_pin; //IO pins of IO_MUX muxed signals
const uint8_t spid_iomux_pin;
const uint8_t spiq_iomux_pin;

7
components/spi_flash/test/test_esp_flash.c
View file

@ -227,11 +227,8 @@ static void setup_bus(spi_host_device_t host_id)
static void release_bus(int host_id)
{
#if CONFIG_IDF_TARGET_ESP32
if (host_id == HSPI_HOST || host_id == VSPI_HOST) {
#elif CONFIG_IDF_TARGET_ESP32S2
if (host_id == FSPI_HOST || host_id == HSPI_HOST || host_id == VSPI_HOST) {
#endif
//SPI1 bus can't be deinitialized
if (host_id == SPI2_HOST || host_id == SPI3_HOST) {
spi_bus_free(host_id);
}
}