esp_flash: fix set qe bit and write command issues
There used to be dummy phase before out phase in common command transactions. This corrupts the data. The code before never actually operate (clear) the QE bit, once it finds the QE bit is set. It's hard to check whether the QE set/disable functions work well. This commit: 1. Cancel the dummy phase 2. Set and clear the QE bit according to chip settings, allowing tests for QE bits. However for some chips (Winbond for example), it's not forced to clear the QE bit if not able to. 3. Also refactor to allow chip_generic and other chips to share the same code to read and write qe bit; let common command and read command share configure_host_io_mode. 4. Rename read mode to io mode since maybe we will write data with quad mode one day.
This commit is contained in:
Michael (XIAO Xufeng)
parent
8fbece32a9
commit
571864e8ae
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@ -202,21 +202,6 @@ static inline bool spi_flash_ll_host_idle(const spi_dev_t *dev)
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return dev->ext2.st != 0;
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}
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/**
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* Set phases for user-defined transaction to read
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*
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* @param dev Beginning address of the peripheral registers.
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*/
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static inline void spi_flash_ll_read_phase(spi_dev_t *dev)
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{
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typeof (dev->user) user = {
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.usr_command = 1,
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.usr_mosi = 0,
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.usr_miso = 1,
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.usr_addr = 1,
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};
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dev->user = user;
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}
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/*------------------------------------------------------------------------------
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* Configs
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*----------------------------------------------------------------------------*/
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@ -239,7 +224,7 @@ static inline void spi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
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* @param dev Beginning address of the peripheral registers.
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* @param read_mode I/O mode to use in the following transactions.
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*/
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static inline void spi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_read_mode_t read_mode)
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static inline void spi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode)
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{
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typeof (dev->ctrl) ctrl = dev->ctrl;
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ctrl.val &= ~(SPI_FREAD_QIO_M | SPI_FREAD_QUAD_M | SPI_FREAD_DIO_M | SPI_FREAD_DUAL_M);
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@ -155,23 +155,38 @@ esp_err_t spi_flash_hal_set_write_protect(spi_flash_host_driver_t *chip_drv, boo
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bool spi_flash_hal_host_idle(spi_flash_host_driver_t *driver);
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/**
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* Configure the SPI host hardware registers for the specified read mode.
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* @brief Configure the SPI host hardware registers for the specified io mode.
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*
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* Note that calling this configures SPI host registers, so if running any
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* other commands as part of set_read_mode() then these must be run before
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* other commands as part of set_io_mode() then these must be run before
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* calling this function.
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*
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* The command value, address length and dummy cycles are configured according
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* to the format of read commands:
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*
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* - command: 8 bits, value set.
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* - address: 24 bits
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* - dummy: cycles to compensate the input delay
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* - out & in data: 0 bits.
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*
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* The following commands still need to:
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*
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* - Read data: set address value and data (length and contents), no need
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* to touch command and dummy phases.
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* - Common read: set command value, address value (or length to 0 if not used)
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* - Common write: set command value, address value (or length to 0 if not
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* used), disable dummy phase, and set output data.
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*
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* @param driver The driver context
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* @param read_mode The HW read mode to use
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* @param io_mode The HW read mode to use
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* @param addr_bitlen Length of the address phase, in bits
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* @param dummy_cyclelen_base Base cycles of the dummy phase, some extra dummy cycles may be appended to compensate the timing.
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* @param read_command Actual reading command to send to flash chip on the bus.
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* @param command Actual reading command to send to flash chip on the bus.
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*
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* @return always return ESP_OK.
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*/
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esp_err_t spi_flash_hal_configure_host_read_mode(spi_flash_host_driver_t *driver, esp_flash_read_mode_t read_mode,
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uint32_t addr_bitlen, uint32_t dummy_cyclelen_base,
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uint32_t read_command);
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esp_err_t spi_flash_hal_configure_host_io_mode(spi_flash_host_driver_t *driver, uint32_t command, uint32_t addr_bitlen,
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int dummy_cyclelen_base, esp_flash_io_mode_t io_mode);
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/**
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* Poll until the last operation is done.
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@ -61,7 +61,7 @@ typedef enum {
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SPI_FLASH_QIO, ///< Both address & data transferred using quad I/O
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SPI_FLASH_READ_MODE_MAX, ///< The fastest io mode supported by the host is ``ESP_FLASH_READ_MODE_MAX-1``.
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} esp_flash_read_mode_t;
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} esp_flash_io_mode_t;
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///Slowest io mode supported by ESP32, currently SlowRd
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#define SPI_FLASH_READ_MODE_MIN SPI_FLASH_SLOWRD
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@ -130,9 +130,11 @@ struct spi_flash_host_driver_t {
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*/
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bool (*host_idle)(spi_flash_host_driver_t *driver);
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/**
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* Configure the host to work at different read mode.
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* Configure the host to work at different read mode. Responsible to compensate the timing and set IO mode.
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*/
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esp_err_t (*configure_host_read_mode)(spi_flash_host_driver_t *driver, esp_flash_read_mode_t read_mode, uint32_t addr_bitlen, uint32_t dummy_bitlen_base, uint32_t read_command);
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esp_err_t (*configure_host_io_mode)(spi_flash_host_driver_t *driver, uint32_t command,
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uint32_t addr_bitlen, int dummy_bitlen_base,
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esp_flash_io_mode_t io_mode);
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/**
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* Internal use, poll the HW until the last operation is done.
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*/
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@ -67,8 +67,3 @@ esp_err_t spi_flash_hal_init(spi_flash_memspi_data_t *data_out, const spi_flash_
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ESP_EARLY_LOGD(TAG, "extra_dummy: %d", data_out->extra_dummy);
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return ESP_OK;
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}
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static inline spi_dev_t *get_spi_dev(spi_flash_host_driver_t *chip_drv)
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{
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return ((spi_flash_memspi_data_t *)chip_drv->driver_data)->spi;
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}
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@ -52,28 +52,37 @@ esp_err_t spi_flash_hal_device_config(spi_flash_host_driver_t *driver)
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return ESP_OK;
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}
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esp_err_t spi_flash_hal_configure_host_read_mode(spi_flash_host_driver_t *driver, esp_flash_read_mode_t read_mode,
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uint32_t addr_bitlen, uint32_t dummy_cyclelen_base,
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uint32_t read_command)
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esp_err_t spi_flash_hal_configure_host_io_mode(
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spi_flash_host_driver_t *host,
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uint32_t command,
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uint32_t addr_bitlen,
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int dummy_cyclelen_base,
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esp_flash_io_mode_t io_mode)
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{
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// Add dummy cycles to compensate for latency of GPIO matrix and external delay, if necessary...
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int dummy_cyclelen = dummy_cyclelen_base + ((spi_flash_memspi_data_t *)driver->driver_data)->extra_dummy;
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spi_dev_t *dev = get_spi_dev(driver);
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spi_flash_ll_set_command8(dev, command);
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spi_flash_ll_set_addr_bitlen(dev, addr_bitlen);
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spi_flash_ll_set_command8(dev, read_command);
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spi_flash_ll_read_phase(dev);
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spi_flash_ll_set_dummy(dev, dummy_cyclelen);
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spi_flash_ll_set_read_mode(dev, read_mode);
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//disable all data phases, enable them later if needed
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spi_flash_ll_set_miso_bitlen(dev, 0);
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spi_flash_ll_set_mosi_bitlen(dev, 0);
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spi_flash_ll_set_read_mode(dev, io_mode);
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return ESP_OK;
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}
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esp_err_t spi_flash_hal_common_command(spi_flash_host_driver_t *chip_drv, spi_flash_trans_t *trans)
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{
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chip_drv->configure_host_read_mode(chip_drv, SPI_FLASH_FASTRD, 0, 0, 0);
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host->configure_host_io_mode(host, trans->command, 0, 0, SPI_FLASH_FASTRD);
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spi_dev_t *dev = get_spi_dev(chip_drv);
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spi_flash_ll_set_command8(dev, trans->command);
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spi_flash_ll_set_addr_bitlen(dev, 0);
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//disable dummy if no input phase
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if (trans->miso_len == 0) {
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spi_flash_ll_set_dummy(dev, 0);
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}
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spi_flash_ll_set_miso_bitlen(dev, trans->miso_len);
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spi_flash_ll_set_mosi_bitlen(dev, trans->mosi_len);
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@ -122,7 +131,7 @@ void spi_flash_hal_program_page(spi_flash_host_driver_t *chip_drv, const void *b
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esp_err_t spi_flash_hal_read(spi_flash_host_driver_t *chip_drv, void *buffer, uint32_t address, uint32_t read_len)
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{
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spi_dev_t *dev = get_spi_dev(chip_drv);
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//the command is already set by ``spi_flash_hal_configure_host_read_mode`` before.
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//the command is already set by ``spi_flash_hal_configure_host_io_mode`` before.
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spi_flash_ll_set_address(dev, address << 8);
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spi_flash_ll_set_miso_bitlen(dev, read_len * 8);
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spi_flash_ll_user_start(dev);
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@ -3,25 +3,31 @@ if(BOOTLOADER_BUILD)
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# Bootloader needs SPIUnlock from this file, but doesn't
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# need other parts of this component
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set(srcs "spi_flash_rom_patch.c")
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set(cache_srcs "")
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else()
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set(srcs
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set(cache_srcs
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"cache_utils.c"
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"flash_mmap.c"
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"flash_ops.c"
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)
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set(srcs
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"partition.c"
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"spi_flash_rom_patch.c"
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)
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# New implementation
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list(APPEND cache_srcs
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"esp_flash_api.c"
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"esp_flash_spi_init.c"
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"spi_flash_os_func_app.c"
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"spi_flash_os_func_noos.c"
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)
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list(APPEND srcs
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"spi_flash_chip_drivers.c"
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"spi_flash_chip_generic.c"
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"spi_flash_chip_issi.c"
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"spi_flash_os_func_app.c"
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"spi_flash_os_func_noos.c"
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"memspi_host_driver.c"
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"esp_flash_api.c"
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"esp_flash_spi_init.c"
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)
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list(APPEND srcs ${cache_srcs})
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set(priv_requires bootloader_support app_update soc)
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endif()
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@ -30,3 +36,7 @@ idf_component_register(SRCS "${srcs}"
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INCLUDE_DIRS include
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PRIV_INCLUDE_DIRS private_include
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LDFRAGMENTS linker.lf)
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# Avoid cache miss by unexpected inlineing when built by -Os
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set_source_files_properties(${cache_srcs} PROPERTIES COMPILE_FLAGS
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"-fno-inline-functions -fno-inline-small-functions -fno-inline-functions-called-once")
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@ -60,7 +60,7 @@ static const char io_mode_str[][IO_STR_LEN] = {
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"qio",
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};
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_Static_assert(sizeof(io_mode_str)/IO_STR_LEN == SPI_FLASH_READ_MODE_MAX, "the io_mode_str should be consistent with the esp_flash_read_mode_t defined in spi_flash_ll.h");
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_Static_assert(sizeof(io_mode_str)/IO_STR_LEN == SPI_FLASH_READ_MODE_MAX, "the io_mode_str should be consistent with the esp_flash_io_mode_t defined in spi_flash_ll.h");
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/* Static function to notify OS of a new SPI flash operation.
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@ -139,38 +139,51 @@ esp_err_t IRAM_ATTR esp_flash_init(esp_flash_t *chip)
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if (err == ESP_OK) {
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// Try to set the flash mode to whatever default mode was chosen
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err = chip->chip_drv->set_read_mode(chip);
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err = chip->chip_drv->set_io_mode(chip);
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if (err == ESP_ERR_FLASH_NO_RESPONSE && !esp_flash_is_quad_mode(chip)) {
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//some chips (e.g. Winbond) don't support to clear QE, treat as success
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err = ESP_OK;
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}
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}
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// Done: all fields on 'chip' are initialised
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return spiflash_end(chip, err);
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}
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//this is not public, but useful in unit tests
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esp_err_t IRAM_ATTR esp_flash_read_chip_id(esp_flash_t* chip, uint32_t* flash_id)
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{
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esp_err_t err = spiflash_start(chip);
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if (err != ESP_OK) {
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return err;
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}
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// Send generic RDID command twice, check for a matching result and retry in case we just powered on (inner
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// function fails if it sees all-ones or all-zeroes.)
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err = chip->host->read_id(chip->host, flash_id);
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if (err == ESP_OK) { // check we see the same ID twice, in case of transient power-on errors
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uint32_t new_id;
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err = chip->host->read_id(chip->host, &new_id);
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if (err == ESP_OK && (new_id != *flash_id)) {
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err = ESP_ERR_FLASH_NOT_INITIALISED;
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}
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}
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return spiflash_end(chip, err);
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}
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static esp_err_t IRAM_ATTR detect_spi_flash_chip(esp_flash_t *chip)
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{
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esp_err_t err;
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uint32_t flash_id;
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int retries = 10;
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do {
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err = spiflash_start(chip);
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if (err != ESP_OK) {
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return err;
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}
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// Send generic RDID command twice, check for a matching result and retry in case we just powered on (inner
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// function fails if it sees all-ones or all-zeroes.)
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err = chip->host->read_id(chip->host, &flash_id);
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if (err == ESP_OK) { // check we see the same ID twice, in case of transient power-on errors
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uint32_t new_id;
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err = chip->host->read_id(chip->host, &new_id);
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if (err == ESP_OK && (new_id != flash_id)) {
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err = ESP_ERR_FLASH_NOT_INITIALISED;
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}
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}
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err = spiflash_end(chip, err);
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} while (err != ESP_OK && retries-- > 0);
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err = esp_flash_read_chip_id(chip, &flash_id);
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} while (err == ESP_ERR_FLASH_NOT_INITIALISED && retries-- > 0);
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if (err != ESP_OK) {
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return err;
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}
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// Detect the chip and set the chip_drv structure for it
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const spi_flash_chip_t **drivers = esp_flash_registered_chips;
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@ -617,6 +630,36 @@ esp_err_t IRAM_ATTR esp_flash_read_encrypted(esp_flash_t *chip, uint32_t address
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return spi_flash_read_encrypted(address, out_buffer, length);
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}
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// test only, non-public
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IRAM_ATTR esp_err_t esp_flash_get_io_mode(esp_flash_t* chip, bool* qe)
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{
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VERIFY_OP(get_io_mode);
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esp_flash_io_mode_t io_mode;
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esp_err_t err = spiflash_start(chip);
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if (err != ESP_OK) {
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return err;
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}
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err = chip->chip_drv->get_io_mode(chip, &io_mode);
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err = spiflash_end(chip, err);
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if (err == ESP_OK) {
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*qe = (io_mode == SPI_FLASH_QOUT);
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}
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return err;
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}
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IRAM_ATTR esp_err_t esp_flash_set_io_mode(esp_flash_t* chip, bool qe)
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{
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VERIFY_OP(set_io_mode);
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chip->read_mode = (qe? SPI_FLASH_QOUT: SPI_FLASH_SLOWRD);
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esp_err_t err = spiflash_start(chip);
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if (err != ESP_OK) {
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return err;
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}
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err = chip->chip_drv->set_io_mode(chip);
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return spiflash_end(chip, err);
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}
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#ifndef CONFIG_SPI_FLASH_USE_LEGACY_IMPL
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esp_err_t esp_flash_app_disable_protect(bool disable)
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{
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@ -62,7 +62,7 @@ __attribute__((unused)) static const char TAG[] = "spi_flash";
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esp_flash_t *esp_flash_default_chip = NULL;
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static IRAM_ATTR void cs_initialize(esp_flash_t *chip, const esp_flash_spi_device_config_t *config, bool use_iomux)
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static IRAM_ATTR NOINLINE_ATTR void cs_initialize(esp_flash_t *chip, const esp_flash_spi_device_config_t *config, bool use_iomux)
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{
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//Not using spicommon_cs_initialize since we don't want to put the whole
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//spi_periph_signal into the DRAM. Copy these data from flash before the
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@ -63,7 +63,7 @@ struct esp_flash_t {
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const esp_flash_os_functions_t *os_func; ///< Pointer to os-specific hook structure. Call ``esp_flash_init_os_functions()`` to setup this field, after the host is properly initialized.
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void *os_func_data; ///< Pointer to argument for os-specific hooks. Left NULL and will be initialized with ``os_func``.
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esp_flash_read_mode_t read_mode; ///< Configured SPI flash read mode. Set before ``esp_flash_init`` is called.
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esp_flash_io_mode_t read_mode; ///< Configured SPI flash read mode. Set before ``esp_flash_init`` is called.
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uint32_t size; ///< Size of SPI flash in bytes. If 0, size will be detected during initialisation.
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};
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@ -286,6 +286,22 @@ esp_err_t esp_flash_read_encrypted(esp_flash_t *chip, uint32_t address, void *ou
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extern esp_flash_t *esp_flash_default_chip;
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/*******************************************************************************
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* Utility Functions
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******************************************************************************/
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/**
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* @brief Returns true if chip is configured for Quad I/O or Quad Fast Read.
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*
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* @param chip Pointer to SPI flash chip to use. If NULL, esp_flash_default_chip is substituted.
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*
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* @return true if flash works in quad mode, otherwise false
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*/
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static inline bool esp_flash_is_quad_mode(const esp_flash_t *chip)
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{
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return (chip->read_mode == SPI_FLASH_QIO) || (chip->read_mode == SPI_FLASH_QOUT);
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}
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#ifdef __cplusplus
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}
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#endif
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ typedef struct {
|
|||
spi_host_device_t host_id; ///< Bus to use
|
||||
int cs_id; ///< CS pin (signal) to use
|
||||
int cs_io_num; ///< GPIO pin to output the CS signal
|
||||
esp_flash_read_mode_t io_mode; ///< IO mode to read from the Flash
|
||||
esp_flash_io_mode_t io_mode; ///< IO mode to read from the Flash
|
||||
esp_flash_speed_t speed; ///< Speed of the Flash clock
|
||||
int input_delay_ns; ///< Input delay of the data pins, in ns. Set to 0 if unknown.
|
||||
} esp_flash_spi_device_config_t;
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@
|
|||
.read = spi_flash_hal_read, \
|
||||
.max_read_bytes = SPI_FLASH_HAL_MAX_READ_BYTES, \
|
||||
.host_idle = spi_flash_hal_host_idle, \
|
||||
.configure_host_read_mode = spi_flash_hal_configure_host_read_mode, \
|
||||
.configure_host_io_mode = spi_flash_hal_configure_host_io_mode, \
|
||||
.poll_cmd_done = spi_flash_hal_poll_cmd_done, \
|
||||
.flush_cache = memspi_host_flush_cache, \
|
||||
}
|
||||
|
|
|
|||
|
|
@ -149,7 +149,13 @@ struct spi_flash_chip_t {
|
|||
*
|
||||
* Can return ESP_ERR_FLASH_UNSUPPORTED_HOST or ESP_ERR_FLASH_UNSUPPORTED_CHIP if the specified mode is unsupported.
|
||||
*/
|
||||
esp_err_t (*set_read_mode)(esp_flash_t *chip);
|
||||
esp_err_t (*set_io_mode)(esp_flash_t *chip);
|
||||
|
||||
/*
|
||||
* Get whether the Quad Enable (QE) is set. (*out_io_mode)=SPI_FLASH_QOUT if
|
||||
* enabled, otherwise disabled
|
||||
*/
|
||||
esp_err_t (*get_io_mode)(esp_flash_t *chip, esp_flash_io_mode_t* out_io_mode);
|
||||
};
|
||||
|
||||
/* Pointer to an array of pointers to all known drivers for flash chips. This array is used
|
||||
|
|
|
|||
|
|
@ -213,7 +213,21 @@ esp_err_t spi_flash_chip_generic_wait_idle(esp_flash_t *chip, uint32_t timeout_m
|
|||
* - ESP_ERR_TIMEOUT if not idle before timeout
|
||||
* - or other error passed from the ``set_write_protect`` or ``common_command`` function of host driver
|
||||
*/
|
||||
esp_err_t spi_flash_chip_generic_set_read_mode(esp_flash_t *chip);
|
||||
esp_err_t spi_flash_chip_generic_set_io_mode(esp_flash_t *chip);
|
||||
|
||||
/**
|
||||
* Get whether the Quad Enable (QE) is set.
|
||||
*
|
||||
* @param chip Pointer to SPI flash chip to use. If NULL, esp_flash_default_chip is substituted.
|
||||
* @param out_quad_mode Pointer to store the output mode.
|
||||
* - SPI_FLASH_QOUT: QE is enabled
|
||||
* - otherwise: QE is disabled
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK if success
|
||||
* - or other error passed from the ``common_command`` function of host driver
|
||||
*/
|
||||
esp_err_t spi_flash_chip_generic_get_io_mode(esp_flash_t *chip, esp_flash_io_mode_t* out_quad_mode);
|
||||
|
||||
/**
|
||||
* Generic SPI flash chip_drv, uses all the above functions for its operations.
|
||||
|
|
@ -244,6 +258,78 @@ extern const spi_flash_chip_t esp_flash_chip_generic;
|
|||
*/
|
||||
esp_err_t spi_flash_generic_wait_host_idle(esp_flash_t *chip, uint32_t *timeout_ms);
|
||||
|
||||
/// Function pointer type for reading status register with QE bit.
|
||||
typedef esp_err_t (*esp_flash_rdsr_func_t)(esp_flash_t* chip, uint32_t* out_sr);
|
||||
|
||||
/**
|
||||
* Use RDSR2 (35H) to read bit 15-8 of the SR, and RDSR (05H) to read bit 7-0.
|
||||
*
|
||||
* @param chip Pointer to SPI flash chip to use.
|
||||
* @param out_sr Pointer to buffer to hold the status register, 16 bits.
|
||||
*
|
||||
* @return ESP_OK if success, otherwise error code passed from the
|
||||
* `common_command` function of the host driver.
|
||||
*/
|
||||
esp_err_t spi_flash_common_read_status_16b_rdsr_rdsr2(esp_flash_t* chip, uint32_t* out_sr);
|
||||
|
||||
/**
|
||||
* Use RDSR2 (35H) to read bit 15-8 of the SR.
|
||||
*
|
||||
* @param chip Pointer to SPI flash chip to use.
|
||||
* @param out_sr Pointer to buffer to hold the status register, 8 bits.
|
||||
*
|
||||
* @return ESP_OK if success, otherwise error code passed from the
|
||||
* `common_command` function of the host driver.
|
||||
*/
|
||||
esp_err_t spi_flash_common_read_status_8b_rdsr2(esp_flash_t* chip, uint32_t* out_sr);
|
||||
|
||||
/**
|
||||
* Use RDSR (05H) to read bit 7-0 of the SR.
|
||||
*
|
||||
* @param chip Pointer to SPI flash chip to use.
|
||||
* @param out_sr Pointer to buffer to hold the status register, 8 bits.
|
||||
*
|
||||
* @return ESP_OK if success, otherwise error code passed from the
|
||||
* `common_command` function of the host driver.
|
||||
*/
|
||||
esp_err_t spi_flash_common_read_status_8b_rdsr(esp_flash_t* chip, uint32_t* out_sr);
|
||||
|
||||
/// Function pointer type for writing status register with QE bit.
|
||||
typedef esp_err_t (*esp_flash_wrsr_func_t)(esp_flash_t* chip, uint32_t sr);
|
||||
|
||||
/**
|
||||
* Use WRSR (01H) to write bit 7-0 of the SR.
|
||||
*
|
||||
* @param chip Pointer to SPI flash chip to use.
|
||||
* @param sr Value of the status register to write, 8 bits.
|
||||
*
|
||||
* @return ESP_OK if success, otherwise error code passed from the
|
||||
* `common_command` function of the host driver.
|
||||
*/
|
||||
esp_err_t spi_flash_common_write_status_8b_wrsr(esp_flash_t* chip, uint32_t sr);
|
||||
|
||||
/**
|
||||
* Use WRSR (01H) to write bit 15-0 of the SR.
|
||||
*
|
||||
* @param chip Pointer to SPI flash chip to use.
|
||||
* @param sr Value of the status register to write, 16 bits.
|
||||
*
|
||||
* @return ESP_OK if success, otherwise error code passed from the
|
||||
* `common_command` function of the host driver.
|
||||
*/
|
||||
esp_err_t spi_flash_common_write_status_16b_wrsr(esp_flash_t* chip, uint32_t sr);
|
||||
|
||||
/**
|
||||
* Use WRSR2 (31H) to write bit 15-8 of the SR.
|
||||
*
|
||||
* @param chip Pointer to SPI flash chip to use.
|
||||
* @param sr Value of the status register to write, 8 bits.
|
||||
*
|
||||
* @return ESP_OK if success, otherwise error code passed from the
|
||||
* `common_command` function of the host driver.
|
||||
*/
|
||||
esp_err_t spi_flash_common_write_status_8b_wrsr2(esp_flash_t* chip, uint32_t sr);
|
||||
|
||||
/**
|
||||
* @brief Utility function for set_read_mode chip_drv function. If required,
|
||||
* set and check the QE bit in the flash chip to enable the QIO/QOUT mode.
|
||||
|
|
@ -253,16 +339,19 @@ esp_err_t spi_flash_generic_wait_host_idle(esp_flash_t *chip, uint32_t *timeout_
|
|||
*
|
||||
* Registers to actually do Quad transtions and command to be sent in reading
|
||||
* should also be configured via
|
||||
* spi_flash_chip_generic_config_host_read_mode().
|
||||
* spi_flash_chip_generic_config_host_io_mode().
|
||||
*
|
||||
* @param qe_rdsr_command SPI flash command to read status register
|
||||
* @param qe_wrsr_command SPI flash command to write status register
|
||||
* @param qe_sr_bitwidth Width of the status register these commands operate on, in bits.
|
||||
* @param qe_sr_bit Bit mask for enabling Quad Enable functions on this chip.
|
||||
* Note that the bit length and qe position of wrsr_func, rdsr_func and
|
||||
* qe_sr_bit should be consistent.
|
||||
*
|
||||
* @param chip Pointer to SPI flash chip to use.
|
||||
* @param wrsr_func Function pointer for writing the status register
|
||||
* @param rdsr_func Function pointer for reading the status register
|
||||
* @param qe_sr_bit status with the qe bit only.
|
||||
*
|
||||
* @return always ESP_OK (currently).
|
||||
*/
|
||||
esp_err_t spi_flash_common_set_read_mode(esp_flash_t *chip, uint8_t qe_rdsr_command, uint8_t qe_wrsr_command, uint8_t qe_sr_bitwidth, unsigned qe_sr_bit);
|
||||
esp_err_t spi_flash_common_set_io_mode(esp_flash_t *chip, esp_flash_wrsr_func_t wrsr_func, esp_flash_rdsr_func_t rdsr_func, uint32_t qe_sr_bit);
|
||||
|
||||
/**
|
||||
* @brief Configure the host registers to use the specified read mode set in
|
||||
|
|
@ -278,17 +367,4 @@ esp_err_t spi_flash_common_set_read_mode(esp_flash_t *chip, uint8_t qe_rdsr_comm
|
|||
* - ESP_ERR_FLASH_NOT_INITIALISED if chip not initialized properly
|
||||
* - or other error passed from the ``configure_host_mode`` function of host driver
|
||||
*/
|
||||
esp_err_t spi_flash_chip_generic_config_host_read_mode(esp_flash_t *chip);
|
||||
|
||||
/**
|
||||
* @brief Returns true if chip is configured for Quad I/O or Quad Fast Read.
|
||||
*
|
||||
* @param chip Pointer to SPI flash chip to use. If NULL, esp_flash_default_chip is substituted.
|
||||
*
|
||||
* @return true if flash works in quad mode, otherwise false
|
||||
*/
|
||||
static inline bool spi_flash_is_quad_mode(const esp_flash_t *chip)
|
||||
{
|
||||
return (chip->read_mode == SPI_FLASH_QIO) || (chip->read_mode == SPI_FLASH_QOUT);
|
||||
}
|
||||
|
||||
esp_err_t spi_flash_chip_generic_config_host_io_mode(esp_flash_t *chip);
|
||||
|
|
|
|||
|
|
@ -144,7 +144,7 @@ esp_err_t spi_flash_chip_generic_read(esp_flash_t *chip, void *buffer, uint32_t
|
|||
{
|
||||
esp_err_t err = ESP_OK;
|
||||
// Configure the host, and return
|
||||
spi_flash_chip_generic_config_host_read_mode(chip);
|
||||
spi_flash_chip_generic_config_host_io_mode(chip);
|
||||
|
||||
while (err == ESP_OK && length > 0) {
|
||||
uint32_t read_len = MIN(length, chip->host->max_read_bytes);
|
||||
|
|
@ -277,7 +277,7 @@ esp_err_t spi_flash_chip_generic_wait_idle(esp_flash_t *chip, uint32_t timeout_m
|
|||
return (timeout_ms > 0) ? ESP_OK : ESP_ERR_TIMEOUT;
|
||||
}
|
||||
|
||||
esp_err_t spi_flash_chip_generic_config_host_read_mode(esp_flash_t *chip)
|
||||
esp_err_t spi_flash_chip_generic_config_host_io_mode(esp_flash_t *chip)
|
||||
{
|
||||
uint32_t dummy_cyclelen_base;
|
||||
uint32_t addr_bitlen;
|
||||
|
|
@ -320,62 +320,33 @@ esp_err_t spi_flash_chip_generic_config_host_read_mode(esp_flash_t *chip)
|
|||
return ESP_ERR_FLASH_NOT_INITIALISED;
|
||||
}
|
||||
|
||||
return chip->host->configure_host_read_mode(chip->host, chip->read_mode, addr_bitlen, dummy_cyclelen_base, read_command);
|
||||
return chip->host->configure_host_io_mode(chip->host, read_command, addr_bitlen, dummy_cyclelen_base,
|
||||
chip->read_mode);
|
||||
}
|
||||
|
||||
esp_err_t spi_flash_common_set_read_mode(esp_flash_t *chip, uint8_t qe_rdsr_command, uint8_t qe_wrsr_command, uint8_t qe_sr_bitwidth, unsigned qe_sr_bit)
|
||||
{
|
||||
if (spi_flash_is_quad_mode(chip)) {
|
||||
// Ensure quad modes are enabled, using the Quad Enable parameters supplied.
|
||||
spi_flash_trans_t t = {
|
||||
.command = qe_rdsr_command,
|
||||
.mosi_data = 0,
|
||||
.mosi_len = 0,
|
||||
.miso_len = qe_sr_bitwidth,
|
||||
};
|
||||
chip->host->common_command(chip->host, &t);
|
||||
unsigned sr = t.miso_data[0];
|
||||
ESP_EARLY_LOGV(TAG, "set_read_mode: status before 0x%x", sr);
|
||||
if ((sr & qe_sr_bit) == 0) {
|
||||
//some chips needs the write protect to be disabled before writing to Status Register
|
||||
chip->chip_drv->set_chip_write_protect(chip, false);
|
||||
|
||||
sr |= qe_sr_bit;
|
||||
spi_flash_trans_t t = {
|
||||
.command = qe_wrsr_command,
|
||||
.mosi_data = sr,
|
||||
.mosi_len = qe_sr_bitwidth,
|
||||
.miso_len = 0,
|
||||
};
|
||||
chip->host->common_command(chip->host, &t);
|
||||
|
||||
/* Check the new QE bit has stayed set */
|
||||
spi_flash_trans_t t_rdsr = {
|
||||
.command = qe_rdsr_command,
|
||||
.mosi_data = 0,
|
||||
.mosi_len = 0,
|
||||
.miso_len = qe_sr_bitwidth
|
||||
};
|
||||
chip->host->common_command(chip->host, &t_rdsr);
|
||||
sr = t_rdsr.miso_data[0];
|
||||
ESP_EARLY_LOGV(TAG, "set_read_mode: status after 0x%x", sr);
|
||||
if ((sr & qe_sr_bit) == 0) {
|
||||
return ESP_ERR_FLASH_NO_RESPONSE;
|
||||
}
|
||||
|
||||
chip->chip_drv->set_chip_write_protect(chip, true);
|
||||
}
|
||||
}
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t spi_flash_chip_generic_set_read_mode(esp_flash_t *chip)
|
||||
esp_err_t spi_flash_chip_generic_get_io_mode(esp_flash_t *chip, esp_flash_io_mode_t* out_io_mode)
|
||||
{
|
||||
// On "generic" chips, this involves checking
|
||||
// bit 1 (QE) of RDSR2 (35h) result
|
||||
// (it works this way on GigaDevice & Fudan Micro chips, probably others...)
|
||||
const uint8_t BIT_QE = 1 << 1;
|
||||
return spi_flash_common_set_read_mode(chip, CMD_RDSR2, CMD_WRSR2, 8, BIT_QE);
|
||||
uint32_t sr;
|
||||
esp_err_t ret = spi_flash_common_read_status_8b_rdsr2(chip, &sr);
|
||||
if (ret == ESP_OK) {
|
||||
*out_io_mode = ((sr & BIT_QE)? SPI_FLASH_QOUT: 0);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
esp_err_t spi_flash_chip_generic_set_io_mode(esp_flash_t *chip)
|
||||
{
|
||||
// On "generic" chips, this involves checking
|
||||
// bit 9 (QE) of RDSR (05h) result
|
||||
const uint32_t BIT_QE = 1 << 9;
|
||||
return spi_flash_common_set_io_mode(chip,
|
||||
spi_flash_common_write_status_16b_wrsr,
|
||||
spi_flash_common_read_status_16b_rdsr_rdsr2,
|
||||
BIT_QE);
|
||||
}
|
||||
|
||||
static const char chip_name[] = "generic";
|
||||
|
|
@ -409,5 +380,134 @@ const spi_flash_chip_t esp_flash_chip_generic = {
|
|||
.write_encrypted = spi_flash_chip_generic_write_encrypted,
|
||||
|
||||
.wait_idle = spi_flash_chip_generic_wait_idle,
|
||||
.set_read_mode = spi_flash_chip_generic_set_read_mode,
|
||||
.set_io_mode = spi_flash_chip_generic_set_io_mode,
|
||||
.get_io_mode = spi_flash_chip_generic_get_io_mode,
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Utility functions
|
||||
******************************************************************************/
|
||||
|
||||
static esp_err_t spi_flash_common_read_qe_sr(esp_flash_t *chip, uint8_t qe_rdsr_command, uint8_t qe_sr_bitwidth, uint32_t *sr)
|
||||
{
|
||||
spi_flash_trans_t t = {
|
||||
.command = qe_rdsr_command,
|
||||
.mosi_data = 0,
|
||||
.mosi_len = 0,
|
||||
.miso_len = qe_sr_bitwidth,
|
||||
};
|
||||
esp_err_t ret = chip->host->common_command(chip->host, &t);
|
||||
*sr = t.miso_data[0];
|
||||
return ret;
|
||||
}
|
||||
|
||||
static esp_err_t spi_flash_common_write_qe_sr(esp_flash_t *chip, uint8_t qe_wrsr_command, uint8_t qe_sr_bitwidth, uint32_t qe)
|
||||
{
|
||||
spi_flash_trans_t t = {
|
||||
.command = qe_wrsr_command,
|
||||
.mosi_data = qe,
|
||||
.mosi_len = qe_sr_bitwidth,
|
||||
.miso_len = 0,
|
||||
};
|
||||
return chip->host->common_command(chip->host, &t);
|
||||
}
|
||||
|
||||
esp_err_t spi_flash_common_read_status_16b_rdsr_rdsr2(esp_flash_t* chip, uint32_t* out_sr)
|
||||
{
|
||||
uint32_t sr, sr2;
|
||||
esp_err_t ret = spi_flash_common_read_qe_sr(chip, CMD_RDSR2, 8, &sr2);
|
||||
if (ret == ESP_OK) {
|
||||
ret = spi_flash_common_read_qe_sr(chip, CMD_RDSR, 8, &sr);
|
||||
}
|
||||
if (ret == ESP_OK) {
|
||||
*out_sr = (sr & 0xff) | ((sr2 & 0xff) << 8);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
esp_err_t spi_flash_common_read_status_8b_rdsr2(esp_flash_t* chip, uint32_t* out_sr)
|
||||
{
|
||||
return spi_flash_common_read_qe_sr(chip, CMD_RDSR2, 8, out_sr);
|
||||
}
|
||||
|
||||
esp_err_t spi_flash_common_read_status_8b_rdsr(esp_flash_t* chip, uint32_t* out_sr)
|
||||
{
|
||||
return spi_flash_common_read_qe_sr(chip, CMD_RDSR, 8, out_sr);
|
||||
}
|
||||
|
||||
esp_err_t spi_flash_common_write_status_16b_wrsr(esp_flash_t* chip, uint32_t sr)
|
||||
{
|
||||
return spi_flash_common_write_qe_sr(chip, CMD_WRSR, 16, sr);
|
||||
}
|
||||
|
||||
esp_err_t spi_flash_common_write_status_8b_wrsr(esp_flash_t* chip, uint32_t sr)
|
||||
{
|
||||
return spi_flash_common_write_qe_sr(chip, CMD_WRSR, 8, sr);
|
||||
}
|
||||
|
||||
esp_err_t spi_flash_common_write_status_8b_wrsr2(esp_flash_t* chip, uint32_t sr)
|
||||
{
|
||||
return spi_flash_common_write_qe_sr(chip, CMD_WRSR2, 8, sr);
|
||||
}
|
||||
|
||||
esp_err_t spi_flash_common_set_io_mode(esp_flash_t *chip, esp_flash_wrsr_func_t wrsr_func, esp_flash_rdsr_func_t rdsr_func, uint32_t qe_sr_bit)
|
||||
{
|
||||
esp_err_t ret = ESP_OK;
|
||||
const bool is_quad_mode = esp_flash_is_quad_mode(chip);
|
||||
bool update_config = false;
|
||||
const bool force_check = true; //in case some chips doesn't support erase QE
|
||||
|
||||
bool need_check = is_quad_mode;
|
||||
if (force_check) {
|
||||
need_check = true;
|
||||
}
|
||||
|
||||
uint32_t sr_update;
|
||||
if (need_check) {
|
||||
// Ensure quad modes are enabled, using the Quad Enable parameters supplied.
|
||||
uint32_t sr;
|
||||
ret = (*rdsr_func)(chip, &sr);
|
||||
if (ret != ESP_OK) {
|
||||
return ret;
|
||||
}
|
||||
ESP_EARLY_LOGD(TAG, "set_io_mode: status before 0x%x", sr);
|
||||
if (is_quad_mode) {
|
||||
sr_update = sr | qe_sr_bit;
|
||||
} else {
|
||||
sr_update = sr & (~qe_sr_bit);
|
||||
}
|
||||
ESP_EARLY_LOGV(TAG, "set_io_mode: status update 0x%x", sr_update);
|
||||
if (sr != sr_update) {
|
||||
update_config = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (update_config) {
|
||||
//some chips needs the write protect to be disabled before writing to Status Register
|
||||
chip->chip_drv->set_chip_write_protect(chip, false);
|
||||
|
||||
ret = (*wrsr_func)(chip, sr_update);
|
||||
if (ret != ESP_OK) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = chip->chip_drv->wait_idle(chip, DEFAULT_IDLE_TIMEOUT);
|
||||
if (ret != ESP_OK) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Check the new QE bit has stayed set */
|
||||
uint32_t sr;
|
||||
ret = (*rdsr_func)(chip, &sr);
|
||||
if (ret != ESP_OK) {
|
||||
return ret;
|
||||
}
|
||||
ESP_EARLY_LOGD(TAG, "set_io_mode: status after 0x%x", sr);
|
||||
if (sr != sr_update) {
|
||||
ret = ESP_ERR_FLASH_NO_RESPONSE;
|
||||
}
|
||||
|
||||
chip->chip_drv->set_chip_write_protect(chip, true);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -35,13 +35,29 @@ esp_err_t spi_flash_chip_issi_probe(esp_flash_t *chip, uint32_t flash_id)
|
|||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t spi_flash_chip_issi_set_read_mode(esp_flash_t *chip)
|
||||
esp_err_t spi_flash_chip_issi_set_io_mode(esp_flash_t *chip)
|
||||
{
|
||||
/* ISSI uses bit 6 of "basic" SR as Quad Enable */
|
||||
const uint8_t BIT_QE = 1 << 6;
|
||||
return spi_flash_common_set_read_mode(chip, CMD_RDSR, CMD_WRSR, 8, BIT_QE);
|
||||
return spi_flash_common_set_io_mode(chip,
|
||||
spi_flash_common_write_status_8b_wrsr,
|
||||
spi_flash_common_read_status_8b_rdsr,
|
||||
BIT_QE);
|
||||
}
|
||||
|
||||
esp_err_t spi_flash_chip_issi_get_io_mode(esp_flash_t *chip, esp_flash_io_mode_t* out_io_mode)
|
||||
{
|
||||
/* ISSI uses bit 6 of "basic" SR as Quad Enable */
|
||||
const uint8_t BIT_QE = 1 << 6;
|
||||
uint32_t sr;
|
||||
esp_err_t ret = spi_flash_common_read_status_8b_rdsr(chip, &sr);
|
||||
if (ret == ESP_OK) {
|
||||
*out_io_mode = ((sr & BIT_QE)? SPI_FLASH_QOUT: 0);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static const char chip_name[] = "issi";
|
||||
|
||||
// The issi chip can use the functions for generic chips except from set read mode and probe,
|
||||
|
|
@ -73,5 +89,6 @@ const spi_flash_chip_t esp_flash_chip_issi = {
|
|||
.write_encrypted = spi_flash_chip_generic_write_encrypted,
|
||||
|
||||
.wait_idle = spi_flash_chip_generic_wait_idle,
|
||||
.set_read_mode = spi_flash_chip_issi_set_read_mode,
|
||||
.set_io_mode = spi_flash_chip_issi_set_io_mode,
|
||||
.get_io_mode = spi_flash_chip_issi_get_io_mode,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -127,7 +127,7 @@ static void release_bus(int host_id)
|
|||
}
|
||||
}
|
||||
|
||||
static void setup_new_chip(esp_flash_read_mode_t io_mode, esp_flash_speed_t speed)
|
||||
static void setup_new_chip(esp_flash_io_mode_t io_mode, esp_flash_speed_t speed)
|
||||
{
|
||||
//the bus should be initialized before the flash is attached to the bus
|
||||
setup_bus(TEST_HOST);
|
||||
|
|
|
|||
Loading…
Reference in a new issue