Darian Leung
b097dd0a79
Add Task Watchdog backtrace printing
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This commit makes the Task Watchdog print the backtrace of both
cores when it times out.
2020-04-27 18:11:29 +00:00
Felipe Neves
429712c6eb
freertos: moved all xtensa specific files into a separated folder
2020-01-27 16:05:30 -03:00
Anton Maklakov
afbaf74007
tools: Mass fixing of empty prototypes (for -Wstrict-prototypes)
2019-08-01 16:28:56 +07:00
Konstantin Kondrashov
399d2d2605
all: Using xxx_periph.h
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Using xxx_periph.h in whole IDF instead of xxx_reg.h, xxx_struct.h, xxx_channel.h ... .
Cleaned up header files from unnecessary headers (releated to soc/... headers).
2019-06-03 14:15:08 +08:00
Sachin Parekh
f3db0b5a4a
crosscore_init: port*_CRITICAL vanilla FreeRTOS compliance
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Signed-off-by: Sachin Parekh <sachin.parekh@espressif.com>
2019-05-13 16:39:19 +05:30
morris
f5b03c9ea3
misc adjustment of esp32 component
2019-04-03 19:57:46 +08:00
morris
c159984264
separate rom from esp32 component to esp_rom
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1. separate rom include files and linkscript to esp_rom
2. modefiy "include rom/xxx.h" to "include esp32/rom/xxx.h"
3. Forward compatible
4. update mqtt
2019-03-21 18:51:45 +08:00
Angus Gratton
f6442abdeb
esp32: Move esp_crosscore_isr_handle_yield() to IRAM
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Also adds a hint to inline, as this is only called in one place
it seems like a natural candidate...
Closes https://github.com/espressif/esp-idf/issues/2055
2018-06-13 11:36:15 +10:00
Ivan Grokhotkov
f65870566a
crosscore_int: use _ISR version of portENTER/EXIT_CRITICAL in ISR
2018-04-19 18:28:55 +05:30
Ivan Grokhotkov
566f018996
crosscore_int: add support for FREQ_SWITCH event
2017-10-18 12:31:38 +08:00
Tian Hao
26a3cb93c7
component/soc : move dport access header files to soc
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1. move dport access header files to soc
2. reduce dport register write protection. Only protect read operation
2017-05-09 18:06:00 +08:00
Tian Hao
f7e8856520
component/esp32 : fix dualcore bug
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1. When dual core cpu run access DPORT register, must do protection.
2. If access DPORT register, must use DPORT_REG_READ/DPORT_REG_WRITE and DPORT_XXX register operation macro.
2017-05-08 21:53:43 +08:00
Angus Gratton
b6a2329f0f
FreeRTOS: esp_crosscore_int_send_yield() should be in IRAM
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Possible for xQueueGenericSendFromISR -> xTaskRemoveFromEventQueueList
-> taskYIELD_OTHER_CORE code path to occur while cache is off.
2017-01-26 18:53:02 +11:00
Ivan Grokhotkov
a2e0c2432e
esp32: sanity check ISR handler address passed into esp_intr_alloc
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Return ESP_ERR_INVALID_ARG if the handler is not in IRAM (or RTC fast memory)
2017-01-11 11:38:17 +08:00
Ivan Grokhotkov
833102cbf3
esp32: place cross-core interrupt handler into IRAM
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esp_intr_alloc is called with ESP_INTR_FLAG_IRAM, so the ISR should be in IRAM.
2017-01-11 00:52:45 +08:00
Jeroen Domburg
655fd2986a
Add interrupt allocation scheme / interrupt sharing. Also modifies drivers and examples. Also allows interrupts
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to be marked specifically as having a handler that's all in IRAM.
2016-12-08 12:39:33 +08:00
Jeroen Domburg
86d8f63005
Per-CPU interrupt handlers and args
2016-11-10 17:59:46 +08:00
Jeroen Domburg
90b787636a
Remove redundant volatile keyword
2016-10-31 11:00:27 +08:00
Jeroen Domburg
68f39c1ed9
Only init crosscore when FreeRTOS runs in multicore mode, add warnings that cross_int calls are private.
2016-10-27 16:50:28 +08:00
Jeroen Domburg
3371083c16
Add checks for tasks woken up on other CPUs where needed, make xYieldPending and xPendingReadyList per-processor, add configurable ISR stack size to Kconfig, in general fix the entire wake-up-task-on-other-cpu-by-interrupt implementation
2016-10-27 16:07:47 +08:00
Jeroen Domburg
c6477ff10d
Fix int clear, actually call int init code
2016-10-27 12:37:19 +08:00
Jeroen Domburg
d3d9a8bc28
Most code written. Interrupts still do not fire yet.
2016-10-26 21:09:55 +08:00
