26a3cb93c7
1. move dport access header files to soc 2. reduce dport register write protection. Only protect read operation
99 lines
3.2 KiB
C
99 lines
3.2 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdint.h>
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#include <string.h>
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_intr.h"
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#include "esp_intr_alloc.h"
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#include "rom/ets_sys.h"
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#include "rom/uart.h"
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#include "soc/cpu.h"
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#include "soc/dport_reg.h"
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#include "soc/io_mux_reg.h"
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#include "soc/rtc_cntl_reg.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "freertos/queue.h"
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#include "freertos/portmacro.h"
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#define REASON_YIELD (1<<0)
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static portMUX_TYPE reasonSpinlock = portMUX_INITIALIZER_UNLOCKED;
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static volatile uint32_t reason[ portNUM_PROCESSORS ];
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/*
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ToDo: There is a small chance the CPU already has yielded when this ISR is serviced. In that case, it's running the intended task but
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the ISR will cause it to switch _away_ from it. portYIELD_FROM_ISR will probably just schedule the task again, but have to check that.
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*/
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static void IRAM_ATTR esp_crosscore_isr(void *arg) {
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uint32_t myReasonVal;
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//A pointer to the correct reason array item is passed to this ISR.
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volatile uint32_t *myReason=arg;
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//Clear the interrupt first.
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if (xPortGetCoreID()==0) {
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DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
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} else {
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DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, 0);
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}
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//Grab the reason and clear it.
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portENTER_CRITICAL(&reasonSpinlock);
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myReasonVal=*myReason;
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*myReason=0;
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portEXIT_CRITICAL(&reasonSpinlock);
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//Check what we need to do.
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if (myReasonVal&REASON_YIELD) {
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portYIELD_FROM_ISR();
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}
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}
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//Initialize the crosscore interrupt on this core. Call this once
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//on each active core.
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void esp_crosscore_int_init() {
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portENTER_CRITICAL(&reasonSpinlock);
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reason[xPortGetCoreID()]=0;
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portEXIT_CRITICAL(&reasonSpinlock);
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esp_err_t err;
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if (xPortGetCoreID()==0) {
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err = esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[xPortGetCoreID()], NULL);
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} else {
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err = esp_intr_alloc(ETS_FROM_CPU_INTR1_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[xPortGetCoreID()], NULL);
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}
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assert(err == ESP_OK);
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}
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void IRAM_ATTR esp_crosscore_int_send_yield(int coreId) {
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assert(coreId<portNUM_PROCESSORS);
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//Mark the reason we interrupt the other CPU
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portENTER_CRITICAL(&reasonSpinlock);
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reason[coreId]|=REASON_YIELD;
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portEXIT_CRITICAL(&reasonSpinlock);
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//Poke the other CPU.
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if (coreId==0) {
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DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
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} else {
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DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, DPORT_CPU_INTR_FROM_CPU_1);
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}
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}
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