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misc adjustment of esp32 component

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This commit is contained in:
morris 2019-03-26 16:30:43 +08:00 committed by suda-morris
parent 30e3e26834
commit f5b03c9ea3
62 changed files with 146 additions and 302 deletions
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5
components/bootloader/subproject/main/esp32.bootloader.rom.ld
View file

@ -2,3 +2,8 @@ PROVIDE ( ets_update_cpu_frequency = 0x40008550 ); /* Updates g_ticks_per_us on
PROVIDE ( MD5Final = 0x4005db1c );
PROVIDE ( MD5Init = 0x4005da7c );
PROVIDE ( MD5Update = 0x4005da9c );
/* bootloader will use following functions from xtensa hal library */
xthal_get_ccount = 0x4000c050;
xthal_get_ccompare = 0x4000c078;
xthal_set_ccompare = 0x4000c058;

2
components/bt/bt.c
View file

@ -30,7 +30,7 @@
#include "esp_types.h"
#include "esp_system.h"
#include "esp_task.h"
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp_attr.h"
#include "esp_phy_init.h"
#include "esp_bt.h"

2
components/driver/gpio.c
View file

@ -13,7 +13,7 @@
// limitations under the License.
#include <esp_types.h>
#include "esp_err.h"
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp_intr_alloc.h"
#include "freertos/FreeRTOS.h"
#include "freertos/xtensa_api.h"

2
components/driver/i2c.c
View file

@ -15,7 +15,7 @@
#include <stdio.h>
#include "esp_types.h"
#include "esp_attr.h"
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp_log.h"
#include "malloc.h"
#include "freertos/FreeRTOS.h"

2
components/driver/i2s.c
View file

@ -33,7 +33,7 @@
#include "driver/dac.h"
#include "adc1_i2s_private.h"
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp_err.h"
#include "esp_log.h"
#include "esp_pm.h"

2
components/driver/include/driver/can.h
View file

@ -21,7 +21,7 @@ extern "C" {
#include "freertos/FreeRTOS.h"
#include "esp_types.h"
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp_err.h"
#include "gpio.h"

2
components/driver/include/driver/mcpwm.h
View file

@ -19,7 +19,7 @@
#include "soc/soc.h"
#include "driver/gpio.h"
#include "driver/periph_ctrl.h"
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp_intr_alloc.h"
#ifdef __cplusplus

2
components/driver/include/driver/pcnt.h
View file

@ -2,7 +2,7 @@
#define __PCNT_H__
#include <esp_types.h>
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp_err.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"

2
components/driver/include/driver/touch_pad.h
View file

@ -17,7 +17,7 @@
#ifdef __cplusplus
extern "C" {
#endif
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp_err.h"
#include "esp_intr_alloc.h"
#include "soc/touch_channel.h"

2
components/driver/ledc.c
View file

@ -13,7 +13,7 @@
// limitations under the License.
#include <esp_types.h>
#include <string.h>
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp_intr_alloc.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"

2
components/driver/mcpwm.c
View file

@ -15,7 +15,7 @@
#include <stdio.h>
#include "esp_log.h"
#include "esp_err.h"
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp_intr_alloc.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"

2
components/driver/periph_ctrl.c
View file

@ -12,7 +12,7 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#include <esp_types.h>
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
#include "freertos/xtensa_api.h"

2
components/driver/rmt.c
View file

@ -18,7 +18,7 @@
#include "freertos/semphr.h"
#include "freertos/xtensa_api.h"
#include "freertos/ringbuf.h"
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp_log.h"
#include "esp_err.h"
#include "esp_intr_alloc.h"

2
components/driver/spi_common.c
View file

@ -20,7 +20,7 @@
#include "esp32/rom/ets_sys.h"
#include "esp_types.h"
#include "esp_attr.h"
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp_intr_alloc.h"
#include "esp_log.h"
#include "esp_err.h"

2
components/driver/spi_master.c
View file

@ -126,7 +126,7 @@ We have two bits to control the interrupt:
#include "esp32/rom/ets_sys.h"
#include "esp_types.h"
#include "esp_attr.h"
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp_intr_alloc.h"
#include "esp_log.h"
#include "esp_err.h"

2
components/driver/spi_slave.c
View file

@ -20,7 +20,7 @@
#include "esp32/rom/ets_sys.h"
#include "esp_types.h"
#include "esp_attr.h"
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp_intr_alloc.h"
#include "esp_log.h"
#include "esp_err.h"

2
components/driver/timer.c
View file

@ -14,7 +14,7 @@
#include <string.h>
#include "esp_log.h"
#include "esp_err.h"
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp_intr_alloc.h"
#include "freertos/FreeRTOS.h"
#include "freertos/xtensa_api.h"

2
components/driver/uart.c
View file

@ -14,7 +14,7 @@
#include <string.h>
#include "esp_types.h"
#include "esp_attr.h"
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp_intr_alloc.h"
#include "esp_log.h"
#include "esp_err.h"

3
components/esp32/CMakeLists.txt
View file

@ -20,12 +20,10 @@ else()
"esp_adapter.c"
"esp_timer_esp32.c"
"esp_himem.c"
"freertos_hooks.c"
"gdbstub.c"
"hw_random.c"
"int_wdt.c"
"intr_alloc.c"
"ipc.c"
"panic.c"
"pm_esp32.c"
"pm_trace.c"
@ -70,7 +68,6 @@ else()
target_linker_script(${COMPONENT_TARGET} "ld/esp32.peripherals.ld")
target_link_libraries(${COMPONENT_TARGET} "${CMAKE_CURRENT_SOURCE_DIR}/libhal.a")
target_link_libraries(${COMPONENT_TARGET} gcc)
target_link_libraries(${COMPONENT_TARGET} "-u call_user_start_cpu0")

2
components/esp32/cache_err_int.c
View file

@ -25,7 +25,7 @@
#include <stdbool.h>
#include "freertos/FreeRTOS.h"
#include "esp_err.h"
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp_attr.h"
#include "soc/dport_reg.h"
#include "sdkconfig.h"

3
components/esp32/component.mk
View file

@ -17,8 +17,7 @@ LINKER_SCRIPTS += $(COMPONENT_BUILD_DIR)/esp32.project.ld esp32.peripherals.ld
#ld_include_panic_highint_hdl is added as an undefined symbol because otherwise the
#linker will ignore panic_highint_hdl.S as it has no other files depending on any
#symbols in it.
COMPONENT_ADD_LDFLAGS += $(COMPONENT_PATH)/libhal.a \
-L $(COMPONENT_PATH)/ld \
COMPONENT_ADD_LDFLAGS += -L $(COMPONENT_PATH)/ld \
-T esp32_out.ld \
-u ld_include_panic_highint_hdl \
$(addprefix -T ,$(LINKER_SCRIPTS)) \

2
components/esp32/cpu_start.c
View file

@ -60,7 +60,7 @@
#include "esp_phy_init.h"
#include "esp32/cache_err_int.h"
#include "esp_coexist_internal.h"
#include "esp_panic.h"
#include "esp_debug_helpers.h"
#include "esp_core_dump.h"
#include "esp_app_trace.h"
#include "esp_private/dbg_stubs.h"

2
components/esp32/crosscore_int.c
View file

@ -16,7 +16,7 @@
#include "esp_attr.h"
#include "esp_err.h"
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp_intr_alloc.h"
#include "esp32/rom/ets_sys.h"

2
components/esp32/dport_access.c
View file

@ -25,7 +25,7 @@
#include <sdkconfig.h>
#include "esp_attr.h"
#include "esp_err.h"
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/uart.h"

8
components/esp32/dport_panic_highint_hdl.S
View file

@ -17,7 +17,7 @@
#include <xtensa/corebits.h>
#include <xtensa/config/system.h>
#include "freertos/xtensa_context.h"
#include "esp_panic.h"
#include "esp_private/panic_reason.h"
#include "sdkconfig.h"
#include "soc/soc.h"
#include "soc/dport_reg.h"
@ -137,8 +137,8 @@ xt_highint4:
/* This section is for dport access register protection */
/* Allocate exception frame and save minimal context. */
/* Because the interrupt cause code has protection that only
allows one cpu to enter in the dport section of the L4
interrupt at one time, there's no need to have two
allows one cpu to enter in the dport section of the L4
interrupt at one time, there's no need to have two
_l4_intr_stack for each cpu */
/* This int is edge-triggered and needs clearing. */
@ -192,7 +192,7 @@ xt_highint4:
#endif // CONFIG_FREERTOS_UNICORE
/* The linker has no reason to link in this file; all symbols it exports are already defined
(weakly!) in the default int handler. Define a symbol here so we can use it to have the
(weakly!) in the default int handler. Define a symbol here so we can use it to have the
linker inspect this anyway. */
.global ld_include_panic_highint_hdl

2
components/esp32/esp_adapter.c
View file

@ -29,7 +29,7 @@
#include "esp_types.h"
#include "esp_system.h"
#include "esp_task.h"
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp_attr.h"
#include "esp_log.h"
#include "esp_heap_caps.h"

2
components/esp32/gdbstub.c
View file

@ -23,7 +23,7 @@
#include "soc/uart_reg.h"
#include "soc/io_mux_reg.h"
#include "esp_private/gdbstub.h"
#include "esp_panic.h"
#include "esp_debug_helpers.h"
#include "driver/gpio.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"

94
components/esp32/include/esp_deep_sleep.h
View file

@ -1,94 +0,0 @@
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
/**
* @file esp_deep_sleep.h
* @brief legacy definitions of esp_deep_sleep APIs
*
* This file provides compatibility for applications using esp_deep_sleep_* APIs.
* New applications should use functions defined in "esp_sleep.h" instead.
* These functions and types will be deprecated at some point.
*/
#warning esp_deep_sleep.h will be deprecated in the next release. Use esp_sleep.h instead.
#include "esp_sleep.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef esp_sleep_pd_domain_t esp_deep_sleep_pd_domain_t;
typedef esp_sleep_pd_option_t esp_deep_sleep_pd_option_t;
typedef esp_sleep_ext1_wakeup_mode_t esp_ext1_wakeup_mode_t;
typedef esp_sleep_wakeup_cause_t esp_deep_sleep_wakeup_cause_t;
inline static esp_err_t esp_deep_sleep_enable_ulp_wakeup(void)
{
return esp_sleep_enable_ulp_wakeup();
}
inline static esp_err_t esp_deep_sleep_enable_timer_wakeup(uint64_t time_in_us)
{
return esp_sleep_enable_timer_wakeup(time_in_us);
}
inline static esp_err_t esp_deep_sleep_enable_touchpad_wakeup(void)
{
return esp_sleep_enable_touchpad_wakeup();
}
inline static touch_pad_t esp_deep_sleep_get_touchpad_wakeup_status()
{
return esp_sleep_get_touchpad_wakeup_status();
}
inline static esp_err_t esp_deep_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level)
{
return esp_sleep_enable_ext0_wakeup(gpio_num, level);
}
inline static esp_err_t esp_deep_sleep_enable_ext1_wakeup(uint64_t mask, esp_ext1_wakeup_mode_t mode)
{
return esp_sleep_enable_ext1_wakeup(mask, mode);
}
inline static esp_err_t esp_deep_sleep_pd_config(
esp_deep_sleep_pd_domain_t domain,
esp_deep_sleep_pd_option_t option)
{
return esp_sleep_pd_config(domain, option);
}
inline static esp_deep_sleep_wakeup_cause_t esp_deep_sleep_get_wakeup_cause()
{
return esp_sleep_get_wakeup_cause();
}
#define ESP_DEEP_SLEEP_WAKEUP_UNDEFINED ESP_SLEEP_WAKEUP_UNDEFINED
#define ESP_DEEP_SLEEP_WAKEUP_EXT0 ESP_SLEEP_WAKEUP_EXT0
#define ESP_DEEP_SLEEP_WAKEUP_EXT1 ESP_SLEEP_WAKEUP_EXT1
#define ESP_DEEP_SLEEP_WAKEUP_TIMER ESP_SLEEP_WAKEUP_TIMER
#define ESP_DEEP_SLEEP_WAKEUP_TOUCHPAD ESP_SLEEP_WAKEUP_TOUCHPAD
#define ESP_DEEP_SLEEP_WAKEUP_ULP ESP_SLEEP_WAKEUP_ULP
#ifdef __cplusplus
}
#endif

2
components/esp32/include/esp_deepsleep.h
View file

@ -1,2 +0,0 @@
#warning esp_deepsleep.h has been renamed to esp_sleep.h, please update include directives
#include "esp_sleep.h"

78
components/esp32/include/esp_intr.h
View file

@ -12,78 +12,6 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_INTR_H__
#define __ESP_INTR_H__
#include "esp32/rom/ets_sys.h"
#include "freertos/xtensa_api.h"
#ifdef __cplusplus
extern "C" {
#endif
#define ESP_CCOMPARE_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_CCOMPARE_INUM, (func), (void *)(arg))
#define ESP_EPWM_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_EPWM_INUM, (func), (void *)(arg))
#define ESP_MPWM_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_MPWM_INUM, (func), (void *)(arg))
#define ESP_SPI1_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_SPI1_INUM, (func), (void *)(arg))
#define ESP_SPI2_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_SPI2_INUM, (func), (void *)(arg))
#define ESP_SPI3_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_SPI3_INUM, (func), (void *)(arg))
#define ESP_I2S0_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_I2S0_INUM, (func), (void *)(arg))
#define ESP_PCNT_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_PCNT_INUM, (func), (void *)(arg))
#define ESP_LEDC_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_LEDC_INUM, (func), (void *)(arg))
#define ESP_WMAC_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_WMAC_INUM, (func), (void *)(arg))
#define ESP_FRC_TIMER1_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_FRC_TIMER1_INUM, (func), (void *)(arg))
#define ESP_FRC_TIMER2_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_FRC_TIMER2_INUM, (func), (void *)(arg))
#define ESP_GPIO_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_GPIO_INUM, (func), (void *)(arg))
#define ESP_UART0_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_UART0_INUM, (func), (void *)(arg))
#define ESP_WDT_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_WDT_INUM, (func), (void *)(arg))
#define ESP_RTC_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_RTC_INUM, (func), (void *)(arg))
#define ESP_SLC_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_SLC_INUM, (func), (void *)(arg))
#define ESP_RMT_CTRL_INTRL(func,arg)\
xt_set_interrupt_handler(ETS_RMT_CTRL_INUM, (func), (void *)(arg))
#define ESP_INTR_ENABLE(inum) \
xt_ints_on((1<<inum))
#define ESP_INTR_DISABLE(inum) \
xt_ints_off((1<<inum))
#ifdef __cplusplus
}
#endif
#endif /* __ESP_INTR_H__ */
#pragma once
#warning esp_intr.h is deprecated, please include esp_intr_alloc.h instead
#include "esp_intr_alloc.h"

34
components/esp32/include/esp_intr_alloc.h
View file

@ -18,6 +18,7 @@
#include <stdint.h>
#include <stdbool.h>
#include "esp_err.h"
#include "freertos/xtensa_api.h"
#ifdef __cplusplus
extern "C" {
@ -80,7 +81,10 @@ extern "C" {
// This is used to provide SystemView with positive IRQ IDs, otherwise sheduler events are not shown properly
#define ETS_INTERNAL_INTR_SOURCE_OFF (-ETS_INTERNAL_PROFILING_INTR_SOURCE)
typedef void (*intr_handler_t)(void *arg);
#define ESP_INTR_ENABLE(inum) xt_ints_on((1<<inum))
#define ESP_INTR_DISABLE(inum) xt_ints_off((1<<inum))
typedef void (*intr_handler_t)(void *arg);
typedef struct intr_handle_data_t intr_handle_data_t;
@ -88,7 +92,7 @@ typedef intr_handle_data_t* intr_handle_t ;
/**
* @brief Mark an interrupt as a shared interrupt
*
*
* This will mark a certain interrupt on the specified CPU as
* an interrupt that can be used to hook shared interrupt handlers
* to.
@ -105,7 +109,7 @@ esp_err_t esp_intr_mark_shared(int intno, int cpu, bool is_in_iram);
/**
* @brief Reserve an interrupt to be used outside of this framework
*
*
* This will mark a certain interrupt on the specified CPU as
* reserved, not to be allocated for any reason.
*
@ -137,7 +141,7 @@ esp_err_t esp_intr_reserve(int intno, int cpu);
* choice of interrupts that this routine can choose from. If this value
* is 0, it will default to allocating a non-shared interrupt of level
* 1, 2 or 3. If this is ESP_INTR_FLAG_SHARED, it will allocate a shared
* interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return
* interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return
* from this function with the interrupt disabled.
* @param handler The interrupt handler. Must be NULL when an interrupt of level >3
* is requested, because these types of interrupts aren't C-callable.
@ -158,7 +162,7 @@ esp_err_t esp_intr_alloc(int source, int flags, intr_handler_t handler, void *ar
*
*
* This essentially does the same as esp_intr_alloc, but allows specifying a register and mask
* combo. For shared interrupts, the handler is only called if a read from the specified
* combo. For shared interrupts, the handler is only called if a read from the specified
* register, ANDed with the mask, returns non-zero. By passing an interrupt status register
* address and a fitting mask, this can be used to accelerate interrupt handling in the case
* a shared interrupt is triggered; by checking the interrupt statuses first, the code can
@ -171,7 +175,7 @@ esp_err_t esp_intr_alloc(int source, int flags, intr_handler_t handler, void *ar
* choice of interrupts that this routine can choose from. If this value
* is 0, it will default to allocating a non-shared interrupt of level
* 1, 2 or 3. If this is ESP_INTR_FLAG_SHARED, it will allocate a shared
* interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return
* interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return
* from this function with the interrupt disabled.
* @param intrstatusreg The address of an interrupt status register
* @param intrstatusmask A mask. If a read of address intrstatusreg has any of the bits
@ -198,9 +202,9 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
* If the current core is not the core that registered this interrupt, this routine will be assigned to
* the core that allocated this interrupt, blocking and waiting until the resource is successfully released.
*
* @note
* When the handler shares its source with other handlers, the interrupt status
* bits it's responsible for should be managed properly before freeing it. see
* @note
* When the handler shares its source with other handlers, the interrupt status
* bits it's responsible for should be managed properly before freeing it. see
* ``esp_intr_disable`` for more details. Please do not call this function in ``esp_ipc_call_blocking``.
*
* @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
@ -214,7 +218,7 @@ esp_err_t esp_intr_free(intr_handle_t handle);
/**
* @brief Get CPU number an interrupt is tied to
*
*
* @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
*
* @return The core number where the interrupt is allocated
@ -223,7 +227,7 @@ int esp_intr_get_cpu(intr_handle_t handle);
/**
* @brief Get the allocated interrupt for a certain handle
*
*
* @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
*
* @return The interrupt number
@ -232,13 +236,13 @@ int esp_intr_get_intno(intr_handle_t handle);
/**
* @brief Disable the interrupt associated with the handle
*
* @note
*
* @note
* 1. For local interrupts (ESP_INTERNAL_* sources), this function has to be called on the
* CPU the interrupt is allocated on. Other interrupts have no such restriction.
* 2. When several handlers sharing a same interrupt source, interrupt status bits, which are
* 2. When several handlers sharing a same interrupt source, interrupt status bits, which are
* handled in the handler to be disabled, should be masked before the disabling, or handled
* in other enabled interrupts properly. Miss of interrupt status handling will cause infinite
* in other enabled interrupts properly. Miss of interrupt status handling will cause infinite
* interrupt calls and finally system crash.
*
* @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus

2
components/esp32/int_wdt.c
View file

@ -23,7 +23,7 @@
#include "freertos/task.h"
#include <esp_types.h>
#include "esp_err.h"
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp_attr.h"
#include "esp_freertos_hooks.h"
#include "soc/timer_group_struct.h"

2
components/esp32/intr_alloc.c
View file

@ -26,7 +26,7 @@
#include "esp_err.h"
//#define LOG_LOCAL_LEVEL ESP_LOG_VERBOSE
#include "esp_log.h"
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp_attr.h"
#include "esp_intr_alloc.h"
#include "esp_ipc.h"

5
components/esp32/linker.lf
View file

@ -3,11 +3,6 @@ archive: libesp32.a
entries:
panic (noflash)
[mapping]
archive: libhal.a
entries:
* (noflash_text)
[mapping]
archive: libgcc.a
entries:

5
components/esp32/panic.c
View file

@ -33,7 +33,8 @@
#include "soc/rtc_wdt.h"
#include "esp_private/gdbstub.h"
#include "esp_panic.h"
#include "esp_debug_helpers.h"
#include "esp_private/panic_reason.h"
#include "esp_attr.h"
#include "esp_err.h"
#include "esp_core_dump.h"
@ -382,7 +383,7 @@ static void illegal_instruction_helper(XtExcFrame *frame)
panicPutStr("Memory dump at 0x");
panicPutHex(epc);
panicPutStr(": ");
panicPutHex(*pepc);
panicPutStr(" ");
panicPutHex(*(pepc + 1));

2
components/esp32/task_wdt.c
View file

@ -25,7 +25,7 @@
#include "freertos/semphr.h"
#include <esp_types.h>
#include "esp_err.h"
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp_intr_alloc.h"
#include "esp_attr.h"
#include "esp_freertos_hooks.h"

2
components/esp_common/CMakeLists.txt
View file

@ -11,6 +11,8 @@ else()
"src/esp_err_to_name.c"
"src/esp_timer.c"
"src/ets_timer_legacy.c"
"src/freertos_hooks.c"
"src/ipc.c"
"src/pm_locks.c"
"src/stack_check.c")
set(COMPONENT_ADD_INCLUDEDIRS "include")

0
components/esp32/include/esp_freertos_hooks.h → components/esp_common/include/esp_freertos_hooks.h
View file

0
components/esp32/include/esp_ipc.h → components/esp_common/include/esp_ipc.h
View file

0
components/esp32/esp_err_to_name.c.in → components/esp_common/src/esp_err_to_name.c.in
View file

0
components/esp32/freertos_hooks.c → components/esp_common/src/freertos_hooks.c
View file

0
components/esp32/ipc.c → components/esp_common/src/ipc.c
View file

10
components/espcoredump/src/core_dump_common.c
View file

@ -14,7 +14,7 @@
#include <string.h>
#include <stdbool.h>
#include "esp32/rom/crc.h"
#include "esp_panic.h"
#include "esp_debug_helpers.h"
#include "esp_partition.h"
#include "esp_core_dump_priv.h"
@ -37,15 +37,15 @@ static esp_err_t esp_core_dump_write_binary(void *frame, core_dump_write_config_
task_num = esp_core_dump_get_tasks_snapshot(tasks, CONFIG_ESP32_CORE_DUMP_MAX_TASKS_NUM, &tcb_sz);
ESP_COREDUMP_LOGI("Found tasks: (%d)!", task_num);
// Take TCB padding into account, actual TCB size will be stored in header
if (tcb_sz % sizeof(uint32_t))
tcb_sz_padded = (tcb_sz / sizeof(uint32_t) + 1) * sizeof(uint32_t);
else
tcb_sz_padded = tcb_sz;
// Verifies all tasks in the snapshot
for (i = 0; i < task_num; i++) {
for (i = 0; i < task_num; i++) {
task_is_valid = esp_core_dump_process_tcb(frame, &tasks[i], tcb_sz);
// Check if task tcb is corrupted
if (!task_is_valid) {
@ -67,7 +67,7 @@ static esp_err_t esp_core_dump_write_binary(void *frame, core_dump_write_config_
// Add core dump header size
data_len += sizeof(core_dump_header_t);
ESP_COREDUMP_LOG_PROCESS("Core dump len = %lu (%d %d)", data_len, task_num, write_cfg->bad_tasks_num);
// Prepare write
if (write_cfg->prepare) {
err = write_cfg->prepare(write_cfg->priv, &data_len);

6
components/espcoredump/src/core_dump_port.c
View file

@ -13,7 +13,7 @@
// limitations under the License.
#include <string.h>
#include <stdbool.h>
#include "esp_panic.h"
#include "esp_debug_helpers.h"
#include "esp_core_dump_priv.h"
const static DRAM_ATTR char TAG[] __attribute__((unused)) = "esp_core_dump_port";
@ -41,7 +41,7 @@ uint32_t esp_core_dump_get_tasks_snapshot(core_dump_task_header_t* const tasks,
bool esp_core_dump_process_tcb(void *frame, core_dump_task_header_t *task_snaphort, uint32_t tcb_sz)
{
XtExcFrame *exc_frame = (XtExcFrame*)frame;
if (!esp_tcb_addr_is_sane((uint32_t)task_snaphort->tcb_addr, tcb_sz)) {
ESP_COREDUMP_LOG_PROCESS("Bad TCB addr %x!", task_snaphort->tcb_addr);
return false;
@ -74,7 +74,7 @@ bool esp_core_dump_process_tcb(void *frame, core_dump_task_header_t *task_snapho
}
bool esp_core_dump_process_stack(core_dump_task_header_t* task_snaphort, uint32_t *length)
{
{
uint32_t len = 0;
bool task_is_valid = false;
len = (uint32_t)task_snaphort->stack_end - (uint32_t)task_snaphort->stack_start;

5
components/freertos/CMakeLists.txt
View file

@ -1,8 +1,8 @@
set(COMPONENT_ADD_INCLUDEDIRS include)
set(COMPONENT_PRIV_INCLUDEDIRS include/freertos)
set(COMPONENT_SRCS "FreeRTOS-openocd.c"
"croutine.c"
set(COMPONENT_SRCS "croutine.c"
"event_groups.c"
"FreeRTOS-openocd.c"
"list.c"
"port.c"
"portasm.S"
@ -20,6 +20,7 @@ set(COMPONENT_SRCS "FreeRTOS-openocd.c"
# app_trace is required by FreeRTOS headers only when CONFIG_SYSVIEW_ENABLE=y,
# but requirements can't depend on config options, so always require it.
set(COMPONENT_REQUIRES app_trace)
set(COMPONENT_PRIV_REQUIRES esp_common)
set(COMPONENT_ADD_LDFRAGMENTS linker.lf)
register_component()

4
components/freertos/port.c
View file

@ -103,7 +103,7 @@
#include "FreeRTOS.h"
#include "task.h"
#include "esp_panic.h"
#include "esp_debug_helpers.h"
#include "esp_heap_caps.h"
#include "esp_private/crosscore_int.h"
@ -446,7 +446,7 @@ void uxPortCompareSetExtram(volatile uint32_t *addr, uint32_t compare, uint32_t
#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
vPortCPUAcquireMutexIntsDisabled(&extram_mux, portMUX_NO_TIMEOUT, __FUNCTION__, __LINE__);
#else
vPortCPUAcquireMutexIntsDisabled(&extram_mux, portMUX_NO_TIMEOUT);
vPortCPUAcquireMutexIntsDisabled(&extram_mux, portMUX_NO_TIMEOUT);
#endif
prev=*addr;
if (prev==compare) {

2
components/freertos/tasks.c
View file

@ -78,7 +78,7 @@ task.h is included from an application file. */
#include "esp32/rom/ets_sys.h"
#include "esp_newlib.h"
#include "esp_panic.h"
#include "esp_debug_helpers.h"
/* FreeRTOS includes. */
#include "FreeRTOS.h"

4
components/freertos/xtensa_vector_defaults.S
View file

@ -13,12 +13,12 @@
// limitations under the License.
#include "xtensa_rtos.h"
#include "esp_panic.h"
#include "esp_private/panic_reason.h"
#include "sdkconfig.h"
#include "soc/soc.h"
/*
This file contains the default handlers for the high interrupt levels as well as some specialized exceptions.
This file contains the default handlers for the high interrupt levels as well as some specialized exceptions.
The default behaviour is to just exit the interrupt or call the panic handler on the exceptions
*/

50
components/freertos/xtensa_vectors.S
View file

@ -34,14 +34,14 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
medium level interrupts, by calling xt_set_interrupt_handler(). These
handlers can be written in C, and must obey C calling convention. The
handler table is indexed by the interrupt number. Each handler may be
provided with an argument.
provided with an argument.
Note that the system timer interrupt is handled specially, and is
dispatched to the RTOS-specific handler. This timer cannot be hooked
by application code.
Optional hooks are also provided to install a handler per level at
run-time, made available by compiling this source file with
Optional hooks are also provided to install a handler per level at
run-time, made available by compiling this source file with
'-DXT_INTEXC_HOOKS' (useful for automated testing).
!! This file is a template that usually needs to be modified to handle !!
@ -81,17 +81,17 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
This allows more flexibility in locating code without the performance
overhead of the 'l32r' literal data load in cases where the destination
is in range of 'call0'. There is an additional benefit in that 'call0'
has a longer range than 'j' due to the target being word-aligned, so
has a longer range than 'j' due to the target being word-aligned, so
the 'l32r' sequence is less likely needed.
3. The use of 'call0' with -mlongcalls requires that register a0 not be
live at the time of the call, which is always the case for a function
3. The use of 'call0' with -mlongcalls requires that register a0 not be
live at the time of the call, which is always the case for a function
call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'.
4. This use of 'call0' is independent of the C function call ABI.
*******************************************************************************/
#include "xtensa_rtos.h"
#include "esp_panic.h"
#include "esp_private/panic_reason.h"
#include "sdkconfig.h"
#include "soc/soc.h"
#include "soc/dport_reg.h"
@ -365,7 +365,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/*
--------------------------------------------------------------------------------
Panic handler.
Should be reached by call0 (preferable) or jump only. If call0, a0 says where
Should be reached by call0 (preferable) or jump only. If call0, a0 says where
from. If on simulator, display panic message and abort, else loop indefinitely.
--------------------------------------------------------------------------------
*/
@ -437,7 +437,7 @@ panic_print_hex_a:
panic_print_hex_ok:
s32i a5,a3,0
slli a2,a2,4
addi a4,a4,-1
bnei a4,0,panic_print_hex_loop
movi a5,' '
@ -456,12 +456,12 @@ panic_print_hex_ok:
--------------------------------------------------------------------------------
Hooks to dynamically install handlers for exceptions and interrupts.
Allows automated regression frameworks to install handlers per test.
Consists of an array of function pointers indexed by interrupt level,
Consists of an array of function pointers indexed by interrupt level,
with index 0 containing the entry for user exceptions.
Initialized with all 0s, meaning no handler is installed at each level.
See comment in xtensa_rtos.h for more details.
*WARNING* This array is for all CPUs, that is, installing a hook for
*WARNING* This array is for all CPUs, that is, installing a hook for
one CPU will install it for all others as well!
--------------------------------------------------------------------------------
*/
@ -491,7 +491,7 @@ _xt_intexc_hooks:
the appropriate stack frame, saves a few vector-specific registers and
calls XT_RTOS_INT_ENTER to save the rest of the interrupted context
and enter the RTOS, then sets up a C environment. It then calls the
user's interrupt handler code (which may be coded in C) and finally
user's interrupt handler code (which may be coded in C) and finally
calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
While XT_RTOS_INT_EXIT does not return directly to the interruptee,
@ -867,7 +867,7 @@ _xt_syscall_exc:
--------------------------------------------------------------------------------
Co-Processor Exception Handler (jumped to from User Exception Handler).
These exceptions are generated by co-processor instructions, which are only
allowed in thread code (not in interrupts or kernel code). This restriction is
allowed in thread code (not in interrupts or kernel code). This restriction is
deliberately imposed to reduce the burden of state-save/restore in interrupts.
--------------------------------------------------------------------------------
*/
@ -984,7 +984,7 @@ _xt_coproc_exc:
or a4, a4, a2 /* a4 = CPENABLE | (1 << n) */
wsr a4, CPENABLE
/*
/*
Keep loading _xt_coproc_owner_sa[n] atomic (=load once, then use that value
everywhere): _xt_coproc_release assumes it works like this in order not to need
locking.
@ -1030,8 +1030,8 @@ locking.
/*
The config-specific HAL macro invoked below destroys a2-5, preserves a0-1.
It is theoretically possible for Xtensa processor designers to write TIE
that causes more address registers to be affected, but it is generally
It is theoretically possible for Xtensa processor designers to write TIE
that causes more address registers to be affected, but it is generally
unlikely. If that ever happens, more registers needs to be saved/restored
around this macro invocation, and the value in a15 needs to be recomputed.
*/
@ -1056,8 +1056,8 @@ locking.
/*
The config-specific HAL macro invoked below destroys a2-5, preserves a0-1.
It is theoretically possible for Xtensa processor designers to write TIE
that causes more address registers to be affected, but it is generally
It is theoretically possible for Xtensa processor designers to write TIE
that causes more address registers to be affected, but it is generally
unlikely. If that ever happens, more registers needs to be saved/restored
around this macro invocation.
*/
@ -1138,12 +1138,12 @@ _xt_lowint1:
/* Save rest of interrupt context and enter RTOS. */
call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */
/* !! We are now on the RTOS system stack !! */
/* !! We are now on the RTOS system stack !! */
/* Set up PS for C, enable interrupts above this level and clear EXCM. */
#ifdef __XTENSA_CALL0_ABI__
movi a0, PS_INTLEVEL(1) | PS_UM
#else
#else
movi a0, PS_INTLEVEL(1) | PS_UM | PS_WOE
#endif
wsr a0, PS
@ -1175,7 +1175,7 @@ _xt_lowint1:
the appropriate stack frame, saves a few vector-specific registers and
calls XT_RTOS_INT_ENTER to save the rest of the interrupted context
and enter the RTOS, then sets up a C environment. It then calls the
user's interrupt handler code (which may be coded in C) and finally
user's interrupt handler code (which may be coded in C) and finally
calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
While XT_RTOS_INT_EXIT does not return directly to the interruptee,
@ -1602,7 +1602,7 @@ and used for purposes requiring very short service times.
Here are templates for high priority (level 2+) interrupt vectors.
They assume only one interrupt per level to avoid the burden of identifying
which interrupts at this level are pending and enabled. This allows for
which interrupts at this level are pending and enabled. This allows for
minimum latency and avoids having to save/restore a2 in addition to a0.
If more than one interrupt per high priority level is configured, this burden
is on the handler which in any case must provide a way to save and restore
@ -1727,12 +1727,12 @@ _NMIExceptionVector:
WINDOW OVERFLOW AND UNDERFLOW EXCEPTION VECTORS AND ALLOCA EXCEPTION HANDLER
Here is the code for each window overflow/underflow exception vector and
Here is the code for each window overflow/underflow exception vector and
(interspersed) efficient code for handling the alloca exception cause.
Window exceptions are handled entirely in the vector area and are very
tight for performance. The alloca exception is also handled entirely in
tight for performance. The alloca exception is also handled entirely in
the window vector area so comes at essentially no cost in code size.
Users should never need to modify them and Cadence Design Systems recommends
Users should never need to modify them and Cadence Design Systems recommends
they do not.
Window handlers go at predetermined vector locations according to the

2
components/heap/test/test_malloc.c
View file

@ -17,7 +17,7 @@
#include "soc/io_mux_reg.h"
#include "esp_heap_caps.h"
#include "esp_panic.h"
#include "esp_debug_helpers.h"
#include "sdkconfig.h"

2
components/mbedtls/port/esp_bignum.c
View file

@ -31,7 +31,7 @@
#include "soc/hwcrypto_reg.h"
#include "esp_system.h"
#include "esp_log.h"
#include "esp_intr.h"
#include "esp_intr_alloc.h"
#include "esp_intr_alloc.h"
#include "esp_attr.h"

2
components/xtensa/CMakeLists.txt
View file

@ -5,3 +5,5 @@ set(COMPONENT_ADD_INCLUDEDIRS "include" "${IDF_TARGET}/include")
set(COMPONENT_ADD_LDFRAGMENTS linker.lf)
register_component()
target_link_libraries(${COMPONENT_TARGET} "${CMAKE_CURRENT_SOURCE_DIR}/${IDF_TARGET}/libhal.a")

2
components/xtensa/component.mk
View file

@ -1,4 +1,6 @@
COMPONENT_ADD_INCLUDEDIRS := include esp32/include
COMPONENT_ADD_LDFLAGS += $(COMPONENT_PATH)/esp32/libhal.a
COMPONENT_ADD_LDFRAGMENTS += linker.lf

0
components/esp32/libhal.a → components/xtensa/esp32/libhal.a
View file

39
components/esp32/include/esp_panic.h → components/xtensa/include/esp_debug_helpers.h
View file

@ -1,39 +1,24 @@
#ifndef PANIC_H
#define PANIC_H
#pragma once
#ifdef __cplusplus
extern "C"
{
extern "C" {
#endif
#define PANIC_RSN_NONE 0
#define PANIC_RSN_DEBUGEXCEPTION 1
#define PANIC_RSN_DOUBLEEXCEPTION 2
#define PANIC_RSN_KERNELEXCEPTION 3
#define PANIC_RSN_COPROCEXCEPTION 4
#define PANIC_RSN_INTWDT_CPU0 5
#define PANIC_RSN_INTWDT_CPU1 6
#define PANIC_RSN_CACHEERR 7
#define PANIC_RSN_MAX 7
#ifndef __ASSEMBLER__
#include "esp_err.h"
/**
* @brief If an OCD is connected over JTAG. set breakpoint 0 to the given function
* address. Do nothing otherwise.
* @param data Pointer to the target breakpoint position
*/
void esp_set_breakpoint_if_jtag(void *fn);
#define ESP_WATCHPOINT_LOAD 0x40000000
#define ESP_WATCHPOINT_STORE 0x80000000
#define ESP_WATCHPOINT_ACCESS 0xC0000000
/**
* @brief If an OCD is connected over JTAG. set breakpoint 0 to the given function
* address. Do nothing otherwise.
* @param fn Pointer to the target breakpoint position
*/
void esp_set_breakpoint_if_jtag(void *fn);
/**
* @brief Set a watchpoint to break/panic when a certain memory range is accessed.
*
@ -45,7 +30,7 @@ void esp_set_breakpoint_if_jtag(void *fn);
*
* @return ESP_ERR_INVALID_ARG on invalid arg, ESP_OK otherwise
*
* @warning The ESP32 watchpoint hardware watches a region of bytes by effectively
* @warning The ESP32 watchpoint hardware watches a region of bytes by effectively
* masking away the lower n bits for a region with size 2^n. If adr does
* not have zero for these lower n bits, you may not be watching the
* region you intended.
@ -68,10 +53,8 @@ static inline bool esp_stack_ptr_is_sane(uint32_t sp)
{
return !(sp < 0x3ffae010UL || sp > 0x3ffffff0UL || ((sp & 0xf) != 0));
}
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif

4
components/xtensa/include/esp_panic.h Normal file
View file

@ -0,0 +1,4 @@
#pragma once
#warning "esp_panic.h is deprecated, please use esp_debug_helpers.h or/and esp_private/panic_reason.h"
#include "esp_private/panic_reason.h"
#include "esp_debug_helpers.h"

11
components/xtensa/include/esp_private/panic_reason.h Normal file
View file

@ -0,0 +1,11 @@
#pragma once
#define PANIC_RSN_NONE 0
#define PANIC_RSN_DEBUGEXCEPTION 1
#define PANIC_RSN_DOUBLEEXCEPTION 2
#define PANIC_RSN_KERNELEXCEPTION 3
#define PANIC_RSN_COPROCEXCEPTION 4
#define PANIC_RSN_INTWDT_CPU0 5
#define PANIC_RSN_INTWDT_CPU1 6
#define PANIC_RSN_CACHEERR 7
#define PANIC_RSN_MAX 7

5
components/xtensa/linker.lf
View file

@ -2,3 +2,8 @@
archive: libxtensa.a
entries:
eri (noflash_text)
[mapping]
archive: libhal.a
entries:
* (noflash_text)

4
docs/Doxyfile
View file

@ -161,9 +161,9 @@ INPUT = \
../../components/esp_common/include/esp_int_wdt.h \
../../components/esp_common/include/esp_task_wdt.h \
## Hooks
../../components/esp32/include/esp_freertos_hooks.h \
../../components/esp_common/include/esp_freertos_hooks.h \
## Inter-Processor Call
../../components/esp32/include/esp_ipc.h \
../../components/esp_common/include/esp_ipc.h \
## Over The Air Updates (OTA)
../../components/app_update/include/esp_ota_ops.h \
## ESP HTTPS OTA

2
tools/ci/executable-list.txt
View file

@ -1,6 +1,6 @@
# Some tools
components/app_update/gen_empty_partition.py
components/esp32/ld/elf_to_ld.sh
tools/elf_to_ld.sh
components/espcoredump/espcoredump.py
components/heap/test_multi_heap_host/test_all_configs.sh
components/idf_test/unit_test/TestCaseScript/IDFUnitTest/__init__.py

0
components/esp32/ld/elf_to_ld.sh → tools/elf_to_ld.sh
View file

3
tools/gen_esp_err_to_name.py
View file

@ -319,7 +319,8 @@ def main():
idf_path = os.path.realpath(os.path.join(os.path.dirname(os.path.abspath(__file__)), '..'))
parser = argparse.ArgumentParser(description='ESP32 esp_err_to_name lookup generator for esp_err_t')
parser.add_argument('--c_input', help='Path to the esp_err_to_name.c.in template input.', default=idf_path + '/components/esp32/esp_err_to_name.c.in')
parser.add_argument('--c_input', help='Path to the esp_err_to_name.c.in template input.',
default=idf_path + '/components/esp_common/src/esp_err_to_name.c.in')
parser.add_argument('--c_output', help='Path to the esp_err_to_name.c output.', default=idf_path + '/components/esp32/esp_err_to_name.c')
parser.add_argument('--rst_output', help='Generate .rst output and save it into this file')
args = parser.parse_args()