Commit graph

244 commits

Author SHA1 Message Date
Ivan Grokhotkov
fb9c106bcb soc/rtc: add function to get/set VDDSDIO configuration
Also consider case of VDDSDIO force powered on in rtc_sleep.
2017-11-03 15:49:09 +08:00
Ivan Grokhotkov
5a294c9acd soc/gpio: fix description of GPIO_STRAP_REG 2017-11-03 15:49:09 +08:00
Ivan Grokhotkov
80eb3b6ddb Merge branch 'bugfix/light_sleep_current' into 'master'
soc/rtc: fix increased current consumption in light sleep

See merge request !1483
2017-11-02 18:26:23 +08:00
XiaXiaotian
42cefc173f refractor WiFi clock setting
Do not set WiFi clock in PHY initializing function, move it to WiFi
   start/stop function.
2017-11-02 15:24:21 +08:00
wangmengyang
bd6394db92 component/bt: clean up WIFI_CLK_EN_REG settings for Bluetooth
1. move settings of WIFI_CLK_EN_REG for bluetooth into controller init/deinit APIs
2. modify the bit mask used in phy_rf init/deinit to use WIFI-BT shared bits
2017-11-02 15:24:21 +08:00
Ivan Grokhotkov
9bfb45aa1d soc/rtc: fix increased current consumption in light sleep
This fixes a configuration issue of RTC, which caused light sleep current
to be 1.35mA instead of 0.85mA.
2017-11-02 13:57:26 +08:00
Ivan Grokhotkov
eb5752c635 esp_restart: fix possible race while stalling other CPU, enable WDT early
Previously esp_restart would stall the other CPU before enabling RTC_WDT.
If the other CPU was executing an s32c1i instruction, the lock signal
from CPU to the arbiter would still be held after CPU was stalled. If
the CPU running esp_restart would then try to access the same locked
memory pool, it would be stuck, because lock signal would never be
released.

With this change, esp_restart resets the other CPU before stalling it.
Ideally, we would want to reset the CPU and keep it in reset, but the
hardware doesn't have such feature for PRO_CPU (it is possible to hold
APP_CPU in reset using DPORT register). Given that ROM code will not use
s32c1i in the first few hundred cycles, doing reset and then stall seems
to be safe.

In addition to than, RTC_WDT initialization is moved to the beginning of
the function, to prevent possible lock-up if CPU stalling still has any
issue.
2017-10-26 19:53:53 +08:00
Ivan Grokhotkov
f11ad0c904 soc/rtc: fix spurious warnings about XTAL frequency on startup
1. Make sure that 8MD256 clock used to estimate XTAL frequency is enabled
   before trying to use rtc_clk_cal_ratio.
   This fixes "Bogus XTAL frequency: 0 MHz" warnings after software reset.

2. Don't call rtc_clk_xtal_freq_estimate if XTAL frequency is already
   known. This reduces startup time after deep sleep or software reset.

3. Compare known XTAL frequency and estimated one before printing a
   warning. This fixes "Possibly invalid CONFIG_ESP32_XTAL_FREQ setting
   (40MHz). Detected 40 MHz." warnings.
2017-10-26 19:53:53 +08:00
Ivan Grokhotkov
9317cb3434 soc/rtc: add tests for CPU frequency switching
These tests switch between PLL and XTAL frequencies for 10 seconds.
2017-10-26 19:53:53 +08:00
Ivan Grokhotkov
6d4ed4ff6c soc/rtc: wait for SLOW_CLK cycle when switching CPU clock
Previous implementation waited for 20us after setting
RTC_CNTL_SOC_CLK_SEL_XTL register, using ets_delay_us, assuming that
the CPU was running at XTAL frequency. In reality, clock switch happened
on the next RTC_SLOW_CLK cycle, and CPU could be running at the previous
frequency (for example, 240 MHz) until then.
ets_delay_us would wait for 20 us * 40 cycles per us = 800 CPU cycles
(assuming 40 MHz XTAL; even less with a 26 MHz XTAL).
But if CPU was running at 240 MHz, 800 cycles would pass in just 3.3us,
while SLOW_CLK cycle could happen as much as 1/150kHz = 6.7us after
RTC_CNTL_SOC_CLK_SEL_XTL was set. So the software would not actually wait
long enough for the clock switch to happen, and would disable the PLL
while CPU was still clocked from PLL, leading to a halt.

This implementation uses rtc_clk_wait_for_slow_cycle() function to wait
until the clock switch, removing the need to wait for a fixed number of
CPU cycles.
2017-10-26 19:53:53 +08:00
Ivan Grokhotkov
05a0fbd49b soc/rtc: add a function to wait for slow clock cycle
Some RTC features are synchronized to RTC_SLOW_CLK, so sometimes
software needs to wait for the next slow clock cycle.
This function implements waiting using Timer Group clock calibration
feature.
2017-10-26 19:53:53 +08:00
esp32de
7c0020bfd0 feat(adc2): append adc2 support and api and the lock with WIFI module
append adc support and api
- esp_err_t adc2_config_width(adc_bits_width_t width_bit);
- esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten);
- int adc2_get_voltage(adc2_channel_t channel);
2017-10-26 14:35:29 +08:00
Ivan Grokhotkov
59b7d98fec Merge branch 'feature/dfs' into 'master'
Dynamic frequency scaling

See merge request !1189
2017-10-22 12:34:11 +08:00
Ivan Grokhotkov
b6f37bda97 Merge branch 'feature/i2s_built_in_adc' into 'master'
feature(I2S-ADC): add ADC mode for I2S.

See merge request !1077
2017-10-20 15:52:56 +08:00
Ivan Grokhotkov
099565635b soc: correct values of SOC_BYTE_ACCESSIBLE_LOW, SOC_MEM_INTERNAL_LOW
Internal byte accessible memory starts with Internal ROM 1 at 0x3FF90000.
Region of RTC fast memory starting at 0x3FF80000 is not used in IDF as
it is mapped to PRO CPU only.
2017-10-19 21:35:21 +08:00
Ivan Grokhotkov
fba9678c56 uart: add support for REF_TICK 2017-10-18 14:19:20 +08:00
Ivan Grokhotkov
b03e08dc4e soc/rtc: add function to convert CPU frequency in MHz to rtc_cpu_freq_t 2017-10-18 14:19:15 +08:00
Ivan Grokhotkov
a242ae6d0b soc/rtc: add fast paths for switching between PLL and XTAL 2017-10-18 14:19:14 +08:00
Jeroen Domburg
740f8a79f0 Add logic to make external RAM usable with malloc() 2017-09-28 17:17:50 +08:00
michael
9d9e771933 fix(global, log): fix esp_log(_early)_timestamp readings after startup by correct the CCOUNT register when switching CPU clock.
TW#13332, Closes #700
2017-09-26 15:18:17 +08:00
Tian Hao
3e2ee24e4f component/bt : support bluetooth controller DRAM release dynamically
1. remove CONFIG_BT_DRAM_RELEASE from Kconfig
2. add API to release bluetooth controller DRAM to heap
2017-09-21 14:31:20 +08:00
michael
8244fa95fe feat(log): add new function to log buffer with level and hex dump. 2017-09-18 11:44:54 +08:00
Wangjialin
2fceec4d85 feature(I2S-ADC): add ADC mode for I2S.
1. Support built-in ADC for I2S.
2. Modify code of ADC, made no change to the original APIs.
3. Add APIs in I2S:
esp_err_t i2s_set_adc_mode(adc_unit_t adc_unit, adc1_channel_t adc_channel);
4. Add I2S ADC/DAC example code.
5. add old-fashion definition to make it more compatible
6. replase spi_flash_ APIs with esp_partition_ APIs
7. add example of generating audio table from wav
8. change example sound
2017-09-14 13:24:08 +08:00
Jeroen Domburg
875ae6a134 Add option to allocate external RAM using heap_alloc_caps 2017-09-14 10:47:44 +08:00
Ivan Grokhotkov
1e7c3854d3 Merge branch 'bugfix/warn_on_invalid_xtal_freq' into 'master'
soc/rtc: warn if detected XTAL frequency does not match configured one

See merge request !1242
2017-09-11 18:15:11 +08:00
Ivan Grokhotkov
de038f502c Merge branch 'feature/gpio_channel_macro' into 'master'
feat(global): add macros for GPIO->channel lookup

See merge request !1170
2017-09-11 12:15:08 +08:00
Ivan Grokhotkov
5a88f90a33 soc/rtc: warn if detected XTAL frequency does not match configured one
Since 9a8c0392, XTAL frequency is set to 40MHz by default, and users
of 26MHz boards need to select 26MHz manually. Most users are not aware
of this change, and existing getting started guides do not mention that
XTAL frequency needs to be set for some boards. So users are left with
garbage output from UART without any clue what to check.

This change adds a warning in case specific XTAL frequency was set, and
it does not match automatically detected one. This should help users
fix the issue.
2017-09-11 11:42:26 +08:00
Angus Gratton
1c7b8aa3a5 Heap tracing support 2017-09-07 16:32:05 +10:00
michael
08b9fbc242 feat(global): add macros for GPIO->channel lookup
including: macros for dac, adc, touch, rtc_gpio, uart and clk_out.

TW#13970
2017-09-07 10:40:25 +08:00
Jeroen Domburg
34372a091c Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet. 2017-09-04 12:05:49 +08:00
Ivan Grokhotkov
5666fc0a56 Merge branch 'feature/esp_timer_improvements' into 'master'
esp_timer improvements

See merge request !1172
2017-09-01 16:14:01 +08:00
Ivan Grokhotkov
d2acf1ce77 sleep: add light sleep, factor out APIs common for deep/light sleep 2017-09-01 10:36:14 +08:00
Ivan Grokhotkov
f8b719d911 soc/rtc: add sleep flag to control powerdown of VDD_SDIO 2017-09-01 10:36:14 +08:00
Ivan Grokhotkov
c743bdac88 soc/rtc: round APB clock frequency to nearest MHz 2017-09-01 10:34:36 +08:00
Ivan Grokhotkov
a25eb825e1 Merge branch 'bugfix/dport_protect_crypto' into 'master'
add protection for crypto registers in DPORT

See merge request !928
2017-08-30 11:45:35 +08:00
Ivan Grokhotkov
547ef83020 Merge branch 'feature/disable_some_perip_clk_when_cpu_start' into 'master'
Disable some peripheral clocks when cpu starts

See merge request !1089
2017-08-30 11:43:38 +08:00
XiaXiaotian
4776f73ca4 Disable some peripheral clocks when cpu starts
All peripheral clocks are default enabled after chip is powered on.
    When CPU starts, if reset reason is CPU reset, disable those clocks
    that are not enabled before reset. Otherwise, disable all those
    useless clocks.
    These peripheral clocks must be enabled when the peripherals are
    initialized and disabled when they are deinitialized.
2017-08-29 11:18:42 +08:00
michael
c7173e0d08 fix(struct_h): add extern "C" protection to *_struct.h header files. 2017-08-28 18:10:46 +08:00
Ivan Grokhotkov
82763a02af Merge branch 'feature/ets_timer' into 'master'
esp_timer: add high-resolution timer api

See merge request !1090
2017-08-28 16:38:11 +08:00
Ivan Grokhotkov
d8b66e5088 soc: release interrupts which are not reserved by timers any more 2017-08-28 11:35:27 +08:00
Ivan Grokhotkov
b636f81619 Merge branch 'bugfix/spi_command' into 'master'
fix(spi_master): fix the command field to make it more intuitive to use.

See merge request !1119
2017-08-28 10:29:56 +08:00
Angus Gratton
2624e10055 esp32 hwcrypto: Use AES registers directly 2017-08-25 16:08:03 +10:00
Angus Gratton
cb31222e8b dport access: Add _DPORT_REG_SET_BIT & _DPORT_REG_CLR_BIT 2017-08-25 16:08:02 +10:00
Ivan Grokhotkov
08287852ab esp32: add protection for DPORT registers of RSA 2017-08-25 16:08:02 +10:00
Ivan Grokhotkov
a66df0826e soc: fix/update definitions related to FRC timers
1. BIT(8) of CTRL is actually read-only bit indicating interrupt status

2. BIT(0) or CTRL had inverted meaning: 1 is “level”, 0 is “edge”

3. Add definitions of prescaler values
2017-08-24 16:33:12 +08:00
Wang Jia Lin
f1ecffb46c Merge branch 'bugfix/touch_pad_driver' into 'master'
driver(touch): fix bug and add more features

See merge request !1056
2017-08-23 19:12:39 +08:00
Wangjialin
842caaab21 driver(touch): fix bug and add more features
1. add sens_struct.h
2. add definition of RTCCNTL and RTCIO
3. modify touch pad examples
4. update example code.
5. add comments add option in menuconfig
6. fix issue that pad index 8 and 9 are mismatched
7. add touch_pad_read_filtered() api to get value filtered by iir filter
8. modify touch pad isr func
9. Make the items in perihperal.ld in the sequence of address
10. delete Kconfig for touch pad
11. add touchpad filter APIs to adjust the filter
12. add touch_pad into index.rst
13. add touch_pad in Doxyfile
14. add touch_pad.rst
2017-08-22 21:21:39 +08:00
michael
4c9754726f fix(spi_master): fix the command field to make it more intuitive to use. 2017-08-21 20:37:57 +08:00
michael
ed1d084aea fix(spi_master): make the address field more intuitive to use.
The address field should be placed at the highest bits of address and slv_wr_status registers. Instead of breaking the address into two parts and fill in each register, move the address to the highest bits and write to the registers respectively.

Breaking change: if you fill-in the SPI address filed in a previous version in some way and it works correctly, you still have to rewrite the address, in a more intuitive way.
2017-08-15 14:49:31 +08:00
michael
99769f0b00 fix(spi_master): fix the bug that VSPI no respond when host changed
from HSPI to VSPI, and vice versa.

fix the SPI control bits written wrong in the headers.

TW#12123, Github#477
2017-07-21 14:50:17 +08:00
Angus Gratton
17adb40ca8 bootloader: Calculate SHA256 hash of image on every boot
Makes app image booting more reliable (256-bit rather than 8-bit verification.)

Some measurements, time to boot a 655KB app.bin file and run to app_main() execution.

(All for rev 1 silicon, ie no 340ms spurious WDT delay.)

80MHz QIO mode:
before = 300ms
after = 140ms

40MHz DIO mode:
before = 712ms
after = 577ms

40MHz DIO mode, secure boot enabled
before = 1380ms
after = 934ms

(Secure boot involves two ECC signature verifications (partition table, app) that take approx 300ms each with 80MHz CPU.)
2017-07-19 18:31:59 +10:00
Ivan Grokhotkov
0ae916d555 Merge branch 'feature/high_level_interrupts' into 'master'
Break out high-level interrupts so a component can override them

See merge request !675
2017-07-18 10:42:31 +08:00
Ivan Grokhotkov
7fc25f18d2 Merge branch 'feature/enable_brownout_detector' into 'master'
Enable brownout detector

See merge request !811
2017-07-13 11:40:37 +08:00
Angus Gratton
ad60c30de0 heap: Rename memory "tags" to "types" to avoid confusion w/ old tag allocator API 2017-07-10 17:46:03 +08:00
Angus Gratton
8d7074ed5c soc: Move esp_ptr_dma_capable() function to soc_memory_layout.h 2017-07-10 17:46:03 +08:00
Angus Gratton
71c70cb15c heap: Refactor heap regions/capabilities out of FreeRTOS
Remove tagged heap API, rename caps_xxx to heap_caps_xxx

Also includes additional heap_caps_xxx inspection functions.
2017-07-10 17:46:03 +08:00
Angus Gratton
5ee49fd311 heap: Add new multi_heap heap implementation to replace FreeRTOS-based tagged heaps 2017-07-10 17:46:03 +08:00
Ivan Grokhotkov
01b185977c brownout detector: enable by default
Because of errata related to BOD reset function, brownout is handled as follows:

- attach an ISR to brownout interrupt
- when ISR happens, print a message and do a software restart
- esp_restart_nonos enables RTC watchdog, so if restart fails,
  there will be  one more attempt to restart (using the RTC
  watchdog)
2017-07-10 17:25:55 +08:00
Ivan Grokhotkov
780569c04a esp32: fix RTC watchdog configuration in esp_restart
RTC watchdog didn’t have any actions configured for any of the stages.
This change configures it to use SW_SYSTEM_RESET at stage 0 and a
full reset at stage 1. The timeout is now calculated based on
RTC_SLOW_CLK frequency.
2017-07-10 17:21:49 +08:00
Tian Hao
7a79d31db0 fix reg operation missing 2017-07-07 20:04:24 +08:00
Jeroen Domburg
d3290479b2 Merge panic and dport high level interrupt code to both use int level 4 2017-07-07 12:51:33 +08:00
Ivan Grokhotkov
6b2e16e51b soc: fix typo in register name 2017-07-06 12:36:06 +08:00
Jack
ab9f63aba7 fix bug that uart register base address macro was wrong 2017-06-23 19:56:12 +08:00
Tian Hao
09f7cf45dd component/bt : fix interrupt number conflict
1. the typical problem is when push keyboard on serial tool, the bluetooth may stop.
2017-06-15 19:41:54 +08:00
Ivan Grokhotkov
06accaf851 add C++ include guards to header files which are missing them
Fixes https://github.com/espressif/esp-idf/issues/628
2017-05-31 17:20:17 +08:00
Jiang Jiang Jian
9229902dff Merge branch 'bugfix/lib_dport_access' into 'master'
component/esp32 : fix library dport access protections.

1. add esp32 library access DPORT register protections.
2. add bluetooth library access DPORT register protections.
3. change register operation(suffix/prefix) to new style.

See merge request !757
2017-05-18 14:56:38 +08:00
Tian Hao
52515d0edf component/esp32 : update wifi library and phy library 2017-05-17 11:46:53 +08:00
Ivan Grokhotkov
98e15df7f6 examples: add ULP ADC example 2017-05-16 13:15:02 +08:00
Tian Hao
3d22f1ee2f component/esp32 : fix library sport access protections.
1. add esp32 library access DPORT register protections.
2. add bluetooth library access DPORT register protections.
3. change register operation(suffix/prefix) to new style.
2017-05-13 19:55:11 +08:00
Jiang Jiang Jian
a6608648db Merge branch 'driver_merge_tmp/mcpwm' into 'master'
feature: Motor Control PWM(mcpwm) driver and examples



See merge request !698
2017-05-12 18:21:38 +08:00
Jiang Jiang Jian
bb25ac91f4 Merge branch 'bugfix/dualcore' into 'master'
component/soc: fix register access protection missing

- fix dport register access protection missing
- add rom function protect
- add normal register function check

See merge request !747
2017-05-12 18:19:31 +08:00
Kewal M Shah
2008f4d88c feature: add Motor Control PWM(mcpwm) driver
1. Name change from chopper to carrier, block diagram update, minor changes to example codes
2. mcpwm_reg.h changed, brought uniformity in comments, worked on suggestions, duty to accept float. Some name changes!
3. Minor readme changes and Indetation
4. Minor change:  move mcpwm_reg.h and mcpwm_struct.h to new path
5. Minor change: addition of BLDC example code and Readme
6. Name changed from epwm to mcpwm
7. Improve the reg name in mcpwm_struct.h
8. Name change chopper>carrier, deadband>deadtime
2017-05-12 15:47:59 +08:00
Tian Hao
377a1f5ea1 component/esp32 : do more fix of dualcore bug
1. the cache API in romcode will access DPORT register, so protect it.
2. fix STALL spelling.
3. check dport access by non-dport access function
2017-05-12 15:41:51 +08:00
Ivan Grokhotkov
15a6145961 Merge branch 'feature/get_chip_ver' into 'master'
add API to get chip info

This change adds an API to get chip info, such as chip model, enabled capabilities, size of embedded flash, silicon revision.

Hello_world example is modified to print out the information about the chip. The example is also simplified by moving all code into the main task.

Ref TW12031.

See merge request !549
2017-05-11 12:05:55 +08:00
Tian Hao
26a3cb93c7 component/soc : move dport access header files to soc
1. move dport access header files to soc
2. reduce dport register write protection. Only protect read operation
2017-05-09 18:06:00 +08:00
Tian Hao
f7e8856520 component/esp32 : fix dualcore bug
1. When dual core cpu run access DPORT register, must do protection.
2. If access DPORT register, must use DPORT_REG_READ/DPORT_REG_WRITE and DPORT_XXX register operation macro.
2017-05-08 21:53:43 +08:00
Ivan Grokhotkov
2260c714e7 add esp_chip_info API 2017-05-05 17:28:30 +08:00
Tian Hao
5c0d0d4854 component/bt : change VHCI interrupt type to software interrupt(int no 7) 2017-04-28 17:20:06 +08:00
Jeroen Domburg
46fa2cfb46 Merge branch 'feature/spi_slave' into 'master'
Split common SPI stuff out of master driver; add slave driver; add workaround for DMA issue.

This merge req mainly adds a slave device. In order to do this, the original master driver is refactored into common code shared by master and slave modes, and a slave driver is added.

The other things added are:
- Added a workaround for a 'feature' of the ESP32 silicon that can lock up the receive DMA channel in some situations. This can only be fixed by resetting *both* DMA channels. The workaround implemented makes sure that the reset only happens when both channels are idle
- Got rid of the automatic choice between register- and DMA-based transfers. The master (and slave) code will now always go for a DMA transfer if a DMA channel is given, and always go for register-based transfers if no DMA channel is given.
- Add in a bunch of fixes for outstanding Github issues.

See merge request !659
2017-04-27 12:28:42 +08:00
Jeroen Domburg
e9c372bc2d SPI: Split common SPI stuff out of master driver; add slave driver; add workaround for DMA issue. 2017-04-27 11:49:04 +08:00
Ivan Grokhotkov
0fe765a977 Merge branch 'feature/32k_xtal' into 'master'
add support for 32k XTAL as RTC_SLOW_CLK source

- RTC_CNTL_SLOWCLK_FREQ define is removed; rtc_clk_slow_freq_get_hz
  function can be used instead to get an approximate RTC_SLOW_CLK
  frequency

- Clock calibration is performed at startup. The value is saved and used
  for timekeeping and when entering deep sleep.

- When using the 32k XTAL, startup code will wait for the oscillator to
  start up. This can be possibly optimized by starting a separate task
  to wait for oscillator startup, and performing clock switch in that
  task.

- Fix a bug that 32k XTAL would be disabled in rtc_clk_init.

- Fix a rounding error in rtc_clk_cal, which caused systematic frequency
  error.

- Fix an overflow bug which caused rtc_clk_cal to timeout early if the
  slow_clk_cycles argument would exceed certain value

- Improve 32k XTAL oscillator startup time by introducing bootstrapping
  code, which uses internal pullup/pulldown resistors on 32K_N/32K_P
  pins to set better initial conditions for the oscillator.

Ref TW11683.

Ref https://esp32.com/viewtopic.php?f=13&t=1570

Fixes https://github.com/espressif/esp-idf/issues/337.

See merge request !696
2017-04-26 14:01:59 +08:00
Ivan Grokhotkov
6353bc40d7 Add support for 32k XTAL as RTC_SLOW_CLK source
- RTC_CNTL_SLOWCLK_FREQ define is removed; rtc_clk_slow_freq_get_hz
  function can be used instead to get an approximate RTC_SLOW_CLK
  frequency

- Clock calibration is performed at startup. The value is saved and used
  for timekeeping and when entering deep sleep.

- When using the 32k XTAL, startup code will wait for the oscillator to
  start up. This can be possibly optimized by starting a separate task
  to wait for oscillator startup, and performing clock switch in that
  task.

- Fix a bug that 32k XTAL would be disabled in rtc_clk_init.

- Fix a rounding error in rtc_clk_cal, which caused systematic frequency
  error.

- Fix an overflow bug which caused rtc_clk_cal to timeout early if the
  slow_clk_cycles argument would exceed certain value

- Improve 32k XTAL oscillator startup time by introducing bootstrapping
  code, which uses internal pullup/pulldown resistors on 32K_N/32K_P
  pins to set better initial conditions for the oscillator.
2017-04-26 12:43:22 +08:00
Angus Gratton
e2479b46f7 secure boot: Fix bootloader image verification failure
* Failure prevented secure boot from enabling.
* Also adds unit test cases for esp_image_basic_verify()

Ref https://esp32.com/viewtopic.php?f=2&t=1602
TW11878
2017-04-26 11:23:35 +10:00
Ivan Grokhotkov
3323f31cfb soc: implement XTAL frequency detection
ROM code already implements XTAL frequency detection, but it uses the 8M
clock before the clock tuning parameters are initialized. With the
zero clock tuning parameter, 8M clock has significant frequency deviation
at high temperatures, which can lead to erroneous detection of 40 MHz
crystal as a 26 MHz one.

This change adds XTAL frequency detection code to rtc_clk_init routine,
and detection is performed after the 8M clock tuning parameter as been
initialized.
2017-04-24 15:29:30 +08:00
Alexey Gerenkov
77a92e6dcc esp32: Added dumping info from traceport upon reset by any WDT
- Last PC info and waiti mode indication are printed for both CPUs
 - Raw traceport regs values are printed only for log levels higher than DEBUG
2017-04-23 22:07:56 +03:00
Ivan Grokhotkov
404e89da4d Merge branch 'bugfix/rtc_reg_fields' into 'master'
soc: allow REG_SET_FIELD to be used for bit fields

- Fixes an issue with `rtc_clk_apll_enable`: https://esp32.com/viewtopic.php?f=13&t=1673
- Fixes `rtc_clk_fast_freq_set` function always selecting XTAL/4 as fast clock source.
- Fixes regression in deep sleep current (7uA instead of 5uA).

See merge request !674
2017-04-21 19:40:45 +08:00
Ivan Grokhotkov
6e9d60ef70 rtc_clk_init: handle case when XTAL frequency has already been set
On first reset, ROM code writes the estimated XTAL frequency into
RTC_APB_FREQ_REG (aka STORE5). If the application doesn’t specify exact
XTAL frequency (which is always the case for now), rtc_clk_init will
guess what kind of XTAL is used (26M or 40M), based on the estimated
frequency. Later, detected frequency is written into RTC_XTAL_FREQ_REG
(aka STORE4).

When the application switches clock source to PLL, APB frequency changes
and RTC_APB_FREQ_REG is updated. If the application encounters an RTC
WDT reset, RTC_APB_FREQ_REG will not be updated prior to reset. Once the
application starts up again, it will attempt to auto-detect XTAL
frequency based on RTC_APB_FREQ_REG, which now has value of 80000000.
This will fail, and rtc_clk_xtal_freq_estimate will fall back to the
default value of 26 MHz. Due to an incorrect XTAL frequency, PLL
initialization will also take incorrect path, and PLL will run at a
different frequency. Depending on the application this may cause just
garbage output on UART or a crash (if WiFi is used).
2017-04-21 10:33:58 +08:00
Ivan Grokhotkov
5d1bb42c18 soc: allow REG_SET_FIELD to be used with single-bit fields 2017-04-18 17:34:26 +08:00
Ivan Grokhotkov
faaf59ccb3 soc: define missing M, V macros for nrx, bb, fe, emac, iomux
Recipe:
- Add _M and _V for single-bit fields
  Search: (#define (\w+)\s*(\(BIT\(\d+\)\)))
  Replace: \1\n#define \2_M \3\n#define \2_V 1

- Add _M and _V for multi-bit fields
  Search: (#define (\w+)\s*(0x[\dA-Fa-f]+))
  Replace: \1\n#define \2_M (\2_V << \2_S)\n#define \2_V \3
2017-04-18 17:34:26 +08:00
Jeroen Domburg
0b79d07d34 add detection of invalid cache access
- fix level 4 interrupt vectors to produce correct backtrace
- initialize invalid cache access interrupt on startup
- handle invalid cache access in panic handler
2017-04-13 15:27:38 +08:00
Ivan Grokhotkov
3c6c1e36ec soc: add invalid cache access interrupt bits to dport_reg 2017-04-13 15:27:38 +08:00
Ivan Grokhotkov
7ee8ee8b7e soc: add source code of rtc_clk, rtc_pm 2017-04-11 15:45:54 +08:00
Ivan Grokhotkov
9ff446e6f9 soc: convert line endings to unix 2017-04-11 15:44:22 +08:00
Ivan Grokhotkov
d6dbf15a1f soc: move header files into soc component 2017-04-11 14:06:40 +08:00