Commit graph

394 commits

Author SHA1 Message Date
Jeroen Domburg
b52788e764 Add reserved DMA/internal region 2017-05-18 16:48:52 +08:00
Jeroen Domburg
5c13d7385c Remove superfluous task_is_internal check, port dport interrupt to separate int handler 2017-05-16 15:36:18 +08:00
Jeroen Domburg
754f574aab Rebasing to latest master 2017-05-16 14:10:59 +08:00
Jeroen Domburg
202a5db2d2 Rework high interrupt code to be able to link to external handlers; add psram test that swarms cpu with interrupts 2017-05-16 13:14:30 +08:00
Jeroen Domburg
e954277d7b Fix up tests for stack not in psram on flash, add small testcase 2017-05-16 13:12:59 +08:00
Jeroen Domburg
671787a966 After rebasing, it was found out that flushing the cache drops the writeback-pending psram cache lines on the ground. We now evict these by reading 64/128K of memory before flushing the cache. Also fixes a snafu in psram cache mode (inverted hi/lo and even/odd selectors) as well as an option to not let the heap allocator touch the psram. 2017-05-16 13:11:59 +08:00
Jeroen Domburg
84b728e7fd Some fixes to MR comments 2017-05-16 13:11:58 +08:00
Jeroen Domburg
0049b918b4 Fix psram silicon bug test; clean up Kconfig mess, clean out psram unused functions warnings 2017-05-16 13:11:56 +08:00
Jeroen Domburg
c6d01c2bd2 Fix dualcore PSRAM. 2017-05-16 13:11:30 +08:00
Jeroen Domburg
c9a2463f3b Add Doom psram test, fix free_heap_size/minimum_ever_heap_size calls to also understand combinations of caps, add psram support to allocator. At the moment, psram only works for the first core because of some funny business in the MMU of the 2nd core. 2017-05-16 13:10:52 +08:00
Jeroen Domburg
10402186bc Add internal memory capability to heap alloc, add some PSRAM tests 2017-05-16 13:09:50 +08:00
Wangjialin
0a88301fce update psram example files
1. update psram code
2. add missing files
3. add psram example
4. add mmu and psram init
2017-05-16 13:08:28 +08:00
Jiang Jiang Jian
bb25ac91f4 Merge branch 'bugfix/dualcore' into 'master'
component/soc: fix register access protection missing

- fix dport register access protection missing
- add rom function protect
- add normal register function check

See merge request !747
2017-05-12 18:19:31 +08:00
Tian Hao
377a1f5ea1 component/esp32 : do more fix of dualcore bug
1. the cache API in romcode will access DPORT register, so protect it.
2. fix STALL spelling.
3. check dport access by non-dport access function
2017-05-12 15:41:51 +08:00
Ivan Grokhotkov
15a6145961 Merge branch 'feature/get_chip_ver' into 'master'
add API to get chip info

This change adds an API to get chip info, such as chip model, enabled capabilities, size of embedded flash, silicon revision.

Hello_world example is modified to print out the information about the chip. The example is also simplified by moving all code into the main task.

Ref TW12031.

See merge request !549
2017-05-11 12:05:55 +08:00
Ivan Grokhotkov
c742f7d860 Merge branch 'feature/base_mac_address' into 'master'
Optimize configuration of base MAC address

Application developer can call APIs to configure base MAC address
instead of using menuconfig.

See merge request !744
2017-05-11 12:01:51 +08:00
Jiang Jiang Jian
c518325385 Merge branch 'bugfix/dualcore_dport' into 'master'
component/esp32 : fix dualcore bug

1. When dual core cpu run access DPORT register, must do protection.
2. If access DPORT register, must use DPORT_REG_READ/DPORT_REG_WRITE and DPORT_XXX register operation macro.

See merge request !742
2017-05-10 11:27:01 +08:00
XiaXiaotian
b22067a8f0 Optimize configuration of base MAC address
Application developer can call APIs to configure base MAC address
    instead of using menuconfig.
2017-05-10 10:15:07 +08:00
Tian Hao
26a3cb93c7 component/soc : move dport access header files to soc
1. move dport access header files to soc
2. reduce dport register write protection. Only protect read operation
2017-05-09 18:06:00 +08:00
Tian Hao
f7e8856520 component/esp32 : fix dualcore bug
1. When dual core cpu run access DPORT register, must do protection.
2. If access DPORT register, must use DPORT_REG_READ/DPORT_REG_WRITE and DPORT_XXX register operation macro.
2017-05-08 21:53:43 +08:00
Ivan Grokhotkov
2260c714e7 add esp_chip_info API 2017-05-05 17:28:30 +08:00
Jeroen Domburg
8af3fe4e84 Warn against and check for non-DMA-capable pointers being passed to SPI when DMA is used 2017-05-05 12:28:03 +08:00
Jiang Jiang Jian
899a5d223f Merge branch 'feature/opt_scan_before_connect' into 'master'
optimize scan before station connecting to AP

1. Store the information of AP(ssid, password, bssid, channel, etc)
    into nvs when station connects to AP successfully. If station
    connects to the same AP next time, it will scan the stored channel of the AP
    first.

2. Add a parameter of channel for scanning before connecting to AP.
    If the channel is set to 0, station will scan full channels. If it
    is set to 1~13, station will only scan the channel.

See merge request !704
2017-04-27 21:11:13 +08:00
XiaXiaotian
100d2dd938 optimize scan before station connecting to AP
1. Store the information of AP(ssid, password, bssid, channel, etc)
    into nvs when station connects to AP successfully. If station
    connects to the same AP next time, it will scan the stored channel of the AP
    first.

    2. Add a parameter of channel for scanning before connecting to AP.
    If it is set to 1~13, station will scan starting from the channel.
    If the channel of AP is unknown, set it to 0.
2017-04-27 14:28:52 +08:00
Ivan Grokhotkov
1324e565fa Merge branch 'bugfix/esp32_core_dump_sanity_checks' into 'master'
esp32: Core dump sanity checks

Adds sanity checks when doing core dump to flash

- CRC for core dump flash partition config
- Tasks with corrupted TCBs are skipped
- Assertions to check that nothing is written beyond core dump flash partition

Ref TW11879

See merge request !686
2017-04-27 10:43:58 +08:00
Alexey Gerenkov
98895af68b esp32: Core dump sanity checks were added
- CRC for core dump flash partition config
 - Tasks with corrupted TCBs are skipped
 - Assertions to check that nothing is written beyond core dump flash partition
2017-04-26 21:13:02 +03:00
Ivan Grokhotkov
6353bc40d7 Add support for 32k XTAL as RTC_SLOW_CLK source
- RTC_CNTL_SLOWCLK_FREQ define is removed; rtc_clk_slow_freq_get_hz
  function can be used instead to get an approximate RTC_SLOW_CLK
  frequency

- Clock calibration is performed at startup. The value is saved and used
  for timekeeping and when entering deep sleep.

- When using the 32k XTAL, startup code will wait for the oscillator to
  start up. This can be possibly optimized by starting a separate task
  to wait for oscillator startup, and performing clock switch in that
  task.

- Fix a bug that 32k XTAL would be disabled in rtc_clk_init.

- Fix a rounding error in rtc_clk_cal, which caused systematic frequency
  error.

- Fix an overflow bug which caused rtc_clk_cal to timeout early if the
  slow_clk_cycles argument would exceed certain value

- Improve 32k XTAL oscillator startup time by introducing bootstrapping
  code, which uses internal pullup/pulldown resistors on 32K_N/32K_P
  pins to set better initial conditions for the oscillator.
2017-04-26 12:43:22 +08:00
Jiang Jiang Jian
3f4e917ad6 Merge branch 'feature/ppp_over_serial' into 'master'
Enable experimental/unsupported PPP over Serial driver

From PR #272 https://github.com/espressif/esp-idf/pull/272

See merge request !690
2017-04-25 14:02:55 +08:00
XiaXiaotian
0c358c37f5 remove unneeded header file including 2017-04-24 16:11:26 +08:00
Jiang Jiang Jian
97142bb8db Merge branch 'feature/support_read_mac_addr_from_customer_efuse' into 'master'
Add customer MAC address that read from efuse



See merge request !673
2017-04-24 11:30:55 +08:00
XiaXiaotian
5553fbd537 add base MAC address storage choice.
Base MAC address can be stored in default manufacture-defined or customer
    pre-defined place in EFUSE and other place e.g. flash or EEPROM.
    If choose to use base MAC address which is stored in other place, please
    call esp_base_mac_addr_set_external() before initializing WiFi/BT/Ehternet.
2017-04-21 14:55:11 +08:00
Adrian Muzyka
47c722d674 Enable lwip PPPoS support
* Fix some lwip api bugs
 * Added PPP_SUPPORT parameter to lwip Kconfig
 * Added example pppos_client

Merges #272 https://github.com/espressif/esp-idf/pull/272
2017-04-21 14:23:34 +10:00
Alexey Gerenkov
55f1a63faf esp32: Adds functionality for application tracing over JTAG
- Implements application tracing module which allows to send arbitrary
   data to host over JTAG. This feature is useful for analyzing
   program modules behavior, dumping run-time application data etc.
 - Implements printf-like logging functions on top of apptrace module.
   This feature is a kind of semihosted printf functionality with lower
   overhead and impact on system behaviour as compared to standard printf.
2017-04-17 23:26:29 +03:00
Ivan Grokhotkov
15ec487fde Merge branch 'feature/esp32_d2wd_support' into 'master'
ESP32-D2WD support

Support ESP32-D2WD with integrated flash in ESP-IDF.

Includes fix for https://github.com/espressif/esp-idf/issues /521


See merge request !639
2017-04-14 20:57:39 +08:00
Jiang Jiang Jian
9050307dfe Merge branch 'feature/check_invalid_cache_access' into 'master'
Detect invalid cache access

This MR adds always-on feature which detects cache invalid access and triggers panic handler when invalid access interrupt is raised.


See merge request !660
2017-04-13 16:11:19 +08:00
Angus Gratton
f7793840e1 bootloader: Add QIO support for ESP32-D2WD SPI flash 2017-04-13 17:55:47 +10:00
Angus Gratton
85e76a7cfc spiflash ROM functions: Remove Quad I/O mode enable/disable code from flash ROM functions
Confusion here is that original ROM has two functions:

* SPIReadModeCnfig() - sets mode, calls enable_qio_mode/disable_qio_mode
* SPIMasterReadModeCnfig() - As above, but doesn't set QIO mode in status register

However we never want to use the ROM method to set/clear QIO mode flag, as not all flash chips work this way. Instead we
do it in flash_qio_mode.c in bootloader.

So in both cases (ROM or "patched ROM") we now call SPIMasterReadModeCnfig(), which is now named
esp_rom_spiflash_config_readmode().
2017-04-13 17:54:42 +10:00
Jeroen Domburg
0b79d07d34 add detection of invalid cache access
- fix level 4 interrupt vectors to produce correct backtrace
- initialize invalid cache access interrupt on startup
- handle invalid cache access in panic handler
2017-04-13 15:27:38 +08:00
XiaXiaotian
454d00e2ae check wifi state when wifi deinit is called 2017-04-13 14:34:40 +08:00
XiaXiaotian
d61959b583 change scanned ap's ssid array len to 33 2017-04-13 10:09:07 +08:00
Ivan Grokhotkov
9edab21385 Merge branch 'feature/rtc_clk_impl' into 'master'
Introduce soc component, add source of rtc_clk and rtc_pm libraries

This MR adds parts of the RTC library source code (initialization, clock selection functions, sleep functions). WiFi-related power management functions are kept inside the precompiled library. Most of RTC library APIs have been renamed.

Default CPU frequency option in Kconfig is set to 160MHz, pending qualification of 240MHz mode at high temperatures.

Register header files are moved into the new soc component, which will contain chip-specific header files and low-level non-RTOS-aware APIs (such as rtc_ APIs). Some of the files from ESP32 component were also moved: cpu_util.c, brownout.c, and the corresponding header files. Further refactoring of ESP32 component into more meaningful layers (chip-specific low level functions; chip-specific RTOS aware functions; framework-specific RTOS-related functions) will be done in future MRs.

See merge request !633
2017-04-12 10:38:23 +08:00
Ivan Grokhotkov
7ee8ee8b7e soc: add source code of rtc_clk, rtc_pm 2017-04-11 15:45:54 +08:00
Ivan Grokhotkov
d6dbf15a1f soc: move header files into soc component 2017-04-11 14:06:40 +08:00
Ivan Grokhotkov
724673be83 soc: add apb_ctrl, struct headers for rtc_cntl and rtc_io 2017-04-11 14:06:40 +08:00
Alexey Gerenkov
0860f46220 spi_flash: Fixed bug in SPI flash ROM driver to work with embedded flash chip
1) fixed SPI_read_status: added check for flash busy flag in matrix mode
2) fixed SPI_page_program: enable write before writing data to SPI FIFO
3) SPI flash ROM funcs replacement is controlled via menuconfig option
2017-04-11 10:51:19 +08:00
Ivan Grokhotkov
aa817a1475 Merge branch 'bugfix/esp_error_check_release_builds' into 'master'
fix warnings generated by ESP_ERROR_CHECK(variable) in release builds

This uses the same pattern as “assert” in release builds to silence the
warning. At the same time, we make sure that if a statement is wrapped
into ESP_ERROR_CHECK, it is executed in release build as well.

Fixes https://github.com/espressif/esp-idf/issues/497

See merge request !641
2017-04-10 12:18:47 +08:00
Ivan Grokhotkov
275b574ace fix warnings generated by ESP_ERROR_CHECK(variable) in release builds
This uses the same pattern as “assert” in release builds to silence the
warning. At the same time, we make sure that if a statement is wrapped
into ESP_ERROR_CHECK, it is executed in release build as well.
2017-04-07 15:24:58 +08:00
Ivan Grokhotkov
85e709705b Merge branch 'bugfix/btdm_task_priority' into 'master'
component/bt : modify bluetooth task priority

modify bluetooth task priority to lower than IPC task priority.

See merge request !631
2017-04-07 14:56:31 +08:00
Alexey Gerenkov
c142b9b9e5 esp32: RWDT is used to reboot system in case of panic handler crash
also fixes TG1WDG protection bug in panic handler
2017-04-07 02:34:29 +03:00
Tian Hao
ecb75b69fd component/bt : modify bluetooth task priority 2017-04-01 17:17:57 +08:00