Crash_Override/OVMS3-idf
1
0
Fork 0
Code Issues Pull requests Projects Releases Wiki Activity

Remove superfluous task_is_internal check, port dport interrupt to separate int handler

Browse source
This commit is contained in:
Jeroen Domburg 2017-05-16 15:36:18 +08:00
parent 5c50419aef
commit 5c13d7385c
6 changed files with 136 additions and 13 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
components/esp32/Kconfig
View file

@ -254,17 +254,6 @@ config MEMMAP_SPIRAM_ALLOC_LIMIT_INTERNAL
endif
choice NUMBER_OF_MAC_ADDRESS_GENERATED_FROM_EFUSE
bool "Number of MAC address generated from the hardware MAC address in efuse"
default FOUR_MAC_ADDRESS_FROM_EFUSE
help
Config the number of MAC address which is generated from the hardware MAC address in efuse.
If the number is two, the MAC addresses of WiFi station and bluetooth are generated from
the hardware MAC address in efuse. The MAC addresses of WiFi softap and ethernet are derived
from that of WiFi station and bluetooth respectively.
If the number is four, the MAC addresses of WiFi station, WiFi softap, bluetooth and ethernet
are all generated from the hardware MAC address in efuse.
choice NUMBER_OF_UNIVERSAL_MAC_ADDRESS
bool "Number of universally administered (by IEEE) MAC address"
default FOUR_UNIVERSAL_MAC_ADDRESS

1
components/esp32/component.mk
View file

@ -37,6 +37,7 @@ COMPONENT_ADD_LDFLAGS := -lesp32 \
-T esp32_out.ld \
-u ld_include_panic_highint_hdl \
-u ld_include_psram_tst \
-u ld_include_dport_int \
$(addprefix -T ,$(LINKER_SCRIPTS))
ALL_LIB_FILES := $(patsubst %,$(COMPONENT_PATH)/lib/lib%.a,$(LIBS))

101
components/esp32/dport_int.S Normal file
View file

@ -0,0 +1,101 @@
#include <xtensa/coreasm.h>
#include <xtensa/corebits.h>
#include <xtensa/config/system.h>
#include <xtensa/simcall.h>
#include "esp_panic.h"
#include "sdkconfig.h"
#include "soc/soc.h"
#include "soc/dport_reg.h"
#include "freertos/xtensa_context.h"
#define L5_INTR_STACK_SIZE 8
#define L5_INTR_A2_OFFSET 0
#define L5_INTR_A3_OFFSET 4
.data
_l5_intr_stack:
.space L5_INTR_STACK_SIZE
.section .iram1,"ax"
.global xt_highint5
.type _xt_highint5,@function
.align 4
_xt_highint5:
#ifdef XT_INTEXC_HOOKS
/* Call interrupt hook if present to (pre)handle interrupts. */
movi a0, _xt_intexc_hooks
l32i a0, a0, 5<<2
beqz a0, 1f
.Ln_xt_highint5_call_hook:
callx0 a0 /* must NOT disturb stack! */
1:
#endif
/* This section is for access dport register protection */
/* Allocate exception frame and save minimal context. */
/* Because the interrupt cause code have protection that only
allow one cpu enter in L5 interrupt at one time, so
there needn't have two _l5_intr_stack for each cpu */
movi a0, _l5_intr_stack
s32i a2, a0, L5_INTR_A2_OFFSET
s32i a3, a0, L5_INTR_A3_OFFSET
/* Check interrupt */
rsr a0, INTERRUPT
extui a0, a0, ETS_DPORT_INUM, 1 /* get dport int bit */
beqz a0, 1f
/* handle dport interrupt */
/* get CORE_ID */
getcoreid a0
beqz a0, 2f
/* current cpu is 1 */
movi a0, DPORT_CPU_INTR_FROM_CPU_3_REG
movi a2, 0
s32i a2, a0, 0 /* clear intr */
movi a0, 0 /* other cpu id */
j 3f
2:
/* current cpu is 0 */
movi a0, DPORT_CPU_INTR_FROM_CPU_2_REG
movi a2, 0
s32i a2, a0, 0 /* clear intr */
movi a0, 1 /* other cpu id */
3:
/* set and wait flag */
movi a2, dport_access_start
addx4 a2, a0, a2
movi a3, 1
s32i a3, a2, 0
memw
movi a2, dport_access_end
addx4 a2, a0, a2
.check_dport_access_end:
l32i a3, a2, 0
beqz a3, .check_dport_access_end
1:
movi a0, _l5_intr_stack
l32i a2, a0, L5_INTR_A2_OFFSET
l32i a3, a0, L5_INTR_A3_OFFSET
rsync /* ensure register restored */
rsr a0, EXCSAVE_5 /* restore a0 */
rfi 5
.align 4
.L_xt_highint5_exit:
rsr a0, EXCSAVE_5 /* restore a0 */
rfi 5
/* The linker has no reason to link in this file; all symbols it exports are already defined
(weakly!) in the default int handler. Define a symbol here so we can use it to have the
linker inspect this anyway. */
.global ld_include_dport_int
ld_include_dport_int:

33
components/esp32/include/esp_cache_err_int.h Normal file
View file

@ -0,0 +1,33 @@
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/**
* @brief initialize cache invalid access interrupt
*
* This function enables cache invalid access interrupt source and connects it
* to interrupt input number ETS_CACHEERR_INUM (see soc/soc.h). It is called
* from the startup code.
*/
void esp_cache_err_int_init();
/**
* @brief get the CPU which caused cache invalid access interrupt
* @return
* - PRO_CPU_NUM, if PRO_CPU has caused cache IA interrupt
* - APP_CPU_NUM, if APP_CPU has caused cache IA interrupt
* - (-1) otherwise
*/
int esp_cache_err_get_cpuid();

2
components/freertos/xtensa_vectors.S
View file

@ -116,7 +116,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define XIE_ARG 4
#define XIE_SIZE 8
/*
Macro get_percpu_entry_for - convert a per-core ID into a multicore entry.
Basically does reg=reg*portNUM_PROCESSORS+current_core_id
@ -137,6 +136,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
add \reg,\scratch,\reg
#endif
.endm
/*
--------------------------------------------------------------------------------
Macro extract_msb - return the input with only the highest bit set.

1
components/spi_flash/flash_ops.c
View file

@ -103,7 +103,6 @@ size_t IRAM_ATTR spi_flash_get_chip_size()
static inline void IRAM_ATTR spi_flash_guard_start()
{
assert(esp32_task_stack_is_internal() && "SPI operation called from task which has its stack in external memory");
if (s_flash_guard_ops && s_flash_guard_ops->start) {
s_flash_guard_ops->start();
}