Commit graph

449 commits

Author SHA1 Message Date
Renz Christian Bagaporo
2b100789b7 esp32, esp32s2: move panic handling code to new component 2020-03-10 19:56:24 +08:00
Renz Christian Bagaporo
db608736fb freertos: implement get core id with cpu abstraction 2020-02-27 07:14:21 +05:00
Sachin Parekh
301dacfb33 Exception handlers for LoadStoreError and LoadStoreAlignmentError
Configurable option to use IRAM as byte accessible memory (in single core mode) using
load-store (non-word aligned and non-word size IRAM access specific) exception handlers.
This allows to use IRAM for use-cases where certain performance penalty
(upto 170 cpu cycles per load or store operation) is acceptable. Additional configuration
option has been provided to redirect mbedTLS specific in-out content length buffers to
IRAM (in single core mode), allows to save 20KB per TLS connection.
2020-02-26 20:21:59 +08:00
Felipe Neves
9c8289b0d9 shared_stack: using watchpoint 1 to monitor the shared_stack instead of watchpoint 0 2020-02-10 12:03:30 -03:00
Konstantin Kondrashov
739eb05bb9 esp32: add implementation of esp_timer based on TG0 LAC timer
Closes: IDF-979
2020-02-06 14:00:18 +08:00
Angus Gratton
86034ad049 Merge branch 'feature/freertos_fpu_isr' into 'master'
feature/fpu: Enable usage of FPU inside of a ISR

Closes IDF-100

See merge request espressif/esp-idf!7348
2020-01-30 13:38:37 +08:00
Felipe Neves
429712c6eb freertos: moved all xtensa specific files into a separated folder 2020-01-27 16:05:30 -03:00
Felipe Neves
5cbb3f05c0 freertos: Added experimental, optional FPU usage on level 1 ISR 2020-01-27 10:55:03 -03:00
Felipe Neves
670ea56df2 freertos: added fpu in isr test case 2020-01-27 10:55:03 -03:00
Ivan Grokhotkov
cbb84e8f5e esp32s2: fix THREADPTR calculation, re-enable FreeRTOS TLS tests
1. Clarify THREADPTR calculation in FreeRTOS code, explaining where
the constant 0x10 offset comes from.

2. On the ESP32-S2, .flash.rodata section had different default
alignment (8 bytes instead of 16), which resulted in different offset
of the TLS sections. Unfortunately I haven’t found a way to query
section alignment from C code, or to use a constant value to define
section alignment in the linker script. The linker scripts are
modified to force a fixed 16 byte alignment for .flash.rodata on the
ESP32 and ESP32-S2beta. Note that the base address of .flash.rodata
was already 16 byte aligned, so this has not changed the actual
memory layout of the application.

Full explanation of the calculation below.

Assume we have the TLS template section base address
(tls_section_vma), the address of a TLS variable in the template
(address), and the final relocation value (offset). The linker
calculates:
offset = address - tls_section_vma + align_up(TCB_SIZE, alignment).

At run time, the TLS section gets copied from _thread_local_start
(in .rodata) to task_thread_local_start. Let’s assume that an address
of a variable in the runtime TLS section is runtime_address.
Access to this address will happen by calculating THREADPTR + offset.
So, by a series of substitutions:

THREADPTR + offset = runtime_address THREADPTR = runtime_address - offset
THREADPTR = runtime_address - (address - tls_section_vma + align_up(TCB_SIZE, alignment)) THREADPTR = (runtime_address - address) + tls_section_vma - align_up(TCB_SIZE, alignment)

The difference between runtime_address and address is same as the
difference between task_thread_local_start and _thread_local_start.
And tls_section_vma is the address of .rodata section, i.e.
_rodata_start. So we arrive to

THREADPTR = task_thread_local_start - _thread_local_start + _rodata_start - align_up(TCB_SIZE, alignment).

The idea with TCB_SIZE being added to the THREADPTR when computing
the relocation was to let the OS save TCB pointer in the TREADPTR
register. The location of the run-time TLS section was assumed to be
immediately after the TCB, aligned to whatever the section alignment
was. However in our case the problem is that the run-time TLS section
is stored not next to the TCB, but at the top of the stack. Plus,
even if it was stored next to the TCB, the size of a FreeRTOS TCB is
not equal to 8 bytes (TCB_SIZE hardcoded in the linker). So we have
to calculate THREADPTR in a slightly obscure way, to compensate for
these differences.

Closes IDF-1239
2020-01-23 11:29:22 +01:00
morris
e30cd361a8 global: rename esp32s2beta to esp32s2 2020-01-22 12:14:38 +08:00
Felipe Neves
73592d9bc4 spin_lock: added new spinlock interface and decoupled it from RTOS
spin_lock: cleaned-up port files and removed portmux files

components/soc: decoupled compare and set operations from FreeRTOS

soc/spinlock: filled initial implementation of spinlock refactor

It will decouple the spinlocks into separated components with not depencences of freertos
an similar interface was provided focusing the readabillity and maintenance, also
naming to spinlocks were adopted. On FreeRTOS side the legacy portMUX macros
gained a form of wrapper functions that calls the spinlocks component thus
minimizing the impact on RTOS side.

This feature aims to close IDF-967

soc/spinlock: spinlocks passed on unit test, missing test corner cases

components/compare_set: added better function namings plus minor performance optimization on spinlocks

soc/spinlock: code reordering to remove ISC C90 mix error

freertos/portmacro: gor rid of critical sections multiline macros, placed inline functions instead

soc/spinlock: improved spinlock performance from internal RAM

For cases where the spinlock is executed from IRAM, there is no
need to check where the spinlock object is placed on memory,
removing this checks caused a great improvement on performance.
2020-01-22 06:20:34 +08:00
Felipe Neves
5d7564a039 freertos/Kconfig: make optimized task selection dependent on FREERTOS_UNICORE option
freertos: fix decrement loop of high priority task selection
2020-01-14 09:58:14 -03:00
Felipe Neves
2c612ec1dc components/freertos: using the optimized task selection on esp32s2beta
components/freertos: cleaned up multicore option scheduler.

components/freertos:  more cleanup and test optimization to present realistic results

components/freertos: remove unused macros of optimized task selection when multicore is used
2020-01-14 09:58:14 -03:00
Felipe Neves
77bf1ff1c0 freertos/tests: added test to evaluate scheduling time
freertos/Kconfig: fix trailing space on optimized scheduler option

freertos/tests: moved test context variables inside of test task.

The public variables used on scheduling time test now were packed into a structure allocated on  test case task stack and passed to tasks as arguments saving RAM comsumption.
2020-01-14 09:58:14 -03:00
Felipe Neves
d4c82606fb components/freertos: added and enabled the optimized task selection
FreeRTOS  have an platform dependent configuration to enable selection task in a optimized way.

Provided the platform dependent functions in order to allow the scheduler to use the optimized algorithms by telling to the port layer where to found bitscan instruction i.e. NSAU.

This closes IDF-1116

components/freertos: added option to disable the optimized scheduler
2020-01-14 09:58:14 -03:00
Angus Gratton
bdf6c00154 Merge branch 'feature/likely_unlikely' into 'master'
Adding likely unlikely macros to hot code paths

Closes IDF-284

See merge request espressif/esp-idf!6368
2020-01-10 14:05:07 +08:00
Angus Gratton
6ab9f846c9 Merge branch 'bugfix/compare_and_setextram' into 'master'
bugfix/pthread: fix pthread_once() race condiion possibility adding critical section in compare and set function

Closes IDFGH-2448

See merge request espressif/esp-idf!7236
2020-01-10 12:29:54 +08:00
Krzysztof Bociurko
c7dfb435f8 Fixed error in return type of xTaskCreateStatic*
Signed-off-by: Darian <darian@espressif.com>

Merges https://github.com/espressif/esp-idf/pull/2651
2020-01-09 14:01:20 +08:00
Felipe Neves
9800750f15 freertos/port: Put critical sections around uxPortCompareSetExtram() to prevent preemption during its execution.
Closes: https://github.com/espressif/esp-idf/issues/4561
2020-01-07 10:53:30 -03:00
michael
4220752aed ut: Move tests back from "esp32" subfolder
DISABLED_FOR_TARGETS macros are used

Partly revert "ci: disable unavailable tests for esp32s2beta"

This partly reverts commit 76a3a5fb48.

Partly revert "ci: disable UTs for esp32s2beta without runners"

This partly reverts commit eb158e9a22.

Partly revert "fix unit test and examples for s2beta"

This partly reverts commit 9baa7826be.

Partly revert "efuse: Add support for esp32s2beta"

This partly reverts commit db84ba868c.
2020-01-06 17:13:53 +08:00
Felipe Neves
d059a955ae freertos: removed likely macros from non-port specifics parts of freertos
fatfs: moved esp_compiler header file inside of disk implementation file
2020-01-03 14:42:57 -03:00
Felipe Neves
1b76253e0e newlib/assert: placed unlikely macro as part of assertion
newlib/assert: replace unlikely with likely to keep original assertion

newlib/assert: fix assert macro that uses likely

freertos/port: add the missing sdkconfig.h back

newlib/assert: assert macro back to a single line
2020-01-03 14:42:55 -03:00
Felipe Neves
fc00236d79 components/esp_common: added esp_macros.h that aims to hold useful macros
esp_common/esp_compiler: renamed esp_macros file to a more specific one

esp_common/esp_compiler: removed CONTAINER_OF macro, it was a duplicate

components/freertos: placed likely macros around port and critical sections

component/freertos: placed likely macros on lists module

components/freertos: placed unlikely macros inside of assertion points, they likely wont fail

components/freertos: added likely macros on queue modules

FreeRTOS queues are one of most hot code path, because to queues itself tend to
be used a lot by the applications, besides that, queues are the basic primitive
to form both mutexes and semaphores, The focus here is to place likely
macros inside lowest level send and receive routines, since they're common
from all kobjects: semaphores, queues, mutexes and FR internals (like timer queue)

components/lwip: placed likely/unlikey on net-interfaces code

components/fatfs: added unlikely macros on disk drivers code

components/spiffs: added unlikely macros on low level fs driver

components/freertos: added likely/unlikely macros on timers and ticker

freertos/event_group: placed likely/unlikely macros on hot event group code paths

components/sdmmc: placed likely / unlikely macros on lower level path of sdmmc

components/bt: placed unlikely macros around bt HCI functions calling

components/lwip: added likely/unlikely macros on OS port code section

components/freertos: fix code style on tick handler
2020-01-03 14:42:49 -03:00
Ivan Grokhotkov
891eb3b020 freertos: save/restore PS and EPC1 around window spilling
Since in b0491307, which has introduced the optimized window spill
procedure, _xt_context_save did not work correctly when called from
_xt_syscall_exc. This was because unlike _xt_lowint1, _xt_syscall_exc
does not save PS and EPC1. The new version of _xt_context_save
modified PS (on purpose) and EPC1 (accidentally, due to window
overflow exceptions), which resulted in a crash upon 'rfi' from the
syscall.

This commit adds restoring of PS and EPC1 in _xt_context_save. It also
slightly reduces the number of instructions used to prepare PS for
window spill.

Unit test for setjmp/longjmp (which were broken by this regression)
is added.

Closes https://github.com/espressif/esp-idf/issues/4541
2019-12-27 11:27:01 +01:00
KonstantinKondrashov
1687c53700 freertos: Fix save_context. Add RSYNC after WSR
RSYNC waits for all previously fetched WSR.* instructions to be performed before inter-
preting the register fields of the next instruction.
2019-12-21 14:10:38 +00:00
Mahavir Jain
2e73c2818b freertos: re-enable mutext test for esp32s2beta 2019-12-16 11:55:32 +05:30
Angus Gratton
f50df36ebf Merge branch 'feature/external_github_prs' into 'master'
Include external github PRs

Closes IDFGH-2291, IDFGH-2306, IDFGH-2315, and IDFGH-2307

See merge request espressif/esp-idf!6931
2019-12-10 12:33:32 +08:00
Mahavir Jain
8e28226935 Disable few test cases for ESP32S2BETA
These test cases will be fixed in subsequent MR
2019-12-09 16:30:55 +05:30
Mahavir Jain
a737fd4865 Fix issue with timer usage in FreeRTOS tests 2019-12-09 13:33:45 +05:30
Andrei Gramakov
6cd17c1e8c freertos: added a FreeRTOS property returning "original" include path 2019-12-06 12:16:54 +01:00
Felipe Neves
57522059aa freertos/tests: fixed wrong header file on isr latency test 2019-12-04 10:41:00 -03:00
Felipe Neves
0ea6453b1c freertos: changed isr time test case variables to static 2019-12-04 10:41:00 -03:00
Felipe Neves
55cbc213f3 components/freertos: create the test task with highest priority to ensure peer-to-peer ISR to task sync 2019-12-04 10:40:27 -03:00
Felipe Neves
64a50f0423 components/freertos: fixed isr test failling when run multiple times 2019-12-04 10:40:27 -03:00
Felipe Neves
c64e108a1d components/freertos: removed CONFIG_FREERTOS_ISR_STATS the ISR test is now self contained 2019-12-04 10:39:22 -03:00
Felipe Neves
bcdc35be59 components/freertos: refactor of isr_latency tests to perform full measurement 2019-12-04 10:39:22 -03:00
Felipe Neves
8b6b97ec57 freertos/xtensa_context: fixed small typo 2019-12-04 10:39:22 -03:00
Felipe Neves
e480435879 components/freertos: removed some dead ifdefs 2019-12-04 10:39:22 -03:00
Felipe Neves
c14fc39b0a components/freertos: fixed typos and licence placement on external code 2019-12-04 10:39:22 -03:00
Felipe Neves
64f918bd70 freertos/xtensa_context: added conditional compiling option around isr cycle measurement
It is possible to enable and disable the isr time measurement on context save and
it related test via menuconfig by the new option: FREERTOS_ISR_STATS
2019-12-04 10:39:22 -03:00
Felipe Neves
346b12e29a freertos/test: added spill register timer measurement test 2019-12-04 10:39:22 -03:00
Felipe Neves
5ce7a33c87 freertos/xtensa_context.S: fix some dread tabs 2019-12-04 10:39:22 -03:00
Felipe Neves
cd11787153 freertos/xt_asm_utils: added documentation of current windows spill solution 2019-12-04 10:39:22 -03:00
Felipe Neves
768d115e85 freertos/Kconfig: removed isr optimization option from menuconfig 2019-12-04 10:39:22 -03:00
Felipe Neves
eb740ca8e4 freertos/xtensa_context: modification of interrupt handler is workin, needs stabilization 2019-12-04 10:39:22 -03:00
Felipe Neves
d185625162 freertos/xtensa_context: added infrastructure to receive the spill register optimized code 2019-12-04 10:39:22 -03:00
Michael (XIAO Xufeng)
087c8f6065 essl: new component to communicate with esp serial slave devices 2019-12-03 22:58:41 +08:00
Ivan Grokhotkov
477e66103c Merge branch 'feature/esp32s2beta_apptrace_port' into 'master'
esp32s2: Adds apptrace support

Closes IDF-510 and IDF-1032

See merge request espressif/esp-idf!5610
2019-11-22 05:33:35 +08:00
chenjianqiang
9f9da9ec96 feat(timer): refator timer group driver
1. add hal and low-level layer for timer group
2. add callback functions to handle interrupt
3. add timer deinit function
4. add timer spinlock take function
2019-11-21 14:14:19 +08:00