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freertos/test: added spill register timer measurement test

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This commit is contained in:
Felipe Neves 2019-10-14 23:32:31 -03:00
parent 5ce7a33c87
commit 346b12e29a
3 changed files with 81 additions and 5 deletions
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61
components/freertos/test/test_improved_isr_time.c Normal file
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@ -0,0 +1,61 @@
#include <esp_types.h>
#include <stdio.h>
#include "esp32/rom/ets_sys.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "freertos/queue.h"
#include "freertos/xtensa_api.h"
#include "esp_intr_alloc.h"
#include "xtensa/hal.h"
#include "unity.h"
#include "soc/cpu.h"
#include "test_utils.h"
static SemaphoreHandle_t end_sema;
extern uint32_t isr_enter_spent_time_cycles;
volatile static uint32_t isr_enter_spent_time_cycles_copy;
static void testint(void *arg) {
xthal_set_ccompare(1, xthal_get_ccount()+8000000);
}
static void nested3(void) {
intr_handle_t handle;
esp_err_t err = esp_intr_alloc(ETS_INTERNAL_TIMER1_INTR_SOURCE, 0, &testint, NULL, &handle);
TEST_ASSERT_EQUAL_HEX32(ESP_OK, err);
xthal_set_ccompare(1, xthal_get_ccount()+8000000);
vTaskDelay(10);
isr_enter_spent_time_cycles_copy = isr_enter_spent_time_cycles;
ets_printf("Average time spent on context save is: %d cycles\n\n", isr_enter_spent_time_cycles_copy);
xSemaphoreGive(end_sema);
vTaskDelete(NULL);
}
static void nested2(void) {
nested3();
}
static void nested1(void) {
nested2();
}
static void test_task(void *arg) {
(void)arg;
nested1();
}
TEST_CASE("isr handling time test", "[freertos]")
{
end_sema = xSemaphoreCreateBinary();
TEST_ASSERT(end_sema != NULL);
xTaskCreatePinnedToCore(test_task, "tst" , 4096, NULL, 3, NULL, 0);
BaseType_t result = xSemaphoreTake(end_sema, portMAX_DELAY);
TEST_ASSERT_EQUAL_HEX32(pdTRUE, result);
TEST_PERFORMANCE_LESS_THAN(SPILL_REG_CYCLES, "%d cycles" ,isr_enter_spent_time_cycles_copy);
}

24
components/freertos/xtensa_context.S
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@ -57,10 +57,19 @@ NOERROR: .error "C preprocessor needed for this file: make sure its filename\
#include <xtensa/overlay_os_asm.h>
#endif
/*
--------------------------------------------------------------------------------
ISR overhead statistics data:
--------------------------------------------------------------------------------
*/
.data
.align 16
.global isr_enter_spent_time_cycles
isr_enter_spent_time_cycles:
.word 0
.text
/*******************************************************************************
_xt_context_save
@ -99,7 +108,6 @@ Exit conditions:
.literal_position
.align 4
_xt_context_save:
s32i a2, sp, XT_STK_A2
s32i a3, sp, XT_STK_A3
s32i a4, sp, XT_STK_A4
@ -182,10 +190,17 @@ _not_l1:
and a2, a2, a3
wsr a2, PS
rsync
rsr a2, CCOUNT
addi sp, sp, XT_STK_FRMSZ /* go back to spill register region */
SPILL_ALL_WINDOWS /* place the live register windows there */
addi sp, sp, -XT_STK_FRMSZ /* return the current stack pointer and proceed with conext save*/
rsr a3, CCOUNT
sub a3, a3, a2
movi a2, isr_enter_spent_time_cycles
s32i a3,a2,0
#endif
l32i a12, sp, XT_STK_TMP0 /* temp. save stuff in stack frame */
@ -197,7 +212,6 @@ _not_l1:
#endif
ret
/*******************************************************************************
_xt_context_restore

1
components/idf_test/include/idf_performance.h
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@ -32,6 +32,7 @@
#define IDF_PERFORMANCE_MAX_ESP32_CYCLES_PER_SQRT 140
// SHA256 hardware throughput at 240MHz, threshold set lower than worst case
#define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC 9.0
#define IDF_PERFORMANCE_MAX_SPILL_REG_CYCLES 150
#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 19000
#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 180000