Commit graph

124 commits

Author SHA1 Message Date
Angus Gratton
871ba41a09 bootloader: Remove unnecessary KEEP on data/bss sections, save static RAM 2017-07-19 18:31:59 +10:00
Angus Gratton
d1b66a08c1 bootloader: Add option to build with Link Time Optimisation enabled 2017-07-19 18:31:59 +10:00
Angus Gratton
17adb40ca8 bootloader: Calculate SHA256 hash of image on every boot
Makes app image booting more reliable (256-bit rather than 8-bit verification.)

Some measurements, time to boot a 655KB app.bin file and run to app_main() execution.

(All for rev 1 silicon, ie no 340ms spurious WDT delay.)

80MHz QIO mode:
before = 300ms
after = 140ms

40MHz DIO mode:
before = 712ms
after = 577ms

40MHz DIO mode, secure boot enabled
before = 1380ms
after = 934ms

(Secure boot involves two ECC signature verifications (partition table, app) that take approx 300ms each with 80MHz CPU.)
2017-07-19 18:31:59 +10:00
Angus Gratton
0c8888d68f bootloader: Combine loading from flash & verifying to save boot time
Still needs updating to account for secure boot.
2017-07-19 18:25:17 +10:00
Angus Gratton
ec64fa3416 bootloader flash QIO mode: Restore DIO/DOUT mode if enabling quad fails
Previously, flash was degraded to single I/O mode.
2017-07-19 15:04:09 +10:00
Angus Gratton
0715d1f8c1 bootloader: When customising SPI flash pins in efuse, set WP pin in menuconfig
Allows custom configurations for QIO/QOUT mode.
2017-07-19 15:04:08 +10:00
Angus Gratton
d664e32394 build system: Use component.mk for all components, refactor bootloader build
For config-only components, component.mk should now contain "COMPONENT_CONFIG_ONLY := 1"

Also refactored some of the generation of linker paths, library list. This required cleaning up the way the bootloader
project works, it's now mostly independent from the parent.
2017-07-19 09:10:48 +10:00
Angus Gratton
2b0f623259 bootloader/early boot: Error out if >192KB of static DRAM is allocated (temporary fix)
Currently the last 128KB of DRAM is reserved for the bootloader & early boot stacks. This means if >192KB of static DRAM
is allocated, the only available heap is this region - which is disabled until the scheduler starts. As a result, you
get either heap corruption on early boot if the static data overlaps startup heap (leading to very weird errors), or
FreeRTOS will fail to start when it can't malloc() anything.

Long term fix is to move the stacks & bootloader data to the very end of RAM, and only reserve that part for early
boot. This is a little fiddly because of also wanting to make sure this memory is not preemptively fragmented when it
gets reintroduced to the heap. This will become more important if/when we have more static allocation options in the
future.

For now, these errors make it clear why the boot has failed.

Ref TW13909
2017-07-12 13:06:56 +08:00
Ivan Grokhotkov
75658ee29b bootloader: workaround for clock switching bug in ESP32 rev. 0
In ESP32 rev. 0, switching between 240MHz and 80MHz (even via an
intermediate frequency of 40MHz) may cause the chip to lock up.
The bootloader used to enable 80MHz CPU clock at startup, which could
cause lock up after software reset. With this change, if 240MHz CPU
clock is enabled in menuconfig, bootloader will also use 240MHz to avoid
lock-up.
2017-06-15 18:15:35 +08:00
jack
ba32dd30a1 bugfix:Fix bug that wdt reset information for CPU1 was not correct 2017-06-05 18:26:14 +08:00
Tian Hao
26a3cb93c7 component/soc : move dport access header files to soc
1. move dport access header files to soc
2. reduce dport register write protection. Only protect read operation
2017-05-09 18:06:00 +08:00
Tian Hao
f7e8856520 component/esp32 : fix dualcore bug
1. When dual core cpu run access DPORT register, must do protection.
2. If access DPORT register, must use DPORT_REG_READ/DPORT_REG_WRITE and DPORT_XXX register operation macro.
2017-05-08 21:53:43 +08:00
Ivan Grokhotkov
fe695a9af8 Merge branch 'feature/cpu_restart_sequence' into 'master'
Restart sequence requires set up for app cpu.

These changes required to make correct restart of CPU form JTAG.

See merge request !703
2017-04-27 09:30:42 +08:00
Ivan Grokhotkov
0fe765a977 Merge branch 'feature/32k_xtal' into 'master'
add support for 32k XTAL as RTC_SLOW_CLK source

- RTC_CNTL_SLOWCLK_FREQ define is removed; rtc_clk_slow_freq_get_hz
  function can be used instead to get an approximate RTC_SLOW_CLK
  frequency

- Clock calibration is performed at startup. The value is saved and used
  for timekeeping and when entering deep sleep.

- When using the 32k XTAL, startup code will wait for the oscillator to
  start up. This can be possibly optimized by starting a separate task
  to wait for oscillator startup, and performing clock switch in that
  task.

- Fix a bug that 32k XTAL would be disabled in rtc_clk_init.

- Fix a rounding error in rtc_clk_cal, which caused systematic frequency
  error.

- Fix an overflow bug which caused rtc_clk_cal to timeout early if the
  slow_clk_cycles argument would exceed certain value

- Improve 32k XTAL oscillator startup time by introducing bootstrapping
  code, which uses internal pullup/pulldown resistors on 32K_N/32K_P
  pins to set better initial conditions for the oscillator.

Ref TW11683.

Ref https://esp32.com/viewtopic.php?f=13&t=1570

Fixes https://github.com/espressif/esp-idf/issues/337.

See merge request !696
2017-04-26 14:01:59 +08:00
Dmitry Yakovlev
00aa73c6cf Restart sequence requires set up for app cpu. 2017-04-26 07:47:37 +03:00
Ivan Grokhotkov
6353bc40d7 Add support for 32k XTAL as RTC_SLOW_CLK source
- RTC_CNTL_SLOWCLK_FREQ define is removed; rtc_clk_slow_freq_get_hz
  function can be used instead to get an approximate RTC_SLOW_CLK
  frequency

- Clock calibration is performed at startup. The value is saved and used
  for timekeeping and when entering deep sleep.

- When using the 32k XTAL, startup code will wait for the oscillator to
  start up. This can be possibly optimized by starting a separate task
  to wait for oscillator startup, and performing clock switch in that
  task.

- Fix a bug that 32k XTAL would be disabled in rtc_clk_init.

- Fix a rounding error in rtc_clk_cal, which caused systematic frequency
  error.

- Fix an overflow bug which caused rtc_clk_cal to timeout early if the
  slow_clk_cycles argument would exceed certain value

- Improve 32k XTAL oscillator startup time by introducing bootstrapping
  code, which uses internal pullup/pulldown resistors on 32K_N/32K_P
  pins to set better initial conditions for the oscillator.
2017-04-26 12:43:22 +08:00
Angus Gratton
08cfcbb6ea bootloader: Add some debug logging around OTA selection 2017-04-26 11:23:35 +10:00
Angus Gratton
e2479b46f7 secure boot: Fix bootloader image verification failure
* Failure prevented secure boot from enabling.
* Also adds unit test cases for esp_image_basic_verify()

Ref https://esp32.com/viewtopic.php?f=2&t=1602
TW11878
2017-04-26 11:23:35 +10:00
Ivan Grokhotkov
6b237de909 Add XTAL frequency selection to Kconfig
This change allows XTAL frequency to be selected using menuconfig
2017-04-24 15:55:02 +08:00
Alexey Gerenkov
77a92e6dcc esp32: Added dumping info from traceport upon reset by any WDT
- Last PC info and waiti mode indication are printed for both CPUs
 - Raw traceport regs values are printed only for log levels higher than DEBUG
2017-04-23 22:07:56 +03:00
Ivan Grokhotkov
15ec487fde Merge branch 'feature/esp32_d2wd_support' into 'master'
ESP32-D2WD support

Support ESP32-D2WD with integrated flash in ESP-IDF.

Includes fix for https://github.com/espressif/esp-idf/issues /521


See merge request !639
2017-04-14 20:57:39 +08:00
Angus Gratton
f7793840e1 bootloader: Add QIO support for ESP32-D2WD SPI flash 2017-04-13 17:55:47 +10:00
Angus Gratton
85e76a7cfc spiflash ROM functions: Remove Quad I/O mode enable/disable code from flash ROM functions
Confusion here is that original ROM has two functions:

* SPIReadModeCnfig() - sets mode, calls enable_qio_mode/disable_qio_mode
* SPIMasterReadModeCnfig() - As above, but doesn't set QIO mode in status register

However we never want to use the ROM method to set/clear QIO mode flag, as not all flash chips work this way. Instead we
do it in flash_qio_mode.c in bootloader.

So in both cases (ROM or "patched ROM") we now call SPIMasterReadModeCnfig(), which is now named
esp_rom_spiflash_config_readmode().
2017-04-13 17:54:42 +10:00
Ivan Grokhotkov
9edab21385 Merge branch 'feature/rtc_clk_impl' into 'master'
Introduce soc component, add source of rtc_clk and rtc_pm libraries

This MR adds parts of the RTC library source code (initialization, clock selection functions, sleep functions). WiFi-related power management functions are kept inside the precompiled library. Most of RTC library APIs have been renamed.

Default CPU frequency option in Kconfig is set to 160MHz, pending qualification of 240MHz mode at high temperatures.

Register header files are moved into the new soc component, which will contain chip-specific header files and low-level non-RTOS-aware APIs (such as rtc_ APIs). Some of the files from ESP32 component were also moved: cpu_util.c, brownout.c, and the corresponding header files. Further refactoring of ESP32 component into more meaningful layers (chip-specific low level functions; chip-specific RTOS aware functions; framework-specific RTOS-related functions) will be done in future MRs.

See merge request !633
2017-04-12 10:38:23 +08:00
Ivan Grokhotkov
7ee8ee8b7e soc: add source code of rtc_clk, rtc_pm 2017-04-11 15:45:54 +08:00
Alexey Gerenkov
0860f46220 spi_flash: Fixed bug in SPI flash ROM driver to work with embedded flash chip
1) fixed SPI_read_status: added check for flash busy flag in matrix mode
2) fixed SPI_page_program: enable write before writing data to SPI FIFO
3) SPI flash ROM funcs replacement is controlled via menuconfig option
2017-04-11 10:51:19 +08:00
Ivan Grokhotkov
61c33ca24e make: don’t override TEST_COMPONENTS
When idf_monitor is launched from make, it gets modified TEST_COMPONENTS
variable which contains full paths to the test components instead of the
names. This causes TEST_COMPONENT_PATHS to be empty and the unit test
app gets built without any test components.

This change introduces an internal TEST_COMPONENTS_LIST variable which
gets set either from $(COMPONENTS) if TESTS_ALL is 1, and from
TEST_COMOPONENTS otherwise.
Bootloader makefile is also fixed to avoid propagating TESTS_ALL to the
bootloader build step.
2017-03-09 19:43:39 +08:00
Ivan Grokhotkov
8911e666a0 Merge branch 'feature/docs_partition_ota_flash' into 'master'
Partition/SPI/OTA docs & OTA new functionality

* Update partition, SPI flash & OTA docs to reflect functionality changes
* Refactor OTA implementation to perform checks mentioned in API doc
* Add new functions to OTA API: esp_ota_get_running_partition() & esp_ota_get_next_update_partition() functions
* Add spi_flash_cache2phys() & spi_flash_phys2cache() functions to support esp_ota_get_running_partition()


See merge request !513
2017-03-03 11:27:01 +08:00
Ivan Grokhotkov
848494b20f Merge branch 'feature/enable_qio_directly' into 'master'
Enable SPI flash Quad I/O in bootloader

Bootloader checks flash ID, enables Quad I/O mode based on flash type.

See merge request !479
2017-03-03 11:25:52 +08:00
Angus Gratton
c3544dc090 Build system: Fix error if librtc submodule not available to bootloader
Closes #220 https://github.com/espressif/esp-idf/issues/220
2017-02-22 11:59:37 +11:00
Angus Gratton
1f3a2e900c docs: Improve/clarify partition, OTA & SPI flash docs
Related to #313 https://github.com/espressif/esp-idf/issues/313
2017-02-20 15:31:42 +11:00
XiaXiaotian
eb14284c92 disable PHY and RF when stop WiFi and disable BT
1. Add disable PHY and RF when WiFi and BT are both disabled(including call sniffer disable API).

2. Do not init PHY and RF when cpu start. Init PHY and RF when call Wifi or BT start APIs(including sniffer enable API).

3. Add a temporary lib: librtc_clk.a and will delete it when CPU frequency switching function is done.

4. Add an function to get OS tick rate.

5. Do not put the whole pp.a in iram0, only put lmac.o, ieee80211_misc.o, ets_time.o and wdev.o in iram0.
2017-02-17 10:24:54 +08:00
Ivan Grokhotkov
413f05ce09 Merge branch 'docs/flash_encryption_disable' into 'master'
Docs: Document flash encryption disable steps, clean up flash encryption & secure boot docs

Generate clean up of flash encryption & secure boot docs

Including steps for disabling flash encryption (for people who accidentally enable it).

See merge request !500
2017-02-15 13:31:08 +08:00
Angus Gratton
7c7edab328 flash encryption/secure boot: Restructure documentation
Also add steps to disable flash encryption, as some people seem to
accidentally enable it.

Explicitly mark the flash encryption and secure boot as "READ DOCS
FIRST" in menuconfig.
2017-02-15 09:42:46 +11:00
Angus Gratton
76d4f65ff9 bootloader: Add more flexible QIO support, for non-orthogonal command sets
Should allow enabling QIO mode on WinBond (not yet tested).
2017-02-09 08:44:05 +11:00
Angus Gratton
68cba2a1fb Bootloader: Support switching to Quad I/O mode during boot process 2017-02-09 08:44:05 +11:00
Angus Gratton
813395adcb OTA: Fall back to factory partition if ota data partition is invalid 2017-01-26 16:20:06 +11:00
Ivan Grokhotkov
8c26dd8d38 Merge branch 'feature/idf_version' into 'master'
build system: add IDF_VER environment variable and preprocessor define

This adds an `IDF_VER` preprocessor define which is obtained from `git describe`.

Looks like `v1.0-275-g0efaa4f` for non-release version or `v2.0` for a tagged (release) version.

See merge request !403
2017-01-11 11:34:28 +08:00
Ivan Grokhotkov
89e0ecc272 build system: add IDF_VER environment variable and preprocessor define 2017-01-11 00:24:50 +08:00
Ivan Grokhotkov
c1b06bf0a2 bootloader: export ets_update_cpu_frequency 2017-01-09 03:08:24 +08:00
Ivan Grokhotkov
339267ffc9 Merge branch 'feature/bootloader_rng' into 'master'
Enable bootloader entropy source for RNG

Enables an entropy source when bootloader starts up, which both seeds the RNG for use before WiFi/BT stack is enabled and provides an adequate RNG for secure boot & flash encryption key generation.

A prerequisite was enabling 80MHz operation, so the CPU is now set to 80MHz as soon as second stage bootloader starts running.

See merge request !363
2017-01-07 18:46:10 +08:00
Ivan Grokhotkov
0b264f4f7b bootloader: update ld script comment 2017-01-06 13:47:53 +08:00
Liu Zhi Fu
1b38494df4 bootloader: modify bootloader dram start address to 0x3fff0000
Modify bootloader dram_seg from address 0x3ffc0000 to 0x3fff0000, len from
0x20000 to 0x10000. Please be notified that this is just a workaround for
fixing app data overwrite bootloader data issue!
2017-01-06 13:44:09 +08:00
Angus Gratton
3922ce47b2 bootloader: Enable early boot RNG entropy source
This reverts commit ceb8566970.
2017-01-04 17:07:12 +11:00
Angus Gratton
83442526e0 bootloader: Allow custom baud rate on UART 0 2017-01-04 16:24:12 +11:00
Angus Gratton
2e3ca1c2f7 bootloader: Boost bootloader CPU to 80MHz
Partially needed to use RNG, also useful to improve boot performance.
2017-01-04 16:07:19 +11:00
Angus Gratton
76e61ded30 bootloader: Call esp_partition_table_basic_verify() as part of standard boot
Was previously only verified during flash encryption.
2016-12-30 14:19:46 +11:00
Angus Gratton
d245f016ea esptool: Add new options to reset before/after, detect flash size 2016-12-30 14:19:46 +11:00
Ivan Grokhotkov
05fcdcfedb Merge branch 'bugfix/make_erase_flash' into 'master'
build system: Fix bug where erase_flash was always invoked for flash

Order-only prerequisites do not work for phony targets!

See merge request !337
2016-12-25 09:13:58 +08:00
Angus Gratton
abb7668af7 build system: Fix bug where erase_flash was always invoked for flash
Order-only prerequisites do not work for phony targets!
2016-12-22 16:37:28 +11:00