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bootloader: When customising SPI flash pins in efuse, set WP pin in menuconfig

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Allows custom configurations for QIO/QOUT mode.
This commit is contained in:
Angus Gratton 2017-06-20 10:47:46 +10:00
parent d436331faf
commit 0715d1f8c1
2 changed files with 31 additions and 14 deletions
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21
components/bootloader/Kconfig.projbuild
View file

@ -28,8 +28,22 @@ config LOG_BOOTLOADER_LEVEL
default 4 if LOG_BOOTLOADER_LEVEL_DEBUG
default 5 if LOG_BOOTLOADER_LEVEL_VERBOSE
endmenu
config BOOTLOADER_SPI_WP_PIN
int "SPI Flash WP Pin when customising pins via efuse (read help)"
range 0 33
default 7
depends on FLASHMODE_QIO || FLASHMODE_QOUT
help
This value is ignored unless flash mode is set to QIO or QOUT *and* the SPI flash pins have been
overriden by setting the efuses SPI_PAD_CONFIG_xxx.
When this is the case, the Efuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka ESP32
pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in Efuse. That pin number is compiled into the bootloader
instead.
The default value (GPIO 7) is correct for WP pin on ESP32-D2WD integrated flash.
endmenu # Bootloader
menu "Security features"
@ -212,6 +226,5 @@ config SECURE_BOOT_TEST_MODE
This option is for testing purposes only - it completely disables secure boot protection.
endmenu # potentially insecure
endmenu
endmenu # Potentially Insecure
endmenu # Security features

24
components/bootloader/subproject/main/flash_qio_mode.c
View file

@ -35,9 +35,6 @@
#define CMD_RDSR 0x05
#define CMD_RDSR2 0x35 /* Not all SPI flash uses this command */
#define ESP32_D2WD_WP_GPIO 7 /* ESP32-D2WD has this GPIO wired to WP pin of flash */
static const char *TAG = "qio_mode";
typedef unsigned (*read_status_fn_t)();
@ -67,6 +64,12 @@ static void write_status_8b_wrsr2(unsigned new_status);
/* Write 16 bit status using WRSR */
static void write_status_16b_wrsr(unsigned new_status);
#define ESP32_D2WD_WP_GPIO 7 /* ESP32-D2WD has this GPIO wired to WP pin of flash */
#ifndef CONFIG_BOOTLOADER_SPI_WP_PIN // Set in menuconfig if SPI flasher config is set to a quad mode
#define CONFIG_BOOTLOADER_SPI_WP_PIN ESP32_D2WD_WP_GPIO
#endif
/* Array of known flash chips and data to enable Quad I/O mode
Manufacturer & flash ID can be tested by running "esptool.py
@ -160,15 +163,16 @@ static void enable_qio_mode(read_status_fn_t read_status_fn,
const uint32_t spiconfig = ets_efuse_get_spiconfig();
if (spiconfig != EFUSE_SPICONFIG_SPI_DEFAULTS && spiconfig != EFUSE_SPICONFIG_HSPI_DEFAULTS) {
// spiconfig specifies a custom efuse pin configuration. This config defines all pins -except- WP.
// spiconfig specifies a custom efuse pin configuration. This config defines all pins -except- WP,
// which is compiled into the bootloader instead.
//
// For now, in this situation we only support Quad I/O mode for ESP32-D2WD where WP pin is known.
// Most commonly an overriden pin mapping means ESP32-D2WD. Warn if chip is ESP32-D2WD
// but someone has changed the WP pin assignment from that chip's WP pin.
uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_RESERVE);
uint32_t pkg_ver = chip_ver & 0x7;
const uint32_t PKG_VER_ESP32_D2WD = 2; // TODO: use chip detection API once available
if (pkg_ver != PKG_VER_ESP32_D2WD) {
ESP_LOGE(TAG, "Quad I/O is only supported for standard pin numbers or ESP32-D2WD. Falling back to Dual I/O.");
return;
const int PKG_VER_ESP32_D2WD = 2; // TODO: use chip detection API once available
if (pkg_ver == PKG_VER_ESP32_D2WD && CONFIG_BOOTLOADER_SPI_WP_PIN != ESP32_D2WD_WP_GPIO) {
ESP_LOGW(TAG, "Chip is ESP32-D2WD but flash WP pin is different value to internal flash");
}
}
@ -205,7 +209,7 @@ static void enable_qio_mode(read_status_fn_t read_status_fn,
esp_rom_spiflash_config_readmode(mode);
esp_rom_spiflash_select_qio_pins(ESP32_D2WD_WP_GPIO, spiconfig);
esp_rom_spiflash_select_qio_pins(CONFIG_BOOTLOADER_SPI_WP_PIN, spiconfig);
}
static unsigned read_status_8b_rdsr()