This commit adds support for CPU max freqeuency rating
bits in CPU. Bootloader will now print an error if attempting
to 160MHz rated ESP32 at 240MHz.
EFUSE_CHIP_VER_RESERVE has been replaced by the
frequency rating bits. Dependancies on EFUSE_CHIP_VER_RESERVE
have been changed to use EFUSE_CHIP_VER_PKG
This commit removes the lookup table mode due to inferior performance when compared
to linear mode under attenuation 0, 1 and 2. However small portions of the lookup table
are kept for the higher voltages of atten 3 (above ADC reading 2880). That voltage range
in atten 3 has non linear characteristics making the LUT performan better than linear mode.
This commit updates the esp_adc_cal ocmponent to support new calibration methods
which utilize calibratoin values stored in eFuse. This commit includes LUT mode
The TRM describes IOMUX registers are IO_MUX_x_REG for x in GPIO0-39.
Until now ESP-IDF describes them as PERIPHS_IO_MUX_(pinname)_U
This commit adds additional IOMUX register names which match the ones used in the TRM.
1. move settings of WIFI_CLK_EN_REG for bluetooth into controller init/deinit APIs
2. modify the bit mask used in phy_rf init/deinit to use WIFI-BT shared bits
Previously esp_restart would stall the other CPU before enabling RTC_WDT.
If the other CPU was executing an s32c1i instruction, the lock signal
from CPU to the arbiter would still be held after CPU was stalled. If
the CPU running esp_restart would then try to access the same locked
memory pool, it would be stuck, because lock signal would never be
released.
With this change, esp_restart resets the other CPU before stalling it.
Ideally, we would want to reset the CPU and keep it in reset, but the
hardware doesn't have such feature for PRO_CPU (it is possible to hold
APP_CPU in reset using DPORT register). Given that ROM code will not use
s32c1i in the first few hundred cycles, doing reset and then stall seems
to be safe.
In addition to than, RTC_WDT initialization is moved to the beginning of
the function, to prevent possible lock-up if CPU stalling still has any
issue.
Some RTC features are synchronized to RTC_SLOW_CLK, so sometimes
software needs to wait for the next slow clock cycle.
This function implements waiting using Timer Group clock calibration
feature.
append adc support and api
- esp_err_t adc2_config_width(adc_bits_width_t width_bit);
- esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten);
- int adc2_get_voltage(adc2_channel_t channel);
Internal byte accessible memory starts with Internal ROM 1 at 0x3FF90000.
Region of RTC fast memory starting at 0x3FF80000 is not used in IDF as
it is mapped to PRO CPU only.
1. Support built-in ADC for I2S.
2. Modify code of ADC, made no change to the original APIs.
3. Add APIs in I2S:
esp_err_t i2s_set_adc_mode(adc_unit_t adc_unit, adc1_channel_t adc_channel);
4. Add I2S ADC/DAC example code.
5. add old-fashion definition to make it more compatible
6. replase spi_flash_ APIs with esp_partition_ APIs
7. add example of generating audio table from wav
8. change example sound
All peripheral clocks are default enabled after chip is powered on.
When CPU starts, if reset reason is CPU reset, disable those clocks
that are not enabled before reset. Otherwise, disable all those
useless clocks.
These peripheral clocks must be enabled when the peripherals are
initialized and disabled when they are deinitialized.
1. BIT(8) of CTRL is actually read-only bit indicating interrupt status
2. BIT(0) or CTRL had inverted meaning: 1 is “level”, 0 is “edge”
3. Add definitions of prescaler values
