Commit graph

96 commits

Author SHA1 Message Date
Jeroen Domburg
c46d7e60b0 Also add cache mode choice to menuconfig 2017-05-16 13:14:32 +08:00
Jeroen Domburg
202a5db2d2 Rework high interrupt code to be able to link to external handlers; add psram test that swarms cpu with interrupts 2017-05-16 13:14:30 +08:00
Jeroen Domburg
b63921a99c Add option to enable compiler psram workaround. Needs custom crosstool. 2017-05-16 13:13:01 +08:00
Jeroen Domburg
d970307120 Change default mode to low/high for dualcore 2017-05-16 13:13:01 +08:00
Jeroen Domburg
671787a966 After rebasing, it was found out that flushing the cache drops the writeback-pending psram cache lines on the ground. We now evict these by reading 64/128K of memory before flushing the cache. Also fixes a snafu in psram cache mode (inverted hi/lo and even/odd selectors) as well as an option to not let the heap allocator touch the psram. 2017-05-16 13:11:59 +08:00
Jeroen Domburg
84b728e7fd Some fixes to MR comments 2017-05-16 13:11:58 +08:00
Jeroen Domburg
0049b918b4 Fix psram silicon bug test; clean up Kconfig mess, clean out psram unused functions warnings 2017-05-16 13:11:56 +08:00
Jeroen Domburg
c6d01c2bd2 Fix dualcore PSRAM. 2017-05-16 13:11:30 +08:00
Jeroen Domburg
c9a2463f3b Add Doom psram test, fix free_heap_size/minimum_ever_heap_size calls to also understand combinations of caps, add psram support to allocator. At the moment, psram only works for the first core because of some funny business in the MMU of the 2nd core. 2017-05-16 13:10:52 +08:00
Wangjialin
0a88301fce update psram example files
1. update psram code
2. add missing files
3. add psram example
4. add mmu and psram init
2017-05-16 13:08:28 +08:00
Tian Hao
f7e8856520 component/esp32 : fix dualcore bug
1. When dual core cpu run access DPORT register, must do protection.
2. If access DPORT register, must use DPORT_REG_READ/DPORT_REG_WRITE and DPORT_XXX register operation macro.
2017-05-08 21:53:43 +08:00
Ivan Grokhotkov
fe695a9af8 Merge branch 'feature/cpu_restart_sequence' into 'master'
Restart sequence requires set up for app cpu.

These changes required to make correct restart of CPU form JTAG.

See merge request !703
2017-04-27 09:30:42 +08:00
Dmitry Yakovlev
baeab37560 Debug info removed. 2017-04-26 10:31:05 +03:00
Dmitry Yakovlev
00aa73c6cf Restart sequence requires set up for app cpu. 2017-04-26 07:47:37 +03:00
Ivan Grokhotkov
6353bc40d7 Add support for 32k XTAL as RTC_SLOW_CLK source
- RTC_CNTL_SLOWCLK_FREQ define is removed; rtc_clk_slow_freq_get_hz
  function can be used instead to get an approximate RTC_SLOW_CLK
  frequency

- Clock calibration is performed at startup. The value is saved and used
  for timekeeping and when entering deep sleep.

- When using the 32k XTAL, startup code will wait for the oscillator to
  start up. This can be possibly optimized by starting a separate task
  to wait for oscillator startup, and performing clock switch in that
  task.

- Fix a bug that 32k XTAL would be disabled in rtc_clk_init.

- Fix a rounding error in rtc_clk_cal, which caused systematic frequency
  error.

- Fix an overflow bug which caused rtc_clk_cal to timeout early if the
  slow_clk_cycles argument would exceed certain value

- Improve 32k XTAL oscillator startup time by introducing bootstrapping
  code, which uses internal pullup/pulldown resistors on 32K_N/32K_P
  pins to set better initial conditions for the oscillator.
2017-04-26 12:43:22 +08:00
Alexey Gerenkov
77a92e6dcc esp32: Added dumping info from traceport upon reset by any WDT
- Last PC info and waiti mode indication are printed for both CPUs
 - Raw traceport regs values are printed only for log levels higher than DEBUG
2017-04-23 22:07:56 +03:00
Jeroen Domburg
f73c6f875c Merge branch 'bugfix/dont_log_before_bss_inited' into 'master'
Remove ESP_EARLY_LOGI before bss is initialized; it crashes the CPU

There's an ESP_EARLY_LOGI line that can get called before the BSS is initialized; the early logging code doesn't cope well with that: it checks if FreeRTOS is up, but the variables it uses for that contains garbage because it isn't cleared yet, giving the wrong result. The logging code then tries to set a mux, crashing the entire system. This patch removes the log line and adds a warning at the BSS initialization line not to do anything complex before that point.

Fixes https://github.com/espressif/esp-idf/issues/523

See merge request !671
2017-04-18 11:21:31 +08:00
Alexey Gerenkov
55f1a63faf esp32: Adds functionality for application tracing over JTAG
- Implements application tracing module which allows to send arbitrary
   data to host over JTAG. This feature is useful for analyzing
   program modules behavior, dumping run-time application data etc.
 - Implements printf-like logging functions on top of apptrace module.
   This feature is a kind of semihosted printf functionality with lower
   overhead and impact on system behaviour as compared to standard printf.
2017-04-17 23:26:29 +03:00
Ivan Grokhotkov
639557d975 trace: add Kconfig options for app level trace
CONFIG_MEMMAP_TRACEMEM is now a hidden underlying option, which can be enabled using either CONFIG_ESP32_TRAX or CONFIG_ESP32_APP_TRACE
2017-04-17 22:19:14 +03:00
Jeroen Domburg
76a4082de7 Remove ESP_EARLY_LOGI before bss is initialized; it crashes the CPU 2017-04-16 23:34:03 +08:00
Jeroen Domburg
0b79d07d34 add detection of invalid cache access
- fix level 4 interrupt vectors to produce correct backtrace
- initialize invalid cache access interrupt on startup
- handle invalid cache access in panic handler
2017-04-13 15:27:38 +08:00
Ivan Grokhotkov
7ee8ee8b7e soc: add source code of rtc_clk, rtc_pm 2017-04-11 15:45:54 +08:00
Ivan Grokhotkov
8915c18f8a esp32: initialize cross-core interrupt in single core mode
The software interrupt originally used as the cross-core interrupt is
now also used to yield from a FreeRTOS critical section; therefore it
must be initialized for single core mode as well.

Fixes https://github.com/espressif/esp-idf/issues/496
2017-04-07 14:48:08 +08:00
Alexey Gerenkov
c142b9b9e5 esp32: RWDT is used to reboot system in case of panic handler crash
also fixes TG1WDG protection bug in panic handler
2017-04-07 02:34:29 +03:00
Ivan Grokhotkov
6ad0a157e3 driver/rtc: add APIs to enable/disable hold function 2017-03-24 10:11:13 +08:00
Jeroen Domburg
0db8b00b8a tight 28k 2017-03-08 19:04:28 +08:00
XiaXiaotian
bb0298bc71 coexist: enable coexist when wifi&bt are enabled, disable coexist when one of wifi&bt is disabled. 2017-02-20 23:53:25 +08:00
XiaXiaotian
eb14284c92 disable PHY and RF when stop WiFi and disable BT
1. Add disable PHY and RF when WiFi and BT are both disabled(including call sniffer disable API).

2. Do not init PHY and RF when cpu start. Init PHY and RF when call Wifi or BT start APIs(including sniffer enable API).

3. Add a temporary lib: librtc_clk.a and will delete it when CPU frequency switching function is done.

4. Add an function to get OS tick rate.

5. Do not put the whole pp.a in iram0, only put lmac.o, ieee80211_misc.o, ets_time.o and wdev.o in iram0.
2017-02-17 10:24:54 +08:00
Ivan Grokhotkov
777816cb99 phy_init: don’t rewrite valid calibration data
In the default PHY init routine, calibration data is loaded from NVS.
Most of the time the incremental changes to calibration will be fairly
small, so we don’t need to rewrite the existing calibration data stored
in the NVS.

Possible enhancement to be done in the future: expose a function in PHY
library to tell how big was the change in calibration data. If the
change was significant, then calibration data stored in NVS should be
updated.
2017-02-07 15:14:45 +08:00
Alexey Gerenkov
04acc88023 esp32: Fixes watchdog problem when printing core dump to uart
Also fixes generation of core dumps when flash cache is disabled
2017-02-01 18:39:28 +03:00
me-no-dev
865b21d5a1 Fix compilation if CONSOLE_UART is set to NONE
CONFIG_CONSOLE_UART_BAUDRATE is not defined
2017-01-18 15:36:10 +02:00
Ivan Grokhotkov
f20135af54 esp32: compile PHY-related code only when WiFi is enabled
Fixes https://github.com/espressif/esp-idf/issues/230, https://github.com/espressif/esp-idf/issues/237
2017-01-16 02:38:32 +08:00
Alexey Gerenkov
ad66fbe5ad esp32: Fixes issues discussed during code review of MR!341
The following issues mentioned during MR!341 review were fixed:
1) Core dump test application description
2) Usage of CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH and CONFIG_ESP32_ENABLE_COREDUMP_TO_UART
3) FLASH_GUARD_START macro usage is fixed in flash API
4) Core dump module logging facility
5) cache util functions doc updated
6) interactive delay before print core dump to uart
7) core dump partion support in build system
2017-01-12 19:38:19 +03:00
Alexey Gerenkov
39ddc7b836 esp32: Fixes several issues in core dump feature
1) PS is fixed up to allow GDB backtrace to work properly
2) MR!341 discussion: in core dump module: esp_panicPutXXX was replaced by ets_printf.
3) MR!341 discussion: core dump flash magic number was changed.
4) MR!341 discussion: SPI flash access API was redesigned to allow flexible critical section management.
5) test app for core dump feature was added
6) fixed base64 file reading issues on Windows platform
7) now raw bin core file is deleted upon core loader failure by epscoredump.py
2017-01-11 20:51:28 +03:00
Alexey Gerenkov
23f836659d esp32: Add core dump printing to UART feature 2017-01-11 20:51:28 +03:00
Alexey Gerenkov
4a3e160888 esp32: Add core dump saving to flash feature
Complimentary changes:
1) Partition table definitions files with core dump partition
2) Special sub-type for core dump partition
3) Special version of spi_flash_xxx
4) espcoredump.py is script to get core dump from flash and print useful info
5) FreeRTOS API was extended to get tasks snapshots
2017-01-11 20:51:28 +03:00
Ivan Grokhotkov
35115885c5 deep sleep: add API to control power down 2016-12-16 14:30:27 +08:00
Jeroen Domburg
78161a1fe3 Replace non-multicore-aware rom funcs with multicore-aware funcs, ESP_LOG->ESP_EARLY_LOG fix, reserve ints used in wireless libs. Fixes WiFi crashing 2016-12-13 13:24:01 +08:00
Jeroen Domburg
655fd2986a Add interrupt allocation scheme / interrupt sharing. Also modifies drivers and examples. Also allows interrupts
to be marked specifically as having a handler that's all in IRAM.
2016-12-08 12:39:33 +08:00
Ivan Grokhotkov
e3eff5deb9 cpu_start: tabs->spaces 2016-12-08 10:20:12 +08:00
Ivan Grokhotkov
13d802262a cpu_start: disable boot watchdog only after starting the main task
Boot watchdogs were disabled very early in startup code. It was possible to introduce an infinite loop anywhere in the many functions called from startup code, and this would not be detected by interrupt watchdog and task watchdog. This change postpones disabling of boot watchdogs to the point when the scheduler is running. Also replaces register expressed using integer address with a name.
2016-12-08 01:42:37 +08:00
Ivan Grokhotkov
b3f6cd08db support for console redirection to other UART
This change adds a set of menuconfig options to set custom UART#, baud rate, and pins, for console output.
Setting happens in bootloader startup code for PRO CPU, and in application startup code for APP CPU.
Ref. TW8146
2016-12-08 01:42:37 +08:00
Tian Hao
5a9801aca7 Merge branch 'master' into feature/btdm_bluedroid
# Conflicts:
#	components/esp32/cpu_freq.c
#	components/esp32/lib
2016-11-29 18:38:37 +08:00
Tian Hao
b5f03a36d5 component/bt : fix sw coexit call mistake 2016-11-24 20:09:52 +08:00
Tian Hao
55e0690f69 component/bt : wifi/bt software coexist option
1. option of sw coexist
2. cpu set freq function modify
3. update lib
4. ld add static data address
2016-11-24 19:57:47 +08:00
Ivan Grokhotkov
46a39b1e0f catch log output from WiFi libs 2016-11-22 21:14:36 +08:00
Ivan Grokhotkov
8b2f933a51 Implement system_* APIs in IDF 2016-11-22 21:14:36 +08:00
Ivan Grokhotkov
541b142654 phy_init: reduce the amount of hardwired logic, add coexist init 2016-11-18 20:11:17 +08:00
Ivan Grokhotkov
4db29f74a0 add PHY init support 2016-11-18 20:11:16 +08:00
Ivan Grokhotkov
6dd3681115 fix order of creation of standard streams
With existing order, file descriptors assigned to stdin, stdout, stderr didn't match standard assignment.
https://github.com/espressif/esp-idf/issues/67
2016-11-08 20:17:08 +08:00