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243 commits

Author SHA1 Message Date
Angus Gratton
c7738f24fc Merge branch 'bugfix/ledc_driver_enums' into 'master' 
driver: Avoid possible accidental mismatch between ledc_clk_src_t & ledc_clk_cfg_t enum

See merge request espressif/esp-idf!7021
 2020-01-10 15:34:43 +08:00
Darian Leung
a049e02d96 can: Refactor CAN to use HAL and LowLevel layers 
The following commit refactors the CAN driver such that
it is split into HAL and Lowlevel layers. The following
changes have also been made:

- Added bit field members to can_message_t as alternative
  to message flags. Updated examples and docs accordingly
- Register field names and fields of can_dev_t updated
 2020-01-09 16:13:51 +08:00
michael
f676a3b190 driver, soc: update multichip support headers 2020-01-06 17:13:54 +08:00
Ivan Grokhotkov
52f8aa2adb Merge branch 'feature/heap_non_os_build' into 'master' 
heap: make compatible with non-OS builds, remove target dependence

Closes IDF-1236

See merge request espressif/esp-idf!7051
 2020-01-03 17:12:51 +08:00
Ivan Grokhotkov
d9534b3d6a soc: fix backtraces containing ROM functions 
esp_ptr_executable would return false for pointers to ROM, which would
interrupt the backtrace. This makes ROM ranges recognized as
executable.
 2020-01-02 18:42:46 +01:00
Ivan Grokhotkov
4bbfa6e494 Merge branch 'feature/soc_ledc_caps' into 'master' 
soc: add ledc_caps.h, replace target-based ifdefs with caps-based

See merge request espressif/esp-idf!6858
 2019-12-30 18:47:11 +08:00
Ivan Grokhotkov
e4d45608d3 soc: add ledc_caps.h, replace target-based ifdefs with caps-based 2019-12-28 20:33:21 +00:00
Ivan Grokhotkov
3285ed116d heap: make compatible with non-OS builds, remove target dependence 2019-12-27 12:40:06 +01:00
morris
7baf7ce273 ethernet: optimise tx and rx 2019-12-24 11:18:31 +08:00
michael
11fa11000f spi: re-enable the unit tests for esp32s2beta 2019-12-23 10:22:59 +08:00
Mahavir Jain
e8db1c4da0 Merge branch 'feature/enable_i2s_tests_on_esp32s2beta' into 'master' 
Enable i2s and freertos test/s on esp32s2beta

See merge request espressif/esp-idf!6790
 2019-12-18 17:51:54 +08:00
kewal shah
eec8212237 add simplified API to set UART threshold values for RX FIFO full and TX FIFO empty 2019-12-16 20:26:04 +00:00
Angus Gratton
435dd546cc driver: Avoid possible accidental mismatch between ledc_clk_src_t & ledc_clk_cfg_t enum 
ledc_types.h includes two similar enums, ledc_clk_src_t & ledc_clk_cfg_t. Latter was added in
ESP-IDF v4.0.

The two enums do different things but there are two similar names: LEDC_REF_TICK / LEDC_USE_REF_TICK
and LEDC_APB_CLK / LEDC_USE_APB_CLK.

Because C will accept any enum or integer value for an enum argument, there's no easy way to check
the correct enum is passed without using static analysis.

To avoid accidental errors, make the numeric values for the two similarly named enums the same.,

Noticed when looking into https://github.com/espressif/esp-idf/issues/4476
 2019-12-16 19:43:11 +11:00
Mahavir Jain
8b05cf41ad i2s: enable tests for esp32s2beta 2019-12-16 11:53:33 +05:30
Wang Jia Lin
f5e60524ac Merge branch 'bugfix/fix_i2c_driver_breakingchange_issue' into 'master' 
bugfix(i2c): fix I2C driver breaking change issue

See merge request espressif/esp-idf!6809
 2019-12-06 16:50:16 +08:00
houwenxiang
aac935ec81 bugfix(i2c): fix I2C driver breaking change issue. 
1. Fixed I2C driver breaking change issue.
    2. Add I2C UT test case.
 2019-12-04 15:51:36 +08:00
houwenxiang
e4230d11ca bugfix(UART): fix uart driver spinlock misused bug 
1. fix uart driver spinlock misused bug
    2. add uart driver ut test case
    3. undo the change in light_sleep_example_main.c
 2019-12-03 16:06:31 +08:00
Wang Jia Lin
1ffcb54444 Merge branch 'bugfix/fix_esp32-s2_rtc_io_issue' into 'master' 
bugfix(gpio): fix esp32 s2 rtc io issue and gpio testcase issues

See merge request espressif/esp-idf!6832
 2019-12-03 11:17:41 +08:00
Renz Christian Bagaporo
e6ad330018 ble_mesh_wifi_coexist example: Disable Wi-Fi RX IRAM optimisation 
Otherwise IRAM usage is too high in this example.
 2019-11-28 09:20:00 +08:00
Fu Zhi Bo
3a468a1ffd Refactor the touch sensor driver 2019-11-27 20:08:44 +08:00
xiongyu
af4c455417 bugfix(gpio):fix esp32 s2 rtc io issue 
* Modify the function implementation of ESP32-S2 RTC GPIO
  On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register.
  On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
* Add ESP32-S2 support of unit test
* Modify the pull-up test of unit test
* Modify the interrupt test of unit test
* Modify input and output mode test of unit test
 2019-11-27 17:18:20 +08:00
Angus Gratton
91b7a7beaf Merge branch 'bugfix/timer_intr_status_get' into 'master' 
bugfix(timer): fix get intr status function

See merge request espressif/esp-idf!6807
 2019-11-27 09:13:16 +08:00
Angus Gratton
64c8b640a1 Merge branch 'feature/log_component_noos' into 'master' 
log: make compatible with non-OS builds

See merge request espressif/esp-idf!6787
 2019-11-27 08:34:22 +08:00
chenjianqiang
bcfe684951 bugfix(timer): add a macro to control making the XTAL related functions 2019-11-26 12:39:46 +00:00
chenjianqiang
856d9f7d89 bugfix(timer): recover get raw interrupt status function 2019-11-26 12:39:46 +00:00
houwenxiang
f27ae9b0e2 feature: Add uart hal support. 2019-11-26 20:01:50 +08:00
Angus Gratton
f2a1a6105a Merge branch 'feat/mcpwm_hal' 
Manual merge of !6626
 2019-11-25 17:18:48 +11:00
Angus Gratton
6dd36fd571 Merge branch 'refactor/hal_gpio_driver' 
Manual merge of !5597
 2019-11-25 10:49:40 +11:00
Angus Gratton
f34edba8f3 Merge branch 'feature/adc_driver_hal_support' 
Manual merge of !6044
 2019-11-25 10:22:06 +11:00
michael
538540ce21 mcpwm: add HAL layer support 
Also improved the unit tests a bit.
 2019-11-25 00:36:30 +08:00
xiongyu
a3b79e9202 refactor(gpio): add hal gpio driver 2019-11-22 17:24:53 +08:00
fuzhibo
f49b192a5e refactor the adc driver 2019-11-22 15:42:16 +08:00
Mahavir Jain
25c0752682 i2s: fix regression in retrieval of chip revision causing apll test to fail 2019-11-22 11:46:38 +05:30
fuzhibo
03ac1aaafd dac: refactor driver add hal 2019-11-22 11:44:46 +08:00
Ivan Grokhotkov
951ed739f7 soc/cpu: add non-xtensa-specific replacement of xthal_get_ccount 2019-11-21 19:22:35 +01:00
houwenxiang
28286183d1 feature(I2C): Add i2c hal support. 2019-11-21 20:34:07 +08:00
chenjianqiang
857dec108d feat(ledc): refactor ledc driver 
1. add hal and low-level layer for ledc driver
2. support esp32s2beta ledc
 2019-11-21 16:25:22 +08:00
chenjianqiang
9f9da9ec96 feat(timer): refator timer group driver 
1. add hal and low-level layer for timer group
2. add callback functions to handle interrupt
3. add timer deinit function
4. add timer spinlock take function
 2019-11-21 14:14:19 +08:00
xiongyu
e62b831867 refactor(sigmadelta): add hal sigmadelta driver 2019-11-21 11:53:07 +08:00
fuzhibo
0c2bf7c8bc rtcio: add hal for driver 2019-11-21 10:40:49 +08:00
Angus Gratton
b30b0e59fa Merge branch 'feature/add_rmt_hal' into 'master' 
rmt: add hal layer and new examples

Closes IDF-841, IDF-844, and IDF-857

See merge request espressif/esp-idf!5649
 2019-11-21 09:53:54 +08:00
morris
8fd8695ea1 rmt: add HAL layer 2019-11-20 10:54:21 +08:00
xiongyu
8c76a3c10d refactor(i2s): add hal i2s driver 2019-11-19 22:19:19 +08:00
xiongyu
b1a72866ca refactor(pcnt): add hal pcnt driver 2019-11-18 14:35:46 +08:00
Angus Gratton
8675a818f9 Merge branch 'master' into feature/esp32s2beta_merge 2019-10-22 13:51:49 +11:00
Ivan Grokhotkov
c7d8ef52ca Merge branch 'fix/esp_flash_no_qe' into 'master' 
esp_flash: fix the QE write issue in high freq, and support UT for external chips

Closes IDF-888

See merge request espressif/esp-idf!5736
 2019-10-20 13:59:30 +08:00
Angus Gratton
ae21d669b9 Merge branch 'master' into feature/esp32s2beta_merge 2019-10-17 18:22:08 +11:00
Darian
820fd6447d can: Add support for lower bit rates 
This commit adds support for lower bit rates in the CAN Driver for
ESP32 Rev 2 or later chips.
 2019-10-17 12:33:17 +08:00
Angus Gratton
496ede9bcd Merge branch 'master' into feature/esp32s2beta_merge 2019-10-15 14:59:27 +11:00
Michael (XIAO Xufeng)
571864e8ae esp_flash: fix set qe bit and write command issues 
There used to be dummy phase before out phase in common command
transactions. This corrupts the data.

The code before never actually operate (clear) the QE bit, once it finds
the QE bit is set. It's hard to check whether the QE set/disable
functions work well.

This commit:

1. Cancel the dummy phase

2. Set and clear the QE bit according to chip settings, allowing tests
   for QE bits. However for some chips (Winbond for example), it's not
   forced to clear the QE bit if not able to.

3. Also refactor to allow chip_generic and other chips to share the same
   code to read and write qe bit; let common command and read command share
   configure_host_io_mode.

4. Rename read mode to io mode since maybe we will write data with quad
   mode one day.
 2019-10-14 17:25:58 +08:00