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rmt: add HAL layer

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This commit is contained in:
morris 2019-11-19 16:10:02 +08:00
parent bcf1f992ff
commit 8fd8695ea1
14 changed files with 2375 additions and 1414 deletions
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1267
components/driver/include/driver/rmt.h
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821
components/driver/rmt.c
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658
components/driver/test/esp32/test_rmt.c
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@ -1,51 +1,54 @@
/**
* please connect GPIO18 to GPIO19
* @brief To run this unit test, MAKE SURE GPIO18(TX) is connected to GPIO19(RX)!
*
*/
#include "stdio.h"
#include <stdio.h>
#include <string.h>
#include "driver/rmt.h"
#include "sdkconfig.h"
#include "unity.h"
#include "test_utils.h"
#include "driver/rmt.h"
#include "driver/periph_ctrl.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/queue.h"
#include "freertos/semphr.h"
#include "esp_err.h"
#include "esp_log.h"
#include "driver/periph_ctrl.h"
#include "soc/soc.h"
#include "soc/rmt_periph.h"
static const char* TAG = "RMT";
static const char *TAG = "RMT.test";
#define RMT_RX_ACTIVE_LEVEL 1 /*!< Data bit is active high for self test mode */
#define RMT_TX_CARRIER_EN 0 /*!< Disable carrier for self test mode */
#define RMT_RX_ACTIVE_LEVEL 1 /*!< Data bit is active high for self test mode */
#define RMT_TX_CARRIER_EN 0 /*!< Disable carrier for self test mode */
#define RMT_TX_CHANNEL 1 /*!< RMT channel for transmitter */
#define RMT_TX_GPIO_NUM 18 /*!< GPIO number for transmitter signal */
#define RMT_RX_CHANNEL 0 /*!< RMT channel for receiver */
#define RMT_RX_GPIO_NUM 19 /*!< GPIO number for receiver */
#define RMT_CLK_DIV 100 /*!< RMT counter clock divider */
#define RMT_TICK_10_US (APB_CLK_FREQ / RMT_CLK_DIV / 100000) /*!< RMT counter value for 10 us */
#define RMT_TX_CHANNEL 1 /*!< RMT channel for transmitter */
#define RMT_TX_GPIO_NUM 18 /*!< GPIO number for transmitter signal */
#define RMT_RX_CHANNEL 0 /*!< RMT channel for receiver */
#define RMT_RX_GPIO_NUM 19 /*!< GPIO number for receiver */
#define RMT_CLK_DIV 100 /*!< RMT counter clock divider */
#define RMT_TICK_10_US (80000000/RMT_CLK_DIV/100000) /*!< RMT counter value for 10 us.(Source clock is APB clock) */
// NEC protocol related parameters
#define HEADER_HIGH_US 9000 /*!< NEC protocol header: positive 9ms */
#define HEADER_LOW_US 4500 /*!< NEC protocol header: negative 4.5ms*/
#define BIT_ONE_HIGH_US 560 /*!< NEC protocol data bit 1: positive 0.56ms */
#define BIT_ONE_LOW_US (2250 - BIT_ONE_HIGH_US) /*!< NEC protocol data bit 1: negative 1.69ms */
#define BIT_ZERO_HIGH_US 560 /*!< NEC protocol data bit 0: positive 0.56ms */
#define BIT_ZERO_LOW_US (1120 - BIT_ZERO_HIGH_US) /*!< NEC protocol data bit 0: negative 0.56ms */
#define BIT_END 560 /*!< NEC protocol end: positive 0.56ms */
#define BIT_MARGIN 160 /*!< NEC parse margin time */
#define HEADER_HIGH_US 9000 /*!< NEC protocol header: positive 9ms */
#define HEADER_LOW_US 4500 /*!< NEC protocol header: negative 4.5ms*/
#define BIT_ONE_HIGH_US 560 /*!< NEC protocol data bit 1: positive 0.56ms */
#define BIT_ONE_LOW_US (2250-BIT_ONE_HIGH_US) /*!< NEC protocol data bit 1: negative 1.69ms */
#define BIT_ZERO_HIGH_US 560 /*!< NEC protocol data bit 0: positive 0.56ms */
#define BIT_ZERO_LOW_US (1120-BIT_ZERO_HIGH_US) /*!< NEC protocol data bit 0: negative 0.56ms */
#define BIT_END 560 /*!< NEC protocol end: positive 0.56ms */
#define BIT_MARGIN 20 /*!< NEC parse margin time */
#define ITEM_DURATION(d) ((d & 0x7fff)*10/RMT_TICK_10_US) /*!< Parse duration time from memory register value */
#define DATA_ITEM_NUM 34 /*!< NEC code item number: header + 32bit data + end */
#define RMT_TX_DATA_NUM 100 /*!< NEC tx test data number */
#define RMT_ITEM32_TIMEOUT_US 9500 /*!< RMT receiver timeout value(us) */
#define ITEM_DURATION(d) ((d & 0x7fff) * 10 / RMT_TICK_10_US) /*!< Parse duration time from memory register value */
#define DATA_ITEM_NUM 34 /*!< NEC code item number: header + 32bit data + end */
#define RMT_TX_DATA_NUM 50 /*!< NEC tx test data number */
#define RMT_ITEM32_TIMEOUT_US 9500 /*!< RMT receiver timeout value(us) */
/**
* @brief Build register value of waveform for NEC one data bit
*/
static inline void fill_item_level(rmt_item32_t* item, int high_us, int low_us)
static inline void fill_item_level(rmt_item32_t *item, int high_us, int low_us)
{
item->level0 = 1;
item->duration0 = (high_us) / 10 * RMT_TICK_10_US;
@ -56,7 +59,7 @@ static inline void fill_item_level(rmt_item32_t* item, int high_us, int low_us)
/**
* @brief Generate NEC header value: active 9ms + negative 4.5ms
*/
static void fill_item_header(rmt_item32_t* item)
static void fill_item_header(rmt_item32_t *item)
{
fill_item_level(item, HEADER_HIGH_US, HEADER_LOW_US);
}
@ -64,7 +67,7 @@ static void fill_item_header(rmt_item32_t* item)
/*
* @brief Generate NEC data bit 1: positive 0.56ms + negative 1.69ms
*/
static void fill_item_bit_one(rmt_item32_t* item)
static void fill_item_bit_one(rmt_item32_t *item)
{
fill_item_level(item, BIT_ONE_HIGH_US, BIT_ONE_LOW_US);
}
@ -72,7 +75,7 @@ static void fill_item_bit_one(rmt_item32_t* item)
/**
* @brief Generate NEC data bit 0: positive 0.56ms + negative 0.56ms
*/
static void fill_item_bit_zero(rmt_item32_t* item)
static void fill_item_bit_zero(rmt_item32_t *item)
{
fill_item_level(item, BIT_ZERO_HIGH_US, BIT_ZERO_LOW_US);
}
@ -80,7 +83,7 @@ static void fill_item_bit_zero(rmt_item32_t* item)
/**
* @brief Generate NEC end signal: positive 0.56ms
*/
static void fill_item_end(rmt_item32_t* item)
static void fill_item_end(rmt_item32_t *item)
{
fill_item_level(item, BIT_END, 0x7fff);
}
@ -90,8 +93,8 @@ static void fill_item_end(rmt_item32_t* item)
*/
static inline bool check_in_range(int duration_ticks, int target_us, int margin_us)
{
if(( ITEM_DURATION(duration_ticks) < (target_us + margin_us))
&& ( ITEM_DURATION(duration_ticks) > (target_us - margin_us))) {
if ((ITEM_DURATION(duration_ticks) < (target_us + margin_us)) &&
(ITEM_DURATION(duration_ticks) > (target_us - margin_us))) {
return true;
} else {
return false;
@ -101,11 +104,11 @@ static inline bool check_in_range(int duration_ticks, int target_us, int margin_
/**
* @brief Check whether this value represents an NEC header
*/
static bool header_if(rmt_item32_t* item)
static bool header_if(rmt_item32_t *item)
{
if((item->level0 == RMT_RX_ACTIVE_LEVEL && item->level1 != RMT_RX_ACTIVE_LEVEL)
&& check_in_range(item->duration0, HEADER_HIGH_US, BIT_MARGIN)
&& check_in_range(item->duration1, HEADER_LOW_US, BIT_MARGIN)) {
if ((item->level0 == RMT_RX_ACTIVE_LEVEL && item->level1 != RMT_RX_ACTIVE_LEVEL) &&
check_in_range(item->duration0, HEADER_HIGH_US, BIT_MARGIN) &&
check_in_range(item->duration1, HEADER_LOW_US, BIT_MARGIN)) {
return true;
}
return false;
@ -114,11 +117,11 @@ static bool header_if(rmt_item32_t* item)
/**
* @brief Check whether this value represents an NEC data bit 1
*/
static bool bit_one_if(rmt_item32_t* item)
static bool bit_one_if(rmt_item32_t *item)
{
if((item->level0 == RMT_RX_ACTIVE_LEVEL && item->level1 != RMT_RX_ACTIVE_LEVEL)
&& check_in_range(item->duration0, BIT_ONE_HIGH_US, BIT_MARGIN)
&& check_in_range(item->duration1, BIT_ONE_LOW_US, BIT_MARGIN)) {
if ((item->level0 == RMT_RX_ACTIVE_LEVEL && item->level1 != RMT_RX_ACTIVE_LEVEL) &&
check_in_range(item->duration0, BIT_ONE_HIGH_US, BIT_MARGIN) &&
check_in_range(item->duration1, BIT_ONE_LOW_US, BIT_MARGIN)) {
return true;
}
return false;
@ -127,35 +130,34 @@ static bool bit_one_if(rmt_item32_t* item)
/**
* @brief Check whether this value represents an NEC data bit 0
*/
static bool bit_zero_if(rmt_item32_t* item)
static bool bit_zero_if(rmt_item32_t *item)
{
if((item->level0 == RMT_RX_ACTIVE_LEVEL && item->level1 != RMT_RX_ACTIVE_LEVEL)
&& check_in_range(item->duration0, BIT_ZERO_HIGH_US, BIT_MARGIN)
&& check_in_range(item->duration1, BIT_ZERO_LOW_US, BIT_MARGIN)) {
if ((item->level0 == RMT_RX_ACTIVE_LEVEL && item->level1 != RMT_RX_ACTIVE_LEVEL) &&
check_in_range(item->duration0, BIT_ZERO_HIGH_US, BIT_MARGIN) &&
check_in_range(item->duration1, BIT_ZERO_LOW_US, BIT_MARGIN)) {
return true;
}
return false;
}
/**
* @brief Parse NEC 32 bit waveform to address and command.
*/
static int parse_items(rmt_item32_t* item, int item_num, uint16_t* addr, uint16_t* data)
static int parse_items(rmt_item32_t *item, int item_num, uint16_t *addr, uint16_t *data)
{
int w_len = item_num;
if(w_len < DATA_ITEM_NUM) {
if (w_len < DATA_ITEM_NUM) {
return -1;
}
int i = 0, j = 0;
if(!header_if(item++)) {
if (!header_if(item++)) {
return -1;
}
uint16_t addr_t = 0;
for(j = 0; j < 16; j++) {
if(bit_one_if(item)) {
for (j = 0; j < 16; j++) {
if (bit_one_if(item)) {
addr_t |= (1 << j);
} else if(bit_zero_if(item)) {
} else if (bit_zero_if(item)) {
addr_t |= (0 << j);
} else {
return -1;
@ -164,10 +166,10 @@ static int parse_items(rmt_item32_t* item, int item_num, uint16_t* addr, uint16_
i++;
}
uint16_t data_t = 0;
for(j = 0; j < 16; j++) {
if(bit_one_if(item)) {
for (j = 0; j < 16; j++) {
if (bit_one_if(item)) {
data_t |= (1 << j);
} else if(bit_zero_if(item)) {
} else if (bit_zero_if(item)) {
data_t |= (0 << j);
} else {
return -1;
@ -183,16 +185,16 @@ static int parse_items(rmt_item32_t* item, int item_num, uint16_t* addr, uint16_
/**
* @brief Build NEC 32bit waveform.
*/
static int build_items(int channel, rmt_item32_t* item, int item_num, uint16_t addr, uint16_t cmd_data)
static int build_items(int channel, rmt_item32_t *item, int item_num, uint16_t addr, uint16_t cmd_data)
{
int i = 0, j = 0;
if(item_num < DATA_ITEM_NUM) {
if (item_num < DATA_ITEM_NUM) {
return -1;
}
fill_item_header(item++);
i++;
for(j = 0; j < 16; j++) {
if(addr & 0x1) {
for (j = 0; j < 16; j++) {
if (addr & 0x1) {
fill_item_bit_one(item);
} else {
fill_item_bit_zero(item);
@ -201,8 +203,8 @@ static int build_items(int channel, rmt_item32_t* item, int item_num, uint16_t a
i++;
addr >>= 1;
}
for(j = 0; j < 16; j++) {
if(cmd_data & 0x1) {
for (j = 0; j < 16; j++) {
if (cmd_data & 0x1) {
fill_item_bit_one(item);
} else {
fill_item_bit_zero(item);
@ -216,12 +218,11 @@ static int build_items(int channel, rmt_item32_t* item, int item_num, uint16_t a
return i;
}
static void set_tx_data(int tx_channel, uint16_t cmd, uint16_t addr, int item_num, rmt_item32_t* item, int offset)
static void set_tx_data(int tx_channel, uint16_t cmd, uint16_t addr, int item_num, rmt_item32_t *item, int offset)
{
while(1) {
while (1) {
int i = build_items(tx_channel, item + offset, item_num - offset, ((~addr) << 8) | addr, cmd);
printf("cmd :%d\n", cmd);
if(i < 0) {
if (i < 0) {
break;
}
cmd++;
@ -233,25 +234,25 @@ static void set_tx_data(int tx_channel, uint16_t cmd, uint16_t addr, int item_nu
static int get_rx_data(RingbufHandle_t rb)
{
uint16_t tmp = 0;
while(rb) {
while (rb) {
size_t rx_size = 0;
rmt_item32_t* rx_item = (rmt_item32_t*) xRingbufferReceive(rb, &rx_size, 1000);
if(rx_item) {
rmt_item32_t *rx_item = (rmt_item32_t *)xRingbufferReceive(rb, &rx_size, 1000);
if (rx_item) {
uint16_t rmt_addr;
uint16_t rmt_cmd;
int rx_offset = 0;
while(1) {
while (1) {
int res = parse_items(rx_item + rx_offset, rx_size / 4 - rx_offset, &rmt_addr, &rmt_cmd);
if(res > 0) {
if (res > 0) {
rx_offset += res + 1;
ESP_LOGI(TAG, "RMT RCV --- addr: 0x%04x cmd: 0x%04x", rmt_addr, rmt_cmd);
ESP_LOGI(TAG, "receive cmd %d from addr %d", rmt_cmd, rmt_addr & 0xFF);
TEST_ASSERT(rmt_cmd == tmp);
tmp++;
} else {
break;
}
}
vRingbufferReturnItem(rb, (void*) rx_item);
vRingbufferReturnItem(rb, (void *)rx_item);
} else {
break;
}
@ -305,7 +306,7 @@ static void rx_init(void)
.rx_config = rx_cfg,
};
rmt_config(&rmt_rx);
rmt_driver_install(rmt_rx.channel, (sizeof(rmt_item32_t) * DATA_ITEM_NUM * (RMT_TX_DATA_NUM+6)), 0);
rmt_driver_install(rmt_rx.channel, (sizeof(rmt_item32_t) * DATA_ITEM_NUM * (RMT_TX_DATA_NUM + 6)), 0);
}
TEST_CASE("RMT init config", "[rmt][test_env=UT_T1_RMT]")
@ -376,12 +377,12 @@ TEST_CASE("RMT init config", "[rmt][test_env=UT_T1_RMT]")
TEST_CASE("RMT init set function", "[rmt][test_env=UT_T1_RMT]")
{
rmt_channel_t channel = 7;
TEST_ESP_OK(rmt_driver_install(channel, 0, 0));
TEST_ESP_OK(rmt_set_pin(channel, RMT_MODE_RX, RMT_RX_GPIO_NUM));
TEST_ESP_OK(rmt_set_clk_div(channel, RMT_CLK_DIV*2));
TEST_ESP_OK(rmt_set_clk_div(channel, RMT_CLK_DIV * 2));
TEST_ESP_OK(rmt_set_mem_block_num(channel, 1));
TEST_ESP_OK(rmt_set_rx_filter(channel, 1, 100));
TEST_ESP_OK(rmt_set_rx_idle_thresh(channel, RMT_ITEM32_TIMEOUT_US / 10 * (RMT_TICK_10_US)*2));
TEST_ESP_OK(rmt_driver_install(channel, 0, 0));
TEST_ESP_OK(rmt_set_rx_idle_thresh(channel, RMT_ITEM32_TIMEOUT_US / 10 * (RMT_TICK_10_US) * 2));
TEST_ESP_OK(rmt_driver_uninstall(channel));
}
@ -405,8 +406,8 @@ TEST_CASE("RMT clock devider, clock source set(logic analyzer)", "[rmt][ignore]"
rmt_tx.rmt_mode = RMT_MODE_TX;
TEST_ESP_OK(rmt_config(&rmt_tx));
TEST_ESP_OK(rmt_get_clk_div(RMT_TX_CHANNEL, &div_cnt));
TEST_ESP_OK(rmt_driver_install(rmt_tx.channel, 0, 0));
TEST_ESP_OK(rmt_get_clk_div(RMT_TX_CHANNEL, &div_cnt));
TEST_ASSERT_EQUAL_UINT8(div_cnt, RMT_CLK_DIV);
vTaskDelay(1000 / portTICK_PERIOD_MS);
@ -435,19 +436,16 @@ TEST_CASE("RMT rx set and get properties", "[rmt][test_env=UT_T1_RMT]")
TEST_ESP_OK(rmt_get_clk_div(channel, &div_cnt));
TEST_ESP_OK(rmt_get_mem_block_num(channel, &memNum));
TEST_ESP_OK(rmt_get_rx_idle_thresh(channel, &idleThreshold));
TEST_ESP_OK(rmt_get_memory_owner(channel, &owner));
TEST_ASSERT_EQUAL_UINT8(div_cnt, RMT_CLK_DIV);
TEST_ASSERT_EQUAL_UINT8(memNum, 1);
TEST_ASSERT_EQUAL_UINT16(idleThreshold, RMT_ITEM32_TIMEOUT_US / 10 * (RMT_TICK_10_US));
TEST_ASSERT_EQUAL_INT(owner, RMT_MEM_OWNER_RX);
//eRR
TEST_ESP_OK(rmt_set_pin(channel, RMT_MODE_RX, 22));
TEST_ESP_OK(rmt_set_clk_div(channel, RMT_CLK_DIV*2));
TEST_ESP_OK(rmt_set_clk_div(channel, RMT_CLK_DIV * 2));
TEST_ESP_OK(rmt_set_mem_block_num(channel, 2));
TEST_ESP_OK(rmt_set_rx_filter(channel, 1, 100));
TEST_ESP_OK(rmt_set_rx_idle_thresh(channel, RMT_ITEM32_TIMEOUT_US / 10 * (RMT_TICK_10_US)*2));
TEST_ESP_OK(rmt_set_rx_idle_thresh(channel, RMT_ITEM32_TIMEOUT_US / 10 * (RMT_TICK_10_US) * 2));
TEST_ESP_OK(rmt_set_memory_owner(channel, RMT_MEM_OWNER_RX));
TEST_ESP_OK(rmt_get_clk_div(channel, &div_cnt));
@ -455,9 +453,9 @@ TEST_CASE("RMT rx set and get properties", "[rmt][test_env=UT_T1_RMT]")
TEST_ESP_OK(rmt_get_rx_idle_thresh(channel, &idleThreshold));
TEST_ESP_OK(rmt_get_memory_owner(channel, &owner));
TEST_ASSERT_EQUAL_UINT8(div_cnt, RMT_CLK_DIV*2);
TEST_ASSERT_EQUAL_UINT8(div_cnt, RMT_CLK_DIV * 2);
TEST_ASSERT_EQUAL_UINT8(memNum, 2);
TEST_ASSERT_EQUAL_UINT16(idleThreshold, RMT_ITEM32_TIMEOUT_US / 10 * (RMT_TICK_10_US)*2);
TEST_ASSERT_EQUAL_UINT16(idleThreshold, RMT_ITEM32_TIMEOUT_US / 10 * (RMT_TICK_10_US) * 2);
TEST_ASSERT_EQUAL_INT(owner, RMT_MEM_OWNER_RX);
TEST_ESP_OK(rmt_driver_uninstall(channel));
@ -475,16 +473,14 @@ TEST_CASE("RMT tx set and get properties", "[rmt][test_env=UT_T1_RMT]")
TEST_ESP_OK(rmt_get_clk_div(channel, &div_cnt));
TEST_ESP_OK(rmt_get_mem_block_num(channel, &memNum));
TEST_ESP_OK(rmt_get_tx_loop_mode(channel, &loop_en));
TEST_ESP_OK(rmt_get_memory_owner(channel, &owner));
TEST_ASSERT_EQUAL_INT8(loop_en, 0);
TEST_ASSERT_EQUAL_UINT8(div_cnt, RMT_CLK_DIV);
TEST_ASSERT_EQUAL_UINT8(memNum, 1);
TEST_ASSERT_EQUAL_INT(owner, RMT_MEM_OWNER_TX);
//reset by "set"
TEST_ESP_OK(rmt_set_pin(channel, RMT_MODE_TX, RMT_TX_GPIO_NUM));
TEST_ESP_OK(rmt_set_clk_div(channel, RMT_CLK_DIV*2));
TEST_ESP_OK(rmt_set_clk_div(channel, RMT_CLK_DIV * 2));
TEST_ESP_OK(rmt_set_mem_block_num(channel, 2));
TEST_ESP_OK(rmt_set_tx_loop_mode(channel, 1));
TEST_ESP_OK(rmt_set_tx_carrier(channel, 0, 1, 0, 1));
@ -497,280 +493,28 @@ TEST_CASE("RMT tx set and get properties", "[rmt][test_env=UT_T1_RMT]")
TEST_ESP_OK(rmt_get_memory_owner(channel, &owner));
TEST_ASSERT_EQUAL_INT8(loop_en, 1);
TEST_ASSERT_EQUAL_UINT8(div_cnt, RMT_CLK_DIV*2);
TEST_ASSERT_EQUAL_UINT8(div_cnt, RMT_CLK_DIV * 2);
TEST_ASSERT_EQUAL_UINT8(memNum, 2);
TEST_ASSERT_EQUAL_INT(owner, RMT_MEM_OWNER_TX);
rmt_item32_t items[1];
items[0].duration0 = 300 / 10 * RMT_TICK_10_US; //300us
items[0].level0 = 1;
items[0].duration1 = 0;
items[0].level1 = 0;
for(int i=0; i<100; i++) {
TEST_ESP_OK(rmt_write_items(RMT_TX_CHANNEL, items,
1, /* Number of items */
1 /* wait till done */));
vTaskDelay(10/portTICK_PERIOD_MS); //every 10ms to write the item
rmt_item32_t item;
item.duration0 = 300 / 10 * RMT_TICK_10_US; //300us
item.level0 = 1;
item.duration1 = 0;
item.level1 = 0;
for (int i = 0; i < 100; i++) {
TEST_ESP_OK(rmt_write_items(RMT_TX_CHANNEL, &item,
1, /* Number of items */
1 /* wait till done */));
vTaskDelay(10 / portTICK_PERIOD_MS); //every 10ms to write the item
}
TEST_ESP_OK(rmt_driver_uninstall(channel));
}
TEST_CASE("RMT memory test", "[rmt][test_env=UT_T1_RMT]")
{
rmt_config_t rmt_rx;
rmt_rx.channel = RMT_RX_CHANNEL;
rmt_rx.gpio_num = RMT_RX_GPIO_NUM;
rmt_rx.clk_div = RMT_CLK_DIV;
rmt_rx.mem_block_num = 1;
rmt_rx.rmt_mode = RMT_MODE_RX;
rmt_rx.rx_config.filter_en = true;
rmt_rx.rx_config.filter_ticks_thresh = 100;
rmt_rx.rx_config.idle_threshold = RMT_ITEM32_TIMEOUT_US / 10 * (RMT_TICK_10_US);
TEST_ESP_OK(rmt_config(&rmt_rx));
for(int i = 0; i<100; i++) {
TEST_ESP_OK(rmt_driver_install(rmt_rx.channel, 1000, 0));
TEST_ESP_OK(rmt_driver_uninstall(rmt_rx.channel));
}
}
// RMT channel num and memory block relationship
TEST_CASE("RMT memory block test", "[rmt][test_env=UT_T1_RMT]")
{
rmt_channel_t channel = 0;
rmt_config_t rmt_rx;
rmt_rx.channel = channel;
rmt_rx.gpio_num = RMT_RX_GPIO_NUM;
rmt_rx.clk_div = RMT_CLK_DIV;
rmt_rx.mem_block_num = 1;
rmt_rx.rmt_mode = RMT_MODE_RX;
rmt_rx.rx_config.filter_en = true;
rmt_rx.rx_config.filter_ticks_thresh = 100;
rmt_rx.rx_config.idle_threshold = RMT_ITEM32_TIMEOUT_US / 10 * (RMT_TICK_10_US);
TEST_ESP_OK(rmt_config(&rmt_rx));
TEST_ESP_OK(rmt_driver_install(rmt_rx.channel, 1000, 0));
TEST_ESP_OK(rmt_set_mem_block_num(channel, 8));
TEST_ASSERT(rmt_set_mem_block_num(channel, 9)==ESP_ERR_INVALID_ARG);
TEST_ASSERT(rmt_set_mem_block_num(channel, -1)==ESP_ERR_INVALID_ARG);
TEST_ESP_OK(rmt_driver_uninstall(rmt_rx.channel));
rmt_rx.channel = 7;
TEST_ESP_OK(rmt_config(&rmt_rx));
TEST_ESP_OK(rmt_driver_install(rmt_rx.channel, 1000, 0));
TEST_ASSERT(rmt_set_mem_block_num(rmt_rx.channel, 2)==ESP_ERR_INVALID_ARG);
TEST_ASSERT(rmt_set_mem_block_num(rmt_rx.channel, -1)==ESP_ERR_INVALID_ARG);
TEST_ESP_OK(rmt_driver_uninstall(rmt_rx.channel));
}
TEST_CASE("RMT send waveform(logic analyzer)", "[rmt][test_env=UT_T1_RMT][ignore]")
{
tx_init();
rmt_item32_t items[1];
items[0].duration0 = 300 / 10 * RMT_TICK_10_US; //300us
items[0].level0 = 1;
for(int i=0; i<500; i++) {
TEST_ESP_OK(rmt_write_items(RMT_TX_CHANNEL, items,
1, /* Number of items */
1 /* wait till done */));
vTaskDelay(10/portTICK_PERIOD_MS); //every 10ms to write the item
}
TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
}
TEST_CASE("RMT basic TX and RX", "[rmt][test_env=UT_T1_RMT]")
{
tx_init();
int tx_channel = RMT_TX_CHANNEL;
uint16_t cmd = 0x0;
uint16_t addr = 0x11;
int tx_num = RMT_TX_DATA_NUM;
ESP_LOGI(TAG, "RMT TX DATA");
size_t size = (sizeof(rmt_item32_t) * DATA_ITEM_NUM * tx_num);
rmt_item32_t* item = (rmt_item32_t*) malloc(size);
int item_num = DATA_ITEM_NUM * tx_num;
memset((void*) item, 0, size);
int offset = 0;
int rx_channel = RMT_RX_CHANNEL;
rx_init();
RingbufHandle_t rb = NULL;
rmt_get_ringbuf_handle(rx_channel, &rb);
rmt_rx_start(rx_channel, 1);
// send data
set_tx_data(tx_channel, cmd, addr, item_num, item, offset);
rmt_write_items(tx_channel, item, item_num, 1);
free(item);
// receive data
uint16_t tmp = get_rx_data(rb);
TEST_ASSERT(tmp == 100);
TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
TEST_ESP_OK(rmt_driver_uninstall(RMT_RX_CHANNEL));
}
TEST_CASE("RMT TX write item not wait", "[rmt][test_env=UT_T1_RMT]")
{
tx_init();
int tx_channel = RMT_TX_CHANNEL;
uint16_t cmd = 0x0;
uint16_t addr = 0x11;
int tx_num = RMT_TX_DATA_NUM;
ESP_LOGI(TAG, "RMT TX DATA");
size_t size = (sizeof(rmt_item32_t) * DATA_ITEM_NUM * tx_num);
rmt_item32_t* item = (rmt_item32_t*) malloc(size);
int item_num = DATA_ITEM_NUM * tx_num;
memset((void*) item, 0, size);
int offset = 0;
int rx_channel = RMT_RX_CHANNEL;
rx_init();
RingbufHandle_t rb = NULL;
rmt_get_ringbuf_handle(rx_channel, &rb);
rmt_rx_start(rx_channel, 1);
// send data
set_tx_data(tx_channel, cmd, addr, item_num, item, offset);
rmt_write_items(tx_channel, item, item_num, 0);
free(item);
// receive data
uint16_t tmp = get_rx_data(rb);
TEST_ASSERT(tmp < 100);
TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
TEST_ESP_OK(rmt_driver_uninstall(RMT_RX_CHANNEL));
}
TEST_CASE("RMT TX write item wait some ticks", "[rmt][test_env=UT_T1_RMT]")
{
tx_init();
int tx_channel = RMT_TX_CHANNEL;
uint16_t cmd = 0x0;
uint16_t addr = 0x11;
int tx_num = RMT_TX_DATA_NUM;
ESP_LOGI(TAG, "RMT TX DATA");
size_t size = (sizeof(rmt_item32_t) * DATA_ITEM_NUM * tx_num);
rmt_item32_t* item = (rmt_item32_t*) malloc(size);
int item_num = DATA_ITEM_NUM * tx_num;
memset((void*) item, 0, size);
int offset = 0;
int rx_channel = RMT_RX_CHANNEL;
rx_init();
RingbufHandle_t rb = NULL;
rmt_get_ringbuf_handle(rx_channel, &rb);
rmt_rx_start(rx_channel, 1);
// send data
set_tx_data(tx_channel, cmd, addr, item_num, item, offset);
rmt_write_items(tx_channel, item, item_num, 0);
rmt_wait_tx_done(tx_channel, portMAX_DELAY);
free(item);
// receive data
uint16_t tmp = get_rx_data(rb);
TEST_ASSERT(tmp == 100);
TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
TEST_ESP_OK(rmt_driver_uninstall(RMT_RX_CHANNEL));
}
TEST_CASE("RMT TX stop test", "[rmt][test_env=UT_T1_RMT]")
{
int rx_channel = RMT_RX_CHANNEL;
rx_init();
RingbufHandle_t rb = NULL;
rmt_get_ringbuf_handle(rx_channel, &rb);
rmt_rx_start(rx_channel, 1);
vTaskDelay(10);
tx_init();
int tx_channel = RMT_TX_CHANNEL;
int tx_num = RMT_TX_DATA_NUM;
ESP_LOGI(TAG, "RMT TX DATA");
size_t size = (sizeof(rmt_item32_t) * DATA_ITEM_NUM * tx_num);
rmt_item32_t* item = (rmt_item32_t*) malloc(size);
int item_num = DATA_ITEM_NUM * tx_num;
memset((void*) item, 0, size);
int offset = 0;
uint16_t cmd = 0x0;
uint16_t addr = 0x11;
// send data
set_tx_data(tx_channel, cmd, addr, item_num, item, offset);
rmt_write_items(tx_channel, item, item_num, 0);
vTaskDelay(1000 / portTICK_PERIOD_MS);
rmt_tx_stop(tx_channel);
free(item);
// receive data
uint16_t tmp = get_rx_data(rb);
TEST_ASSERT(tmp < 100);
TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
TEST_ESP_OK(rmt_driver_uninstall(RMT_RX_CHANNEL));
}
TEST_CASE("RMT loop_en test", "[rmt][test_env=UT_T1_RMT][ignore]")
{
rmt_tx_config_t tx_cfg = {
.loop_en = true, // set it as true
.carrier_duty_percent = 50,
.carrier_freq_hz = 38000,
.carrier_level = 1,
.carrier_en = RMT_TX_CARRIER_EN,
.idle_level = 0,
.idle_output_en = true,
};
rmt_config_t rmt_tx = {
.channel = RMT_TX_CHANNEL,
.gpio_num = RMT_TX_GPIO_NUM,
.mem_block_num = 1,
.clk_div = RMT_CLK_DIV,
.tx_config = tx_cfg,
.rmt_mode = 0,
};
rmt_config(&rmt_tx);
rmt_driver_install(rmt_tx.channel, 0, 0);
TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
int rx_channel = RMT_RX_CHANNEL;
rx_init();
RingbufHandle_t rb = NULL;
rmt_get_ringbuf_handle(rx_channel, &rb);
rmt_rx_start(rx_channel, 1);
vTaskDelay(10);
tx_init();
int tx_channel = RMT_TX_CHANNEL;
int tx_num = RMT_TX_DATA_NUM;
ESP_LOGI(TAG, "RMT TX DATA");
size_t size = (sizeof(rmt_item32_t) * DATA_ITEM_NUM * tx_num);
rmt_item32_t* item = (rmt_item32_t*) malloc(size);
int item_num = DATA_ITEM_NUM * tx_num;
memset((void*) item, 0, size);
int offset = 0;
uint16_t cmd = 0x0;
uint16_t addr = 0x11;
// send data
set_tx_data(tx_channel, cmd, addr, item_num, item, offset);
rmt_write_items(tx_channel, item, item_num, 0);
vTaskDelay(1000 / portTICK_PERIOD_MS);
rmt_tx_stop(tx_channel);
free(item);
// receive data
uint16_t tmp = get_rx_data(rb);
TEST_ASSERT(tmp < 100);
TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
TEST_ESP_OK(rmt_driver_uninstall(RMT_RX_CHANNEL));
}
TEST_CASE("RMT use multi channel", "[rmt][test_env=UT_T1_RMT]")
{
rmt_tx_config_t tx_cfg = {
.loop_en = true, // set it as true
.loop_en = true, // set it as true
.carrier_duty_percent = 50,
.carrier_freq_hz = 38000,
.carrier_level = 1,
@ -805,3 +549,215 @@ TEST_CASE("RMT use multi channel", "[rmt][test_env=UT_T1_RMT]")
TEST_ESP_OK(rmt_driver_uninstall(7));
}
TEST_CASE("RMT memory test", "[rmt][test_env=UT_T1_RMT]")
{
rmt_config_t rmt_rx;
rmt_rx.channel = RMT_RX_CHANNEL;
rmt_rx.gpio_num = RMT_RX_GPIO_NUM;
rmt_rx.clk_div = RMT_CLK_DIV;
rmt_rx.mem_block_num = 1;
rmt_rx.rmt_mode = RMT_MODE_RX;
rmt_rx.rx_config.filter_en = true;
rmt_rx.rx_config.filter_ticks_thresh = 100;
rmt_rx.rx_config.idle_threshold = RMT_ITEM32_TIMEOUT_US / 10 * (RMT_TICK_10_US);
TEST_ESP_OK(rmt_config(&rmt_rx));
for (int i = 0; i < 100; i++) {
TEST_ESP_OK(rmt_driver_install(rmt_rx.channel, 1000, 0));
TEST_ESP_OK(rmt_driver_uninstall(rmt_rx.channel));
}
}
// RMT channel num and memory block relationship
TEST_CASE("RMT memory block test", "[rmt][test_env=UT_T1_RMT]")
{
rmt_channel_t channel = 0;
rmt_config_t rmt_rx;
rmt_rx.channel = channel;
rmt_rx.gpio_num = RMT_RX_GPIO_NUM;
rmt_rx.clk_div = RMT_CLK_DIV;
rmt_rx.mem_block_num = 1;
rmt_rx.rmt_mode = RMT_MODE_RX;
rmt_rx.rx_config.filter_en = true;
rmt_rx.rx_config.filter_ticks_thresh = 100;
rmt_rx.rx_config.idle_threshold = RMT_ITEM32_TIMEOUT_US / 10 * (RMT_TICK_10_US);
TEST_ESP_OK(rmt_config(&rmt_rx));
TEST_ESP_OK(rmt_driver_install(rmt_rx.channel, 1000, 0));
TEST_ESP_OK(rmt_set_mem_block_num(channel, 8));
TEST_ASSERT(rmt_set_mem_block_num(channel, 9) == ESP_ERR_INVALID_ARG);
TEST_ASSERT(rmt_set_mem_block_num(channel, -1) == ESP_ERR_INVALID_ARG);
TEST_ESP_OK(rmt_driver_uninstall(rmt_rx.channel));
rmt_rx.channel = 7;
TEST_ESP_OK(rmt_config(&rmt_rx));
TEST_ESP_OK(rmt_driver_install(rmt_rx.channel, 1000, 0));
TEST_ASSERT(rmt_set_mem_block_num(rmt_rx.channel, 2) == ESP_ERR_INVALID_ARG);
TEST_ASSERT(rmt_set_mem_block_num(rmt_rx.channel, -1) == ESP_ERR_INVALID_ARG);
TEST_ESP_OK(rmt_driver_uninstall(rmt_rx.channel));
}
TEST_CASE("RMT send waveform(logic analyzer)", "[rmt][test_env=UT_T1_RMT][ignore]")
{
tx_init();
rmt_item32_t items[1];
items[0].duration0 = 300 / 10 * RMT_TICK_10_US; //300us
items[0].level0 = 1;
for (int i = 0; i < 500; i++) {
TEST_ESP_OK(rmt_write_items(RMT_TX_CHANNEL, items,
1, /* Number of items */
1 /* wait till done */));
vTaskDelay(10 / portTICK_PERIOD_MS); //every 10ms to write the item
}
TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
}
TEST_CASE("RMT basic TX and RX", "[rmt][test_env=UT_T1_RMT]")
{
rx_init();
RingbufHandle_t rb = NULL;
rmt_get_ringbuf_handle(RMT_RX_CHANNEL, &rb);
rmt_rx_start(RMT_RX_CHANNEL, 1);
ESP_LOGI(TAG, "Star receiving RMT data...");
tx_init();
uint16_t cmd = 0x0;
uint16_t addr = 0x11;
int num_items = DATA_ITEM_NUM * RMT_TX_DATA_NUM;
rmt_item32_t *items = calloc(num_items + 1, sizeof(rmt_item32_t));
vTaskDelay(pdMS_TO_TICKS(2000));
ESP_LOGI(TAG, "Sending RMT data...");
// send data
set_tx_data(RMT_TX_CHANNEL, cmd, addr, num_items, items, 0);
// wait until tx done
rmt_write_items(RMT_TX_CHANNEL, items, num_items, 1);
free(items);
// receive data
uint16_t tmp = get_rx_data(rb);
TEST_ASSERT(tmp == RMT_TX_DATA_NUM);
TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
TEST_ESP_OK(rmt_driver_uninstall(RMT_RX_CHANNEL));
}
TEST_CASE("RMT TX write item wait some ticks", "[rmt][test_env=UT_T1_RMT]")
{
rx_init();
RingbufHandle_t rb = NULL;
rmt_get_ringbuf_handle(RMT_RX_CHANNEL, &rb);
rmt_rx_start(RMT_RX_CHANNEL, 1);
ESP_LOGI(TAG, "Star receiving RMT data...");
tx_init();
uint16_t cmd = 0x0;
uint16_t addr = 0x11;
int num_items = DATA_ITEM_NUM * RMT_TX_DATA_NUM;
rmt_item32_t *items = calloc(num_items + 1, sizeof(rmt_item32_t));
vTaskDelay(pdMS_TO_TICKS(2000));
ESP_LOGI(TAG, "Sending RMT data...");
// send data
set_tx_data(RMT_TX_CHANNEL, cmd, addr, num_items, items, 0);
rmt_write_items(RMT_TX_CHANNEL, items, num_items, 0);
rmt_wait_tx_done(RMT_TX_CHANNEL, portMAX_DELAY);
free(items);
// receive data
uint16_t tmp = get_rx_data(rb);
TEST_ASSERT(tmp == RMT_TX_DATA_NUM);
TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
TEST_ESP_OK(rmt_driver_uninstall(RMT_RX_CHANNEL));
}
TEST_CASE("RMT TX stop test", "[rmt][test_env=UT_T1_RMT]")
{
rx_init();
RingbufHandle_t rb = NULL;
rmt_get_ringbuf_handle(RMT_RX_CHANNEL, &rb);
rmt_rx_start(RMT_RX_CHANNEL, 1);
ESP_LOGI(TAG, "Star receiving RMT data...");
tx_init();
uint16_t cmd = 0x0;
uint16_t addr = 0x11;
int num_items = DATA_ITEM_NUM * RMT_TX_DATA_NUM;
rmt_item32_t *items = calloc(num_items + 1, sizeof(rmt_item32_t));
vTaskDelay(pdMS_TO_TICKS(2000));
ESP_LOGI(TAG, "Sending RMT data...");
// send data
set_tx_data(RMT_TX_CHANNEL, cmd, addr, num_items, items, 0);
rmt_write_items(RMT_TX_CHANNEL, items, num_items, 0);
vTaskDelay(1000 / portTICK_PERIOD_MS);
rmt_tx_stop(RMT_TX_CHANNEL);
free(items);
// receive data
uint16_t tmp = get_rx_data(rb);
TEST_ASSERT(tmp < RMT_TX_DATA_NUM);
TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
TEST_ESP_OK(rmt_driver_uninstall(RMT_RX_CHANNEL));
}
TEST_CASE("RMT loop_en test", "[rmt][test_env=UT_T1_RMT][ignore]")
{
rmt_tx_config_t tx_cfg = {
.loop_en = true, // set it as true
.carrier_duty_percent = 50,
.carrier_freq_hz = 38000,
.carrier_level = 1,
.carrier_en = RMT_TX_CARRIER_EN,
.idle_level = 0,
.idle_output_en = true,
};
rmt_config_t rmt_tx = {
.channel = RMT_TX_CHANNEL,
.gpio_num = RMT_TX_GPIO_NUM,
.mem_block_num = 1,
.clk_div = RMT_CLK_DIV,
.tx_config = tx_cfg,
.rmt_mode = 0,
};
rmt_config(&rmt_tx);
rmt_driver_install(rmt_tx.channel, 0, 0);
TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
int rx_channel = RMT_RX_CHANNEL;
rx_init();
RingbufHandle_t rb = NULL;
rmt_get_ringbuf_handle(rx_channel, &rb);
rmt_rx_start(rx_channel, 1);
vTaskDelay(10);
tx_init();
int tx_channel = RMT_TX_CHANNEL;
int tx_num = RMT_TX_DATA_NUM;
ESP_LOGI(TAG, "RMT TX DATA");
size_t size = (sizeof(rmt_item32_t) * DATA_ITEM_NUM * tx_num);
rmt_item32_t *item = (rmt_item32_t *)malloc(size);
int item_num = DATA_ITEM_NUM * tx_num;
memset((void *)item, 0, size);
int offset = 0;
uint16_t cmd = 0x0;
uint16_t addr = 0x11;
// send data
set_tx_data(tx_channel, cmd, addr, item_num, item, offset);
rmt_write_items(tx_channel, item, item_num, 0);
vTaskDelay(1000 / portTICK_PERIOD_MS);
rmt_tx_stop(tx_channel);
free(item);
// receive data
uint16_t tmp = get_rx_data(rb);
TEST_ASSERT(tmp < RMT_TX_DATA_NUM);
TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
TEST_ESP_OK(rmt_driver_uninstall(RMT_RX_CHANNEL));
}

1
components/soc/CMakeLists.txt
View file

@ -12,6 +12,7 @@ list(APPEND include_dirs include)
list(APPEND srcs
"src/memory_layout_utils.c"
"src/lldesc.c"
"src/hal/rmt_hal.c"
"src/hal/spi_hal.c"
"src/hal/spi_hal_iram.c"
"src/hal/spi_slave_hal.c"

297
components/soc/esp32/include/hal/rmt_ll.h Normal file
View file

@ -0,0 +1,297 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include "soc/rmt_struct.h"
#include "soc/rmt_caps.h"
static inline void rmt_ll_reset_counter_clock_div(rmt_dev_t *dev, uint32_t channel)
{
dev->conf_ch[channel].conf1.ref_cnt_rst = 1;
dev->conf_ch[channel].conf1.ref_cnt_rst = 0;
}
static inline void rmt_ll_reset_tx_pointer(rmt_dev_t *dev, uint32_t channel)
{
dev->conf_ch[channel].conf1.mem_rd_rst = 1;
dev->conf_ch[channel].conf1.mem_rd_rst = 0;
}
static inline void rmt_ll_reset_rx_pointer(rmt_dev_t *dev, uint32_t channel)
{
dev->conf_ch[channel].conf1.mem_wr_rst = 1;
dev->conf_ch[channel].conf1.mem_wr_rst = 0;
}
static inline void rmt_ll_start_tx(rmt_dev_t *dev, uint32_t channel)
{
dev->conf_ch[channel].conf1.tx_start = 1;
}
static inline void rmt_ll_stop_tx(rmt_dev_t *dev, uint32_t channel)
{
RMTMEM.chan[channel].data32[0].val = 0;
dev->conf_ch[channel].conf1.tx_start = 0;
dev->conf_ch[channel].conf1.mem_rd_rst = 1;
dev->conf_ch[channel].conf1.mem_rd_rst = 0;
}
static inline void rmt_ll_enable_rx(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf1.rx_en = enable;
}
static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf0.mem_pd = enable;
}
static inline bool rmt_ll_is_mem_power_down(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf0.mem_pd;
}
static inline void rmt_ll_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)
{
dev->conf_ch[channel].conf0.mem_size = block_num;
}
static inline uint32_t rmt_ll_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf0.mem_size;
}
static inline void rmt_ll_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
{
dev->conf_ch[channel].conf0.div_cnt = div;
}
static inline uint32_t rmt_ll_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf0.div_cnt;
}
static inline void rmt_ll_enable_tx_pingpong(rmt_dev_t *dev, bool enable)
{
dev->apb_conf.mem_tx_wrap_en = enable;
}
static inline void rmt_ll_enable_mem_access(rmt_dev_t *dev, bool enable)
{
dev->apb_conf.fifo_mask = enable;
}
static inline void rmt_ll_set_rx_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
{
dev->conf_ch[channel].conf0.idle_thres = thres;
}
static inline uint32_t rmt_ll_get_rx_idle_thres(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf0.idle_thres;
}
static inline void rmt_ll_set_mem_owner(rmt_dev_t *dev, uint32_t channel, uint8_t owner)
{
dev->conf_ch[channel].conf1.mem_owner = owner;
}
static inline uint32_t rmt_ll_get_mem_owner(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.mem_owner;
}
static inline void rmt_ll_enable_tx_cyclic(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf1.tx_conti_mode = enable;
}
static inline bool rmt_ll_is_tx_cyclic_enabled(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.tx_conti_mode;
}
static inline void rmt_ll_enable_rx_filter(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf1.rx_filter_en = enable;
}
static inline void rmt_ll_set_rx_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
{
dev->conf_ch[channel].conf1.rx_filter_thres = thres;
}
static inline void rmt_ll_set_counter_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src)
{
dev->conf_ch[channel].conf1.ref_always_on = src;
}
static inline uint32_t rmt_ll_get_counter_clock_src(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.ref_always_on;
}
static inline void rmt_ll_enable_tx_idle(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf1.idle_out_en = enable;
}
static inline bool rmt_ll_is_tx_idle_enabled(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.idle_out_en;
}
static inline void rmt_ll_set_tx_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
{
dev->conf_ch[channel].conf1.idle_out_lv = level;
}
static inline uint32_t rmt_ll_get_tx_idle_level(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.idle_out_lv;
}
static inline uint32_t rmt_ll_get_channel_status(rmt_dev_t *dev, uint32_t channel)
{
return dev->status_ch[channel];
}
static inline void rmt_ll_set_tx_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
{
dev->tx_lim_ch[channel].limit = limit;
}
static inline void rmt_ll_enable_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel * 3));
dev->int_ena.val |= (enable << (channel * 3));
}
static inline void rmt_ll_enable_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel * 3 + 1));
dev->int_ena.val |= (enable << (channel * 3 + 1));
}
static inline void rmt_ll_enable_err_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel * 3 + 2));
dev->int_ena.val |= (enable << (channel * 3 + 2));
}
static inline void rmt_ll_enable_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel + 24));
dev->int_ena.val |= (enable << (channel + 24));
}
static inline void rmt_ll_clear_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel * 3));
}
static inline void rmt_ll_clear_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel * 3 + 1));
}
static inline void rmt_ll_clear_err_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel * 3 + 2));
}
static inline void rmt_ll_clear_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel + 24));
}
static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return ((status & 0x01) >> 0) | ((status & 0x08) >> 2) | ((status & 0x40) >> 4) | ((status & 0x200) >> 6) |
((status & 0x1000) >> 8) | ((status & 0x8000) >> 10) | ((status & 40000) >> 12) | ((status & 0x200000) >> 14);
}
static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return ((status & 0x02) >> 1) | ((status & 0x10) >> 3) | ((status & 0x80) >> 5) | ((status & 0x400) >> 7) |
((status & 0x2000) >> 9) | ((status & 0x10000) >> 11) | ((status & 80000) >> 13) | ((status & 0x400000) >> 15);
}
static inline uint32_t rmt_ll_get_err_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return ((status & 0x04) >> 2) | ((status & 0x20) >> 4) | ((status & 0x100) >> 6) | ((status & 0x800) >> 8) |
((status & 0x4000) >> 10) | ((status & 0x20000) >> 12) | ((status & 100000) >> 14) | ((status & 0x800000) >> 16);
}
static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return (status & 0xFF000000) >> 24;
}
static inline void rmt_ll_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
{
dev->carrier_duty_ch[channel].high = high_ticks;
dev->carrier_duty_ch[channel].low = low_ticks;
}
static inline void rmt_ll_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
{
*high_ticks = dev->carrier_duty_ch[channel].high;
*low_ticks = dev->carrier_duty_ch[channel].low;
}
static inline void rmt_ll_enable_tx_carrier(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf0.carrier_en = enable;
}
static inline void rmt_ll_set_carrier_to_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
{
dev->conf_ch[channel].conf0.carrier_out_lv = level;
}
static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const rmt_item32_t *data, uint32_t length, uint32_t off)
{
length = (off + length) > RMT_CHANNEL_MEM_WORDS ? (RMT_CHANNEL_MEM_WORDS - off) : length;
for (uint32_t i = 0; i < length; i++) {
mem->chan[channel].data32[i + off].val = data[i].val;
}
}
/************************************************************************************************
* Following Low Level APIs only used for backward compatible, will be deprecated in the future!
***********************************************************************************************/
static inline void rmt_ll_set_intr_enable_mask(uint32_t mask)
{
RMT.int_ena.val |= mask;
}
static inline void rmt_ll_clr_intr_enable_mask(uint32_t mask)
{
RMT.int_ena.val &= (~mask);
}
#ifdef __cplusplus
}
#endif

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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#define RMT_CHANNEL_MEM_WORDS (64) /*!< Each channel owns 64 words memory */
/**
* @brief RMT channel ID
*
*/
typedef enum {
RMT_CHANNEL_0, /*!< RMT channel number 0 */
RMT_CHANNEL_1, /*!< RMT channel number 1 */
RMT_CHANNEL_2, /*!< RMT channel number 2 */
RMT_CHANNEL_3, /*!< RMT channel number 3 */
RMT_CHANNEL_4, /*!< RMT channel number 4 */
RMT_CHANNEL_5, /*!< RMT channel number 5 */
RMT_CHANNEL_6, /*!< RMT channel number 6 */
RMT_CHANNEL_7, /*!< RMT channel number 7 */
RMT_CHANNEL_MAX /*!< Number of RMT channels */
} rmt_channel_id_t;
#ifdef __cplusplus
}
#endif

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components/soc/esp32s2beta/include/hal/rmt_ll.h Normal file
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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include "soc/rmt_struct.h"
#include "soc/rmt_caps.h"
static inline void rmt_ll_reset_counter_clock_div(rmt_dev_t *dev, uint32_t channel)
{
}
static inline void rmt_ll_reset_tx_pointer(rmt_dev_t *dev, uint32_t channel)
{
dev->conf_ch[channel].conf1.mem_rd_rst = 1;
dev->conf_ch[channel].conf1.mem_rd_rst = 0;
}
static inline void rmt_ll_reset_rx_pointer(rmt_dev_t *dev, uint32_t channel)
{
dev->conf_ch[channel].conf1.mem_wr_rst = 1;
dev->conf_ch[channel].conf1.mem_wr_rst = 0;
}
static inline void rmt_ll_start_tx(rmt_dev_t *dev, uint32_t channel)
{
dev->conf_ch[channel].conf1.tx_start = 1;
}
static inline void rmt_ll_stop_tx(rmt_dev_t *dev, uint32_t channel)
{
dev->conf_ch[channel].conf1.tx_stop = 1;
}
static inline void rmt_ll_enable_rx(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf1.rx_en = enable;
}
static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf0.mem_pd = enable;
}
static inline bool rmt_ll_is_mem_power_down(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf0.mem_pd;
}
static inline void rmt_ll_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)
{
dev->conf_ch[channel].conf0.mem_size = block_num;
}
static inline uint32_t rmt_ll_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf0.mem_size;
}
static inline void rmt_ll_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
{
dev->conf_ch[channel].conf0.div_cnt = div;
}
static inline uint32_t rmt_ll_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf0.div_cnt;
}
static inline void rmt_ll_enable_tx_pingpong(rmt_dev_t *dev, bool enable)
{
dev->apb_conf.mem_tx_wrap_en = enable;
}
static inline void rmt_ll_enable_mem_access(rmt_dev_t *dev, bool enable)
{
dev->apb_conf.fifo_mask = enable;
}
static inline void rmt_ll_set_rx_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
{
dev->conf_ch[channel].conf0.idle_thres = thres;
}
static inline uint32_t rmt_ll_get_rx_idle_thres(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf0.idle_thres;
}
static inline void rmt_ll_set_mem_owner(rmt_dev_t *dev, uint32_t channel, uint8_t owner)
{
dev->conf_ch[channel].conf1.mem_owner = owner;
}
static inline uint32_t rmt_ll_get_mem_owner(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.mem_owner;
}
static inline void rmt_ll_enable_tx_cyclic(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf1.tx_conti_mode = enable;
}
static inline bool rmt_ll_is_tx_cyclic_enabled(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.tx_conti_mode;
}
static inline void rmt_ll_enable_rx_filter(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf1.rx_filter_en = enable;
}
static inline void rmt_ll_set_rx_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
{
dev->conf_ch[channel].conf1.rx_filter_thres = thres;
}
static inline void rmt_ll_set_counter_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src)
{
dev->conf_ch[channel].conf1.ref_always_on = src;
}
static inline uint32_t rmt_ll_get_counter_clock_src(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.ref_always_on;
}
static inline void rmt_ll_enable_tx_idle(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf1.idle_out_en = enable;
}
static inline bool rmt_ll_is_tx_idle_enabled(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.idle_out_en;
}
static inline void rmt_ll_set_tx_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
{
dev->conf_ch[channel].conf1.idle_out_lv = level;
}
static inline uint32_t rmt_ll_get_tx_idle_level(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.idle_out_lv;
}
static inline uint32_t rmt_ll_get_channel_status(rmt_dev_t *dev, uint32_t channel)
{
return dev->status_ch[channel].val;
}
static inline void rmt_ll_set_tx_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
{
dev->tx_lim_ch[channel].limit = limit;
}
static inline void rmt_ll_enable_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel * 3));
dev->int_ena.val |= (enable << (channel * 3));
}
static inline void rmt_ll_enable_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel * 3 + 1));
dev->int_ena.val |= (enable << (channel * 3 + 1));
}
static inline void rmt_ll_enable_err_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel * 3 + 2));
dev->int_ena.val |= (enable << (channel * 3 + 2));
}
static inline void rmt_ll_enable_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel + 12));
dev->int_ena.val |= (enable << (channel + 12));
}
static inline void rmt_ll_clear_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel * 3));
}
static inline void rmt_ll_clear_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel * 3 + 1));
}
static inline void rmt_ll_clear_err_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel * 3 + 2));
}
static inline void rmt_ll_clear_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel + 12));
}
static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return ((status & 0x01) >> 0) | ((status & 0x08) >> 2) | ((status & 0x40) >> 4) | ((status & 0x200) >> 6);
}
static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return ((status & 0x02) >> 1) | ((status & 0x10) >> 3) | ((status & 0x80) >> 5) | ((status & 0x400) >> 7);
}
static inline uint32_t rmt_ll_get_err_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return ((status & 0x04) >> 2) | ((status & 0x20) >> 4) | ((status & 0x100) >> 6) | ((status & 0x800) >> 8);;
}
static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return (status & 0xF000) >> 12;
}
static inline void rmt_ll_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
{
dev->carrier_duty_ch[channel].high = high_ticks;
dev->carrier_duty_ch[channel].low = low_ticks;
}
static inline void rmt_ll_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
{
*high_ticks = dev->carrier_duty_ch[channel].high;
*low_ticks = dev->carrier_duty_ch[channel].low;
}
static inline void rmt_ll_enable_tx_carrier(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf0.carrier_en = enable;
}
static inline void rmt_ll_set_carrier_to_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
{
dev->conf_ch[channel].conf0.carrier_out_lv = level;
}
static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const rmt_item32_t *data, uint32_t length, uint32_t off)
{
length = (off + length) > RMT_CHANNEL_MEM_WORDS ? (RMT_CHANNEL_MEM_WORDS - off) : length;
for (uint32_t i = 0; i < length; i++) {
mem->chan[channel].data32[i + off].val = data[i].val;
}
}
/************************************************************************************************
* Following Low Level APIs only used for backward compatible, will be deprecated in the future!
***********************************************************************************************/
static inline void rmt_ll_set_intr_enable_mask(uint32_t mask)
{
RMT.int_ena.val |= mask;
}
static inline void rmt_ll_clr_intr_enable_mask(uint32_t mask)
{
RMT.int_ena.val &= (~mask);
}
#ifdef __cplusplus
}
#endif

39
components/soc/esp32s2beta/include/soc/rmt_caps.h Normal file
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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#define RMT_CHANNEL_MEM_WORDS (64) /*!< Each channel owns 64 words memory */
/**
* @brief RMT channel ID
*
*/
typedef enum {
RMT_CHANNEL_0, /*!< RMT channel number 0 */
RMT_CHANNEL_1, /*!< RMT channel number 1 */
RMT_CHANNEL_2, /*!< RMT channel number 2 */
RMT_CHANNEL_3, /*!< RMT channel number 3 */
RMT_CHANNEL_MAX /*!< Number of RMT channels */
} rmt_channel_id_t;
#ifdef __cplusplus
}
#endif

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components/soc/esp32s2beta/include/soc/rmt_struct.h
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@ -13,6 +13,9 @@
// limitations under the License.
#ifndef _SOC_RMT_STRUCT_H_
#define _SOC_RMT_STRUCT_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
@ -298,4 +301,4 @@ extern rmt_mem_t RMTMEM;
}
#endif
#endif /* _SOC_RMT_STRUCT_H_ */
#endif /* _SOC_RMT_STRUCT_H_ */

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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "soc/rmt_struct.h"
#include "soc/rmt_caps.h"
/**
* @brief HAL context type of RMT driver
*
*/
typedef struct {
rmt_dev_t *regs; /*!< RMT Register base address */
rmt_mem_t *mem; /*!< RMT Memory base address */
} rmt_hal_context_t;
#define RMT_MEM_OWNER_SW (0) /*!< RMT Memory ownership belongs to software side */
#define RMT_MEM_OWNER_HW (1) /*!< RMT Memory ownership belongs to hardware side */
/**
* @brief Initialize the RMT HAL driver
*
* @param hal: RMT HAL context
*/
void rmt_hal_init(rmt_hal_context_t *hal);
/**
* @brief Reset RMT HAL driver
*
* @param hal: RMT HAL context
*/
void rmt_hal_reset(rmt_hal_context_t *hal);
/**
* @brief Reset RMT Channel specific HAL driver
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
*/
void rmt_hal_channel_reset(rmt_hal_context_t *hal, uint32_t channel);
/**
* @brief Set counter clock for RMT channel
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param base_clk_hz: base clock for RMT internal channel (counter clock will divide from it)
* @param counter_clk_hz: target counter clock
*/
void rmt_hal_set_counter_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t counter_clk_hz);
/**
* @brief Get counter clock for RMT channel
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param base_clk_hz: base clock for RMT internal channel (counter clock will divide from it)
* @return counter clock in Hz
*/
uint32_t rmt_hal_get_counter_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz);
/**
* @brief Set carrier clock for RMT channel
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param base_clk_hz: base clock for RMT carrier generation (carrier clock will divide from it)
* @param carrier_clk_hz: target carrier clock
* @param carrier_clk_duty: duty ratio of carrier clock
*/
void rmt_hal_set_carrier_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t carrier_clk_hz, float carrier_clk_duty);
/**
* @brief Get carrier clock for RMT channel
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param base_clk_hz: base clock for RMT carrier generation
* @param carrier_clk_hz: target carrier clock
* @param carrier_clk_duty: duty ratio of carrier clock
*/
void rmt_hal_get_carrier_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t *carrier_clk_hz, float *carrier_clk_duty);
/**
* @brief Set filter threshold for RMT Receive channel
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param base_clk_hz: base clock for RMT receive filter
* @param thres_us: threshold of RMT receive filter, in us
*/
void rmt_hal_set_rx_filter_thres(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t thres_us);
/**
* @brief Set idle threshold for RMT Receive channel
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param base_clk_hz: base clock for RMT receive channel
* @param thres_us: IDLE threshold for RMT receive channel
*/
void rmt_hal_set_rx_idle_thres(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t thres_us);
/**
* @brief Receive a frame from RMT channel
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param buf: buffer to store received RMT frame
* @return number of items that get received
*/
uint32_t rmt_hal_receive(rmt_hal_context_t *hal, uint32_t channel, rmt_item32_t *buf);
/**
* @brief Transmit a from by RMT
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param src: RMT items to transmit
* @param length: length of RMT items to transmit
* @param offset: offset of RMT internal memory to store the items
*/
void rmt_hal_transmit(rmt_hal_context_t *hal, uint32_t channel, const rmt_item32_t *src, uint32_t length, uint32_t offset);
#ifdef __cplusplus
}
#endif

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@ -0,0 +1,108 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief RMT Channel Type
*
*/
typedef rmt_channel_id_t rmt_channel_t;
/**
* @brief RMT Internal Memory Owner
*
*/
typedef enum {
RMT_MEM_OWNER_TX, /*!< RMT RX mode, RMT transmitter owns the memory block*/
RMT_MEM_OWNER_RX, /*!< RMT RX mode, RMT receiver owns the memory block*/
RMT_MEM_OWNER_MAX,
} rmt_mem_owner_t;
/**
* @brief Clock Source of RMT Channel
*
*/
typedef enum {
RMT_BASECLK_REF, /*!< RMT source clock system reference tick, 1MHz by default (not supported in this version) */
RMT_BASECLK_APB, /*!< RMT source clock is APB CLK, 80Mhz by default */
RMT_BASECLK_MAX,
} rmt_source_clk_t;
/**
* @brief RMT Data Mode
*
* @note We highly recommended to use MEM mode not FIFO mode since there will be some gotcha in FIFO mode.
*
*/
typedef enum {
RMT_DATA_MODE_FIFO, /*<! RMT memory access in FIFO mode */
RMT_DATA_MODE_MEM, /*<! RMT memory access in memory mode */
RMT_DATA_MODE_MAX,
} rmt_data_mode_t;
/**
* @brief RMT Channel Working Mode (TX or RX)
*
*/
typedef enum {
RMT_MODE_TX, /*!< RMT TX mode */
RMT_MODE_RX, /*!< RMT RX mode */
RMT_MODE_MAX
} rmt_mode_t;
/**
* @brief RMT Idle Level
*
*/
typedef enum {
RMT_IDLE_LEVEL_LOW, /*!< RMT TX idle level: low Level */
RMT_IDLE_LEVEL_HIGH, /*!< RMT TX idle level: high Level */
RMT_IDLE_LEVEL_MAX,
} rmt_idle_level_t;
/**
* @brief RMT Carrier Level
*
*/
typedef enum {
RMT_CARRIER_LEVEL_LOW, /*!< RMT carrier wave is modulated for low Level output */
RMT_CARRIER_LEVEL_HIGH, /*!< RMT carrier wave is modulated for high Level output */
RMT_CARRIER_LEVEL_MAX
} rmt_carrier_level_t;
/**
* @brief RMT Channel Status
*
*/
typedef enum {
RMT_CHANNEL_UNINIT, /*!< RMT channel uninitialized */
RMT_CHANNEL_IDLE, /*!< RMT channel status idle */
RMT_CHANNEL_BUSY, /*!< RMT channel status busy */
} rmt_channel_status_t;
/**
* @brief Data struct of RMT channel status
*/
typedef struct {
rmt_channel_status_t status[RMT_CHANNEL_MAX]; /*!< Store the current status of each channel */
} rmt_channel_status_result_t;
#ifdef __cplusplus
}
#endif

106
components/soc/src/hal/rmt_hal.c Normal file
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@ -0,0 +1,106 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "hal/rmt_hal.h"
#include "hal/rmt_ll.h"
void rmt_hal_init(rmt_hal_context_t *hal)
{
hal->regs = &RMT;
hal->mem = &RMTMEM;
}
void rmt_hal_reset(rmt_hal_context_t *hal)
{
}
void rmt_hal_channel_reset(rmt_hal_context_t *hal, uint32_t channel)
{
rmt_ll_reset_tx_pointer(hal->regs, channel);
rmt_ll_reset_rx_pointer(hal->regs, channel);
rmt_ll_enable_err_interrupt(hal->regs, channel, false);
rmt_ll_enable_tx_end_interrupt(hal->regs, channel, false);
rmt_ll_enable_tx_thres_interrupt(hal->regs, channel, false);
rmt_ll_enable_rx_end_interrupt(hal->regs, channel, false);
rmt_ll_clear_err_interrupt(hal->regs, channel);
rmt_ll_clear_tx_end_interrupt(hal->regs, channel);
rmt_ll_clear_tx_thres_interrupt(hal->regs, channel);
rmt_ll_clear_rx_end_interrupt(hal->regs, channel);
}
void rmt_hal_set_counter_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t counter_clk_hz)
{
rmt_ll_reset_counter_clock_div(hal->regs, channel);
uint32_t counter_div = (base_clk_hz + counter_clk_hz / 2) / counter_clk_hz;
rmt_ll_set_counter_clock_div(hal->regs, channel, counter_div);
}
uint32_t rmt_hal_get_counter_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz)
{
return base_clk_hz / rmt_ll_get_counter_clock_div(hal->regs, channel);
}
void rmt_hal_set_carrier_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t carrier_clk_hz, float carrier_clk_duty)
{
uint32_t carrier_div = (base_clk_hz + carrier_clk_hz / 2) / carrier_clk_hz;
uint32_t div_high = (uint32_t)(carrier_div * carrier_clk_duty);
uint32_t div_low = carrier_div - div_high;
rmt_ll_set_carrier_high_low_ticks(hal->regs, channel, div_high, div_low);
}
void rmt_hal_get_carrier_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t *carrier_clk_hz, float *carrier_clk_duty)
{
uint32_t div_high = 0;
uint32_t div_low = 0;
rmt_ll_get_carrier_high_low_ticks(hal->regs, channel, &div_high, &div_low);
*carrier_clk_hz = base_clk_hz / (div_high + div_low);
*carrier_clk_duty = (float)div_high / (div_high + div_low);
}
void rmt_hal_set_rx_filter_thres(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t thres_us)
{
uint32_t thres = (uint32_t)(base_clk_hz / 1e6 * thres_us);
rmt_ll_set_rx_filter_thres(hal->regs, channel, thres);
}
void rmt_hal_set_rx_idle_thres(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t thres_us)
{
uint32_t thres = (uint32_t)(base_clk_hz / 1e6 * thres_us);
rmt_ll_set_rx_idle_thres(hal->regs, channel, thres);
}
uint32_t rmt_hal_receive(rmt_hal_context_t *hal, uint32_t channel, rmt_item32_t *buf)
{
uint32_t len = 0;
rmt_ll_set_mem_owner(hal->regs, channel, RMT_MEM_OWNER_SW);
for (len = 0; len < RMT_CHANNEL_MEM_WORDS; len++) {
buf[len].val = hal->mem->chan[channel].data32[len].val;
if (!(buf[len].val & 0x7FFF)) {
break;
} else if (!(buf[len].val & 0x7FFF0000)) {
len++;
break;
}
}
rmt_ll_set_mem_owner(hal->regs, channel, RMT_MEM_OWNER_HW);
rmt_ll_reset_rx_pointer(hal->regs, channel);
return len;
}
void rmt_hal_transmit(rmt_hal_context_t *hal, uint32_t channel, const rmt_item32_t *src, uint32_t length, uint32_t offset)
{
rmt_ll_set_mem_owner(hal->regs, channel, RMT_MEM_OWNER_SW);
rmt_ll_write_memory(hal->mem, channel, src, length, offset);
rmt_ll_set_mem_owner(hal->regs, channel, RMT_MEM_OWNER_HW);
}

1
docs/Doxyfile
View file

@ -103,6 +103,7 @@ INPUT = \
../../components/driver/include/driver/touch_pad.h \
../../components/driver/include/driver/uart.h \
../../components/esp_adc_cal/include/esp_adc_cal.h \
../../components/soc/include/hal/rmt_types.h \
../../components/soc/include/hal/spi_types.h \
../../components/soc/include/hal/pcnt_types.h \
../../components/soc/esp32/include/soc/adc_channel.h \

11
docs/en/api-reference/peripherals/rmt.rst
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@ -153,7 +153,7 @@ Now, depending on how the channel is configured, we are ready to either `Transmi
Transmit Data
-------------
Before being able to transmit some RMT pulses, we need to define the pulse pattern. The minimum pattern recognized by the RMT controller, later called an 'item', is provided in a structure :cpp:type:`rmt_item32_t`, see :component_file:`soc/esp32/include/soc/rmt_struct.h`. Each item consists of two pairs of two values. The first value in a pair describes the signal duration in ticks and is 15 bits long, the second provides the signal level (high or low) and is contained in a single bit. A block of couple of items and the structure of an item is presented below.
Before being able to transmit some RMT pulses, we need to define the pulse pattern. The minimum pattern recognized by the RMT controller, later called an 'item', is provided in a structure :cpp:type:`rmt_item32_t`, see :component_file:`soc/esp32/include/soc/rmt_caps.h`. Each item consists of two pairs of two values. The first value in a pair describes the signal duration in ticks and is 15 bits long, the second provides the signal level (high or low) and is contained in a single bit. A block of couple of items and the structure of an item is presented below.
.. packetdiag::
:caption: Structure of RMT items (L - signal level)
@ -176,7 +176,7 @@ Before being able to transmit some RMT pulses, we need to define the pulse patte
127: L
}
For a simple example how to define a block of items see :example:`peripherals/rmt_tx`.
For a simple example how to define a block of items see :example:`peripherals/rmt/morse_code`.
The items are provided to the RMT controller by calling function :cpp:func:`rmt_write_items`. This function also automatically triggers start of transmission. It may be called to wait for transmission completion or exit just after transmission start. In such case you can wait for the transmission end by calling :cpp:func:`rmt_wait_tx_done`. This function does not limit the number of data items to transmit. It is using an interrupt to successively copy the new data chunks to RMT's internal memory as previously provided data are sent out.
@ -188,7 +188,7 @@ Receive Data
Before starting the receiver we need some storage for incoming items. The RMT controller has 512 x 32-bits of internal RAM shared between all eight channels. In typical scenarios it is not enough as an ultimate storage for all incoming (and outgoing) items. Therefore this API supports retrieval of incoming items on the fly to save them in a ring buffer of a size defined by the user. The size is provided when calling :cpp:func:`rmt_driver_install` discussed above. To get a handle to this buffer call :cpp:func:`rmt_get_ringbuf_handle`.
With the above steps complete we can start the receiver by calling :cpp:func:`rmt_rx_start` and then move to checking what's inside the buffer. To do so, you can use common FreeRTOS functions that interact with the ring buffer. Please see an example how to do it in :example:`peripherals/rmt_nec_tx_rx`.
With the above steps complete we can start the receiver by calling :cpp:func:`rmt_rx_start` and then move to checking what's inside the buffer. To do so, you can use common FreeRTOS functions that interact with the ring buffer. Please see an example how to do it in :example:`peripherals/rmt/ir_protocols`.
To stop the receiver, call :cpp:func:`rmt_rx_stop`.
@ -256,8 +256,9 @@ If the RMT driver has been installed with :cpp:func:`rmt_driver_install` for som
Application Examples
--------------------
* A simple RMT TX example: :example:`peripherals/rmt_tx`.
* NEC remote control TX and RX example: :example:`peripherals/rmt_nec_tx_rx`.
* A simple RMT TX example: :example:`peripherals/rmt/morse_code`.
* Another RMT TX example, specific to drive a common RGB LED strip: :example:`peripherals/rmt/led_strip`.
* NEC remote control TX and RX example: :example:`peripherals/rmt/ir_protocols`.
API Reference