These functions were discarded but not provided in ROM.
Generated from commit 8ad0aa7d6 in newlib script repo. Didn't rebuild most of libc/libc_nano,
only appended the missing object files to the existing archives (should save some git churn).
In the queue registry test, start_sem is given twice to let both tasks
start the test. Each task takes start_sem, does some work, gives done_sem,
and goes on to wait for start_sem again.
It may happen that one task can grab start_sem, add queues to the
registry, give done_sem, then grab start_sem again, delete the queues
from the registry, and give done_sem again. At this point, main test
task takes done_sem twice and proceeds to verify that queues have been
added to the registry. But in fact, the first task has already deleted
its queues from the registry, and the second one might not have added
the queues yet. This causes test to fail.
This changes the test to use separate start semaphores for each task,
to avoid the race condition.
1. All the registers of touch sensor 8 and 9 are mismatched except the ‘dac’ field in touch register of RTC IO
2. To swap the index for sensor 8 and 9 in APIs.
This commit makes the configQUEUE_REGISTRY_SIZE and
configGENERATE_RUN_TIME_STATS configurable in menuconfig.
- configQUEUE_REGISTRY_SIZE can now be set in menuconfig.
- The functions vQueueAddToRegistry() and vQueueUnregisterQueue() were made
SMP compatbile
- pcQueueGetName() was backported from FreeRTOS v9.0.0
- Added test case for Queue Registry functions
- configGENERATE_RUN_TIME_STATS can now be enabled in menuconfig. CCOUNT or
esp_timer can be selected as the FreeRTOS run time clock in menuconfig as
well, although CCOUNT will overflow quickly.
- Run time stats collection (in vTaskSwitchContext) and generation (in
uxTaskGetSystemState) have been made SMP compatible. Therefore
vTaskGetRunTimeStats() now displays the run time usage of each task as a
percentage of total runtime of both CPUs
Squash
- Remove ASCII-only configuration, CP437 is used instead
- Add dynamic code page configuration
See components/fatfs/src/00history.txt for FATFS changelog.
Reported from github:
https://github.com/espressif/esp-idf/issues/1219https://github.com/espressif/esp-idf/issues/1202
After providing a simple code to digital team, they confirmed that this is a hardware bug.
Root cause:
The fifo reset signal is incorrectly connected
If we want to reset tx fifo of UART2, we have to set txfifo_rst bit of both UART1 and UART2
If we want to reset rx fifo of UART2, we have to set rxfifo_rst bit of both UART1 and UART2
Workaround:
we don't use fifo rst bit in driver.
Documentation:
Digital team would update TRM and give more explanation about this issue.
1. use esp_timer instead of FreeRTOS timer to implement osi_alarm in bluedroid
2. Remove two APIs: osi_alarm_now() and osi_alarm_time_diff() and modify the hci layer logic that use them
3. Implement osi_alarm_get_remaining_ms()
4. Move the definition of struct alarm_t in source file "alarm.c"
5. Add definition of module error code
To achieve reliable operation with GD flash at 80MHz, need to raise
core voltage.
This causes the following current consumption increase:
At 80MHz: from 29mA to 33mA
At 160MHz: from 41mA to 47mA
Test conditions: 2 cores running code from IRAM, remaining peripherals
clock gated.
Earlier recursive mutex was being used for this but since
SCOMPARE1 is already being saved/restored during context
switch, atomic compare and set can be used for this.
Signed-off-by: Mahavir Jain <mahavir@espressif.com>
Test cases were added for the following functions
- xTaskNotify(), xTaskNotifyGive(), xTaskNotifyFromISR(), vTaskNotifyGiveFromISR(),
- xTaskNotifyWait(), ulTaskNotifyTake()
- vTaskDelayUntil()
The following function was made smp compatible and tested as well
- eTaskGetState()
Old behavior assumes message compressed when any of 2 most significant bits are set,
But in fact Message compressed only when both those bits are set to 1.
Also maximal label length should be 63 bytes.
Renamed the internal rc to __err_rc to avoid clashes with local variables.
This code would not do the expected thing with the original ESP_ERROR_CHECK macro:
esp_err_t my_func(esp_err_t x)
{
assert(x == 23);
}
esp_err_t rc = 23; //some value that is important fo the user
ESP_ERROR_CHECK(my_func(rc));
The macro will expand to:
esp_err_t rc = (my_func(rc));
And the code will assert, as my_func will receive a random value - whatever is in the internal macro rc temp variable. This is due to the C weirdness of allowing this code:
int x = x; //x has a random value.
Pointer tcpip_api_call *m should be converted to pppapi_msg* instead of pppapi_msg_msg*
in pppapi_do_ppp_set_default(), pppapi_do_ppp_free() and so on.
It solve this issue https://github.com/espressif/esp-idf/pull/1028
so there is no need to patch ip4.c because now netif_defauilt is setted correctly.
Also it prevents memory corruption when pppapi_free() is called.
This commit reverts the revert on the new task watchdog API. It also
fixes the following bug which caused the reversion.
- sdkconfig TASK_WDT_TIMEOUT_S has been reverted from the unit of ms back to the
unit of seconds. Fixes bug where projects using the new API without rebuilding sdkconfig
would cause the old default value of 5 to be interpreted in ms.
This commit also adds the following features to the task watchdog
- Updated idle hook registration to be compatible with dual core hooks
- Updated dual core hooks to support deregistration for cpu
- Legacy mode has been removed and esp_task_wdt_feed() is now replaced by
esp_task_wdt_reset(). esp_task_wdt_feed() is deprecated
- Idle hooks to reset are now registered/deregistered when the idle tasks are
added/deleted from the Task Watchdog instead of at Task Watchdog init/deinit
- Updated example
1. V366, fix a problem which initialize current can reach 800mA.
2. V365, fix a problem for pll_cap tracking in Coexist (BT & WIFI)
mode. The problem will make Coexist (BT & WIFI) WIFI AP mode TX
Fail in high temperature(>70).
3. V364, fix a bug of BT and Wifi coexist (hung in function of
force_wifi_mode())
component/bt: Fix the bug of master don't send pair request to the slave when the sec_act set to the value of ESP_BLE_SEC_ENCRYPT.
See merge request !1376
1. move settings of WIFI_CLK_EN_REG for bluetooth into controller init/deinit APIs
2. modify the bit mask used in phy_rf init/deinit to use WIFI-BT shared bits
This commit updates various test cases throughout esp-idf such that
the values used for timer divider pass the assertions in the timer component.
Timer divider values must be between 2 to 65536
Previously esp_restart would stall the other CPU before enabling RTC_WDT.
If the other CPU was executing an s32c1i instruction, the lock signal
from CPU to the arbiter would still be held after CPU was stalled. If
the CPU running esp_restart would then try to access the same locked
memory pool, it would be stuck, because lock signal would never be
released.
With this change, esp_restart resets the other CPU before stalling it.
Ideally, we would want to reset the CPU and keep it in reset, but the
hardware doesn't have such feature for PRO_CPU (it is possible to hold
APP_CPU in reset using DPORT register). Given that ROM code will not use
s32c1i in the first few hundred cycles, doing reset and then stall seems
to be safe.
In addition to than, RTC_WDT initialization is moved to the beginning of
the function, to prevent possible lock-up if CPU stalling still has any
issue.
1. Make sure that 8MD256 clock used to estimate XTAL frequency is enabled
before trying to use rtc_clk_cal_ratio.
This fixes "Bogus XTAL frequency: 0 MHz" warnings after software reset.
2. Don't call rtc_clk_xtal_freq_estimate if XTAL frequency is already
known. This reduces startup time after deep sleep or software reset.
3. Compare known XTAL frequency and estimated one before printing a
warning. This fixes "Possibly invalid CONFIG_ESP32_XTAL_FREQ setting
(40MHz). Detected 40 MHz." warnings.
Previous implementation waited for 20us after setting
RTC_CNTL_SOC_CLK_SEL_XTL register, using ets_delay_us, assuming that
the CPU was running at XTAL frequency. In reality, clock switch happened
on the next RTC_SLOW_CLK cycle, and CPU could be running at the previous
frequency (for example, 240 MHz) until then.
ets_delay_us would wait for 20 us * 40 cycles per us = 800 CPU cycles
(assuming 40 MHz XTAL; even less with a 26 MHz XTAL).
But if CPU was running at 240 MHz, 800 cycles would pass in just 3.3us,
while SLOW_CLK cycle could happen as much as 1/150kHz = 6.7us after
RTC_CNTL_SOC_CLK_SEL_XTL was set. So the software would not actually wait
long enough for the clock switch to happen, and would disable the PLL
while CPU was still clocked from PLL, leading to a halt.
This implementation uses rtc_clk_wait_for_slow_cycle() function to wait
until the clock switch, removing the need to wait for a fixed number of
CPU cycles.
Some RTC features are synchronized to RTC_SLOW_CLK, so sometimes
software needs to wait for the next slow clock cycle.
This function implements waiting using Timer Group clock calibration
feature.
