1. New tests for SD card on slot 0. Currently frequency for 4-bit mode
has to be reduced in the test.
2. Change pin for CD/WP tests, re-enable CD tests.
Works for 3.3V eMMC in 4 line mode.
Not implemented:
- DDR mode for SD cards (UHS-I) also need voltage to be switched to 1.8V.
- 8-line DDR mode for eMMC to be implemented later.
It is possible to utilize some of the routines related to otadata
partition validation, after firmware image is downloaded to RAM. Hence
these routines should be part of app cpu cache, so that they do not
get overwritten by firmware.
Signed-off-by: Mahavir Jain <mahavir@espressif.com>
Allows OTA updates to be secured via signature checks, without requiring the overhead or complexity
of a full secure boot implementation.
Uses same signing mechanisms (build system and/or espsecure.py as Secure Boot).
Requires:
* [ ] More testing
* [ ] Documentation
res was declared as “bool” so expression
((count == 0) ? A2D_SET_ONE_BIT : A2D_SET_MULTL_BIT)
always evaluated to “true”, and was implicitly converted to
A2D_SET_ONE_BIT.
Avoids growing the result of hardware bignum operations
(particularly for multiplication)
Fixes bugs where some Elliptic Curve operations fail or corrupt memory,
as they assume length of the number is never greater than the number of
non-zero limbs.
Includes some general refactoring to standardize terminology.
Closes https://github.com/espressif/esp-idf/issues/1556
Fixes TW12984
Adds test cases for both these issues.
1. after memory release MR merged, due to the get acl number condition is not completed, it will cause get acl number value incorrect
2. It may cause set Security Mode (BR/EDR) enable failed
1. change static emac-dma memory to dynamic
2. add esp_eth_deinit
3. modify ethernet example
4. add testcase for ethernet deinit function
5. GPIO0 could not output the 50MHz clock to PHY, so remove this configuration
1. new APIs: esp_mesh_get_subnet_nodes_num() and esp_mesh_get_subnet_nodes_list().
2. fix hard to find the parent during connect.
3. disable Wi-Fi channel switch function.
4. fix a typo of MESH_EVENT_NO_PARENT_FOUND.
esp_reset_reason_init would check for reset reason hint, and
unconditionally set RTC_RESET_CAUSE_REG (which is also
RTC_ENTRY_ADDR_REG) to hint value 0, i.e. 0x80000000. However the ROM
code treats this value as valid deep sleep wake stub entry point, and
tries to jump to it.
Clear RTC_RESET_CAUSE_REG only if it contained a valid reset reason
hint, and simply set the register value to 0 when doing so. Also add
a check to esp_get_deep_sleep_wake_stub function that deep sleep wake
stub entry address must be in IRAM.
Reported in https://esp32.com/viewtopic.php?f=13&t=6919.
Fix following WiFi bugs:
1. Shouldn't scan when connect
2. Check beacon length in modem sleep
3. Fix the bug that AP may deauth wrong station when inactivity timer expires
4. Fix the bug that WiFi assert the system when receiving empty MCS in association response frame
Multiple modules register their callback BTA_GATTS_AppRegister().
If any of the callbacks do not free the allocated pointer in
BTA_GATTS_CONF_EVT event, then this can result in memory leak.
So, free the pointer after the callback function is called and remove
the calls to free in the callback functions as it is now not required
Signed-off-by: Hrishikesh Dhayagude <hrishi@espressif.com>
This is just a quick glance at all the header files exposed to the
users from cleanup point of view.
Signed-off-by: Hrishikesh Dhayagude <hrishi@espressif.com>
We have fixed a bug in test script. Before that, we didn't do strict check when generate the mesh tree, which makes the test pass.
Temp disable these cases, to let CI pass before bug fixed.
When 32k XTAL was selected as clock source, if the first calibration
attempt failed, the code would fall back to 150kHz internal clock.
Calibration with the internal clock will always succeed.
Therefore `wait` would always be either 0 or 1. Based on this, some
code in this routine can be eliminated.
Marking a page full does not skip it from page selection process and the
same page might get returned if there is no other page with more unused
entries. Added a check for the same while storing blobs.
Fixes: https://github.com/espressif/esp-idf/issues/2313
Previous APIs used to set CPU frequency used CPU frequencies listed in
rtc_cpu_freq_t enumeration. This was problematic for two reasons.
First, supporting many possible frequency values obtained by dividing
XTAL frequency was hard, as every value would have to be listed in
the enumeration. Since different base XTAL frequencies are supported,
this further complicated things, since not all of these divided
frequencies would be valid for any given XTAL frequency. Second,
having to deal with enumeration values often involved switch
statements to convert between enumeration and MHz values, handle
PLL/XTAL frequencies separately, etc.
This change introduces rtc_cpu_freq_config_t structure, which contains
CPU frequency (in MHz) and information on how this frequency has to
be generated: clock source (XTAL/PLL), source frequency, clock
divider value. More fields can be added to this structure in the
future. This structure simplifies many parts of the code, since both
frequency value and frequency generation settings can be accessed in
any place in code without the need for conversions.
Additionally, this change adds setting of REF_TICK dividers to support
frequencies lower then XTAL with DFS.
