Merge branch 'fix/spi_dma_config_in_iram' into 'master'
SPI: put dma config and slave functions into IRAM See merge request idf/esp-idf!3038
This commit is contained in:
Ivan Grokhotkov
commit
7abed5fc9e
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@ -6,8 +6,8 @@ config ADC_FORCE_XPD_FSM
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bool "Use the FSM to control ADC power"
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default n
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help
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ADC power can be controlled by the FSM instead of software. This allows the ADC to
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be shut off when it is not working leading to lower power consumption. However
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ADC power can be controlled by the FSM instead of software. This allows the ADC to
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be shut off when it is not working leading to lower power consumption. However
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using the FSM control ADC power will increase the noise of ADC.
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config ADC2_DISABLE_DAC
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@ -20,7 +20,7 @@ config ADC2_DISABLE_DAC
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endmenu # ADC Configuration
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menu "SPI master configuration"
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menu "SPI configuration"
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config SPI_MASTER_IN_IRAM
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bool "Place transmitting functions of SPI master into IRAM"
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@ -44,6 +44,26 @@ config SPI_MASTER_ISR_IN_IRAM
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Place the SPI master ISR in to IRAM to avoid possibly cache miss, or
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being disabled during flash writing access.
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endmenu # SPI Master Configuration
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config SPI_SLAVE_IN_IRAM
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bool "Place transmitting functions of SPI slave into IRAM"
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default n
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select SPI_SLAVE_ISR_IN_IRAM
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help
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Normally only the ISR of SPI slave is placed in the IRAM, so that it
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can work without the flash when interrupt is triggered.
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For other functions, there's some possibility that the flash cache
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miss when running inside and out of SPI functions, which may increase
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the interval of SPI transactions.
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Enable this to put ``queue_trans``, ``get_trans_result`` and
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``transmit`` functions into the IRAM to avoid possible cache miss.
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config SPI_SLAVE_ISR_IN_IRAM
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bool "Place SPI slave ISR function into IRAM"
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default y
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help
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Place the SPI slave ISR in to IRAM to avoid possibly cache miss, or
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being disabled during flash writing access.
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endmenu # SPI Configuration
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endmenu # Driver configurations
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@ -330,7 +330,7 @@ void spicommon_cs_free_io(int cs_gpio_num)
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}
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//Set up a list of dma descriptors. dmadesc is an array of descriptors. Data is the buffer to point to.
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void spicommon_setup_dma_desc_links(lldesc_t *dmadesc, int len, const uint8_t *data, bool isrx)
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void IRAM_ATTR spicommon_setup_dma_desc_links(lldesc_t *dmadesc, int len, const uint8_t *data, bool isrx)
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{
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int n = 0;
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while (len) {
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@ -47,6 +47,18 @@ static const char *SPI_TAG = "spi_slave";
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#define VALID_HOST(x) (x>SPI_HOST && x<=VSPI_HOST)
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#ifdef CONFIG_SPI_SLAVE_ISR_IN_IRAM
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#define SPI_SLAVE_ISR_ATTR IRAM_ATTR
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#else
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#define SPI_SLAVE_ISR_ATTR
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#endif
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#ifdef CONFIG_SPI_SLAVE_IN_IRAM
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#define SPI_SLAVE_ATTR IRAM_ATTR
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#else
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#define SPI_SLAVE_ATTR
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#endif
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typedef struct {
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spi_slave_interface_config_t cfg;
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intr_handle_t intr;
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@ -79,7 +91,7 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b
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spi_chan_claimed=spicommon_periph_claim(host);
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SPI_CHECK(spi_chan_claimed, "host already in use", ESP_ERR_INVALID_STATE);
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if ( dma_chan != 0 ) {
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dma_chan_claimed=spicommon_dma_chan_claim(dma_chan);
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if ( !dma_chan_claimed ) {
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@ -138,7 +150,11 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b
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goto cleanup;
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}
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err = esp_intr_alloc(spicommon_irqsource_for_host(host), ESP_INTR_FLAG_INTRDISABLED, spi_intr, (void *)spihost[host], &spihost[host]->intr);
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int flags = ESP_INTR_FLAG_INTRDISABLED;
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#ifdef CONFIG_SPI_SLAVE_ISR_IN_IRAM
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flags |= ESP_INTR_FLAG_IRAM;
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#endif
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err = esp_intr_alloc(spicommon_irqsource_for_host(host), flags, spi_intr, (void *)spihost[host], &spihost[host]->intr);
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if (err != ESP_OK) {
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ret = err;
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goto cleanup;
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@ -250,14 +266,14 @@ esp_err_t spi_slave_free(spi_host_device_t host)
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}
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esp_err_t spi_slave_queue_trans(spi_host_device_t host, const spi_slave_transaction_t *trans_desc, TickType_t ticks_to_wait)
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esp_err_t SPI_SLAVE_ATTR spi_slave_queue_trans(spi_host_device_t host, const spi_slave_transaction_t *trans_desc, TickType_t ticks_to_wait)
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{
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BaseType_t r;
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SPI_CHECK(VALID_HOST(host), "invalid host", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spihost[host], "host not slave", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spihost[host]->dma_chan == 0 || trans_desc->tx_buffer==NULL || esp_ptr_dma_capable(trans_desc->tx_buffer),
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SPI_CHECK(spihost[host]->dma_chan == 0 || trans_desc->tx_buffer==NULL || esp_ptr_dma_capable(trans_desc->tx_buffer),
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"txdata not in DMA-capable memory", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spihost[host]->dma_chan == 0 || trans_desc->rx_buffer==NULL || esp_ptr_dma_capable(trans_desc->rx_buffer),
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SPI_CHECK(spihost[host]->dma_chan == 0 || trans_desc->rx_buffer==NULL || esp_ptr_dma_capable(trans_desc->rx_buffer),
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"rxdata not in DMA-capable memory", ESP_ERR_INVALID_ARG);
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SPI_CHECK(trans_desc->length <= spihost[host]->max_transfer_sz * 8, "data transfer > host maximum", ESP_ERR_INVALID_ARG);
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@ -268,7 +284,7 @@ esp_err_t spi_slave_queue_trans(spi_host_device_t host, const spi_slave_transact
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}
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esp_err_t spi_slave_get_trans_result(spi_host_device_t host, spi_slave_transaction_t **trans_desc, TickType_t ticks_to_wait)
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esp_err_t SPI_SLAVE_ATTR spi_slave_get_trans_result(spi_host_device_t host, spi_slave_transaction_t **trans_desc, TickType_t ticks_to_wait)
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{
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BaseType_t r;
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SPI_CHECK(VALID_HOST(host), "invalid host", ESP_ERR_INVALID_ARG);
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@ -279,7 +295,7 @@ esp_err_t spi_slave_get_trans_result(spi_host_device_t host, spi_slave_transacti
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}
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esp_err_t spi_slave_transmit(spi_host_device_t host, spi_slave_transaction_t *trans_desc, TickType_t ticks_to_wait)
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esp_err_t SPI_SLAVE_ATTR spi_slave_transmit(spi_host_device_t host, spi_slave_transaction_t *trans_desc, TickType_t ticks_to_wait)
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{
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esp_err_t ret;
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spi_slave_transaction_t *ret_trans;
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@ -316,7 +332,7 @@ static void dumpll(lldesc_t *ll)
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}
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#endif
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static void IRAM_ATTR spi_slave_restart_after_dmareset(void *arg)
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static void SPI_SLAVE_ISR_ATTR spi_slave_restart_after_dmareset(void *arg)
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{
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spi_slave_t *host = (spi_slave_t *)arg;
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esp_intr_enable(host->intr);
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@ -325,7 +341,7 @@ static void IRAM_ATTR spi_slave_restart_after_dmareset(void *arg)
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//This is run in interrupt context and apart from initialization and destruction, this is the only code
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//touching the host (=spihost[x]) variable. The rest of the data arrives in queues. That is why there are
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//no muxes in this code.
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static void IRAM_ATTR spi_intr(void *arg)
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static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg)
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{
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BaseType_t r;
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BaseType_t do_yield = pdFALSE;
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@ -342,7 +358,7 @@ static void IRAM_ATTR spi_intr(void *arg)
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if (host->cur_trans) {
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//when data of cur_trans->length are all sent, the slv_rdata_bit
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//will be the length sent-1 (i.e. cur_trans->length-1 ), otherwise
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//will be the length sent-1 (i.e. cur_trans->length-1 ), otherwise
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//the length sent.
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host->cur_trans->trans_len = host->hw->slv_rd_bit.slv_rdata_bit;
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if ( host->cur_trans->trans_len == host->cur_trans->length - 1 ) {
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