Crash_Override/OVMS3-idf
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31 commits

Author SHA1 Message Date
Konstantin Kondrashov
399d2d2605 all: Using xxx_periph.h 
Using xxx_periph.h in whole IDF instead of xxx_reg.h, xxx_struct.h, xxx_channel.h ... .

Cleaned up header files from unnecessary headers (releated to soc/... headers).
 2019-06-03 14:15:08 +08:00
Angus Gratton
f871cc5ffa Merge branch 'feat/spi_hal_support' into 'master' 
spi_master: refactor and add HAL support

See merge request idf/esp-idf!4159
 2019-04-15 07:57:11 +08:00
morris
f5b03c9ea3 misc adjustment of esp32 component 2019-04-03 19:57:46 +08:00
Michael (XIAO Xufeng)
af2fc96ee1 spi_master: refactor and add HAL support 2019-03-28 17:14:50 +08:00
morris
c159984264 separate rom from esp32 component to esp_rom 
1. separate rom include files and linkscript to esp_rom
2. modefiy "include rom/xxx.h" to "include esp32/rom/xxx.h"
3. Forward compatible
4. update mqtt
 2019-03-21 18:51:45 +08:00
Michael (XIAO Xufeng)
86bcd56109 spi: fix the bug of connecting SPI peripheral to read-only pins 
The requirements of pin capabilites is different for spi master and
slave.  The master needs CS, SCLK, MOSI to be output-able, while slave
needs MISO to be output-able.

Previous code is for master only.

This commit allows to place other 3 pins than MISO on input-only pins
for slaves. Refactoring for spi_common is also included.

Resolves https://github.com/espressif/esp-idf/issues/2455
 2019-02-16 20:03:14 +08:00
Michael (XIAO Xufeng)
9b5d0f3322 spi: shown owner of spi host explicitly 2018-10-29 20:22:44 +08:00
michael
e5ed450d95 spi: move gpio direction config to common func for coinsistence 
(MINOR CHANGE)
 2018-10-04 14:57:31 +08:00
Michael (Xiao Xufeng)
4af51833f3 spi_master: add new polling mode to decrease time cost each transaction 2018-09-20 19:46:46 +08:00
Michael (XIAO Xufeng)
e3557b57be spi: fix the issue that spi cannot be used when flash is disabled 
The dma configuration function called in the ISR should be put into the IRAM.

Fixes https://github.com/espressif/esp-idf/issues/2307.
 2018-08-23 05:21:49 +00:00
michael
45d1c9207c bugfix(spi): resolve the glitch that happens during initialization 2018-06-14 11:29:16 +08:00
Michael (XIAO Xufeng)
77077196fd fix(spi): reset gpios that used by spi when deinited 2018-06-14 11:29:15 +08:00
Michael (XIAO Xufeng)
ebfda40b7c refactor(spi): move pin information into soc folder 2018-06-14 11:29:15 +08:00
Michael (XIAO Xufeng)
939e5693a5 chore(spi): fix the terms of native to iomux 2018-06-06 06:08:39 +00:00
michael
197f594b06 fix(spi): fix the issue when bus flag not set, dual mode cannot be used. 2018-05-08 15:47:26 +08:00
michael
28beafc624 fix(spi): fix the issue that native pins don't work after SPI initialized before 2018-05-08 15:47:25 +08:00
Mahavir Jain
43a12894ea driver/spi: add _ISR counterparts if invoked from interrupt for critical section 
Signed-off-by: Mahavir Jain <mahavir@espressif.com>
 2018-04-19 18:28:55 +05:30
Michael (Xiao Xufeng)
45f8bcf3f8 fix(spi): allow using MISO on GPIO34-39 
Breaking Changes: arguments of ``spicommon_bus_initialize_io`` are changed.

Closes https://github.com/espressif/esp-idf/issues/1736.
 2018-04-12 17:01:38 +08:00
michael
60469c500a fix(spi): fix pin issue with GPIO0 (other pins than CS). 2018-01-29 17:44:36 +08:00
michael
2552fdccd1 chore(spi): add log to show native pins or not when configure pins. 2017-12-28 12:03:29 +08:00
Angus Gratton
0dd9b899b7 periph_ctrl: Refactor to add periph_module_reset(), avoid potential race in SPI DMA workaround 
Also refactor use of direct clock access in unit test ref_clock (probably not a real issue)
 2017-10-02 17:48:16 +11:00
michael
b834fcf78a fix(spi_master): this fix the SPI MOSI output missing bug. 2017-09-04 22:43:51 +08:00
Angus Gratton
71c70cb15c heap: Refactor heap regions/capabilities out of FreeRTOS 
Remove tagged heap API, rename caps_xxx to heap_caps_xxx

Also includes additional heap_caps_xxx inspection functions.
 2017-07-10 17:46:03 +08:00
Jiang Jiang Jian
c518325385 Merge branch 'bugfix/dualcore_dport' into 'master' 
component/esp32 : fix dualcore bug

1. When dual core cpu run access DPORT register, must do protection.
2. If access DPORT register, must use DPORT_REG_READ/DPORT_REG_WRITE and DPORT_XXX register operation macro.

See merge request !742
 2017-05-10 11:27:01 +08:00
Tian Hao
26a3cb93c7 component/soc : move dport access header files to soc 
1. move dport access header files to soc
2. reduce dport register write protection. Only protect read operation
 2017-05-09 18:06:00 +08:00
Tian Hao
f7e8856520 component/esp32 : fix dualcore bug 
1. When dual core cpu run access DPORT register, must do protection.
2. If access DPORT register, must use DPORT_REG_READ/DPORT_REG_WRITE and DPORT_XXX register operation macro.
 2017-05-08 21:53:43 +08:00
Jeroen Domburg
9962cc9c9f Fix out-of-bounds on dmaworkaround_channels_busy 2017-05-08 16:11:46 +08:00
Jeroen Domburg
04b901e629 SPI: More MR issues fixed, style fixup 2017-04-27 11:49:04 +08:00
Jeroen Domburg
cecb846450 SPI: Fix comment for 3wire, make GPIO pins GPIO_MODE_INPUT_OUTOUT. Fixes https://github.com/espressif/esp-idf/issues/533 2017-04-27 11:49:04 +08:00
Jeroen Domburg
4c06dca15c SPI: Small fixes according to MR comments 2017-04-27 11:49:04 +08:00
Jeroen Domburg
e9c372bc2d SPI: Split common SPI stuff out of master driver; add slave driver; add workaround for DMA issue. 2017-04-27 11:49:04 +08:00