esp32s2beta: convert some todos to warnings
This commit is contained in:
Ivan Grokhotkov
parent
4a79d750a5
commit
dcaae4a5fc
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@ -1,16 +1,11 @@
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set(COMPONENT_SRCS "can.c"
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"gpio.c"
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"i2c.c"
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"i2s.c"
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"ledc.c"
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"mcpwm.c"
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"pcnt.c"
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"periph_ctrl.c"
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"rmt.c"
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"rtc_module.c"
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"sdio_slave.c"
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"sdmmc_host.c"
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"sdmmc_transaction.c"
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"sdspi_crc.c"
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"sdspi_host.c"
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"sdspi_transaction.c"
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@ -20,6 +15,16 @@ set(COMPONENT_SRCS "can.c"
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"spi_slave.c"
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"timer.c"
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"uart.c")
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if(CONFIG_IDF_TARGET_ESP32)
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# SDMMC and MCPWM are in ESP32 only, I2S not ported yet.
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list(APPEND COMPONENT_SRCS "i2s.c"
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"mcpwm.c"
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"sdio_slave.c"
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"sdmmc_host.c"
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"sdmmc_transaction.c")
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endif()
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set(COMPONENT_ADD_INCLUDEDIRS "include")
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set(COMPONENT_PRIV_INCLUDEDIRS "include/driver")
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set(COMPONENT_REQUIRES esp_ringbuf soc) #cannot totally hide soc headers, since there are a lot arguments in the driver are chip-dependent
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@ -36,7 +36,6 @@
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#include "esp_pm.h"
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#include "sdkconfig.h"
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#if CONFIG_IDF_TARGET_ESP32
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static const char* I2S_TAG = "I2S";
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@ -1389,4 +1388,3 @@ int i2s_pop_sample(i2s_port_t i2s_num, void *sample, TickType_t ticks_to_wait)
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return bytes_pop;
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}
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}
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#endif
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@ -25,7 +25,6 @@
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#include "driver/periph_ctrl.h"
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#include "sdkconfig.h"
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#if CONFIG_IDF_TARGET_ESP32
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static mcpwm_dev_t *MCPWM[2] = {&MCPWM0, &MCPWM1};
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static const char *MCPWM_TAG = "MCPWM";
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@ -730,4 +729,3 @@ esp_err_t mcpwm_isr_register(mcpwm_unit_t mcpwm_num, void (*fn)(void *), void *a
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ret = esp_intr_alloc((ETS_PWM0_INTR_SOURCE + mcpwm_num), intr_alloc_flags, fn, arg, handle);
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return ret;
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}
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#endif
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@ -25,7 +25,7 @@
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#include "sdmmc_private.h"
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#include "freertos/semphr.h"
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#include "soc/sdmmc_periph.h"
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#if CONFIG_IDF_TARGET_ESP32
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#define SDMMC_EVENT_QUEUE_LENGTH 32
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@ -635,4 +635,4 @@ esp_err_t sdmmc_host_pullup_en(int slot, int width)
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}
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return ESP_OK;
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}
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#endif
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@ -1,44 +1 @@
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ifdef CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION
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PHY_INIT_DATA_OBJ = $(BUILD_DIR_BASE)/phy_init_data.o
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PHY_INIT_DATA_BIN = $(BUILD_DIR_BASE)/phy_init_data.bin
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# Command to flash PHY init data partition
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PHY_INIT_DATA_FLASH_CMD = $(ESPTOOLPY_SERIAL) write_flash $(PHY_DATA_OFFSET) $(PHY_INIT_DATA_BIN)
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ESPTOOL_ALL_FLASH_ARGS += $(PHY_DATA_OFFSET) $(PHY_INIT_DATA_BIN)
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ESP32_COMPONENT_PATH := $(COMPONENT_PATH)
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$(PHY_INIT_DATA_OBJ): $(ESP32_COMPONENT_PATH)/phy_init_data.h $(BUILD_DIR_BASE)/include/sdkconfig.h
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$(summary) CC $(notdir $@)
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printf "#include \"phy_init_data.h\"\n" | $(CC) -I $(BUILD_DIR_BASE)/include -I $(ESP32_COMPONENT_PATH) -I $(ESP32_COMPONENT_PATH)/include -c -o $@ -xc -
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$(PHY_INIT_DATA_BIN): $(PHY_INIT_DATA_OBJ)
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$(summary) BIN $(notdir $@)
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$(OBJCOPY) -O binary $< $@
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phy_init_data: $(PHY_INIT_DATA_BIN)
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phy_init_data-flash: $(BUILD_DIR_BASE)/phy_init_data.bin
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@echo "Flashing PHY init data..."
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$(PHY_INIT_DATA_FLASH_CMD)
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phy_init_data-clean:
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rm -f $(PHY_INIT_DATA_BIN) $(PHY_INIT_DATA_OBJ)
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all: phy_init_data
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flash: phy_init_data
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endif # CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION
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# Enable psram cache bug workaround in compiler if selected
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ifdef CONFIG_SPIRAM_CACHE_WORKAROUND
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CFLAGS+=-mfix-esp32-psram-cache-issue
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CXXFLAGS+=-mfix-esp32-psram-cache-issue
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endif
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# Enable dynamic esp_timer overflow value if building unit tests
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ifneq ("$(TEST_COMPONENTS_LIST)","")
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CPPFLAGS += -DESP_TIMER_DYNAMIC_OVERFLOW_VAL
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endif
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# nothing here, esp32s2beta is not suppoted in Make build system
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@ -48,7 +48,7 @@ static void rtc_brownout_isr_handler()
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void esp_brownout_init()
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{
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//TODO, chip7.2.2 will use i2c inteface to configure brown out threshold
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#warning "TODO: implement brownout threshold configuration for esp32s2beta"
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ESP_ERROR_CHECK( rtc_isr_register(rtc_brownout_isr_handler, NULL, RTC_CNTL_BROWN_OUT_INT_ENA_M) );
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@ -51,6 +51,8 @@ void esp_cache_err_int_init()
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// For this reason, panic handler backtrace will not be correct if the
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// interrupt is connected to PRO CPU and invalid access happens on the APP
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// CPU.
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#warning "TODO: implement cache error access interrupt for esp32s2beta"
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#if 0
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DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_IA_INT_EN_REG,
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DPORT_CACHE_IA_INT_PRO_DRAM1 |
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@ -499,7 +499,8 @@ static void main_task(void* args)
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#endif
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//Add IDLE 0 to task wdt
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#if 0 // TODO: re-enable task WDT
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#warning "cpu_start.c: TODO: re-enable task WDT"
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#if 0
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#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
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TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU(0);
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if(idle_0 != NULL){
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@ -40,6 +40,8 @@
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static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
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static volatile uint32_t reason[ portNUM_PROCESSORS ];
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#warning "crosscore_int: TODO: simplify for esp32s2beta"
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/*
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ToDo: There is a small chance the CPU already has yielded when this ISR is serviced. In that case, it's running the intended task but
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the ISR will cause it to switch _away_ from it. portYIELD_FROM_ISR will probably just schedule the task again, but have to check that.
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@ -41,6 +41,8 @@
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#include "xtensa/core-macros.h"
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#warning "dport_access: TODO: simplify for esp32s2beta"
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#ifndef CONFIG_FREERTOS_UNICORE
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static portMUX_TYPE g_dport_mux = portMUX_INITIALIZER_UNLOCKED;
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@ -37,7 +37,8 @@ we add more types of external RAM memory, this can be made into a more intellige
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#if CONFIG_FREERTOS_UNICORE
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#define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
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#else
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#if 0 /* TODO: no even/odd mode for ESP32S2 PSRAM? */
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#warning "spiram.c: TODO: no even/odd mode for ESP32S2 PSRAM?"
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#if 0
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#define PSRAM_MODE PSRAM_VADDR_MODE_EVENODD
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#else
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#define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH
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@ -570,6 +570,7 @@ void IRAM_ATTR psram_spi_init(psram_spi_num_t spi_num, psram_cache_mode_t mode)
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{
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uint8_t k;
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SET_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_CS_SETUP);
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#warning "psram_spi_init: part of configuration missing for esp32s2beta"
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#if 0
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// SPI_CPOL & SPI_CPHA
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CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(spi_num), SPI_MEM_CK_IDLE_EDGE);
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@ -627,6 +628,9 @@ static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode)
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gpio_matrix_in(PSRAM_SPIWP_IO, SPIWP_IN_IDX, 0);
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gpio_matrix_out(PSRAM_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
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gpio_matrix_in(PSRAM_SPIHD_IO, SPIHD_IN_IDX, 0);
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#warning "psram_gpio_config: parts not implemented for esp32s2beta"
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switch (mode) {
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case PSRAM_CACHE_F80M_S40M:
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extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M;
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@ -713,6 +717,8 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
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s_psram_mode = mode;
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periph_module_enable(PERIPH_SPI_MODULE);
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#warning "psram_enable: some code disabled for esp32s2beta"
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#if 0
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WRITE_PERI_REG(SPI_MEM_EXT3_REG(0), 0x1);
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CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(PSRAM_SPI_1), SPI_MEM_USR_PREP_HOLD_M);
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@ -81,6 +81,7 @@ esp_err_t esp_efuse_mac_get_custom(uint8_t *mac)
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esp_err_t esp_efuse_mac_get_default(uint8_t* mac)
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{
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#warning "esp_efuse_mac_get_default: not implemented for esp32s2beta"
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uint32_t mac_low;
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uint32_t mac_high;
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// uint8_t efuse_crc;
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@ -289,6 +289,9 @@ static void test_handler_post_from_isr(void* event_handler_arg, esp_event_base_t
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}
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#endif
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#if CONFIG_IDF_TARGET_ESP32S2BETA
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#warning "test_event_on_timer_alarm not ported to esp32s2beta"
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#else
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#if CONFIG_ESP_EVENT_POST_FROM_ISR
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void IRAM_ATTR test_event_on_timer_alarm(void* para)
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{
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@ -316,6 +319,7 @@ void IRAM_ATTR test_event_on_timer_alarm(void* para)
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}
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}
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#endif //CONFIG_ESP_EVENT_POST_FROM_ISR
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#endif //CONFIG_IDF_TARGET_ESP32S2BETA
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TEST_CASE("can create and delete event loops", "[event]")
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{
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@ -1188,6 +1192,9 @@ TEST_CASE("can properly prepare event data posted to loop", "[event]")
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TEST_TEARDOWN();
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}
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#if CONFIG_IDF_TARGET_ESP32S2BETA
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#warning "can post events from interrupt handler not ported to esp32s2beta"
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#else
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TEST_CASE("can post events from interrupt handler", "[event]")
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{
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SemaphoreHandle_t sem = xSemaphoreCreateBinary();
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@ -1223,7 +1230,8 @@ TEST_CASE("can post events from interrupt handler", "[event]")
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TEST_TEARDOWN();
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}
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#endif
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#endif // CONFIG_IDF_TARGET_ESP32S2BETA
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#endif // CONFIG_ESP_EVENT_POST_FROM_ISR
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#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
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TEST_CASE("can dump event loop profile", "[event]")
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@ -1277,4 +1285,4 @@ TEST_CASE("can dump event loop profile", "[event]")
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TEST_TEARDOWN();
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}
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#endif
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#endif // CONFIG_ESP_EVENT_LOOP_PROFILING
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@ -195,6 +195,7 @@ rtc_vddsdio_config_t rtc_vddsdio_get_config()
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result.tieh = (sdio_conf_reg & RTC_CNTL_SDIO_TIEH_M) >> RTC_CNTL_SDIO_TIEH_S;
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return result;
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}
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#warning "rtc_vddsdio_get_config: efuse part not implemented for esp32s2beta"
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#if 0
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uint32_t efuse_reg = REG_READ(EFUSE_BLK0_RDATA4_REG);
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if (efuse_reg & EFUSE_RD_SDIO_FORCE) {
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