diff --git a/components/driver/CMakeLists.txt b/components/driver/CMakeLists.txt
index 9b36ca854..8e2ab494b 100644
--- a/components/driver/CMakeLists.txt
+++ b/components/driver/CMakeLists.txt
@@ -1,16 +1,11 @@
 set(COMPONENT_SRCS "can.c"
                    "gpio.c"
                    "i2c.c"
-                   "i2s.c"
                    "ledc.c"
-                   "mcpwm.c"
                    "pcnt.c"
                    "periph_ctrl.c"
                    "rmt.c"
                    "rtc_module.c"
-                   "sdio_slave.c"
-                   "sdmmc_host.c"
-                   "sdmmc_transaction.c"
                    "sdspi_crc.c"
                    "sdspi_host.c"
                    "sdspi_transaction.c"
@@ -20,6 +15,16 @@ set(COMPONENT_SRCS "can.c"
                    "spi_slave.c"
                    "timer.c"
                    "uart.c")
+
+if(CONFIG_IDF_TARGET_ESP32)
+    # SDMMC and MCPWM are in ESP32 only, I2S not ported yet.
+    list(APPEND COMPONENT_SRCS "i2s.c"
+                               "mcpwm.c"
+                               "sdio_slave.c"
+                               "sdmmc_host.c"
+                               "sdmmc_transaction.c")
+endif()
+
 set(COMPONENT_ADD_INCLUDEDIRS "include")
 set(COMPONENT_PRIV_INCLUDEDIRS "include/driver")
 set(COMPONENT_REQUIRES esp_ringbuf soc) #cannot totally hide soc headers, since there are a lot arguments in the driver are chip-dependent
diff --git a/components/driver/i2s.c b/components/driver/i2s.c
index 5381cf67c..6b80c4d1e 100644
--- a/components/driver/i2s.c
+++ b/components/driver/i2s.c
@@ -36,7 +36,6 @@
 #include "esp_pm.h"
 #include "sdkconfig.h"
 
-#if CONFIG_IDF_TARGET_ESP32
 
 static const char* I2S_TAG = "I2S";
 
@@ -1389,4 +1388,3 @@ int i2s_pop_sample(i2s_port_t i2s_num, void *sample, TickType_t ticks_to_wait)
         return bytes_pop;
     }
 }
-#endif
diff --git a/components/driver/mcpwm.c b/components/driver/mcpwm.c
index d3010ce89..bbb837045 100644
--- a/components/driver/mcpwm.c
+++ b/components/driver/mcpwm.c
@@ -25,7 +25,6 @@
 #include "driver/periph_ctrl.h"
 #include "sdkconfig.h"
 
-#if CONFIG_IDF_TARGET_ESP32
 
 static mcpwm_dev_t *MCPWM[2] = {&MCPWM0, &MCPWM1};
 static const char *MCPWM_TAG = "MCPWM";
@@ -730,4 +729,3 @@ esp_err_t mcpwm_isr_register(mcpwm_unit_t mcpwm_num, void (*fn)(void *), void *a
     ret = esp_intr_alloc((ETS_PWM0_INTR_SOURCE + mcpwm_num), intr_alloc_flags, fn, arg, handle);
     return ret;
 }
-#endif
diff --git a/components/driver/sdmmc_host.c b/components/driver/sdmmc_host.c
index b72fb5b0e..920c7353d 100644
--- a/components/driver/sdmmc_host.c
+++ b/components/driver/sdmmc_host.c
@@ -25,7 +25,7 @@
 #include "sdmmc_private.h"
 #include "freertos/semphr.h"
 #include "soc/sdmmc_periph.h"
-#if CONFIG_IDF_TARGET_ESP32
+
 #define SDMMC_EVENT_QUEUE_LENGTH 32
 
 
@@ -635,4 +635,4 @@ esp_err_t sdmmc_host_pullup_en(int slot, int width)
     }
     return ESP_OK;
 }
-#endif
+
diff --git a/components/esp32s2beta/Makefile.projbuild b/components/esp32s2beta/Makefile.projbuild
index 9f92c377d..2e7a94664 100644
--- a/components/esp32s2beta/Makefile.projbuild
+++ b/components/esp32s2beta/Makefile.projbuild
@@ -1,44 +1 @@
-ifdef CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION
-
-PHY_INIT_DATA_OBJ = $(BUILD_DIR_BASE)/phy_init_data.o
-PHY_INIT_DATA_BIN = $(BUILD_DIR_BASE)/phy_init_data.bin
-
-# Command to flash PHY init data partition
-PHY_INIT_DATA_FLASH_CMD = $(ESPTOOLPY_SERIAL) write_flash $(PHY_DATA_OFFSET) $(PHY_INIT_DATA_BIN)
-ESPTOOL_ALL_FLASH_ARGS += $(PHY_DATA_OFFSET) $(PHY_INIT_DATA_BIN)
-
-ESP32_COMPONENT_PATH := $(COMPONENT_PATH)
-
-$(PHY_INIT_DATA_OBJ): $(ESP32_COMPONENT_PATH)/phy_init_data.h $(BUILD_DIR_BASE)/include/sdkconfig.h
-	$(summary) CC $(notdir $@)
-	printf "#include \"phy_init_data.h\"\n" | $(CC) -I $(BUILD_DIR_BASE)/include -I $(ESP32_COMPONENT_PATH) -I $(ESP32_COMPONENT_PATH)/include -c -o $@ -xc -
-
-$(PHY_INIT_DATA_BIN): $(PHY_INIT_DATA_OBJ)
-	$(summary) BIN $(notdir $@)
-	$(OBJCOPY) -O binary $< $@
-
-phy_init_data: $(PHY_INIT_DATA_BIN)
-
-phy_init_data-flash: $(BUILD_DIR_BASE)/phy_init_data.bin
-	@echo "Flashing PHY init data..."
-	$(PHY_INIT_DATA_FLASH_CMD)
-
-phy_init_data-clean:
-	rm -f $(PHY_INIT_DATA_BIN) $(PHY_INIT_DATA_OBJ)
-
-all: phy_init_data
-flash: phy_init_data
-
-endif # CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION
-
-
-# Enable psram cache bug workaround in compiler if selected
-ifdef CONFIG_SPIRAM_CACHE_WORKAROUND
-CFLAGS+=-mfix-esp32-psram-cache-issue
-CXXFLAGS+=-mfix-esp32-psram-cache-issue
-endif
-
-# Enable dynamic esp_timer overflow value if building unit tests
-ifneq ("$(TEST_COMPONENTS_LIST)","")
-CPPFLAGS += -DESP_TIMER_DYNAMIC_OVERFLOW_VAL
-endif
+# nothing here, esp32s2beta is not suppoted in Make build system
\ No newline at end of file
diff --git a/components/esp32s2beta/brownout.c b/components/esp32s2beta/brownout.c
index 9d46e177e..2a5c662e6 100644
--- a/components/esp32s2beta/brownout.c
+++ b/components/esp32s2beta/brownout.c
@@ -48,7 +48,7 @@ static void rtc_brownout_isr_handler()
 
 void esp_brownout_init()
 {
-    //TODO, chip7.2.2 will use i2c inteface to configure brown out threshold
+#warning "TODO: implement brownout threshold configuration for esp32s2beta"
 
     ESP_ERROR_CHECK( rtc_isr_register(rtc_brownout_isr_handler, NULL, RTC_CNTL_BROWN_OUT_INT_ENA_M) );
 
diff --git a/components/esp32s2beta/cache_err_int.c b/components/esp32s2beta/cache_err_int.c
index b57eb157b..015070eb2 100644
--- a/components/esp32s2beta/cache_err_int.c
+++ b/components/esp32s2beta/cache_err_int.c
@@ -51,6 +51,8 @@ void esp_cache_err_int_init()
     // For this reason, panic handler backtrace will not be correct if the
     // interrupt is connected to PRO CPU and invalid access happens on the APP
     // CPU.
+
+#warning "TODO: implement cache error access interrupt for esp32s2beta"
 #if 0
     DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_IA_INT_EN_REG,
         DPORT_CACHE_IA_INT_PRO_DRAM1 |
diff --git a/components/esp32s2beta/cpu_start.c b/components/esp32s2beta/cpu_start.c
index 2ba134726..ea8a70915 100644
--- a/components/esp32s2beta/cpu_start.c
+++ b/components/esp32s2beta/cpu_start.c
@@ -499,7 +499,8 @@ static void main_task(void* args)
 #endif
 
     //Add IDLE 0 to task wdt
-#if 0 // TODO: re-enable task WDT
+#warning "cpu_start.c: TODO: re-enable task WDT"
+#if 0
 #ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
     TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU(0);
     if(idle_0 != NULL){
diff --git a/components/esp32s2beta/crosscore_int.c b/components/esp32s2beta/crosscore_int.c
index 3bfcc60bf..1aa25f6b5 100644
--- a/components/esp32s2beta/crosscore_int.c
+++ b/components/esp32s2beta/crosscore_int.c
@@ -40,6 +40,8 @@
 static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
 static volatile uint32_t reason[ portNUM_PROCESSORS ];
 
+#warning "crosscore_int: TODO: simplify for esp32s2beta"
+
 /*
 ToDo: There is a small chance the CPU already has yielded when this ISR is serviced. In that case, it's running the intended task but
 the ISR will cause it to switch _away_ from it. portYIELD_FROM_ISR will probably just schedule the task again, but have to check that.
diff --git a/components/esp32s2beta/dport_access.c b/components/esp32s2beta/dport_access.c
index 7ec8dc8a2..82282e0f7 100644
--- a/components/esp32s2beta/dport_access.c
+++ b/components/esp32s2beta/dport_access.c
@@ -41,6 +41,8 @@
 
 #include "xtensa/core-macros.h"
 
+#warning "dport_access: TODO: simplify for esp32s2beta"
+
 #ifndef CONFIG_FREERTOS_UNICORE
 static portMUX_TYPE g_dport_mux = portMUX_INITIALIZER_UNLOCKED;
 
diff --git a/components/esp32s2beta/spiram.c b/components/esp32s2beta/spiram.c
index 338691977..9cd3c6ba4 100644
--- a/components/esp32s2beta/spiram.c
+++ b/components/esp32s2beta/spiram.c
@@ -37,7 +37,8 @@ we add more types of external RAM memory, this can be made into a more intellige
 #if CONFIG_FREERTOS_UNICORE
 #define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
 #else
-#if 0 /* TODO: no even/odd mode for ESP32S2 PSRAM? */
+#warning "spiram.c: TODO: no even/odd mode for ESP32S2 PSRAM?"
+#if 0
 #define PSRAM_MODE PSRAM_VADDR_MODE_EVENODD
 #else
 #define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH
diff --git a/components/esp32s2beta/spiram_psram.c b/components/esp32s2beta/spiram_psram.c
index b6b3f3b47..01168cc6a 100644
--- a/components/esp32s2beta/spiram_psram.c
+++ b/components/esp32s2beta/spiram_psram.c
@@ -570,6 +570,7 @@ void IRAM_ATTR psram_spi_init(psram_spi_num_t spi_num, psram_cache_mode_t mode)
 {
     uint8_t k;
     SET_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_CS_SETUP);
+#warning "psram_spi_init: part of configuration missing for esp32s2beta"
 #if 0
     // SPI_CPOL & SPI_CPHA
     CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(spi_num), SPI_MEM_CK_IDLE_EDGE);
@@ -627,6 +628,9 @@ static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode)
     gpio_matrix_in(PSRAM_SPIWP_IO, SPIWP_IN_IDX, 0);
     gpio_matrix_out(PSRAM_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
     gpio_matrix_in(PSRAM_SPIHD_IO, SPIHD_IN_IDX, 0);
+
+#warning "psram_gpio_config: parts not implemented for esp32s2beta"
+
     switch (mode) {
         case PSRAM_CACHE_F80M_S40M:
             extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M;
@@ -713,6 +717,8 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
     s_psram_mode = mode;
 
     periph_module_enable(PERIPH_SPI_MODULE);
+
+#warning "psram_enable: some code disabled for esp32s2beta"
 #if 0
     WRITE_PERI_REG(SPI_MEM_EXT3_REG(0), 0x1);
     CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(PSRAM_SPI_1), SPI_MEM_USR_PREP_HOLD_M);
diff --git a/components/esp32s2beta/system_api.c b/components/esp32s2beta/system_api.c
index f169a6843..85a063d9b 100644
--- a/components/esp32s2beta/system_api.c
+++ b/components/esp32s2beta/system_api.c
@@ -81,6 +81,7 @@ esp_err_t esp_efuse_mac_get_custom(uint8_t *mac)
 
 esp_err_t esp_efuse_mac_get_default(uint8_t* mac)
 {
+#warning "esp_efuse_mac_get_default: not implemented for esp32s2beta"
     uint32_t mac_low;
     uint32_t mac_high;
     // uint8_t efuse_crc;
diff --git a/components/esp_event/test/test_event.c b/components/esp_event/test/test_event.c
index d058f0b80..f30eda216 100644
--- a/components/esp_event/test/test_event.c
+++ b/components/esp_event/test/test_event.c
@@ -289,6 +289,9 @@ static void test_handler_post_from_isr(void* event_handler_arg, esp_event_base_t
 }
 #endif
 
+#if CONFIG_IDF_TARGET_ESP32S2BETA
+#warning "test_event_on_timer_alarm not ported to esp32s2beta"
+#else
 #if CONFIG_ESP_EVENT_POST_FROM_ISR
 void IRAM_ATTR test_event_on_timer_alarm(void* para)
 {
@@ -316,6 +319,7 @@ void IRAM_ATTR test_event_on_timer_alarm(void* para)
     }
 }
 #endif //CONFIG_ESP_EVENT_POST_FROM_ISR
+#endif //CONFIG_IDF_TARGET_ESP32S2BETA
 
 TEST_CASE("can create and delete event loops", "[event]")
 {
@@ -1188,6 +1192,9 @@ TEST_CASE("can properly prepare event data posted to loop", "[event]")
     TEST_TEARDOWN();
 }
 
+#if CONFIG_IDF_TARGET_ESP32S2BETA
+#warning "can post events from interrupt handler not ported to esp32s2beta"
+#else
 TEST_CASE("can post events from interrupt handler", "[event]")
 {
     SemaphoreHandle_t sem = xSemaphoreCreateBinary();
@@ -1223,7 +1230,8 @@ TEST_CASE("can post events from interrupt handler", "[event]")
 
     TEST_TEARDOWN();
 }
-#endif
+#endif // CONFIG_IDF_TARGET_ESP32S2BETA
+#endif // CONFIG_ESP_EVENT_POST_FROM_ISR
 
 #ifdef CONFIG_ESP_EVENT_LOOP_PROFILING
 TEST_CASE("can dump event loop profile", "[event]")
@@ -1277,4 +1285,4 @@ TEST_CASE("can dump event loop profile", "[event]")
 
     TEST_TEARDOWN();
 }
-#endif
+#endif // CONFIG_ESP_EVENT_LOOP_PROFILING
diff --git a/components/soc/esp32s2beta/rtc_init.c b/components/soc/esp32s2beta/rtc_init.c
index c4ce147a4..b241edca6 100644
--- a/components/soc/esp32s2beta/rtc_init.c
+++ b/components/soc/esp32s2beta/rtc_init.c
@@ -195,6 +195,7 @@ rtc_vddsdio_config_t rtc_vddsdio_get_config()
         result.tieh = (sdio_conf_reg & RTC_CNTL_SDIO_TIEH_M) >> RTC_CNTL_SDIO_TIEH_S;
         return result;
     }
+#warning "rtc_vddsdio_get_config: efuse part not implemented for esp32s2beta"
 #if 0
     uint32_t efuse_reg = REG_READ(EFUSE_BLK0_RDATA4_REG);
     if (efuse_reg & EFUSE_RD_SDIO_FORCE) {