Crash_Override/OVMS3-idf
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clean up build warnings

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This commit is contained in:
suda-morris 2019-06-10 15:07:12 +08:00
parent a37ad24137
commit 4a79d750a5
24 changed files with 93 additions and 123 deletions
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2
components/bootloader_support/src/bootloader_clock.c
View file

@ -44,7 +44,7 @@ void bootloader_clock_configure()
#endif
rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
#ifdef CONFIG_IDF_TARGET_ESP32
#if CONFIG_IDF_TARGET_ESP32
clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ;
clk_cfg.cpu_freq_mhz = cpu_freq_mhz;
#elif CONFIG_IDF_TARGET_ESP32S2BETA

18
components/bootloader_support/src/bootloader_init.c
View file

@ -83,7 +83,6 @@ static const char *TAG = "boot";
static esp_err_t bootloader_main();
static void print_flash_info(const esp_image_header_t *pfhdr);
static void update_flash_config(const esp_image_header_t *pfhdr);
static void vddsdio_configure();
static void flash_gpio_configure(const esp_image_header_t *pfhdr);
static void uart_console_configure(void);
static void wdt_reset_check(void);
@ -97,10 +96,10 @@ esp_err_t bootloader_init()
/* Sanity check that static RAM is after the stack */
#ifndef NDEBUG
{
int *sp = get_sp();
assert(&_bss_start <= &_bss_end);
assert(&_data_start <= &_data_end);
#if CONFIG_IDF_TARGET_ESP32
int *sp = get_sp();
assert(sp < &_bss_start);
assert(sp < &_data_start);
#endif
@ -359,21 +358,6 @@ static void print_flash_info(const esp_image_header_t *phdr)
#endif
}
static void vddsdio_configure()
{
#if CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V
rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
if (cfg.enable == 1 && cfg.tieh == RTC_VDDSDIO_TIEH_1_8V) { // VDDSDIO regulator is enabled @ 1.8V
cfg.drefh = 3;
cfg.drefm = 3;
cfg.drefl = 3;
cfg.force = 1;
rtc_vddsdio_set_config(cfg);
ets_delay_us(10); // wait for regulator to become stable
}
#endif // CONFIG_BOOTLOADER_VDDSDIO_BOOST
}
#if CONFIG_IDF_TARGET_ESP32
#define FLASH_CLK_IO 6
#define FLASH_CS_IO 11

2
components/bootloader_support/src/bootloader_random.c
View file

@ -34,7 +34,9 @@ void bootloader_fill_random(void *buffer, size_t length)
{
uint8_t *buffer_bytes = (uint8_t *)buffer;
uint32_t random;
#if CONFIG_IDF_TARGET_ESP32
uint32_t start, now;
#endif
assert(buffer != NULL);

4
components/bootloader_support/src/esp32s2beta/bootloader_clock_esp32s2beta.c
View file

@ -3,9 +3,7 @@
int bootloader_clock_get_rated_freq_mhz()
{
#ifndef CONFIG_HARDWARE_IS_FPGA
#warning "FIXME this needs to be filled in for real hardware"
#endif
#warning "TODO: bootloader_clock_get_rated_freq_mhz implementation in esp32s2"
return 999;
}

4
components/bootloader_support/src/esp32s2beta/flash_encrypt.c
View file

@ -217,7 +217,7 @@ static esp_err_t encrypt_and_load_partition_table(esp_partition_info_t *partitio
ESP_LOGE(TAG, "Failed to read partition table data");
return err;
}
if (esp_partition_table_basic_verify(partition_table, false, num_partitions) == ESP_OK) {
if (esp_partition_table_verify(partition_table, false, num_partitions) == ESP_OK) {
ESP_LOGD(TAG, "partition table is plaintext. Encrypting...");
esp_err_t err = esp_flash_encrypt_region(ESP_PARTITION_TABLE_OFFSET,
FLASH_SECTOR_SIZE);
@ -244,7 +244,7 @@ static esp_err_t encrypt_partition(int index, const esp_partition_info_t *partit
if (partition->type == PART_TYPE_APP) {
/* check if the partition holds a valid unencrypted app */
esp_image_metadata_t data_ignored;
err = esp_image_load(ESP_IMAGE_VERIFY,
err = esp_image_verify(ESP_IMAGE_VERIFY,
&partition->pos,
&data_ignored);
should_encrypt = (err == ESP_OK);

8
components/driver/rtc_module.c
View file

@ -1921,15 +1921,15 @@ static inline void adc1_hall_enable(bool enable)
static int hall_sensor_get_value() //hall sensor without LNA
{
int Sens_Vp0;
int Sens_Vn0;
int Sens_Vp1;
int Sens_Vn1;
int hall_value = 0;
adc_power_on();
#if CONFIG_IDF_TARGET_ESP32
int Sens_Vp0;
int Sens_Vn0;
int Sens_Vp1;
int Sens_Vn1;
portENTER_CRITICAL(&rtc_spinlock);
//disable other peripherals
adc1_fsm_disable();//currently the LNA is not open, close it by default

24
components/esp32s2beta/Kconfig
View file

@ -264,6 +264,26 @@ menu "ESP32S2-specific"
default 2 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO
default 4 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_FOUR
config ESP32S2_ULP_COPROC_ENABLED
bool "Enable Ultra Low Power (ULP) Coprocessor"
default "n"
help
Set to 'y' if you plan to load a firmware for the coprocessor.
If this option is enabled, further coprocessor configuration will appear in the Components menu.
config ESP32S2_ULP_COPROC_RESERVE_MEM
int
prompt "RTC slow memory reserved for coprocessor" if ESP32S2_ULP_COPROC_ENABLED
default 512 if ESP32S2_ULP_COPROC_ENABLED
range 32 8192 if ESP32S2_ULP_COPROC_ENABLED
default 0 if !ESP32S2_ULP_COPROC_ENABLED
range 0 0 if !ESP32S2_ULP_COPROC_ENABLED
help
Bytes of memory to reserve for ULP coprocessor firmware & data.
Data is reserved at the beginning of RTC slow memory.
choice ESP32S2_PANIC
prompt "Panic handler behaviour"
default ESP32S2_PANIC_PRINT_REBOOT
@ -363,7 +383,7 @@ menu "ESP32S2-specific"
# high resolution timekeeping anymore. Instead the esp_timer API, implemented
# using FRC2 timer, is used.
# FRC1 name in the option name is kept for compatibility.
choice ESP32S2__TIME_SYSCALL
choice ESP32S2_TIME_SYSCALL
prompt "Timers used for gettimeofday function"
default ESP32S2_TIME_SYSCALL_USE_RTC_FRC1
help
@ -407,7 +427,7 @@ menu "ESP32S2-specific"
bool "External 32kHz crystal"
endchoice
config ESP32S2__RTC_CLK_CAL_CYCLES
config ESP32S2_RTC_CLK_CAL_CYCLES
int "Number of cycles for RTC_SLOW_CLK calibration"
default 3000 if ESP32S2_RTC_CLK_SRC_EXT_CRYS
default 1024 if ESP32S2_RTC_CLK_SRC_INT_RC

15
components/esp32s2beta/clk.c
View file

@ -78,17 +78,18 @@ void esp_clk_init(void)
case 160:
freq = RTC_CPU_FREQ_160M;
break;
case 80:
freq = RTC_CPU_FREQ_80M;
break;
default:
freq_mhz = 80;
/* no break */
case 80:
freq = RTC_CPU_FREQ_80M;
break;
}
// Wait for UART TX to finish, otherwise some UART output will be lost
// when switching APB frequency
uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
uint32_t freq_before = rtc_clk_cpu_freq_value(rtc_clk_cpu_freq_get()) / MHZ ;
@ -211,10 +212,10 @@ void esp_perip_clk_init(void)
else {
common_perip_clk = DPORT_WDG_CLK_EN |
DPORT_I2S0_CLK_EN |
#if CONFIG_CONSOLE_UART_NUM != 0
#if CONFIG_ESP_CONSOLE_UART_NUM != 0
DPORT_UART_CLK_EN |
#endif
#if CONFIG_CONSOLE_UART_NUM != 1
#if CONFIG_ESP_CONSOLE_UART_NUM != 1
DPORT_UART1_CLK_EN |
#endif
DPORT_USB_CLK_EN |
@ -251,10 +252,10 @@ void esp_perip_clk_init(void)
//Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.
common_perip_clk |= DPORT_I2S0_CLK_EN |
#if CONFIG_CONSOLE_UART_NUM != 0
#if CONFIG_ESP_CONSOLE_UART_NUM != 0
DPORT_UART_CLK_EN |
#endif
#if CONFIG_CONSOLE_UART_NUM != 1
#if CONFIG_ESP_CONSOLE_UART_NUM != 1
DPORT_UART1_CLK_EN |
#endif
DPORT_USB_CLK_EN |

12
components/esp32s2beta/cpu_start.c
View file

@ -287,7 +287,7 @@ void IRAM_ATTR call_start_cpu1()
#else // CONFIG_CONSOLE_UART_NONE
uartAttach();
ets_install_uart_printf();
uart_tx_switch(CONFIG_CONSOLE_UART_NUM);
uart_tx_switch(CONFIG_ESP_CONSOLE_UART_NUM);
#endif
wdt_reset_cpu1_info_enable();
@ -346,11 +346,11 @@ void start_cpu0_default(void)
#ifdef CONFIG_PM_ENABLE
const int uart_clk_freq = REF_CLK_FREQ;
/* When DFS is enabled, use REFTICK as UART clock source */
CLEAR_PERI_REG_MASK(UART_CONF0_REG(CONFIG_CONSOLE_UART_NUM), UART_TICK_REF_ALWAYS_ON);
CLEAR_PERI_REG_MASK(UART_CONF0_REG(CONFIG_ESP_CONSOLE_UART_NUM), UART_TICK_REF_ALWAYS_ON);
#else
const int uart_clk_freq = APB_CLK_FREQ;
#endif // CONFIG_PM_DFS_ENABLE
uart_div_modify(CONFIG_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_CONSOLE_UART_BAUDRATE);
uart_div_modify(CONFIG_ESP_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_CONSOLE_UART_BAUDRATE);
#endif // CONFIG_CONSOLE_UART_NONE
#if CONFIG_ESP32S2_BROWNOUT_DET
@ -363,7 +363,7 @@ void start_cpu0_default(void)
esp_vfs_dev_uart_register();
esp_reent_init(_GLOBAL_REENT);
#ifndef CONFIG_CONSOLE_UART_NONE
const char* default_uart_dev = "/dev/uart/" STRINGIFY(CONFIG_CONSOLE_UART_NUM);
const char* default_uart_dev = "/dev/uart/" STRINGIFY(CONFIG_ESP_CONSOLE_UART_NUM);
_GLOBAL_REENT->_stdin = fopen(default_uart_dev, "r");
_GLOBAL_REENT->_stdout = fopen(default_uart_dev, "w");
_GLOBAL_REENT->_stderr = fopen(default_uart_dev, "w");
@ -434,14 +434,14 @@ void start_cpu1_default(void)
while (port_xSchedulerRunning[0] == 0) {
;
}
#if CONFIG_ESP32_TRAX_TWOBANKS
#if CONFIG_ESP32S2_TRAX_TWOBANKS
trax_start_trace(TRAX_DOWNCOUNT_WORDS);
#endif
#if CONFIG_ESP32_APPTRACE_ENABLE
esp_err_t err = esp_apptrace_init();
assert(err == ESP_OK && "Failed to init apptrace module on APP CPU!");
#endif
#if CONFIG_INT_WDT
#if CONFIG_ESP_INT_WDT
//Initialize the interrupt watch dog for CPU1.
//esp_int_wdt_cpu_init();
#endif

8
components/esp32s2beta/ld/esp32s2beta.ld
View file

@ -66,11 +66,13 @@ MEMORY
Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
*/
rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
len = 0x1000 - CONFIG_ULP_COPROC_RESERVE_MEM
rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM,
len = 0x1000 - CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM
}
_static_data_end = _bss_end;
/* Heap ends at top of dram0_0_seg */
_heap_end = 0x40000000 - CONFIG_TRACEMEM_RESERVE_DRAM;
_heap_end = 0x40000000 - CONFIG_ESP32S2_TRACEMEM_RESERVE_DRAM;
_data_seg_org = ORIGIN(rtc_data_seg);

10
components/esp32s2beta/panic.c
View file

@ -66,8 +66,8 @@
//printf may be broken, so we fix our own printing fns...
static void panicPutChar(char c)
{
while (((READ_PERI_REG(UART_STATUS_REG(CONFIG_CONSOLE_UART_NUM)) >> UART_TXFIFO_CNT_S)&UART_TXFIFO_CNT) >= 126) ;
WRITE_PERI_REG(UART_FIFO_AHB_REG(CONFIG_CONSOLE_UART_NUM), c);
while (((READ_PERI_REG(UART_STATUS_REG(CONFIG_ESP_CONSOLE_UART_NUM)) >> UART_TXFIFO_CNT_S)&UART_TXFIFO_CNT) >= 126) ;
WRITE_PERI_REG(UART_FIFO_AHB_REG(CONFIG_ESP_CONSOLE_UART_NUM), c);
}
static void panicPutStr(const char *c)
@ -411,7 +411,7 @@ static void esp_panic_dig_reset() __attribute__((noreturn));
static void esp_panic_dig_reset()
{
// make sure all the panic handler output is sent from UART FIFO
uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
// switch to XTAL (otherwise we will keep running from the PLL)
rtc_clk_cpu_freq_set(RTC_CPU_FREQ_XTAL);
// reset the digital part
@ -573,7 +573,7 @@ static __attribute__((noreturn)) void commonErrorHandler(XtExcFrame *frame)
#if CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH
esp_core_dump_to_flash(frame);
#endif
#if CONFIG_ESP32_ENABLE_COREDUMP_TO_UART && !CONFIG_ESP32_PANIC_SILENT_REBOOT
#if CONFIG_ESP32_ENABLE_COREDUMP_TO_UART && !CONFIG_ESP32S2_PANIC_SILENT_REBOOT
esp_core_dump_to_uart(frame);
#endif
s_dumping_core = false;
@ -581,7 +581,7 @@ static __attribute__((noreturn)) void commonErrorHandler(XtExcFrame *frame)
}
#endif /* CONFIG_ESP32_ENABLE_COREDUMP */
esp_panic_wdt_stop();
#if CONFIG_ESP32_PANIC_PRINT_REBOOT || CONFIG_ESP32_PANIC_SILENT_REBOOT
#if CONFIG_ESP32S2_PANIC_PRINT_REBOOT || CONFIG_ESP32S2_PANIC_SILENT_REBOOT
panicPutStr("Rebooting...\r\n");
if (frame->exccause != PANIC_RSN_CACHEERR) {
esp_restart_noos();

4
components/esp32s2beta/system_api.c
View file

@ -83,8 +83,8 @@ esp_err_t esp_efuse_mac_get_default(uint8_t* mac)
{
uint32_t mac_low;
uint32_t mac_high;
uint8_t efuse_crc;
uint8_t calc_crc;
// uint8_t efuse_crc;
// uint8_t calc_crc;
// mac_low = REG_READ(EFUSE_BLK0_RDATA1_REG);
// mac_high = REG_READ(EFUSE_BLK0_RDATA2_REG);

8
components/esp_common/include/esp_bit_defs.h
View file

@ -50,8 +50,14 @@
//}}
#ifndef __ASSEMBLER__
#ifndef BIT
#define BIT(nr) (1UL << (nr))
#endif
#ifndef BIT64
#define BIT64(nr) (1ULL << (nr))
#endif
#else
#ifndef BIT
#define BIT(nr) (1 << (nr))
#endif
#endif
#endif

4
components/esp_common/include/esp_system.h
View file

@ -37,7 +37,11 @@ typedef enum {
/** @cond */
#define TWO_UNIVERSAL_MAC_ADDR 2
#define FOUR_UNIVERSAL_MAC_ADDR 4
#if CONFIG_IDF_TARGET_ESP32
#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES
#endif
/** @endcond */
/**

2
components/esp_common/src/dbg_stubs.c
View file

@ -21,7 +21,7 @@
#include "esp_private/dbg_stubs.h"
#include "esp_attr.h"
#if CONFIG_ESP32_DEBUG_STUBS_ENABLE
#if CONFIG_ESP32_DEBUG_STUBS_ENABLE || CONFIG_ESP32S2_DEBUG_STUBS_ENABLE
/*
Debug stubs is actually a table of 4-byte entries. Every entry is equal to zero or must contain meaningfull data.
The first entry is a service one and has the followinf format:

4
components/newlib/time.c
View file

@ -43,11 +43,11 @@
#include "esp32s2beta/rom/ets_sys.h"
#endif
#if defined( CONFIG_ESP32_TIME_SYSCALL_USE_RTC ) || defined( CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1 )
#if defined( CONFIG_ESP32_TIME_SYSCALL_USE_RTC ) || defined( CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1 ) || defined( CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC ) || defined( CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC_FRC1 )
#define WITH_RTC 1
#endif
#if defined( CONFIG_ESP32_TIME_SYSCALL_USE_FRC1 ) || defined( CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1 )
#if defined( CONFIG_ESP32_TIME_SYSCALL_USE_FRC1 ) || defined( CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1 ) || defined( CONFIG_ESP32S2_TIME_SYSCALL_USE_FRC1 ) || defined( CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC_FRC1 )
#define WITH_FRC 1
#endif

2
components/soc/esp32s2beta/cpu_util.c
View file

@ -52,7 +52,7 @@ void IRAM_ATTR esp_cpu_reset(int cpu_id)
bool IRAM_ATTR esp_cpu_in_ocd_debug_mode()
{
#if CONFIG_ESP32_DEBUG_OCDAWARE
#if CONFIG_ESP32S2_DEBUG_OCDAWARE
int dcr;
int reg=0x10200C; //DSRSET register
asm("rer %0,%1":"=r"(dcr):"r"(reg));

46
components/soc/esp32s2beta/include/soc/soc.h
View file

@ -12,48 +12,14 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ESP32_SOC_H_
#define _ESP32_SOC_H_
#pragma once
#ifndef __ASSEMBLER__
#include <stdint.h>
#include "esp_assert.h"
#endif
//Register Bits{{
#define BIT31 0x80000000
#define BIT30 0x40000000
#define BIT29 0x20000000
#define BIT28 0x10000000
#define BIT27 0x08000000
#define BIT26 0x04000000
#define BIT25 0x02000000
#define BIT24 0x01000000
#define BIT23 0x00800000
#define BIT22 0x00400000
#define BIT21 0x00200000
#define BIT20 0x00100000
#define BIT19 0x00080000
#define BIT18 0x00040000
#define BIT17 0x00020000
#define BIT16 0x00010000
#define BIT15 0x00008000
#define BIT14 0x00004000
#define BIT13 0x00002000
#define BIT12 0x00001000
#define BIT11 0x00000800
#define BIT10 0x00000400
#define BIT9 0x00000200
#define BIT8 0x00000100
#define BIT7 0x00000080
#define BIT6 0x00000040
#define BIT5 0x00000020
#define BIT4 0x00000010
#define BIT3 0x00000008
#define BIT2 0x00000004
#define BIT1 0x00000002
#define BIT0 0x00000001
//}}
#include <esp_bit_defs.h>
#define PRO_CPU_NUM (0)
@ -127,12 +93,6 @@
#define ETS_UNCACHED_ADDR(addr) (addr)
#define ETS_CACHED_ADDR(addr) (addr)
#ifndef __ASSEMBLER__
#define BIT(nr) (1UL << (nr))
#else
#define BIT(nr) (1 << (nr))
#endif
#ifndef __ASSEMBLER__
#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END)
@ -373,5 +333,3 @@
//Invalid interrupt for number interrupt matrix
#define ETS_INVALID_INUM 6
#endif /* _ESP32_SOC_H_ */

2
components/soc/esp32s2beta/rtc_clk.c
View file

@ -805,7 +805,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
*/
rtc_xtal_freq_t est_xtal_freq = rtc_clk_xtal_freq_estimate();
if (est_xtal_freq != xtal_freq) {
SOC_LOGW(TAG, "Possibly invalid CONFIG_ESP32_XTAL_FREQ setting (%dMHz). Detected %d MHz.",
SOC_LOGW(TAG, "Possibly invalid CONFIG_ESP32S2_XTAL_FREQ setting (%dMHz). Detected %d MHz.",
xtal_freq, est_xtal_freq);
}
}

14
components/soc/esp32s2beta/soc_memory_layout.c
View file

@ -73,22 +73,22 @@ const soc_memory_region_t soc_memory_regions[] = {
{ SOC_SLOW_EXTRAM_DATA_LOW, SOC_SLOW_EXTRAM_DATA_HIGH - SOC_SLOW_EXTRAM_DATA_LOW, 5, 0}, //SPI SRAM, if available
#endif
#endif
#if CONFIG_INSTRUCTION_CACHE_8KB
#if CONFIG_DATA_CACHE_0KB
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
#if CONFIG_ESP32S2_DATA_CACHE_0KB
{ 0x3FFB2000, 0x2000, 0, 0x400B2000}, //Block 1, can be use as I/D cache memory
{ 0x3FFB4000, 0x2000, 0, 0x400B4000}, //Block 2, can be use as D cache memory
{ 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory
#elif CONFIG_DATA_CACHE_8KB
#elif CONFIG_ESP32S2_DATA_CACHE_8KB
{ 0x3FFB4000, 0x2000, 0, 0x400B4000}, //Block 2, can be use as D cache memory
{ 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory
#else
{ 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory
#endif
#else
#if CONFIG_DATA_CACHE_0KB
#if CONFIG_ESP32S2_DATA_CACHE_0KB
{ 0x3FFB4000, 0x2000, 0, 0x400B4000}, //Block 2, can be use as D cache memory
{ 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory
#elif CONFIG_DATA_CACHE_8KB
#elif CONFIG_ESP32S2_DATA_CACHE_8KB
{ 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory
#endif
#endif
@ -127,8 +127,8 @@ const soc_reserved_region_t soc_reserved_regions[] = {
{ 0x3fff8000, (intptr_t)&_data_start_xtos}, //ROM data region
#if CONFIG_MEMMAP_TRACEMEM
#if CONFIG_MEMMAP_TRACEMEM_TWOBANKS
#if CONFIG_ESP32S2_MEMMAP_TRACEMEM
#if CONFIG_ESP32S2_MEMMAP_TRACEMEM_TWOBANKS
{ 0x3fff8000, 0x40000000 }, //Reserve trace mem region
#else
{ 0x3fff8000, 0x3fffc000 }, //Reserve trace mem region

14
components/spi_flash/cache_utils.c
View file

@ -345,7 +345,7 @@ IRAM_ATTR void esp_config_instruction_cache_mode(void)
cache_ways_t cache_ways;
cache_line_size_t cache_line_size;
#if CONFIG_INSTRUCTION_CACHE_8KB
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
cache_size = CACHE_SIZE_8KB;
#else
@ -377,8 +377,8 @@ IRAM_ATTR void esp_config_data_cache_mode(void)
cache_ways_t cache_ways;
cache_line_size_t cache_line_size;
#if CONFIG_INSTRUCTION_CACHE_8KB
#if CONFIG_DATA_CACHE_8KB
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
#if CONFIG_ESP32S2_DATA_CACHE_8KB
Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
cache_size = CACHE_SIZE_8KB;
#else
@ -386,7 +386,7 @@ IRAM_ATTR void esp_config_data_cache_mode(void)
cache_size = CACHE_SIZE_16KB;
#endif
#else
#if CONFIG_DATA_CACHE_8KB
#if CONFIG_ESP32S2_DATA_CACHE_8KB
Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH, CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID);
cache_size = CACHE_SIZE_8KB;
#else
@ -395,14 +395,14 @@ IRAM_ATTR void esp_config_data_cache_mode(void)
#endif
#endif
#if CONFIG_DATA_CACHE_4WAYS
#if CONFIG_ESP32S2_DATA_CACHE_4WAYS
cache_ways = CACHE_4WAYS_ASSOC;
#else
cache_ways = CACHE_8WAYS_ASSOC;
#endif
#if CONFIG_DATA_CACHE_LINE_16B
#if CONFIG_ESP32S2_DATA_CACHE_LINE_16B
cache_line_size = CACHE_LINE_SIZE_16B;
#elif CONFIG_DATA_CACHE_LINE_32B
#elif CONFIG_ESP32S2_DATA_CACHE_LINE_32B
cache_line_size = CACHE_LINE_SIZE_32B;
#else
cache_line_size = CACHE_LINE_SIZE_64B;

2
components/spi_flash/flash_mmap.c
View file

@ -471,12 +471,14 @@ IRAM_ATTR bool spi_flash_check_and_flush_cache(size_t start_addr, size_t length)
}
if (is_page_mapped_in_cache(page)) {
#if CONFIG_IDF_TARGET_ESP32
#if CONFIG_SPIRAM
esp_spiram_writeback_cache();
#endif
Cache_Flush(0);
#ifndef CONFIG_FREERTOS_UNICORE
Cache_Flush(1);
#endif
#endif
return true;
}

5
components/spiffs/CMakeLists.txt
View file

@ -12,8 +12,3 @@ set(COMPONENT_REQUIRES spi_flash)
set(COMPONENT_PRIV_REQUIRES bootloader_support)
register_component()
set_source_files_properties(
"spiffs/src/spiffs_nucleus.c"
PROPERTIES COMPILE_FLAGS
-Wno-tautological-compare)

2
components/spiffs/component.mk
View file

@ -3,5 +3,3 @@ COMPONENT_PRIV_INCLUDEDIRS := . spiffs/src
COMPONENT_SRCDIRS := . spiffs/src
COMPONENT_SUBMODULES := spiffs
spiffs/src/spiffs_nucleus.o: CFLAGS += -Wno-tautological-compare