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add gpio driver code

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This commit is contained in:
Wangjialin 2016-09-19 17:33:21 +08:00
parent b1ac144874
commit 2be163f6cc
15 changed files with 1160 additions and 225 deletions
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14
components/driver/component.mk Normal file
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#
# Component Makefile
#
# This Makefile should, at the very least, just include $(SDK_PATH)/make/component.mk. By default,
# this will take the sources in this directory, compile them and link them into
# lib(subdirectory_name).a in the build directory. This behaviour is entirely configurable,
# please read the SDK documents if you need to do this.
#
COMPONENT_ADD_INCLUDEDIRS := include
COMPONENT_PRIV_INCLUDEDIRS := include/driver
include $(IDF_PATH)/make/component_common.mk

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components/driver/gpio.c Normal file
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <esp_types.h>
#include "rom/ets_sys.h"
#include "esp_err.h"
#include "esp_intr.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
#include "freertos/xtensa_api.h"
#include "soc/soc.h"
#include "driver/gpio.h"
//TODO: move debug options to menuconfig
#define GPIO_DBG_ENABLE (0)
#define GPIO_WARNING_ENABLE (0)
#define GPIO_ERROR_ENABLE (0)
#define GPIO_INFO_ENABLE (0)
//DBG INFOR
#if GPIO_INFO_ENABLE
#define GPIO_INFO ets_printf
#else
#define GPIO_INFO(...)
#endif
#if GPIO_WARNING_ENABLE
#define GPIO_WARNING(format,...) do{\
ets_printf("[waring][%s#%u]",__FUNCTION__,__LINE__);\
ets_printf(format,##__VA_ARGS__);\
}while(0)
#else
#define GPIO_WARNING(...)
#endif
#if GPIO_ERROR_ENABLE
#define GPIO_ERROR(format,...) do{\
ets_printf("[error][%s#%u]",__FUNCTION__,__LINE__);\
ets_printf(format,##__VA_ARGS__);\
}while(0)
#else
#define GPIO_ERROR(...)
#endif
const uint32_t GPIO_PIN_MUX_REG[40] = {
GPIO_PIN_REG_0,
GPIO_PIN_REG_1,
GPIO_PIN_REG_2,
GPIO_PIN_REG_3,
GPIO_PIN_REG_4,
GPIO_PIN_REG_5,
GPIO_PIN_REG_6,
GPIO_PIN_REG_7,
GPIO_PIN_REG_8,
GPIO_PIN_REG_9,
GPIO_PIN_REG_10,
GPIO_PIN_REG_11,
GPIO_PIN_REG_12,
GPIO_PIN_REG_13,
GPIO_PIN_REG_14,
GPIO_PIN_REG_15,
GPIO_PIN_REG_16,
GPIO_PIN_REG_17,
GPIO_PIN_REG_18,
GPIO_PIN_REG_19,
0,
GPIO_PIN_REG_21,
GPIO_PIN_REG_22,
GPIO_PIN_REG_23,
0,
GPIO_PIN_REG_25,
GPIO_PIN_REG_26,
GPIO_PIN_REG_27,
0,
0,
0,
0,
GPIO_PIN_REG_32,
GPIO_PIN_REG_33,
GPIO_PIN_REG_34,
GPIO_PIN_REG_35,
GPIO_PIN_REG_36,
GPIO_PIN_REG_37,
GPIO_PIN_REG_38,
GPIO_PIN_REG_39
};
static SemaphoreHandle_t gpio_mutex = NULL;
static int is_valid_gpio(int gpio_num)
{
if(gpio_num >= GPIO_PIN_COUNT || GPIO_PIN_MUX_REG[gpio_num] == 0) {
GPIO_ERROR("GPIO io_num=%d does not exist\n",gpio_num);
return 0;
}
return 1;
}
static esp_err_t gpio_mutex_init()
{
if(gpio_mutex == NULL) {
gpio_mutex = xSemaphoreCreateRecursiveMutex();
if(gpio_mutex == NULL)
return ESP_FAIL;
}
return ESP_OK;
}
static esp_err_t gpio_set_intr_type(gpio_num_t gpio_num, uint8_t intr_type)
{
if(!is_valid_gpio(gpio_num))
return ESP_ERR_INVALID_ARG;
if(intr_type >= GPIO_PIN_INTR_MAX) {
GPIO_ERROR("Unknown GPIO intr:%u\n",intr_type);
return ESP_ERR_INVALID_ARG;
}
if(gpio_mutex != NULL) {
xSemaphoreTakeRecursive(gpio_mutex, portMAX_DELAY);
GPIO.pin[gpio_num].int_type = intr_type;
xSemaphoreGiveRecursive(gpio_mutex);
return ESP_OK;
} else {
GPIO_ERROR("Mutex null\n");
return ESP_FAIL;
}
}
static esp_err_t gpio_intr_enable(gpio_num_t gpio_num)
{
if(!is_valid_gpio(gpio_num))
return ESP_ERR_INVALID_ARG;
if(gpio_mutex != NULL) {
xSemaphoreTakeRecursive(gpio_mutex, portMAX_DELAY);
if(xPortGetCoreID() == 0) {
GPIO.pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA; //enable pro cpu intr
} else {
GPIO.pin[gpio_num].int_ena = GPIO_APP_CPU_INTR_ENA; //enable pro cpu intr
}
xSemaphoreGiveRecursive(gpio_mutex);
return ESP_OK;
} else {
GPIO_ERROR("Mutex null\n");
return ESP_FAIL;
}
}
static esp_err_t gpio_intr_disable(gpio_num_t gpio_num)
{
if(!is_valid_gpio(gpio_num))
return ESP_ERR_INVALID_ARG;
if(gpio_mutex != NULL) {
xSemaphoreTakeRecursive(gpio_mutex, portMAX_DELAY);
GPIO.pin[gpio_num].int_ena = 0; //disable GPIO intr
xSemaphoreGiveRecursive(gpio_mutex);
return ESP_OK;
} else {
GPIO_ERROR("Mutex null\n");
return ESP_FAIL;
}
}
static esp_err_t gpio_input_enable(gpio_num_t gpio_num)
{
if(!is_valid_gpio(gpio_num))
return ESP_ERR_INVALID_ARG;
if(gpio_mutex != NULL) {
xSemaphoreTakeRecursive(gpio_mutex, portMAX_DELAY);
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
xSemaphoreGiveRecursive(gpio_mutex);
return ESP_OK;
} else {
GPIO_ERROR("Mutex null\n");
return ESP_FAIL;
}
}
static esp_err_t gpio_input_disable(gpio_num_t gpio_num)
{
if(!is_valid_gpio(gpio_num))
return ESP_ERR_INVALID_ARG;
if(gpio_mutex != NULL) {
xSemaphoreTakeRecursive(gpio_mutex, portMAX_DELAY);
PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
xSemaphoreGiveRecursive(gpio_mutex);
return ESP_OK;
} else {
GPIO_ERROR("Mutex null\n");
return ESP_FAIL;
}
}
static esp_err_t gpio_output_disable(gpio_num_t gpio_num)
{
if(!is_valid_gpio(gpio_num))
return ESP_ERR_INVALID_ARG;
if(gpio_num < 32) {
GPIO.enable_w1tc = (0x1 << gpio_num);
} else {
GPIO.enable1_w1tc.data = (0x1 << (gpio_num - 32));
}
return ESP_OK;
}
static esp_err_t gpio_output_enable(gpio_num_t gpio_num)
{
if(gpio_num >= 34) {
GPIO_ERROR("io_num=%d only input\n",gpio_num);
return ESP_ERR_INVALID_ARG;
}
if(gpio_num >= GPIO_PIN_COUNT || GPIO_PIN_MUX_REG[gpio_num] == 0) {
GPIO_ERROR("io_num=%d not exits\n",gpio_num);
return ESP_ERR_INVALID_ARG;
}
if(gpio_num < 32) {
GPIO.enable_w1ts = (0x1 << gpio_num);
} else {
GPIO.enable1_w1ts.data = (0x1 << (gpio_num - 32));
}
return ESP_OK;
}
esp_err_t gpio_set_level(gpio_num_t gpio_num, uint32_t level)
{
if(!is_valid_gpio(gpio_num))
return ESP_ERR_INVALID_ARG;
if(level) {
if(gpio_num < 32)
GPIO.out_w1ts = (1 << gpio_num);
else
GPIO.out1_w1ts.data = (1 << (gpio_num - 32));
} else {
if(gpio_num < 32)
GPIO.out_w1tc = (1 << gpio_num);
else
GPIO.out1_w1tc.data = (1 << (gpio_num - 32));
}
return ESP_OK;
}
int gpio_get_level(gpio_num_t gpio_num)
{
if(gpio_num < 32) {
return (GPIO.in >> gpio_num) & 0x1;
} else {
return (GPIO.in1.data >> (gpio_num - 32)) & 0x1;
}
}
esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull)
{
if(gpio_mutex != NULL) {
if(!is_valid_gpio(gpio_num))
return ESP_ERR_INVALID_ARG;
xSemaphoreTakeRecursive(gpio_mutex, portMAX_DELAY);
esp_err_t ret = ESP_OK;
switch(pull) {
case GPIO_PULLUP_ONLY:
PIN_PULLUP_EN(GPIO_PIN_MUX_REG[gpio_num]);
PIN_PULLDWN_DIS(GPIO_PIN_MUX_REG[gpio_num]);
break;
case GPIO_PULLDOWN_ONLY:
PIN_PULLUP_DIS(GPIO_PIN_MUX_REG[gpio_num]);
PIN_PULLDWN_EN(GPIO_PIN_MUX_REG[gpio_num]);
break;
case GPIO_PULLUP_PULLDOWN:
PIN_PULLUP_EN(GPIO_PIN_MUX_REG[gpio_num]);
PIN_PULLDWN_EN(GPIO_PIN_MUX_REG[gpio_num]);
break;
case GPIO_FLOATING:
PIN_PULLUP_DIS(GPIO_PIN_MUX_REG[gpio_num]);
PIN_PULLDWN_DIS(GPIO_PIN_MUX_REG[gpio_num]);
break;
default:
GPIO_ERROR("Unknown pull up/down mode,gpio_num=%u,pull=%u\n",gpio_num,pull);
ret = ESP_ERR_INVALID_ARG;
break;
}
xSemaphoreGiveRecursive(gpio_mutex);
return ret;
} else {
GPIO_ERROR("Mutex null\n");
return ESP_FAIL;
}
}
esp_err_t gpio_set_direction(gpio_num_t gpio_num, gpio_direction_t direction)
{
if(gpio_mutex != NULL) {
if(!is_valid_gpio(gpio_num))
return ESP_ERR_INVALID_ARG;
xSemaphoreTakeRecursive(gpio_mutex, portMAX_DELAY);
esp_err_t ret = ESP_OK;
switch(direction) {
case GPIO_DIR_OUTPUT_ONLY:
gpio_input_disable(gpio_num);
gpio_output_enable(gpio_num);
break;
case GPIO_DIR_INPUT_ONLY:
gpio_input_enable(gpio_num);
gpio_output_disable(gpio_num);
break;
case GPIO_DIR_INPUT_AND_OUTPUT:
gpio_input_enable(gpio_num);
gpio_output_enable(gpio_num);
break;
case GPIO_DIR_DISABLE_IO:
gpio_input_disable(gpio_num);
gpio_output_disable(gpio_num);
break;
default:
GPIO_ERROR("Unkown direction type,gpio_num=%u,direction=%u\n",gpio_num,direction);
ret = ESP_ERR_INVALID_ARG;
break;
}
xSemaphoreGiveRecursive(gpio_mutex);
return ret;
} else {
GPIO_ERROR("Mutex null\n");
return ESP_FAIL;
}
}
esp_err_t gpio_config(gpio_config_t *pGPIOConfig)
{
if(gpio_mutex == NULL) {
gpio_mutex = xSemaphoreCreateRecursiveMutex();
if(gpio_mutex == NULL) {
GPIO_ERROR("Mutex null\n");
return ESP_FAIL;
}
}
uint64_t gpio_pin_mask = (pGPIOConfig->pin_bit_mask);
uint32_t io_reg = 0;
uint8_t io_num = 0;
uint64_t bit_valid = 0;
if(pGPIOConfig->pin_bit_mask == 0) {
GPIO_ERROR("GPIO_PIN = 0 \n");
return ESP_ERR_INVALID_ARG;
}
if((pGPIOConfig->mode) & (BIT1)) {
//GPIO 34/35/36/37/38/39 can only be used as input mode;
if((gpio_pin_mask & ( GPIO_SEL_34 | GPIO_SEL_35 | GPIO_SEL_36 | GPIO_SEL_37 | GPIO_SEL_38 | GPIO_SEL_39))) {
GPIO_ERROR("GPIO34-39 can only be used as input mode\n");
return ESP_ERR_INVALID_ARG;
}
}
xSemaphoreTakeRecursive(gpio_mutex, portMAX_DELAY);
do {
io_reg = GPIO_PIN_MUX_REG[io_num];
if(((gpio_pin_mask >> io_num) & BIT(0)) && io_reg) {
GPIO_INFO("Gpio%02d |Mode:",io_num);
if((pGPIOConfig->mode) & GPIO_MODE_INPUT) {
GPIO_INFO("INPUT ");
gpio_input_enable(io_num);
} else {
gpio_input_disable(io_num);
}
if((pGPIOConfig->mode) & BIT2) {
GPIO_INFO("OD ");
GPIO.pin[io_num].pad_driver = 1; /*0x01 Open-drain */
} else {
GPIO.pin[io_num].pad_driver = 0; /*0x00 Normal gpio output */
}
if((pGPIOConfig->mode) & GPIO_MODE_OUTPUT) {
GPIO_INFO("OUTPUT ");
gpio_output_enable(io_num);
} else {
gpio_output_disable(io_num);
}
GPIO_INFO("|");
if(pGPIOConfig->pull_up_en) {
GPIO_INFO("PU ");
PIN_PULLUP_EN(io_reg);
} else {
PIN_PULLUP_DIS(io_reg);
}
if(pGPIOConfig->pull_down_en) {
GPIO_INFO("PD ");
PIN_PULLDWN_EN(io_reg);
} else {
PIN_PULLDWN_DIS(io_reg);
}
GPIO_INFO("Intr:%d |\n",pGPIOConfig->intr_type);
gpio_set_intr_type(io_num, pGPIOConfig->intr_type);
if(pGPIOConfig->intr_type) {
gpio_intr_enable(io_num);
} else {
gpio_intr_disable(io_num);
}
PIN_FUNC_SELECT(io_reg, GPIO_FUNC_SEL); /*function number 2 is GPIO_FUNC for each pin */
} else if(bit_valid && (io_reg == 0)) {
GPIO_WARNING("io_num=%d not exits\n",io_num);
}
io_num++;
} while(io_num < GPIO_PIN_COUNT);
xSemaphoreGiveRecursive(gpio_mutex);
return ESP_OK;
}
esp_err_t gpio_intr_handler_register(uint8_t gpio_intr_num, void (*fn)(void*), void * arg)
{
if(gpio_mutex != NULL) {
xSemaphoreTakeRecursive(gpio_mutex, portMAX_DELAY);
ESP_INTR_DISABLE(gpio_intr_num);
intr_matrix_set(xPortGetCoreID(), ETS_GPIO_INTR_SOURCE, gpio_intr_num);
xt_set_interrupt_handler(gpio_intr_num, fn, arg);
ESP_INTR_ENABLE(gpio_intr_num);
xSemaphoreGiveRecursive(gpio_mutex);
return ESP_OK;
} else {
GPIO_ERROR("Mutex null\n");
return ESP_FAIL;
}
}
/*only level interrupt can be used for wake-up function*/
esp_err_t gpio_pin_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type)
{
if(gpio_mutex != NULL) {
esp_err_t ret = ESP_OK;
xSemaphoreTakeRecursive(gpio_mutex, portMAX_DELAY);
if((intr_type == GPIO_PIN_INTR_LOW_LEVEL) || (intr_type == GPIO_PIN_INTR_HIGH_LEVEL)) {
GPIO.pin[gpio_num].int_type = intr_type;
GPIO.pin[gpio_num].wakeup_enable = 0x1;
} else {
GPIO_ERROR("GPIO wakeup only support Level mode,but edge mode set. gpio_num:%u\n",gpio_num);
ret = ESP_ERR_INVALID_ARG;
}
xSemaphoreGiveRecursive(gpio_mutex);
return ret;
} else {
GPIO_ERROR("Mutex null\n");
return ESP_FAIL;
}
}
esp_err_t gpio_pin_wakeup_disable(gpio_num_t gpio_num)
{
if(gpio_mutex != NULL) {
xSemaphoreTakeRecursive(gpio_mutex, portMAX_DELAY);
GPIO.pin[gpio_num].wakeup_enable = 0;
xSemaphoreGiveRecursive(gpio_mutex);
return ESP_OK;
} else {
GPIO_ERROR("Mutex null\n");
return ESP_FAIL;
}
}

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components/driver/include/driver/gpio.h Normal file
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _DRIVER_GPIO_H_
#define _DRIVER_GPIO_H_
#include <esp_types.h>
#include "soc/gpio_reg.h"
#include "soc/gpio_struct.h"
#include "soc/rtc_io_reg.h"
#include "soc/io_mux_reg.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
extern const uint32_t GPIO_PIN_MUX_REG[40];
#define GPIO_SEL_0 (BIT(0)) /* Pin 0 selected */
#define GPIO_SEL_1 (BIT(1)) /* Pin 1 selected */
#define GPIO_SEL_2 (BIT(2)) /* Pin 2 selected */
#define GPIO_SEL_3 (BIT(3)) /* Pin 3 selected */
#define GPIO_SEL_4 (BIT(4)) /* Pin 4 selected */
#define GPIO_SEL_5 (BIT(5)) /* Pin 5 selected */
#define GPIO_SEL_6 (BIT(6)) /* Pin 6 selected */
#define GPIO_SEL_7 (BIT(7)) /* Pin 7 selected */
#define GPIO_SEL_8 (BIT(8)) /* Pin 8 selected */
#define GPIO_SEL_9 (BIT(9)) /* Pin 9 selected */
#define GPIO_SEL_10 (BIT(10)) /* Pin 10 selected */
#define GPIO_SEL_11 (BIT(11)) /* Pin 11 selected */
#define GPIO_SEL_12 (BIT(12)) /* Pin 12 selected */
#define GPIO_SEL_13 (BIT(13)) /* Pin 13 selected */
#define GPIO_SEL_14 (BIT(14)) /* Pin 14 selected */
#define GPIO_SEL_15 (BIT(15)) /* Pin 15 selected */
#define GPIO_SEL_16 (BIT(16)) /* Pin 16 selected */
#define GPIO_SEL_17 (BIT(17)) /* Pin 17 selected */
#define GPIO_SEL_18 (BIT(18)) /* Pin 18 selected */
#define GPIO_SEL_19 (BIT(19)) /* Pin 19 selected */
#define GPIO_SEL_21 (BIT(21)) /* Pin 21 selected */
#define GPIO_SEL_22 (BIT(22)) /* Pin 22 selected */
#define GPIO_SEL_23 (BIT(23)) /* Pin 23 selected */
#define GPIO_SEL_25 (BIT(25)) /* Pin 25 selected */
#define GPIO_SEL_26 (BIT(26)) /* Pin 26 selected */
#define GPIO_SEL_27 (BIT(27)) /* Pin 27 selected */
#define GPIO_SEL_32 ((uint64_t)(((uint64_t)1)<<32)) /* Pin 32 selected */
#define GPIO_SEL_33 ((uint64_t)(((uint64_t)1)<<33)) /* Pin 33 selected */
#define GPIO_SEL_34 ((uint64_t)(((uint64_t)1)<<34)) /* Pin 34 selected */
#define GPIO_SEL_35 ((uint64_t)(((uint64_t)1)<<35)) /* Pin 35 selected */
#define GPIO_SEL_36 ((uint64_t)(((uint64_t)1)<<36)) /* Pin 36 selected */
#define GPIO_SEL_37 ((uint64_t)(((uint64_t)1)<<37)) /* Pin 37 selected */
#define GPIO_SEL_38 ((uint64_t)(((uint64_t)1)<<38)) /* Pin 38 selected */
#define GPIO_SEL_39 ((uint64_t)(((uint64_t)1)<<39)) /* Pin 39 selected */
#define GPIO_FUNC_SEL 2
#define GPIO_PIN_REG_0 PERIPHS_IO_MUX_GPIO0_U
#define GPIO_PIN_REG_1 PERIPHS_IO_MUX_U0TXD_U
#define GPIO_PIN_REG_2 PERIPHS_IO_MUX_GPIO2_U
#define GPIO_PIN_REG_3 PERIPHS_IO_MUX_U0RXD_U
#define GPIO_PIN_REG_4 PERIPHS_IO_MUX_GPIO4_U
#define GPIO_PIN_REG_5 PERIPHS_IO_MUX_GPIO5_U
#define GPIO_PIN_REG_6 PERIPHS_IO_MUX_SD_CLK_U
#define GPIO_PIN_REG_7 PERIPHS_IO_MUX_SD_DATA0_U
#define GPIO_PIN_REG_8 PERIPHS_IO_MUX_SD_DATA1_U
#define GPIO_PIN_REG_9 PERIPHS_IO_MUX_SD_DATA2_U
#define GPIO_PIN_REG_10 PERIPHS_IO_MUX_SD_DATA3_U
#define GPIO_PIN_REG_11 PERIPHS_IO_MUX_SD_CMD_U
#define GPIO_PIN_REG_12 PERIPHS_IO_MUX_MTDI_U
#define GPIO_PIN_REG_13 PERIPHS_IO_MUX_MTCK_U
#define GPIO_PIN_REG_14 PERIPHS_IO_MUX_MTMS_U
#define GPIO_PIN_REG_15 PERIPHS_IO_MUX_MTDO_U
#define GPIO_PIN_REG_16 PERIPHS_IO_MUX_GPIO16_U
#define GPIO_PIN_REG_17 PERIPHS_IO_MUX_GPIO17_U
#define GPIO_PIN_REG_18 PERIPHS_IO_MUX_GPIO18_U
#define GPIO_PIN_REG_19 PERIPHS_IO_MUX_GPIO19_U
#define GPIO_PIN_REG_20 PERIPHS_IO_MUX_GPIO20_U
#define GPIO_PIN_REG_21 PERIPHS_IO_MUX_GPIO21_U
#define GPIO_PIN_REG_22 PERIPHS_IO_MUX_GPIO22_U
#define GPIO_PIN_REG_23 PERIPHS_IO_MUX_GPIO23_U
#define GPIO_PIN_REG_25 PERIPHS_IO_MUX_GPIO25_U
#define GPIO_PIN_REG_26 PERIPHS_IO_MUX_GPIO26_U
#define GPIO_PIN_REG_27 PERIPHS_IO_MUX_GPIO27_U
#define GPIO_PIN_REG_32 PERIPHS_IO_MUX_GPIO32_U
#define GPIO_PIN_REG_33 PERIPHS_IO_MUX_GPIO33_U
#define GPIO_PIN_REG_34 PERIPHS_IO_MUX_GPIO34_U
#define GPIO_PIN_REG_35 PERIPHS_IO_MUX_GPIO35_U
#define GPIO_PIN_REG_36 PERIPHS_IO_MUX_GPIO36_U
#define GPIO_PIN_REG_37 PERIPHS_IO_MUX_GPIO37_U
#define GPIO_PIN_REG_38 PERIPHS_IO_MUX_GPIO38_U
#define GPIO_PIN_REG_39 PERIPHS_IO_MUX_GPIO39_U
#define GPIO_APP_CPU_INTR_ENA (BIT(0))
#define GPIO_APP_CPU_NMI_INTR_ENA (BIT(1))
#define GPIO_PRO_CPU_INTR_ENA (BIT(2))
#define GPIO_PRO_CPU_NMI_INTR_ENA (BIT(3))
#define GPIO_SDIO_EXT_INTR_ENA (BIT(4))
#define GPIO_PIN_COUNT 40
#define GPIO_ID_PIN0 0
#define GPIO_ID_PIN(n) (GPIO_ID_PIN0 + (n))
#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i * 4)
typedef enum {
GPIO_NUM_0 = 0,
GPIO_NUM_1 = 1,
GPIO_NUM_2 = 2,
GPIO_NUM_3 = 3,
GPIO_NUM_4 = 4,
GPIO_NUM_5 = 5,
GPIO_NUM_6 = 6,
GPIO_NUM_7 = 7,
GPIO_NUM_8 = 8,
GPIO_NUM_9 = 9,
GPIO_NUM_10 = 10,
GPIO_NUM_11 = 11,
GPIO_NUM_12 = 12,
GPIO_NUM_13 = 13,
GPIO_NUM_14 = 14,
GPIO_NUM_15 = 15,
GPIO_NUM_16 = 16,
GPIO_NUM_17 = 17,
GPIO_NUM_18 = 18,
GPIO_NUM_19 = 19,
GPIO_NUM_21 = 21,
GPIO_NUM_22 = 22,
GPIO_NUM_23 = 23,
GPIO_NUM_25 = 25,
GPIO_NUM_26 = 26,
GPIO_NUM_27 = 27,
GPIO_NUM_32 = 32,
GPIO_NUM_33 = 33,
GPIO_NUM_34 = 34, /*input mode only */
GPIO_NUM_35 = 35, /*input mode only */
GPIO_NUM_36 = 36, /*input mode only */
GPIO_NUM_37 = 37, /*input mode only */
GPIO_NUM_38 = 38, /*input mode only */
GPIO_NUM_39 = 39, /*input mode only */
} gpio_num_t;
typedef enum {
GPIO_PIN_INTR_DISABLE = 0, /* disable GPIO interrupt */
GPIO_PIN_INTR_POSEDGE = 1, /* GPIO interrupt type : rising edge */
GPIO_PIN_INTR_NEGEDGE = 2, /* GPIO interrupt type : falling edge */
GPIO_PIN_INTR_ANYEDGE = 3, /* GPIO interrupt type : both rising and falling edge */
GPIO_PIN_INTR_LOW_LEVEL = 4, /* GPIO interrupt type : input low level trigger */
GPIO_PIN_INTR_HIGH_LEVEL = 5, /* GPIO interrupt type : input high level trigger */
GPIO_PIN_INTR_MAX,
} gpio_int_type_t;
typedef enum {
GPIO_MODE_INPUT = (BIT0), /* GPIO mode : input only */
GPIO_MODE_OUTPUT = (BIT1), /* GPIO mode : output only mode */
GPIO_MODE_OUTPUT_OD = ((BIT1)|(BIT2)), /* GPIO mode : output only with open-drain mode */
GPIO_MODE_INPUT_OUTPUT_OD = ((BIT0)|(BIT1)|(BIT2)), /* GPIO mode : output and input with open-drain mode*/
GPIO_MODE_INPUT_OUTPUT = ((BIT0)|(BIT1)), /* GPIO mode : output and input mode */
} gpio_mode_t;
typedef enum {
GPIO_PULLUP_DISABLE = 0x0, /* disable GPIO pull-up resistor */
GPIO_PULLUP_ENABLE = 0x1, /* enable GPIO pull-up resistor */
} gpio_pullup_t;
typedef enum {
GPIO_PULLDOWN_DISABLE = 0x0, /* disable GPIO pull-down resistor */
GPIO_PULLDOWN_ENABLE = 0x1, /* enable GPIO pull-down resistor */
} gpio_pulldown_t;
typedef struct {
uint64_t pin_bit_mask; /* GPIO pin: set with bit mask, each bit maps to a GPIO */
gpio_mode_t mode; /* GPIO mode: set input/output mode */
gpio_pullup_t pull_up_en; /* GPIO pull-up */
gpio_pulldown_t pull_down_en; /* GPIO pull-down */
gpio_int_type_t intr_type; /* GPIO interrupt type */
} gpio_config_t;
typedef enum {
GPIO_DIR_OUTPUT_ONLY, /* GPIO output */
GPIO_DIR_INPUT_ONLY, /* GPIO input */
GPIO_DIR_INPUT_AND_OUTPUT, /* GPIO input + output */
GPIO_DIR_DISABLE_IO, /* GPIO disable */
} gpio_direction_t;
typedef enum {
GPIO_LOW_LEVEL = 0,
GPIO_HIGH_LEVEL = 1,
GPIO_LEVEL_ERR,
} gpio_level_t;
typedef enum {
GPIO_PULLUP_ONLY, /* Pad pull up */
GPIO_PULLDOWN_ONLY, /* Pad pull down */
GPIO_PULLUP_PULLDOWN, /* Pad pull up + pull down*/
GPIO_FLOATING, /* Pad floating */
} gpio_pull_mode_t;
typedef void (*gpio_event_callback)(gpio_num_t gpio_intr_num);
/** \defgroup Driver_APIs Driver APIs
* @brief Driver APIs
*/
/** @addtogroup Driver_APIs
* @{
*/
/** \defgroup GPIO_Driver_APIs GPIO Driver APIs
* @brief GPIO APIs
*/
/** @addtogroup GPIO_Driver_APIs
* @{
*/
/**
* @brief GPIO common configuration
*
* Use this Function ,Configure GPIO's Mode,pull-up,PullDown,IntrType
*
* @parameter[in] pGPIOConfig
* pGPIOConfig.pin_bit_mask : Configure GPIO pins bits,set this parameter with bit mask.
* If you want to configure GPIO34 and GPIO16, pin_bit_mask=GPIO_Pin_16|GPIO_Pin_34;
* pGPIOConfig.mode : Configure GPIO mode,such as output ,input...
* pGPIOConfig.pull_up_en : Enable or Disable pull-up
* pGPIOConfig.pull_down_en : Enable or Disable pull-down
* pGPIOConfig.intr_type : Configure GPIO interrupt trigger type
* @return ESP_OK: success ;
* ESP_ERR_INVALID_ARG: parameters error
* ESP_FAIL : GPIO mutex error
*
*/
esp_err_t gpio_config(gpio_config_t *pGPIOConfig);
/**
* @brief GPIO set output level
*
* @parameter[in] gpio_num : GPIO number.
* If you want to set output level of GPIO16, gpio_num should be GPIO_NUM_16 (16);
* @parameter[in] level : Output level. 0: low ; 1: high
*
* @return ESP_OK : success
* ESP_FAIL : GPIO mutex error
*
*/
esp_err_t gpio_set_level(gpio_num_t gpio_num, uint32_t level);
/**
* @brief GPIO get input level
*
* @parameter[in] gpio_num : GPIO number.
* If you want to get level of pin GPIO16, gpio_num should be GPIO_NUM_16 (16);
*
* @return 0 : the GPIO input level is 0
* 1 : the GPIO input level is 1
*
*/
int gpio_get_level(gpio_num_t gpio_num);
/**
* @brief GPIO set direction
*
* Configure GPIO direction,such as output_only,input_only,output_and_input
*
* @parameter[in] gpio_num : Configure GPIO pins number,it should GPIO number.
* If you want to set direction of GPIO16, gpio_num should be GPIO_NUM_16 (16);
* @parameter[in] direction: Configure GPIO direction,such as output_only,input_only,...
*
* @return ESP_OK : success
* ESP_ERR_INVALID_ARG : fail
* ESP_FAIL : GPIO mutex error
*
*/
esp_err_t gpio_set_direction(gpio_num_t gpio_num, gpio_direction_t direction);
/**
* @brief GPIO set pull
*
* User this Function,configure GPIO pull mode,such as pull-up,pull-down
*
* @parameter[in] gpio_num : Configure GPIO pins number,it should GPIO number.
* If you want to set pull up or down mode for GPIO16,gpio_num should be GPIO_NUM_16 (16);
* @parameter[in] pull : Configure GPIO pull up/down mode,such as pullup_only,pulldown_only,pullup_and_pulldown,...
*
* @return ESP_OK : success
* ESP_ERR_INVALID_ARG : fail
* ESP_FAIL : GPIO mutex error
*
*/
esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull);
/**
* @brief bind input signal to the GPIO
*
* bind input signal to the GPIO,when you want to bind the signal to the GPIO
* First , configure the pad as GPIO,use the gpio_config function or pin_func_as_gpio function
* Second , enable the GPIO input,if you use pin_func_as_gpio,you can use gpio_set_direction function
* Third , call gpio_matrix_in function
*
* @parameter[in] GPIO : Configure GPIO pins number,it should GPIO number.
* If you want to configure GPIO16, gpio_num should be GPIO_NUM_16 (16);
* @parameter[in] signal_idx : the signal_idx,find the signal index from gpio_sig_map.h
*
* @parameter[in] inverse : the signal input inverse, default inverse=0
*
* @return None
*
*/
void gpio_matrix_in(uint32_t GPIO, uint32_t signal_idx, bool inverse) ROMFN_ATTR;
/**
* @brief bind output signal to the GPIO
*
* bind output signal to the GPIO,when you want to bind the signal to the GPIO
* First , configure the pad as GPIO,use the gpio_config function or pin_func_as_gpio function
* Second , enable the GPIO output,if you use pin_func_as_gpio,you can use gpio_set_direction function
* Third , call gpio_matrix_out function
*
* @parameter[in] GPIO : Configure GPIO pins number,it should GPIO number.
* If you want to configure GPIO16,gpio_num should be GPIO_NUM_16 (16);
* @parameter[in] signal_idx : the signal_idx,find the signal index from gpio_sig_map.h
*
* @parameter[in] out_inv : the signal output inverse, default out_inv=0
*
* @parameter[in] oen_inv : the signal output enable inverse, default oen_inv=0
*
* @return None
*
*/
void gpio_matrix_out(uint32_t GPIO, uint32_t signal_idx, bool out_inv, bool oen_inv) ROMFN_ATTR;
/**
* @brief register GPIO interrupt handler, the handler is an ISR.
* The handler will be attached to the same CPU core that this function is running on.
* Users should know that which CPU is running and then pick a INUM that is not used by system.
* We can find the information of INUM and interrupt level in soc.h.
* TODO: to move INUM options to menu_config
* @parameter uint8_t gpio_intr_num : GPIO interrupt number,check the info in soc.h, and please see the core-isa.h for more details
* @parameter void (* fn)(void* ) : interrupt handler function.
* Note that the handler function MUST be defined with attribution of "IRAM_ATTR".
* @parameter void * arg : parameter for handler function
*
* @return ESP_OK : success ;
* ESP_FAIL: gpio_mutex error
*/
esp_err_t gpio_intr_handler_register(uint8_t gpio_intr_num, void (*fn)(void*), void * arg);
/*----------EXAMPLE TO CONIFGURE GPIO AS OUTPUT ------------ */
/* gpio_config_t io_conf;
* io_conf.intr_type = GPIO_PIN_INTR_DISABLE; //disable interrupt
* io_conf.mode = GPIO_MODE_OUTPUT; //set as output mode
* io_conf.pin_bit_mask = GPIO_SEL_18 | GPIO_SEL_19; //bit mask of the pins that you want to set,e.g.GPIO18/19
* io_conf.pull_down_en = 0; //disable pull-down mode
* io_conf.pull_up_en = 0; //disable pull-up mode
* gpio_config(&io_conf); //configure GPIO with the given settings
**/
/*----------EXAMPLE TO CONIFGURE GPIO AS OUTPUT ------------ */
/* io_conf.intr_type = GPIO_PIN_INTR_POSEDGE; //set posedge interrupt
* io_conf.mode = GPIO_MODE_INPUT; //set as input
* io_conf.pin_bit_mask = GPIO_SEL_4 | GPIO_SEL_5; //bit mask of the pins that you want to set, e.g.,GPIO4/5
* io_conf.pull_down_en = 0; //disable pull-down mode
* io_conf.pull_up_en = 1; //enable pull-up mode
* gpio_config(&io_conf); //configure GPIO with the given settings
*----------EXAMPLE TO SET ISR HANDLER ----------------------*/
/* gpio_intr_handler_register(18,gpio_intr_test,NULL); //hook the isr handler for GPIO interrupt
* //the first parameter is INUM, you can pick one form interrupt level 1/2 which is not used by the system.
* //NOTE1:user should arrange the INUMs that used, better not to use a same INUM for different interrupt.
* //NOTE2:do not pick the INUM that already occupied by the system.
* //NOTE3:refer to soc.h to check which INUMs that can be used.
*-------------EXAMPLE OF HANDLER FUNCTION-------------------*/
/*#include "esp_attr.h"
* void IRAM_ATTR gpio_intr_test(void* arg)
*{
* //GPIO intr process
* ets_printf("in gpio_intr\n");
* uint32_t gpio_num = 0;
* uint32_t gpio_intr_status = READ_PERI_REG(GPIO_STATUS_REG); //read status to get interrupt status for GPIO0-31
* uint32_t gpio_intr_status_h = READ_PERI_REG(GPIO_STATUS1_REG);//read status1 to get interrupt status for GPIO32-39
* SET_PERI_REG_MASK(GPIO_STATUS_W1TC_REG, gpio_intr_status); //Clear intr for gpio0-gpio31
* SET_PERI_REG_MASK(GPIO_STATUS1_W1TC_REG, gpio_intr_status_h); //Clear intr for gpio32-39
* do {
* if(gpio_num < 32) {
* if(gpio_intr_status & BIT(gpio_num)) { //gpio0-gpio31
* ets_printf("Intr Gpio%d ,val: %d\n",gpio_num,gpio_get_level(gpio_num));
* //This is a 'isr' handler, you should post an event to process it in RTOS queue.
* }
* } else {
* if(gpio_intr_status_h & BIT(gpio_num - 32)) {
* ets_printf("Intr Gpio%d, val : %d\n",gpio_num,gpio_get_level(gpio_num));
* //This is a 'isr' handler, you should post an event to process it in RTOS queue.
* }
* }
* } while(++gpio_num < GPIO_PIN_COUNT);
*}
*----EXAMPLE OF I2C CONFIG AND PICK SIGNAL FOR IO MATRIX---*/
/* gpio_config_t io_conf;
* io_conf.intr_type = GPIO_PIN_INTR_DISABLE; //disable interrupt
* io_conf.mode = GPIO_MODE_INPUT_OUTPUT_OD; //set as output mode
* io_conf.pin_bit_mask = GPIO_SEL_21 | GPIO_SEL_22; //bit mask of the pins that you want to set,e.g.GPIO21/22
* io_conf.pull_down_en = 0; //disable pull-down mode
* io_conf.pull_up_en = 1; //enable pull-up mode
* gpio_config(&io_conf); //configure GPIO with the given settings
* gpio_matrix_out(21, EXT_I2C_SCL_O_IDX, 0, 0); //set output signal for io_matrix
* gpio_matrix_out(22, EXT_I2C_SDA_O_IDX, 0, 0); //set output signal for io_matrix
* gpio_matrix_in( 22, EXT_I2C_SDA_I_IDX, 0); //set input signal for io_matrix
*
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* _DRIVER_GPIO_H_ */

22
components/esp32/include/soc/gpio_reg.h
View file

@ -280,6 +280,28 @@
#define GPIO_SDIO_INT_H_V 0xFF
#define GPIO_SDIO_INT_H_S 0
#define GPIO_REG(io_num) (GPIO_PIN0_REG + (io_num)*0x4)
#define GPIO_PIN_INT_ENA 0x0000001F
#define GPIO_PIN_INT_ENA_M ((GPIO_PIN_INT_ENA_V)<<(GPIO_PIN_INT_ENA_S))
#define GPIO_PIN_INT_ENA_V 0x0000001F
#define GPIO_PIN_INT_ENA_S 13
#define GPIO_PIN_CONFIG 0x00000003
#define GPIO_PIN_CONFIG_M ((GPIO_PIN_CONFIG_V)<<(GPIO_PIN_CONFIG_S))
#define GPIO_PIN_CONFIG_V 0x00000003
#define GPIO_PIN_CONFIG_S 11
#define GPIO_PIN_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN_WAKEUP_ENABLE_M (BIT(10))
#define GPIO_PIN_WAKEUP_ENABLE_V 0x1
#define GPIO_PIN_WAKEUP_ENABLE_S 10
#define GPIO_PIN_INT_TYPE 0x00000007
#define GPIO_PIN_INT_TYPE_M ((GPIO_PIN_INT_TYPE_V)<<(GPIO_PIN_INT_TYPE_S))
#define GPIO_PIN_INT_TYPE_V 0x00000007
#define GPIO_PIN_INT_TYPE_S 7
#define GPIO_PIN_PAD_DRIVER (BIT(2))
#define GPIO_PIN_PAD_DRIVER_M (BIT(2))
#define GPIO_PIN_PAD_DRIVER_V 0x1
#define GPIO_PIN_PAD_DRIVER_S 2
#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x0088)
/* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt

8
components/esp32/include/soc/gpio_sd_struct.h
View file

@ -21,28 +21,28 @@ typedef volatile struct {
uint32_t reserved16: 16;
};
uint32_t val;
}channel[8];
} channel[8];
union {
struct {
uint32_t reserved0: 31;
uint32_t clk_en: 1;
};
uint32_t val;
}cg;
} cg;
union {
struct {
uint32_t reserved0: 31;
uint32_t spi_swap: 1;
};
uint32_t val;
}misc;
} misc;
union {
struct {
uint32_t date: 28;
uint32_t reserved28: 4;
};
uint32_t val;
}version;
} version;
} gpio_sd_dev_t;
extern gpio_sd_dev_t SIGMADELTA;
#endif /* _SOC_GPIO_SD_STRUCT_H_ */

46
components/esp32/include/soc/gpio_struct.h
View file

@ -24,28 +24,28 @@ typedef volatile struct {
uint32_t reserved8: 24;
};
uint32_t val;
}out1;
} out1;
union {
struct {
uint32_t data: 8; /*GPIO32~39 output value write 1 to set*/
uint32_t reserved8: 24;
};
uint32_t val;
}out1_w1ts;
} out1_w1ts;
union {
struct {
uint32_t data: 8; /*GPIO32~39 output value write 1 to clear*/
uint32_t reserved8: 24;
};
uint32_t val;
}out1_w1tc;
} out1_w1tc;
union {
struct {
uint32_t sel: 8; /*SDIO PADS on/off control from outside*/
uint32_t reserved8: 24;
};
uint32_t val;
}sdio_select;
} sdio_select;
uint32_t enable; /*GPIO0~31 output enable*/
uint32_t enable_w1ts; /*GPIO0~31 output enable write 1 to set*/
uint32_t enable_w1tc; /*GPIO0~31 output enable write 1 to clear*/
@ -55,28 +55,28 @@ typedef volatile struct {
uint32_t reserved8: 24;
};
uint32_t val;
}enable1;
} enable1;
union {
struct {
uint32_t data: 8; /*GPIO32~39 output enable write 1 to set*/
uint32_t reserved8: 24;
};
uint32_t val;
}enable1_w1ts;
} enable1_w1ts;
union {
struct {
uint32_t data: 8; /*GPIO32~39 output enable write 1 to clear*/
uint32_t reserved8: 24;
};
uint32_t val;
}enable1_w1tc;
} enable1_w1tc;
union {
struct {
uint32_t strapping: 16; /*GPIO strapping results: {2'd0 boot_sel_dig[7:1] vsdio_boot_sel boot_sel_chip[5:0]}. Boot_sel_dig[7:1]: {U0RXD SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3}. vsdio_boot_sel: MTDI. boot_sel_chip[5:0]: {GPIO0 U0TXD GPIO2 GPIO4 MTDO GPIO5}*/
uint32_t strapping: 16; /*GPIO strapping results: {2'd0 boot_sel_dig[7:1] vsdio_boot_sel boot_sel_chip[5:0]} . Boot_sel_dig[7:1]: {U0RXD SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3} . vsdio_boot_sel: MTDI. boot_sel_chip[5:0]: {GPIO0 U0TXD GPIO2 GPIO4 MTDO GPIO5} */
uint32_t reserved16:16;
};
uint32_t val;
}strap;
} strap;
uint32_t in; /*GPIO0~31 input value*/
union {
struct {
@ -84,7 +84,7 @@ typedef volatile struct {
uint32_t reserved8: 24;
};
uint32_t val;
}in1;
} in1;
uint32_t status; /*GPIO0~31 interrupt status*/
uint32_t status_w1ts; /*GPIO0~31 interrupt status write 1 to set*/
uint32_t status_w1tc; /*GPIO0~31 interrupt status write 1 to clear*/
@ -94,21 +94,21 @@ typedef volatile struct {
uint32_t reserved8: 24;
};
uint32_t val;
}status1;
} status1;
union {
struct {
uint32_t intr_st: 8; /*GPIO32~39 interrupt status write 1 to set*/
uint32_t reserved8: 24;
};
uint32_t val;
}status1_w1ts;
} status1_w1ts;
union {
struct {
uint32_t intr_st: 8; /*GPIO32~39 interrupt status write 1 to clear*/
uint32_t reserved8: 24;
};
uint32_t val;
}status1_w1tc;
} status1_w1tc;
uint32_t reserved_5c;
uint32_t acpu_int; /*GPIO0~31 APP CPU interrupt status*/
uint32_t acpu_nmi_int; /*GPIO0~31 APP CPU non-maskable interrupt status*/
@ -121,35 +121,35 @@ typedef volatile struct {
uint32_t reserved8: 24;
};
uint32_t val;
}acpu_int1;
} acpu_int1;
union {
struct {
uint32_t intr: 8; /*GPIO32~39 APP CPU non-maskable interrupt status*/
uint32_t reserved8: 24;
};
uint32_t val;
}acpu_nmi_int1;
} acpu_nmi_int1;
union {
struct {
uint32_t intr: 8; /*GPIO32~39 PRO CPU interrupt status*/
uint32_t reserved8: 24;
};
uint32_t val;
}pcpu_int1;
} pcpu_int1;
union {
struct {
uint32_t intr: 8; /*GPIO32~39 PRO CPU non-maskable interrupt status*/
uint32_t reserved8: 24;
};
uint32_t val;
}pcpu_nmi_int1;
} pcpu_nmi_int1;
union {
struct {
uint32_t intr: 8; /*SDIO's extent GPIO32~39 interrupt*/
uint32_t reserved8: 24;
};
uint32_t val;
}cpusdio_int1;
} cpusdio_int1;
union {
struct {
uint32_t reserved0: 2;
@ -162,7 +162,7 @@ typedef volatile struct {
uint32_t reserved18: 14;
};
uint32_t val;
}pin[40];
} pin[40];
union {
struct {
uint32_t rtc_max: 10;
@ -170,7 +170,7 @@ typedef volatile struct {
uint32_t start: 1;
};
uint32_t val;
}cali_conf;
} cali_conf;
union {
struct {
uint32_t value_sync2: 20;
@ -179,7 +179,7 @@ typedef volatile struct {
uint32_t rdy_sync2: 1;
};
uint32_t val;
}cali_data;
} cali_data;
union {
struct {
uint32_t func_sel: 6; /*select one of the 256 inputs*/
@ -188,7 +188,7 @@ typedef volatile struct {
uint32_t reserved8: 24; /*The 256 registers below are selection control for 256 input signals connected to GPIO matrix's 40 GPIO input if GPIO_FUNCx_IN_SEL is set to n(0<=n<40): it means GPIOn input is used for input signal x if GPIO_FUNCx_IN_SEL is set to 0x38: the input signal x is set to 1 if GPIO_FUNCx_IN_SEL is set to 0x30: the input signal x is set to 0*/
};
uint32_t val;
}func_in_sel_cfg[256];
} func_in_sel_cfg[256];
union {
struct {
uint32_t func_sel: 9; /*select one of the 256 output to 40 GPIO*/
@ -198,7 +198,7 @@ typedef volatile struct {
uint32_t reserved12: 20; /*The 40 registers below are selection control for 40 GPIO output if GPIO_FUNCx_OUT_SEL is set to n(0<=n<256): it means GPIOn input is used for output signal x if GPIO_FUNCx_OUT_INV_SEL is set to 1 the output signal x is set to ~value. if GPIO_FUNC0_OUT_SEL is 256 or GPIO_FUNC0_OEN_SEL is 1 using GPIO_ENABLE_DATA[x] for the enable value else using the signal enable*/
};
uint32_t val;
}func_out_sel_cfg[40];
} func_out_sel_cfg[40];
} gpio_dev_t;
extern gpio_dev_t GPIO;
#endif /* _SOC_GPIO_STRUCT_H_ */

44
components/esp32/include/soc/i2c_struct.h
View file

@ -20,7 +20,7 @@ typedef volatile struct {
uint32_t reserved14: 18;
};
uint32_t val;
}scl_low_period;
} scl_low_period;
union {
struct {
uint32_t sda_force_out: 1; /*1：normally output sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/
@ -35,7 +35,7 @@ typedef volatile struct {
uint32_t reserved9: 23;
};
uint32_t val;
}ctr;
} ctr;
union {
struct {
uint32_t ack_rec: 1; /*This register stores the value of ACK bit.*/
@ -55,14 +55,14 @@ typedef volatile struct {
uint32_t reserved31: 1;
};
uint32_t val;
}status_reg;
} status_reg;
union {
struct {
uint32_t tout: 20; /*This register is used to configure the max clock number of receiving a data.*/
uint32_t reserved20:12;
};
uint32_t val;
}timeout;
} timeout;
union {
struct {
uint32_t addr: 15; /*when configured as i2c slave this register is used to configure slave's address.*/
@ -70,7 +70,7 @@ typedef volatile struct {
uint32_t en_10bit: 1; /*This register is used to enable slave 10bit address mode.*/
};
uint32_t val;
}slave_addr;
} slave_addr;
union {
struct {
uint32_t rx_fifo_start_addr: 5; /*This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.*/
@ -80,7 +80,7 @@ typedef volatile struct {
uint32_t reserved20: 12;
};
uint32_t val;
}fifo_st;
} fifo_st;
union {
struct {
uint32_t rx_fifo_full_thrhd: 5;
@ -94,14 +94,14 @@ typedef volatile struct {
uint32_t reserved26: 6;
};
uint32_t val;
}fifo_conf;
} fifo_conf;
union {
struct {
uint32_t data: 8; /*The register represent the byte data read from rx_fifo when use apb fifo access*/
uint32_t reserved8: 24;
};
uint32_t val;
}fifo_data;
} fifo_data;
union {
struct {
uint32_t rx_fifo_full: 1; /*The raw interrupt status bit for rx_fifo full when use apb fifo access.*/
@ -120,7 +120,7 @@ typedef volatile struct {
uint32_t reserved13: 19;
};
uint32_t val;
}int_raw;
} int_raw;
union {
struct {
uint32_t rx_fifo_full: 1; /*Set this bit to clear the rx_fifo_full_int interrupt.*/
@ -139,7 +139,7 @@ typedef volatile struct {
uint32_t reserved13: 19;
};
uint32_t val;
}int_clr;
} int_clr;
union {
struct {
uint32_t rx_fifo_full: 1; /*The enable bit for rx_fifo_full_int interrupt.*/
@ -158,7 +158,7 @@ typedef volatile struct {
uint32_t reserved13: 19;
};
uint32_t val;
}int_ena;
} int_ena;
union {
struct {
uint32_t rx_fifo_full: 1; /*The masked interrupt status for rx_fifo_full_int interrupt.*/
@ -177,28 +177,28 @@ typedef volatile struct {
uint32_t reserved13: 19;
};
uint32_t val;
}int_status;
} int_status;
union {
struct {
uint32_t time: 10; /*This register is used to configure the clock num I2C used to hold the data after the negedge of SCL.*/
uint32_t reserved10: 22;
};
uint32_t val;
}sda_hold;
} sda_hold;
union {
struct {
uint32_t time: 10; /*This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL*/
uint32_t reserved10: 22;
};
uint32_t val;
}sda_sample;
} sda_sample;
union {
struct {
uint32_t period: 14; /*This register is used to configure the clock num during SCL is low level.*/
uint32_t reserved14: 18;
};
uint32_t val;
}scl_high_period;
} scl_high_period;
uint32_t reserved_3c;
union {
struct {
@ -206,28 +206,28 @@ typedef volatile struct {
uint32_t reserved10: 22;
};
uint32_t val;
}scl_start_hold;
} scl_start_hold;
union {
struct {
uint32_t time: 10; /*This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark.*/
uint32_t reserved10: 22;
};
uint32_t val;
}scl_rstart_setup;
} scl_rstart_setup;
union {
struct {
uint32_t time: 14; /*This register is used to configure the clock num after the STOP bit's posedge.*/
uint32_t reserved14: 18;
};
uint32_t val;
}scl_stop_hold;
} scl_stop_hold;
union {
struct {
uint32_t time: 10; /*This register is used to configure the clock num between the posedge of SCL and the posedge of SDA.*/
uint32_t reserved10: 22;
};
uint32_t val;
}scl_stop_setup;
} scl_stop_setup;
union {
struct {
uint32_t thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/
@ -235,7 +235,7 @@ typedef volatile struct {
uint32_t reserved4: 28;
};
uint32_t val;
}scl_filter_cfg;
} scl_filter_cfg;
union {
struct {
uint32_t thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/
@ -243,7 +243,7 @@ typedef volatile struct {
uint32_t reserved4: 28;
};
uint32_t val;
}sda_filter_cfg;
} sda_filter_cfg;
union {
struct {
uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/
@ -255,7 +255,7 @@ typedef volatile struct {
uint32_t done: 1; /*When command0 is done in I2C Master mode this bit changes to high level.*/
};
uint32_t val;
}command[16];
} command[16];
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;

62
components/esp32/include/soc/i2s_struct.h
View file

@ -40,7 +40,7 @@ typedef volatile struct {
uint32_t reserved19: 13;
};
uint32_t val;
}conf;
} conf;
union {
struct {
uint32_t rx_take_data: 1;
@ -63,7 +63,7 @@ typedef volatile struct {
uint32_t reserved17: 15;
};
uint32_t val;
}int_raw;
} int_raw;
union {
struct {
uint32_t rx_take_data: 1;
@ -86,7 +86,7 @@ typedef volatile struct {
uint32_t reserved17: 15;
};
uint32_t val;
}int_st;
} int_st;
union {
struct {
uint32_t rx_take_data: 1;
@ -109,7 +109,7 @@ typedef volatile struct {
uint32_t reserved17: 15;
};
uint32_t val;
}int_ena;
} int_ena;
union {
struct {
uint32_t take_data: 1;
@ -132,7 +132,7 @@ typedef volatile struct {
uint32_t reserved17: 15;
};
uint32_t val;
}int_clr;
} int_clr;
union {
struct {
uint32_t tx_bck_in_delay: 2;
@ -152,7 +152,7 @@ typedef volatile struct {
uint32_t reserved25: 7;
};
uint32_t val;
}timing;
} timing;
union {
struct {
uint32_t rx_data_num: 6;
@ -165,7 +165,7 @@ typedef volatile struct {
uint32_t reserved21: 11;
};
uint32_t val;
}fifo_conf;
} fifo_conf;
uint32_t rx_eof_num;
uint32_t conf_single_data;
union {
@ -175,7 +175,7 @@ typedef volatile struct {
uint32_t reserved5: 27;
};
uint32_t val;
}conf_chan;
} conf_chan;
union {
struct {
uint32_t addr: 20;
@ -186,7 +186,7 @@ typedef volatile struct {
uint32_t park: 1;
};
uint32_t val;
}out_link;
} out_link;
union {
struct {
uint32_t addr: 20;
@ -197,7 +197,7 @@ typedef volatile struct {
uint32_t park: 1;
};
uint32_t val;
}in_link;
} in_link;
uint32_t out_eof_des_addr;
uint32_t in_eof_des_addr;
uint32_t out_eof_bfr_des_addr;
@ -209,7 +209,7 @@ typedef volatile struct {
uint32_t reserved6: 26;
};
uint32_t val;
}ahb_test;
} ahb_test;
uint32_t in_link_dscr;
uint32_t in_link_dscr_bf0;
uint32_t in_link_dscr_bf1;
@ -235,7 +235,7 @@ typedef volatile struct {
uint32_t reserved14: 18;
};
uint32_t val;
}lc_conf;
} lc_conf;
union {
struct {
uint32_t wdata: 9;
@ -244,7 +244,7 @@ typedef volatile struct {
uint32_t reserved17: 15;
};
uint32_t val;
}out_fifo_push;
} out_fifo_push;
union {
struct {
uint32_t rdata: 12;
@ -253,7 +253,7 @@ typedef volatile struct {
uint32_t reserved17: 15;
};
uint32_t val;
}in_fifo_pop;
} in_fifo_pop;
uint32_t lc_state0;
uint32_t lc_state1;
union {
@ -264,7 +264,7 @@ typedef volatile struct {
uint32_t reserved12: 20;
};
uint32_t val;
}lc_hung_conf;
} lc_hung_conf;
uint32_t reserved_78;
uint32_t reserved_7c;
union {
@ -273,14 +273,14 @@ typedef volatile struct {
uint32_t y_min:16;
};
uint32_t val;
}cvsd_conf0;
} cvsd_conf0;
union {
struct {
uint32_t sigma_max:16;
uint32_t sigma_min:16;
};
uint32_t val;
}cvsd_conf1;
} cvsd_conf1;
union {
struct {
uint32_t cvsd_k: 3;
@ -290,7 +290,7 @@ typedef volatile struct {
uint32_t reserved19:13;
};
uint32_t val;
}cvsd_conf2;
} cvsd_conf2;
union {
struct {
uint32_t good_pack_max: 6;
@ -302,7 +302,7 @@ typedef volatile struct {
uint32_t reserved28: 4;
};
uint32_t val;
}plc_conf0;
} plc_conf0;
union {
struct {
uint32_t bad_cef_atten_para: 8;
@ -312,7 +312,7 @@ typedef volatile struct {
uint32_t slide_win_len: 8;
};
uint32_t val;
}plc_conf1;
} plc_conf1;
union {
struct {
uint32_t cvsd_seg_mod: 2;
@ -320,7 +320,7 @@ typedef volatile struct {
uint32_t reserved7: 25;
};
uint32_t val;
}plc_conf2;
} plc_conf2;
union {
struct {
uint32_t en: 1;
@ -335,7 +335,7 @@ typedef volatile struct {
uint32_t reserved13: 19;
};
uint32_t val;
}esco_conf0;
} esco_conf0;
union {
struct {
uint32_t with_en: 1;
@ -345,7 +345,7 @@ typedef volatile struct {
uint32_t reserved4: 28;
};
uint32_t val;
}sco_conf0;
} sco_conf0;
union {
struct {
uint32_t tx_pcm_conf: 3;
@ -357,7 +357,7 @@ typedef volatile struct {
uint32_t reserved10: 22;
};
uint32_t val;
}conf1;
} conf1;
union {
struct {
uint32_t fifo_force_pd: 1;
@ -367,7 +367,7 @@ typedef volatile struct {
uint32_t reserved4: 28;
};
uint32_t val;
}pd_conf;
} pd_conf;
union {
struct {
uint32_t camera_en: 1;
@ -381,7 +381,7 @@ typedef volatile struct {
uint32_t reserved8: 24;
};
uint32_t val;
}conf2;
} conf2;
union {
struct {
uint32_t clkm_div_num: 8;
@ -392,7 +392,7 @@ typedef volatile struct {
uint32_t reserved22: 10;
};
uint32_t val;
}clkm_conf;
} clkm_conf;
union {
struct {
uint32_t tx_bck_div_num: 6;
@ -402,7 +402,7 @@ typedef volatile struct {
uint32_t reserved24: 8;
};
uint32_t val;
}sample_rate_conf;
} sample_rate_conf;
union {
struct {
uint32_t tx_pdm_en: 1;
@ -420,7 +420,7 @@ typedef volatile struct {
uint32_t reserved26: 6;
};
uint32_t val;
}pdm_conf;
} pdm_conf;
union {
struct {
uint32_t tx_pdm_fs: 10;
@ -428,7 +428,7 @@ typedef volatile struct {
uint32_t reserved20:12;
};
uint32_t val;
}pdm_freq_conf;
} pdm_freq_conf;
union {
struct {
uint32_t tx_idle: 1;
@ -437,7 +437,7 @@ typedef volatile struct {
uint32_t reserved3: 29;
};
uint32_t val;
}state;
} state;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;

46
components/esp32/include/soc/ledc_struct.h
View file

@ -24,21 +24,21 @@ typedef volatile struct {
uint32_t clk_en: 1; /*This bit is clock gating control signal. when software configure LED_PWM internal registers it controls the register clock.*/
};
uint32_t val;
}conf0;
} conf0;
union {
struct {
uint32_t hpoint: 20; /*The output value changes to high when htimerx(x=[0 3]) selected by high speed channel has reached reg_hpoint_hsch0[19:0]*/
uint32_t reserved20: 12;
};
uint32_t val;
}hpoint;
} hpoint;
union {
struct {
uint32_t duty: 25; /*The register is used to control output duty. When hstimerx(x=[0 3]) chosen by high speed channel has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
uint32_t reserved25: 7;
};
uint32_t val;
}duty;
} duty;
union {
struct {
uint32_t duty_scale:10; /*This register controls the increase or decrease step scale for high speed channel.*/
@ -48,15 +48,15 @@ typedef volatile struct {
uint32_t duty_start: 1; /*When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/
};
uint32_t val;
}conf1;
} conf1;
union {
struct {
uint32_t duty_read: 25; /*This register represents the current duty of the output signal for high speed channel.*/
uint32_t reserved25: 7;
};
uint32_t val;
}duty_rd;
}high_speed_channel[8];
} duty_rd;
} high_speed_channel[8];
struct{
union {
struct {
@ -67,21 +67,21 @@ typedef volatile struct {
uint32_t reserved5: 27;
};
uint32_t val;
}conf0;
} conf0;
union {
struct {
uint32_t hpoint: 20; /*The output value changes to high when lstimerx(x=[0 3]) selected by low speed channel has reached reg_hpoint_lsch0[19:0]*/
uint32_t reserved20: 12;
};
uint32_t val;
}hpoint;
} hpoint;
union {
struct {
uint32_t duty: 25; /*The register is used to control output duty. When lstimerx(x=[0 3]) choosed by low speed channel has reached reg_lpoint_lsch0 the output signal changes to low. reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4]) (1) reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
uint32_t reserved25: 7;
};
uint32_t val;
}duty;
} duty;
union {
struct {
uint32_t duty_scale:10; /*This register controls the increase or decrease step scale for low speed channel.*/
@ -91,15 +91,15 @@ typedef volatile struct {
uint32_t duty_start: 1; /*When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/
};
uint32_t val;
}conf1;
} conf1;
union {
struct {
uint32_t duty_read: 25; /*This register represents the current duty of the output signal for low speed channel.*/
uint32_t reserved25: 7;
};
uint32_t val;
}duty_r;
}low_speed_channel[8];
} duty_r;
} low_speed_channel[8];
struct{
union {
struct {
@ -111,15 +111,15 @@ typedef volatile struct {
uint32_t reserved26: 6;
};
uint32_t val;
}conf;
} conf;
union {
struct {
uint32_t timer_cnt: 20; /*software can read this register to get the current counter value in high speed timer*/
uint32_t reserved20: 12;
};
uint32_t val;
}value;
}high_speed_timer[4];
} value;
} high_speed_timer[4];
struct{
union {
struct {
@ -132,15 +132,15 @@ typedef volatile struct {
uint32_t reserved27: 5;
};
uint32_t val;
}conf;
} conf;
union {
struct {
uint32_t timer_cnt: 20; /*software can read this register to get the current counter value in low speed timer.*/
uint32_t reserved20: 12;
};
uint32_t val;
}value;
}low_speed_timer[4];
} value;
} low_speed_timer[4];
union {
struct {
uint32_t hstimer0_ovf: 1; /*The interrupt raw bit for high speed channel0 counter overflow.*/
@ -170,7 +170,7 @@ typedef volatile struct {
uint32_t reserved24: 8;
};
uint32_t val;
}int_raw;
} int_raw;
union {
struct {
uint32_t hstimer0_ovf: 1; /*The interrupt status bit for high speed channel0 counter overflow event.*/
@ -199,7 +199,7 @@ typedef volatile struct {
uint32_t reserved24: 8;
};
uint32_t val;
}int_st;
} int_st;
union {
struct {
uint32_t hstimer0_ovf: 1; /*The interrupt enable bit for high speed channel0 counter overflow interrupt.*/
@ -229,7 +229,7 @@ typedef volatile struct {
uint32_t reserved24: 8;
};
uint32_t val;
}int_ena;
} int_ena;
union {
struct {
uint32_t hstimer0_ovf: 1; /*Set this bit to clear high speed channel0 counter overflow interrupt.*/
@ -259,14 +259,14 @@ typedef volatile struct {
uint32_t reserved24: 8;
};
uint32_t val;
}int_clr;
} int_clr;
union {
struct {
uint32_t apb_clk_sel: 1; /*This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz*/
uint32_t reserved1: 31;
};
uint32_t val;
}conf;
} conf;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;

20
components/esp32/include/soc/pcnt_struct.h
View file

@ -34,29 +34,29 @@ typedef volatile struct {
uint32_t ch1_lctrl_mode: 2; /*This register is used to control the mode of channel1's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/
};
uint32_t val;
}conf0;
} conf0;
union {
struct {
uint32_t cnt_thres0:16; /*This register is used to configure thres0 value for unit0.*/
uint32_t cnt_thres1:16; /*This register is used to configure thres1 value for unit0.*/
};
uint32_t val;
}conf1;
} conf1;
union {
struct {
uint32_t cnt_h_lim:16; /*This register is used to configure thr_h_lim value for unit0.*/
uint32_t cnt_l_lim:16; /*This register is used to configure thr_l_lim value for unit0.*/
};
uint32_t val;
}conf2;
}conf_unit[8];
} conf2;
} conf_unit[8];
union {
struct {
uint32_t cnt_val : 16; /*This register stores the current pulse count value for unit0.*/
uint32_t reserved16: 16;
};
uint32_t val;
}cnt_unit[8];
} cnt_unit[8];
union {
struct {
uint32_t cnt_thr_event_u0: 1; /*This is the interrupt raw bit for channel0 event.*/
@ -70,7 +70,7 @@ typedef volatile struct {
uint32_t reserved8: 24;
};
uint32_t val;
}int_raw;
} int_raw;
union {
struct {
uint32_t cnt_thr_event_u0: 1; /*This is the interrupt status bit for channel0 event.*/
@ -84,7 +84,7 @@ typedef volatile struct {
uint32_t reserved8: 24;
};
uint32_t val;
}int_st;
} int_st;
union {
struct {
uint32_t cnt_thr_event_u0: 1; /*This is the interrupt enable bit for channel0 event.*/
@ -98,7 +98,7 @@ typedef volatile struct {
uint32_t reserved8: 24;
};
uint32_t val;
}int_ena;
} int_ena;
union {
struct {
uint32_t cnt_thr_event_u0: 1; /*Set this bit to clear channel0 event interrupt.*/
@ -112,7 +112,7 @@ typedef volatile struct {
uint32_t reserved8: 24;
};
uint32_t val;
}int_clr;
} int_clr;
uint32_t status_unit[8];
union {
struct {
@ -136,7 +136,7 @@ typedef volatile struct {
uint32_t reserved17: 15;
};
uint32_t val;
}ctrl;
} ctrl;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;

20
components/esp32/include/soc/rmt_struct.h
View file

@ -27,7 +27,7 @@ typedef volatile struct {
uint32_t clk_en: 1; /*This bit is used to control clock.when software configure RMT internal registers it controls the register clock.*/
};
uint32_t val;
}conf0;
} conf0;
union {
struct {
uint32_t tx_start: 1; /*Set this bit to start sending data for channel0-7.*/
@ -46,8 +46,8 @@ typedef volatile struct {
uint32_t reserved20: 12;
};
uint32_t val;
}conf1;
}conf_ch[8];
} conf1;
} conf_ch[8];
uint32_t status_ch[8]; /*The status for channel0-7*/
uint32_t apb_mem_addr_ch[8]; /*The ram relative address in channel0-7 by apb fifo access*/
union {
@ -86,7 +86,7 @@ typedef volatile struct {
uint32_t ch7_tx_thr_event: 1; /*The interrupt raw bit for channel 7 turns to high level when transmitter in channel7 have send data more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old data with new data.*/
};
uint32_t val;
}int_raw;
} int_raw;
union {
struct {
uint32_t ch0_tx_end: 1; /*The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0.*/
@ -123,7 +123,7 @@ typedef volatile struct {
uint32_t ch7_tx_thr_event: 1; /*The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw when mt_ch7_tx_thr_event_int_ena is set to 1.*/
};
uint32_t val;
}int_st;
} int_st;
union {
struct {
uint32_t ch0_tx_end: 1; /*Set this bit to enable rmt_ch0_tx_end_int_st.*/
@ -160,7 +160,7 @@ typedef volatile struct {
uint32_t ch7_tx_thr_event: 1; /*Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/
};
uint32_t val;
}int_ena;
} int_ena;
union {
struct {
uint32_t ch0_tx_end: 1; /*Set this bit to clear the rmt_ch0_rx_end_int_raw..*/
@ -197,21 +197,21 @@ typedef volatile struct {
uint32_t ch7_tx_thr_event: 1; /*Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/
};
uint32_t val;
}int_clr;
} int_clr;
union {
struct {
uint32_t low: 16; /*This register is used to configure carrier wave's low level value for channel0-7.*/
uint32_t high:16; /*This register is used to configure carrier wave's high level value for channel0-7.*/
};
uint32_t val;
}carrier_duty_ch[8];
} carrier_duty_ch[8];
union {
struct {
uint32_t limit: 9; /*When channel0-7 sends more than reg_rmt_tx_lim_ch0 data then channel0-7 produce the relative interrupt.*/
uint32_t reserved9: 23;
};
uint32_t val;
}tx_lim_ch[8];
} tx_lim_ch[8];
union {
struct {
uint32_t fifo_mask: 1; /*Set this bit to disable apb fifo access*/
@ -219,7 +219,7 @@ typedef volatile struct {
uint32_t reserved2: 30;
};
uint32_t val;
}apb_conf;
} apb_conf;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t date; /*This is the version register.*/

76
components/esp32/include/soc/spi_struct.h
View file

@ -35,14 +35,14 @@ typedef volatile struct {
uint32_t flash_read: 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
};
uint32_t val;
}cmd;
} cmd;
union {
struct {
uint32_t reserved : 8;
uint32_t usr_addr_value:24; /*[31:8]:address to slave [7:0]:Reserved.*/
};
uint32_t val;
}addr;
} addr;
union {
struct {
uint32_t reserved0: 10; /*reserved*/
@ -63,7 +63,7 @@ typedef volatile struct {
uint32_t reserved27: 5; /*reserved*/
};
uint32_t val;
}ctrl;
} ctrl;
union {
struct {
uint32_t reserved0: 16; /*reserved*/
@ -71,7 +71,7 @@ typedef volatile struct {
uint32_t cs_hold_delay: 4; /*SPI cs signal is delayed by spi clock cycles*/
};
uint32_t val;
}ctrl1;
} ctrl1;
union {
struct {
uint32_t status: 16; /*In the slave mode, it is the status for master to read out.*/
@ -79,7 +79,7 @@ typedef volatile struct {
uint32_t status_ext: 8; /*In the slave mode,it is the status for master to read out.*/
};
uint32_t val;
}rd_status;
} rd_status;
union {
struct {
uint32_t setup_time: 4; /*(cycles-1) of ,prepare, phase by spi clock, this bits combined with spi_cs_setup bit.*/
@ -94,7 +94,7 @@ typedef volatile struct {
uint32_t cs_delay_num: 4; /*spi_cs signal is delayed by system clock cycles*/
};
uint32_t val;
}ctrl2;
} ctrl2;
union {
struct {
uint32_t clkcnt_l: 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0.*/
@ -104,7 +104,7 @@ typedef volatile struct {
uint32_t clk_equ_sysclk: 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock.*/
};
uint32_t val;
}clock;
} clock;
union {
struct {
uint32_t doutdin: 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable.*/
@ -138,7 +138,7 @@ typedef volatile struct {
uint32_t usr_command: 1; /*This bit enable the command phase of an operation.*/
};
uint32_t val;
}user;
} user;
union {
struct {
uint32_t usr_dummy_cyclelen: 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
@ -146,7 +146,7 @@ typedef volatile struct {
uint32_t usr_addr_bitlen: 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/
};
uint32_t val;
}user1;
} user1;
union {
struct {
uint32_t usr_command_value: 16; /*The value of command.*/
@ -154,21 +154,21 @@ typedef volatile struct {
uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/
};
uint32_t val;
}user2;
} user2;
union {
struct {
uint32_t usr_mosi_dbitlen:24; /*The length in bits of write-data. The register value shall be (bit_num-1).*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
}mosi_dlen;
} mosi_dlen;
union {
struct {
uint32_t usr_miso_dbitlen:24; /*The length in bits of read-data. The register value shall be (bit_num-1).*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
}miso_dlen;
} miso_dlen;
uint32_t slv_wr_status; /*In the slave mode this register are the status register for the master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.*/
union {
struct {
@ -185,7 +185,7 @@ typedef volatile struct {
uint32_t reserved31: 1; /*reserved*/
};
uint32_t val;
}pin;
} pin;
union {
struct {
uint32_t rd_buf_done: 1; /*The interrupt raw bit for the completion of read-buffer operation in the slave mode.*/
@ -206,7 +206,7 @@ typedef volatile struct {
uint32_t sync_reset: 1; /*Software reset enable, reset the spi clock line cs line and data lines.*/
};
uint32_t val;
}slave;
} slave;
union {
struct {
uint32_t rdbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-buffer operations.*/
@ -221,7 +221,7 @@ typedef volatile struct {
uint32_t status_bitlen: 5; /*In the slave mode it is the length of status bit.*/
};
uint32_t val;
}slave1;
} slave1;
union {
struct {
uint32_t rdsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1).*/
@ -230,7 +230,7 @@ typedef volatile struct {
uint32_t wrbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1).*/
};
uint32_t val;
}slave2;
} slave2;
union {
struct {
uint32_t rdbuf_cmd_value: 8; /*In the slave mode it is the value of read-buffer command.*/
@ -239,21 +239,21 @@ typedef volatile struct {
uint32_t wrsta_cmd_value: 8; /*In the slave mode it is the value of write-status command.*/
};
uint32_t val;
}slave3;
} slave3;
union {
struct {
uint32_t bit_len: 24; /*In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1).*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
}slv_wrbuf_dlen;
} slv_wrbuf_dlen;
union {
struct {
uint32_t bit_len: 24; /*In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1).*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
}slv_rdbuf_dlen;
} slv_rdbuf_dlen;
union {
struct {
uint32_t req_en: 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/
@ -263,7 +263,7 @@ typedef volatile struct {
uint32_t reserved4: 28; /*reserved*/
};
uint32_t val;
}cache_fctrl;
} cache_fctrl;
union {
struct {
uint32_t reserved0: 1; /*reserved*/
@ -279,7 +279,7 @@ typedef volatile struct {
uint32_t reserved29: 3; /*reserved*/
};
uint32_t val;
}cache_sctrl;
} cache_sctrl;
union {
struct {
uint32_t dio: 1; /*For SPI0 SRAM DIO mode enable . SRAM DIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/
@ -289,7 +289,7 @@ typedef volatile struct {
uint32_t reserved5:27; /*reserved*/
};
uint32_t val;
}sram_cmd;
} sram_cmd;
union {
struct {
uint32_t usr_rd_cmd_value: 16; /*For SPI0 When cache mode is enable it is the read command value of command phase for SRAM.*/
@ -297,7 +297,7 @@ typedef volatile struct {
uint32_t usr_rd_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1).*/
};
uint32_t val;
}sram_drd_cmd;
} sram_drd_cmd;
union {
struct {
uint32_t usr_wr_cmd_value: 16; /*For SPI0 When cache mode is enable it is the write command value of command phase for SRAM.*/
@ -305,14 +305,14 @@ typedef volatile struct {
uint32_t usr_wr_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the in bits of command phase for SRAM. The register value shall be (bit_num-1).*/
};
uint32_t val;
}sram_dwr_cmd;
} sram_dwr_cmd;
union {
struct {
uint32_t slv_rdata_bit:24; /*In the slave mode it is the bit length of read data. The value is the length - 1.*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
}slv_rd_bit;
} slv_rd_bit;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
@ -341,7 +341,7 @@ typedef volatile struct {
uint32_t t_pp_ena: 1; /*page program delay enable.*/
};
uint32_t val;
}ext0;
} ext0;
union {
struct {
uint32_t t_erase_time: 12; /*erase flash delay time by system clock.*/
@ -351,21 +351,21 @@ typedef volatile struct {
uint32_t t_erase_ena: 1; /*erase flash delay enable.*/
};
uint32_t val;
}ext1;
} ext1;
union {
struct {
uint32_t st: 3; /*The status of spi state machine .*/
uint32_t reserved3: 29; /*reserved*/
};
uint32_t val;
}ext2;
} ext2;
union {
struct {
uint32_t int_hold_ena: 2; /*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ,idle, phase 2: hold at ,prepare, phase.*/
uint32_t reserved2: 30; /*reserved*/
};
uint32_t val;
}ext3;
} ext3;
union {
struct {
uint32_t reserved0: 2; /*reserved*/
@ -387,7 +387,7 @@ typedef volatile struct {
uint32_t reserved17: 15; /*reserved*/
};
uint32_t val;
}dma_conf;
} dma_conf;
union {
struct {
uint32_t addr: 20; /*The address of the first outlink descriptor.*/
@ -398,7 +398,7 @@ typedef volatile struct {
uint32_t reserved31: 1; /*reserved*/
};
uint32_t val;
}dma_out_link;
} dma_out_link;
union {
struct {
uint32_t addr: 20; /*The address of the first inlink descriptor.*/
@ -410,7 +410,7 @@ typedef volatile struct {
uint32_t reserved31: 1; /*reserved*/
};
uint32_t val;
}dma_in_link;
} dma_in_link;
union {
struct {
uint32_t rx_en: 1; /*spi dma read data status bit.*/
@ -418,7 +418,7 @@ typedef volatile struct {
uint32_t reserved2: 30; /*spi dma read data from memory count.*/
};
uint32_t val;
}dma_status;
} dma_status;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The enable bit for lack of enough inlink descriptors.*/
@ -433,7 +433,7 @@ typedef volatile struct {
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
}dma_int_ena;
} dma_int_ena;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The raw bit for lack of enough inlink descriptors.*/
@ -448,7 +448,7 @@ typedef volatile struct {
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
}dma_int_raw;
} dma_int_raw;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The status bit for lack of enough inlink descriptors.*/
@ -463,7 +463,7 @@ typedef volatile struct {
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
}dma_int_st;
} dma_int_st;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The clear bit for lack of enough inlink descriptors.*/
@ -478,7 +478,7 @@ typedef volatile struct {
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
}dma_int_clr;
} dma_int_clr;
uint32_t dma_in_err_eof_des_addr; /*The inlink descriptor address when spi dma produce receiving error.*/
uint32_t dma_in_suc_eof_des_addr; /*The last inlink descriptor address when spi dma produce from_suc_eof.*/
uint32_t dma_inlink_dscr; /*The content of current in descriptor pointer.*/
@ -668,7 +668,7 @@ typedef volatile struct {
uint32_t reserved28: 4; /*reserved*/
};
uint32_t val;
}date;
} date;
} spi_dev_t;
extern spi_dev_t SPI0; /* SPI0 IS FOR INTERNAL USE*/
extern spi_dev_t SPI1;

28
components/esp32/include/soc/timer_group_struct.h
View file

@ -27,7 +27,7 @@ typedef volatile struct {
uint32_t enable: 1; /*When set timer 0/1 time-base counter is enabled*/
};
uint32_t val;
}config;
} config;
uint32_t cnt_low; /*Register to store timer 0/1 time-base counter current value lower 32 bits.*/
uint32_t cnt_high; /*Register to store timer 0 time-base counter current value higher 32 bits.*/
uint32_t update; /*Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)*/
@ -36,7 +36,7 @@ typedef volatile struct {
uint32_t load_low; /*Lower 32 bits of the value that will load into timer 0 time-base counter*/
uint32_t load_high; /*higher 32 bits of the value that will load into timer 0 time-base counter*/
uint32_t reload; /*Write any value will trigger timer 0 time-base counter reload*/
}hw_timer[2];
} hw_timer[2];
union {
struct {
uint32_t reserved0: 14;
@ -52,14 +52,14 @@ typedef volatile struct {
uint32_t en: 1; /*When set SWDT is enabled*/
};
uint32_t val;
}wdt_config0;
} wdt_config0;
union {
struct {
uint32_t reserved0: 16;
uint32_t clk_prescale:16; /*SWDT clock prescale value. Period = 12.5ns * value stored in this register*/
};
uint32_t val;
}wdt_config1;
} wdt_config1;
uint32_t wdt_config2; /*Stage 0 timeout value in SWDT clock cycles*/
uint32_t wdt_config3; /*Stage 1 timeout value in SWDT clock cycles*/
uint32_t wdt_config4; /*Stage 2 timeout value in SWDT clock cycles*/
@ -76,14 +76,14 @@ typedef volatile struct {
uint32_t start: 1;
};
uint32_t val;
}rtc_cali_cfg;
} rtc_cali_cfg;
union {
struct {
uint32_t reserved0: 7;
uint32_t value:25;
};
uint32_t val;
}rtc_cali_cfg1;
} rtc_cali_cfg1;
union {
struct {
uint32_t reserved0: 7;
@ -99,14 +99,14 @@ typedef volatile struct {
uint32_t en: 1;
};
uint32_t val;
}lactconfig;
} lactconfig;
union {
struct {
uint32_t reserved0: 6;
uint32_t step_len:26;
};
uint32_t val;
}lactrtc;
} lactrtc;
uint32_t lactlo; /**/
uint32_t lacthi; /**/
uint32_t lactupdate; /**/
@ -124,7 +124,7 @@ typedef volatile struct {
uint32_t reserved4: 28;
};
uint32_t val;
}int_ena;
} int_ena;
union {
struct {
uint32_t t0: 1; /*interrupt when timer0 alarm*/
@ -134,7 +134,7 @@ typedef volatile struct {
uint32_t reserved4:28;
};
uint32_t val;
}int_raw;
} int_raw;
union {
struct {
uint32_t t0: 1; /*interrupt when timer0 alarm*/
@ -144,7 +144,7 @@ typedef volatile struct {
uint32_t reserved4: 28;
};
uint32_t val;
}int_st_timers;
} int_st_timers;
union {
struct {
uint32_t t0: 1; /*interrupt when timer0 alarm*/
@ -154,7 +154,7 @@ typedef volatile struct {
uint32_t reserved4: 28;
};
uint32_t val;
}int_clr_timers;
} int_clr_timers;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
@ -181,14 +181,14 @@ typedef volatile struct {
uint32_t reserved28: 4;
};
uint32_t val;
}timg_date;
} timg_date;
union {
struct {
uint32_t reserved0: 31;
uint32_t en: 1; /*Force clock enable for this regfile*/
};
uint32_t val;
}clk;
} clk;
} timg_dev_t;
extern timg_dev_t TIMERG0;
extern timg_dev_t TIMERG1;

56
components/esp32/include/soc/uart_struct.h
View file

@ -20,7 +20,7 @@ typedef volatile struct {
uint32_t reserved8: 24;
};
uint32_t val;
}fifo;
} fifo;
union {
struct {
uint32_t rxfifo_full: 1; /*This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/
@ -45,7 +45,7 @@ typedef volatile struct {
uint32_t reserved19: 13;
};
uint32_t val;
}int_raw;
} int_raw;
union {
struct {
uint32_t rxfifo_full: 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/
@ -70,7 +70,7 @@ typedef volatile struct {
uint32_t reserved19: 13;
};
uint32_t val;
}int_st;
} int_st;
union {
struct {
uint32_t rxfifo_full: 1; /*This is the enable bit for rxfifo_full_int_st register.*/
@ -95,7 +95,7 @@ typedef volatile struct {
uint32_t reserved19: 13;
};
uint32_t val;
}int_ena;
} int_ena;
union {
struct {
uint32_t rxfifo_full: 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/
@ -120,7 +120,7 @@ typedef volatile struct {
uint32_t reserved19: 13;
};
uint32_t val;
}int_clr;
} int_clr;
union {
struct {
uint32_t div_int: 20; /*The register value is the integer part of the frequency divider's factor.*/
@ -128,7 +128,7 @@ typedef volatile struct {
uint32_t reserved24: 8;
};
uint32_t val;
}clk_div;
} clk_div;
union {
struct {
uint32_t en: 1; /*This is the enable bit for detecting baudrate.*/
@ -137,7 +137,7 @@ typedef volatile struct {
uint32_t reserved16: 16;
};
uint32_t val;
}auto_baud;
} auto_baud;
union {
struct {
uint32_t rxfifo_cnt: 8; /*(rx_mem_cnt rxfifo_cnt) stores the byte number of valid data in receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/
@ -154,7 +154,7 @@ typedef volatile struct {
uint32_t txd: 1; /*This register represent the level value of the internal uart rxd signal.*/
};
uint32_t val;
}status;
} status;
union {
struct {
uint32_t parity: 1; /*This register is used to configure the parity check mode. 0:even 1:odd*/
@ -186,7 +186,7 @@ typedef volatile struct {
uint32_t reserved28: 4;
};
uint32_t val;
}conf0;
} conf0;
union {
struct {
uint32_t rxfifo_full_thrhd: 7; /*When receiver receives more data than its threshold value，receiver will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/
@ -199,28 +199,28 @@ typedef volatile struct {
uint32_t rx_tout_en: 1; /*This is the enable bit for uart receiver's timeout function.*/
};
uint32_t val;
}conf1;
} conf1;
union {
struct {
uint32_t min_cnt: 20; /*This register stores the value of the minimum duration time for the low level pulse， it is used in baudrate-detect process.*/
uint32_t reserved20: 12;
};
uint32_t val;
}lowpulse;
} lowpulse;
union {
struct {
uint32_t min_cnt: 20; /*This register stores the value of the maximum duration time for the high level pulse， it is used in baudrate-detect process.*/
uint32_t reserved20: 12;
};
uint32_t val;
}highpulse;
} highpulse;
union {
struct {
uint32_t edge_cnt: 10; /*This register stores the count of rxd edge change， it is used in baudrate-detect process.*/
uint32_t reserved10: 22;
};
uint32_t val;
}rxd_cnt;
} rxd_cnt;
union {
struct {
uint32_t sw_flow_con_en: 1; /*Set this bit to enable software flow control. it is used with register sw_xon or sw_xoff .*/
@ -232,14 +232,14 @@ typedef volatile struct {
uint32_t reserved6: 26;
};
uint32_t val;
}flow_conf;
} flow_conf;
union {
struct {
uint32_t active_threshold:10; /*When the input rxd edge changes more than this register value， the uart is active from light sleeping mode.*/
uint32_t reserved10: 22;
};
uint32_t val;
}sleep_conf;
} sleep_conf;
union {
struct {
uint32_t xon_threshold: 8; /*when the data amount in receiver's fifo is more than this register value， it will send a xoff char with uart_sw_flow_con_en set to 1.*/
@ -248,7 +248,7 @@ typedef volatile struct {
uint32_t xoff_char: 8; /*This register stores the xoff flow control char.*/
};
uint32_t val;
}swfc_conf;
} swfc_conf;
union {
struct {
uint32_t rx_idle_thrhd:10; /*when receiver takes more time than this register value to receive a byte data， it will produce frame end signal for uhci to stop receiving data.*/
@ -257,7 +257,7 @@ typedef volatile struct {
uint32_t reserved28: 4;
};
uint32_t val;
}idle_conf;
} idle_conf;
union {
struct {
uint32_t en: 1; /*Set this bit to choose rs485 mode.*/
@ -270,28 +270,28 @@ typedef volatile struct {
uint32_t reserved10: 22;
};
uint32_t val;
}rs485_conf;
} rs485_conf;
union {
struct {
uint32_t pre_idle_num:24; /*This register is used to configure the idle duration time before the first at_cmd is received by receiver， when the the duration is less than this register value it will not take the next data received as at_cmd char.*/
uint32_t reserved24: 8;
};
uint32_t val;
}at_cmd_precnt;
} at_cmd_precnt;
union {
struct {
uint32_t post_idle_num:24; /*This register is used to configure the duration time between the last at_cmd and the next data， when the duration is less than this register value it will not take the previous data as at_cmd char.*/
uint32_t reserved24: 8;
};
uint32_t val;
}at_cmd_postcnt;
} at_cmd_postcnt;
union {
struct {
uint32_t rx_gap_tout:24; /*This register is used to configure the duration time between the at_cmd chars， when the duration time is less than this register value it will not take the data as continous at_cmd chars.*/
uint32_t reserved24: 8;
};
uint32_t val;
}at_cmd_gaptout;
} at_cmd_gaptout;
union {
struct {
uint32_t data: 8; /*This register is used to configure the content of at_cmd char.*/
@ -299,7 +299,7 @@ typedef volatile struct {
uint32_t reserved16: 16;
};
uint32_t val;
}at_cmd_char;
} at_cmd_char;
union {
struct {
uint32_t mem_pd: 1; /*Set this bit to power down memory，when reg_mem_pd registers in the 3 uarts are all set to 1 memory will enter low power mode.*/
@ -317,21 +317,21 @@ typedef volatile struct {
uint32_t reserved31: 1;
};
uint32_t val;
}mem_conf;
} mem_conf;
union {
struct {
uint32_t status:24;
uint32_t reserved24: 8;
};
uint32_t val;
}mem_tx_status;
} mem_tx_status;
union {
struct {
uint32_t status:24;
uint32_t reserved24: 8;
};
uint32_t val;
}mem_rx_status;
} mem_rx_status;
union {
struct {
uint32_t rx_cnt: 3; /*refer to the rxfifo_cnt's description.*/
@ -339,21 +339,21 @@ typedef volatile struct {
uint32_t reserved6: 26;
};
uint32_t val;
}mem_cnt_status;
} mem_cnt_status;
union {
struct {
uint32_t min_cnt: 20; /*This register stores the count of rxd pos-edge edge， it is used in baudrate-detect process.*/
uint32_t reserved20: 12;
};
uint32_t val;
}pospulse;
} pospulse;
union {
struct {
uint32_t min_cnt: 20; /*This register stores the count of rxd neg-edge edge， it is used in baudrate-detect process.*/
uint32_t reserved20: 12;
};
uint32_t val;
}negpulse;
} negpulse;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t date; /**/

44
components/esp32/include/soc/uhci_struct.h
View file

@ -43,7 +43,7 @@ typedef volatile struct {
uint32_t reserved24: 8;
};
uint32_t val;
}conf0;
} conf0;
union {
struct {
uint32_t rx_start: 1; /*when a separator char has been send it will produce uhci_rx_start_int interrupt.*/
@ -66,7 +66,7 @@ typedef volatile struct {
uint32_t reserved17: 15;
};
uint32_t val;
}int_raw;
} int_raw;
union {
struct {
uint32_t rx_start: 1;
@ -89,7 +89,7 @@ typedef volatile struct {
uint32_t reserved17: 15;
};
uint32_t val;
}int_st;
} int_st;
union {
struct {
uint32_t rx_start: 1;
@ -112,7 +112,7 @@ typedef volatile struct {
uint32_t reserved17: 15;
};
uint32_t val;
}int_ena;
} int_ena;
union {
struct {
uint32_t rx_start: 1;
@ -135,7 +135,7 @@ typedef volatile struct {
uint32_t reserved17: 15;
};
uint32_t val;
}int_clr;
} int_clr;
union {
struct {
uint32_t full: 1; /*1:DMA out link descriptor's fifo is full.*/
@ -143,7 +143,7 @@ typedef volatile struct {
uint32_t reserved2: 30;
};
uint32_t val;
}dma_out_status;
} dma_out_status;
union {
struct {
uint32_t fifo_wdata: 9; /*This is the data need to be pushed into out link descriptor's fifo.*/
@ -152,7 +152,7 @@ typedef volatile struct {
uint32_t reserved17:15;
};
uint32_t val;
}dma_out_push;
} dma_out_push;
union {
struct {
uint32_t full: 1;
@ -162,7 +162,7 @@ typedef volatile struct {
uint32_t reserved7: 25;
};
uint32_t val;
}dma_in_status;
} dma_in_status;
union {
struct {
uint32_t fifo_rdata: 12; /*This register stores the data pop from in link descriptor's fifo.*/
@ -171,7 +171,7 @@ typedef volatile struct {
uint32_t reserved17: 15;
};
uint32_t val;
}dma_in_pop;
} dma_in_pop;
union {
struct {
uint32_t addr: 20; /*This register stores the least 20 bits of the first out link descriptor's address.*/
@ -182,7 +182,7 @@ typedef volatile struct {
uint32_t park: 1; /*1： the out link descriptor's fsm is in idle state. 0:the out link descriptor's fsm is working.*/
};
uint32_t val;
}dma_out_link;
} dma_out_link;
union {
struct {
uint32_t addr: 20; /*This register stores the least 20 bits of the first in link descriptor's address.*/
@ -194,7 +194,7 @@ typedef volatile struct {
uint32_t park: 1; /*1:the in link descriptor's fsm is in idle state. 0:the in link descriptor's fsm is working*/
};
uint32_t val;
}dma_in_link;
} dma_in_link;
union {
struct {
uint32_t check_sum_en: 1; /*Set this bit to enable decoder to check check_sum in packet header.*/
@ -210,7 +210,7 @@ typedef volatile struct {
uint32_t reserved21: 11;
};
uint32_t val;
}conf1;
} conf1;
uint32_t state0; /**/
uint32_t state1; /**/
uint32_t dma_out_eof_des_addr; /*This register stores the address of out link description when eof bit in this descriptor is 1.*/
@ -225,7 +225,7 @@ typedef volatile struct {
uint32_t reserved6: 26;
};
uint32_t val;
}ahb_test;
} ahb_test;
uint32_t dma_in_dscr; /*The content of current in link descriptor's third dword*/
uint32_t dma_in_dscr_bf0; /*The content of current in link descriptor's first dword*/
uint32_t dma_in_dscr_bf1; /*The content of current in link descriptor's second dword*/
@ -245,7 +245,7 @@ typedef volatile struct {
uint32_t reserved8: 24;
};
uint32_t val;
}escape_conf;
} escape_conf;
union {
struct {
uint32_t txfifo_timeout: 8; /*This register stores the timeout value.when DMA takes more time than this register value to receive a data it will produce uhci_tx_hung_int interrupt.*/
@ -257,7 +257,7 @@ typedef volatile struct {
uint32_t reserved24: 8;
};
uint32_t val;
}hung_conf;
} hung_conf;
uint32_t ack_num; /**/
uint32_t rx_head; /*This register stores the packet header received by DMA*/
union {
@ -269,10 +269,10 @@ typedef volatile struct {
uint32_t reserved8: 24;
};
uint32_t val;
}quick_sent;
} quick_sent;
struct{
uint32_t w_data[2]; /*This register stores the content of short packet's dword*/
}q_data[7];
} q_data[7];
union {
struct {
uint32_t seper_char: 8; /*This register stores the separator char separator char is used to separate the data frame.*/
@ -281,7 +281,7 @@ typedef volatile struct {
uint32_t reserved24: 8;
};
uint32_t val;
}esc_conf0;
} esc_conf0;
union {
struct {
uint32_t seq0: 8; /*This register stores the first substitute char used to replace the separate char.*/
@ -290,7 +290,7 @@ typedef volatile struct {
uint32_t reserved24: 8;
};
uint32_t val;
}esc_conf1;
} esc_conf1;
union {
struct {
uint32_t seq1: 8; /*This register stores the flow control char to turn on the flow_control*/
@ -299,7 +299,7 @@ typedef volatile struct {
uint32_t reserved24: 8;
};
uint32_t val;
}esc_conf2;
} esc_conf2;
union {
struct {
uint32_t seq2: 8; /*This register stores the flow_control char to turn off the flow_control*/
@ -308,14 +308,14 @@ typedef volatile struct {
uint32_t reserved24: 8;
};
uint32_t val;
}esc_conf3;
} esc_conf3;
union {
struct {
uint32_t thrs: 13; /*when the amount of packet payload is larger than this value the process of receiving data is done.*/
uint32_t reserved13:19;
};
uint32_t val;
}pkt_thres;
} pkt_thres;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;