d4d4d7324a
Reduces write cycles, and useful on ESP32 ECO3 as UART_DIS_DL is protected by
the same efuse.
Also fixes accidental macro definition introduced in 7635dce502
131 lines
5.2 KiB
C
131 lines
5.2 KiB
C
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <strings.h>
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#include "sdkconfig.h"
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#include "esp_log.h"
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#include "esp_efuse.h"
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#include "esp_efuse_table.h"
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#include "esp_flash_encrypt.h"
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#include "esp_secure_boot.h"
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#if CONFIG_IDF_TARGET_ESP32
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#define CRYPT_CNT ESP_EFUSE_FLASH_CRYPT_CNT
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#define WR_DIS_CRYPT_CNT ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT
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#elif CONFIG_IDF_TARGET_ESP32S2
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#define CRYPT_CNT ESP_EFUSE_SPI_BOOT_CRYPT_CNT
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#define WR_DIS_CRYPT_CNT ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT
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#endif
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#ifndef BOOTLOADER_BUILD
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static const char *TAG = "flash_encrypt";
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void esp_flash_encryption_init_checks()
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{
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esp_flash_enc_mode_t mode;
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// First check is: if Release mode flash encryption & secure boot are enabled then
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// FLASH_CRYPT_CNT *must* be write protected. This will have happened automatically
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// if bootloader is IDF V4.0 or newer but may not have happened for previous ESP-IDF bootloaders.
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#ifdef CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE
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#ifdef CONFIG_SECURE_BOOT
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if (esp_secure_boot_enabled() && esp_flash_encryption_enabled()) {
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uint8_t flash_crypt_cnt_wr_dis = 0;
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esp_efuse_read_field_blob(WR_DIS_CRYPT_CNT, &flash_crypt_cnt_wr_dis, 1);
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if (!flash_crypt_cnt_wr_dis) {
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uint8_t flash_crypt_cnt = 0;
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esp_efuse_read_field_blob(CRYPT_CNT, &flash_crypt_cnt, CRYPT_CNT[0]->bit_count);
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if (flash_crypt_cnt == (1<<(CRYPT_CNT[0]->bit_count))-1) {
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// If encryption counter is already max, no need to write protect it
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// (this distinction is important on ESP32 ECO3 where write-procted FLASH_CRYPT_CNT also write-protects UART_DL_DIS)
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return;
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}
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ESP_EARLY_LOGE(TAG, "Flash encryption & Secure Boot together requires FLASH_CRYPT_CNT efuse to be write protected. Fixing now...");
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esp_flash_write_protect_crypt_cnt();
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}
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}
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#endif // CONFIG_SECURE_BOOT
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#endif // CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE
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// Second check is to print a warning or error if the current running flash encryption mode
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// doesn't match the expectation from project config (due to mismatched bootloader and app, probably)
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mode = esp_get_flash_encryption_mode();
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if (mode == ESP_FLASH_ENC_MODE_DEVELOPMENT) {
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#ifdef CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE
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ESP_EARLY_LOGE(TAG, "Flash encryption settings error: app is configured for RELEASE but efuses are set for DEVELOPMENT");
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ESP_EARLY_LOGE(TAG, "Mismatch found in security options in bootloader menuconfig and efuse settings. Device is not secure.");
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#else
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ESP_EARLY_LOGW(TAG, "Flash encryption mode is DEVELOPMENT (not secure)");
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#endif
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} else if (mode == ESP_FLASH_ENC_MODE_RELEASE) {
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ESP_EARLY_LOGI(TAG, "Flash encryption mode is RELEASE");
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}
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}
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#endif
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void esp_flash_write_protect_crypt_cnt(void)
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{
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uint8_t flash_crypt_cnt_wr_dis = 0;
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esp_efuse_read_field_blob(WR_DIS_CRYPT_CNT, &flash_crypt_cnt_wr_dis, 1);
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if (!flash_crypt_cnt_wr_dis) {
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esp_efuse_write_field_cnt(WR_DIS_CRYPT_CNT, 1);
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}
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}
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esp_flash_enc_mode_t esp_get_flash_encryption_mode(void)
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{
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uint8_t efuse_flash_crypt_cnt_wr_protected = 0;
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#if CONFIG_IDF_TARGET_ESP32
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uint8_t dis_dl_enc = 0, dis_dl_dec = 0, dis_dl_cache = 0;
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#elif CONFIG_IDF_TARGET_ESP32S2
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uint8_t dis_dl_enc = 0;
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uint8_t dis_dl_icache = 0;
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uint8_t dis_dl_dcache = 0;
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#endif
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esp_flash_enc_mode_t mode = ESP_FLASH_ENC_MODE_DEVELOPMENT;
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if (esp_flash_encryption_enabled()) {
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/* Check if FLASH CRYPT CNT is write protected */
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esp_efuse_read_field_blob(WR_DIS_CRYPT_CNT, &efuse_flash_crypt_cnt_wr_protected, 1);
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if (efuse_flash_crypt_cnt_wr_protected) {
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#if CONFIG_IDF_TARGET_ESP32
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esp_efuse_read_field_blob(ESP_EFUSE_DISABLE_DL_CACHE, &dis_dl_cache, 1);
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esp_efuse_read_field_blob(ESP_EFUSE_DISABLE_DL_ENCRYPT, &dis_dl_enc, 1);
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esp_efuse_read_field_blob(ESP_EFUSE_DISABLE_DL_DECRYPT, &dis_dl_dec, 1);
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/* Check if DISABLE_DL_DECRYPT, DISABLE_DL_ENCRYPT & DISABLE_DL_CACHE are set */
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if ( dis_dl_cache && dis_dl_enc && dis_dl_dec ) {
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mode = ESP_FLASH_ENC_MODE_RELEASE;
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}
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#elif CONFIG_IDF_TARGET_ESP32S2
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esp_efuse_read_field_blob(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT, &dis_dl_enc, 1);
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esp_efuse_read_field_blob(ESP_EFUSE_DIS_DOWNLOAD_ICACHE, &dis_dl_icache, 1);
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esp_efuse_read_field_blob(ESP_EFUSE_DIS_DOWNLOAD_DCACHE, &dis_dl_dcache, 1);
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if (dis_dl_enc && dis_dl_icache && dis_dl_dcache) {
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mode = ESP_FLASH_ENC_MODE_RELEASE;
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}
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#endif
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}
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} else {
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mode = ESP_FLASH_ENC_MODE_DISABLED;
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}
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return mode;
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}
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