772 lines
38 KiB
C
772 lines
38 KiB
C
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_INTERRUPT_REG_H_
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#define _SOC_INTERRUPT_REG_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "soc.h"
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#define DPORT_PRO_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x000)
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/* DPORT_PRO_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_MAC_INTR_MAP 0x0000001F
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#define DPORT_PRO_MAC_INTR_MAP_M ((DPORT_PRO_MAC_INTR_MAP_V)<<(DPORT_PRO_MAC_INTR_MAP_S))
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#define DPORT_PRO_MAC_INTR_MAP_V 0x1F
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#define DPORT_PRO_MAC_INTR_MAP_S 0
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#define DPORT_PRO_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x004)
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/* DPORT_PRO_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_MAC_NMI_MAP 0x0000001F
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#define DPORT_PRO_MAC_NMI_MAP_M ((DPORT_PRO_MAC_NMI_MAP_V)<<(DPORT_PRO_MAC_NMI_MAP_S))
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#define DPORT_PRO_MAC_NMI_MAP_V 0x1F
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#define DPORT_PRO_MAC_NMI_MAP_S 0
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#define DPORT_PRO_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x008)
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/* DPORT_PRO_PWR_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_PWR_INTR_MAP 0x0000001F
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#define DPORT_PRO_PWR_INTR_MAP_M ((DPORT_PRO_PWR_INTR_MAP_V)<<(DPORT_PRO_PWR_INTR_MAP_S))
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#define DPORT_PRO_PWR_INTR_MAP_V 0x1F
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#define DPORT_PRO_PWR_INTR_MAP_S 0
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#define DPORT_PRO_BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x00C)
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/* DPORT_PRO_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_BB_INT_MAP 0x0000001F
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#define DPORT_PRO_BB_INT_MAP_M ((DPORT_PRO_BB_INT_MAP_V)<<(DPORT_PRO_BB_INT_MAP_S))
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#define DPORT_PRO_BB_INT_MAP_V 0x1F
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#define DPORT_PRO_BB_INT_MAP_S 0
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#define DPORT_PRO_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x010)
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/* DPORT_PRO_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_BT_MAC_INT_MAP 0x0000001F
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#define DPORT_PRO_BT_MAC_INT_MAP_M ((DPORT_PRO_BT_MAC_INT_MAP_V)<<(DPORT_PRO_BT_MAC_INT_MAP_S))
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#define DPORT_PRO_BT_MAC_INT_MAP_V 0x1F
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#define DPORT_PRO_BT_MAC_INT_MAP_S 0
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#define DPORT_PRO_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x014)
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/* DPORT_PRO_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_BT_BB_INT_MAP 0x0000001F
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#define DPORT_PRO_BT_BB_INT_MAP_M ((DPORT_PRO_BT_BB_INT_MAP_V)<<(DPORT_PRO_BT_BB_INT_MAP_S))
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#define DPORT_PRO_BT_BB_INT_MAP_V 0x1F
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#define DPORT_PRO_BT_BB_INT_MAP_S 0
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#define DPORT_PRO_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x018)
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/* DPORT_PRO_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_BT_BB_NMI_MAP 0x0000001F
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#define DPORT_PRO_BT_BB_NMI_MAP_M ((DPORT_PRO_BT_BB_NMI_MAP_V)<<(DPORT_PRO_BT_BB_NMI_MAP_S))
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#define DPORT_PRO_BT_BB_NMI_MAP_V 0x1F
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#define DPORT_PRO_BT_BB_NMI_MAP_S 0
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#define DPORT_PRO_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_BASE + 0x01C)
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/* DPORT_PRO_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_RWBT_IRQ_MAP 0x0000001F
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#define DPORT_PRO_RWBT_IRQ_MAP_M ((DPORT_PRO_RWBT_IRQ_MAP_V)<<(DPORT_PRO_RWBT_IRQ_MAP_S))
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#define DPORT_PRO_RWBT_IRQ_MAP_V 0x1F
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#define DPORT_PRO_RWBT_IRQ_MAP_S 0
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#define DPORT_PRO_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_BASE + 0x020)
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/* DPORT_PRO_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_RWBLE_IRQ_MAP 0x0000001F
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#define DPORT_PRO_RWBLE_IRQ_MAP_M ((DPORT_PRO_RWBLE_IRQ_MAP_V)<<(DPORT_PRO_RWBLE_IRQ_MAP_S))
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#define DPORT_PRO_RWBLE_IRQ_MAP_V 0x1F
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#define DPORT_PRO_RWBLE_IRQ_MAP_S 0
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#define DPORT_PRO_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x024)
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/* DPORT_PRO_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_RWBT_NMI_MAP 0x0000001F
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#define DPORT_PRO_RWBT_NMI_MAP_M ((DPORT_PRO_RWBT_NMI_MAP_V)<<(DPORT_PRO_RWBT_NMI_MAP_S))
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#define DPORT_PRO_RWBT_NMI_MAP_V 0x1F
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#define DPORT_PRO_RWBT_NMI_MAP_S 0
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#define DPORT_PRO_RWBLE_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x028)
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/* DPORT_PRO_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_RWBLE_NMI_MAP 0x0000001F
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#define DPORT_PRO_RWBLE_NMI_MAP_M ((DPORT_PRO_RWBLE_NMI_MAP_V)<<(DPORT_PRO_RWBLE_NMI_MAP_S))
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#define DPORT_PRO_RWBLE_NMI_MAP_V 0x1F
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#define DPORT_PRO_RWBLE_NMI_MAP_S 0
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#define DPORT_PRO_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x02C)
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/* DPORT_PRO_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_SLC0_INTR_MAP 0x0000001F
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#define DPORT_PRO_SLC0_INTR_MAP_M ((DPORT_PRO_SLC0_INTR_MAP_V)<<(DPORT_PRO_SLC0_INTR_MAP_S))
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#define DPORT_PRO_SLC0_INTR_MAP_V 0x1F
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#define DPORT_PRO_SLC0_INTR_MAP_S 0
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#define DPORT_PRO_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x030)
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/* DPORT_PRO_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_SLC1_INTR_MAP 0x0000001F
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#define DPORT_PRO_SLC1_INTR_MAP_M ((DPORT_PRO_SLC1_INTR_MAP_V)<<(DPORT_PRO_SLC1_INTR_MAP_S))
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#define DPORT_PRO_SLC1_INTR_MAP_V 0x1F
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#define DPORT_PRO_SLC1_INTR_MAP_S 0
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#define DPORT_PRO_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x034)
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/* DPORT_PRO_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_UHCI0_INTR_MAP 0x0000001F
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#define DPORT_PRO_UHCI0_INTR_MAP_M ((DPORT_PRO_UHCI0_INTR_MAP_V)<<(DPORT_PRO_UHCI0_INTR_MAP_S))
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#define DPORT_PRO_UHCI0_INTR_MAP_V 0x1F
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#define DPORT_PRO_UHCI0_INTR_MAP_S 0
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#define DPORT_PRO_UHCI1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x038)
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/* DPORT_PRO_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_UHCI1_INTR_MAP 0x0000001F
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#define DPORT_PRO_UHCI1_INTR_MAP_M ((DPORT_PRO_UHCI1_INTR_MAP_V)<<(DPORT_PRO_UHCI1_INTR_MAP_S))
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#define DPORT_PRO_UHCI1_INTR_MAP_V 0x1F
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#define DPORT_PRO_UHCI1_INTR_MAP_S 0
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#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x03C)
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/* DPORT_PRO_TG_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_TG_T0_LEVEL_INT_MAP 0x0000001F
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#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_M ((DPORT_PRO_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T0_LEVEL_INT_MAP_S))
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#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_V 0x1F
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#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_S 0
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#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x040)
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/* DPORT_PRO_TG_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_TG_T1_LEVEL_INT_MAP 0x0000001F
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#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_M ((DPORT_PRO_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T1_LEVEL_INT_MAP_S))
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#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_V 0x1F
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#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_S 0
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#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x044)
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/* DPORT_PRO_TG_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP 0x0000001F
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#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_M ((DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S))
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#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V 0x1F
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#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S 0
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#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x048)
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/* DPORT_PRO_TG_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP 0x0000001F
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#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_M ((DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S))
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#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V 0x1F
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#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S 0
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#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x04C)
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/* DPORT_PRO_TG1_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP 0x0000001F
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#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S))
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#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V 0x1F
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#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S 0
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#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x050)
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/* DPORT_PRO_TG1_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP 0x0000001F
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#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S))
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#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V 0x1F
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#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S 0
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#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x054)
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/* DPORT_PRO_TG1_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP 0x0000001F
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#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S))
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#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V 0x1F
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#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S 0
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#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x058)
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/* DPORT_PRO_TG1_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP 0x0000001F
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#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S))
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#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V 0x1F
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#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S 0
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#define DPORT_PRO_GPIO_DPORT_PRO_MAP_REG (DR_REG_INTERRUPT_BASE + 0x05C)
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/* DPORT_PRO_GPIO_DPORT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_GPIO_DPORT_PRO_MAP 0x0000001F
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#define DPORT_PRO_GPIO_DPORT_PRO_MAP_M ((DPORT_PRO_GPIO_DPORT_PRO_MAP_V)<<(DPORT_PRO_GPIO_DPORT_PRO_MAP_S))
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#define DPORT_PRO_GPIO_DPORT_PRO_MAP_V 0x1F
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#define DPORT_PRO_GPIO_DPORT_PRO_MAP_S 0
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#define DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x060)
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/* DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP 0x0000001F
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#define DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP_M ((DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP_V)<<(DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP_S))
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#define DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP_V 0x1F
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#define DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP_S 0
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#define DPORT_PRO_GPIO_DPORT_APP_MAP_REG (DR_REG_INTERRUPT_BASE + 0x064)
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/* DPORT_PRO_GPIO_DPORT_APP_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_GPIO_DPORT_APP_MAP 0x0000001F
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#define DPORT_PRO_GPIO_DPORT_APP_MAP_M ((DPORT_PRO_GPIO_DPORT_APP_MAP_V)<<(DPORT_PRO_GPIO_DPORT_APP_MAP_S))
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#define DPORT_PRO_GPIO_DPORT_APP_MAP_V 0x1F
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#define DPORT_PRO_GPIO_DPORT_APP_MAP_S 0
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#define DPORT_PRO_GPIO_DPORT_APP_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x068)
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/* DPORT_PRO_GPIO_DPORT_APP_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_GPIO_DPORT_APP_NMI_MAP 0x0000001F
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#define DPORT_PRO_GPIO_DPORT_APP_NMI_MAP_M ((DPORT_PRO_GPIO_DPORT_APP_NMI_MAP_V)<<(DPORT_PRO_GPIO_DPORT_APP_NMI_MAP_S))
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#define DPORT_PRO_GPIO_DPORT_APP_NMI_MAP_V 0x1F
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#define DPORT_PRO_GPIO_DPORT_APP_NMI_MAP_S 0
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#define DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x06C)
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/* DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP 0x0000001F
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#define DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP_M ((DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP_V)<<(DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP_S))
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#define DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP_V 0x1F
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#define DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP_S 0
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#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_BASE + 0x070)
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/* DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP 0x0000001F
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#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S))
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#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V 0x1F
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#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S 0
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#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_BASE + 0x074)
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/* DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP 0x0000001F
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#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S))
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#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V 0x1F
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#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S 0
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#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_BASE + 0x078)
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/* DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP 0x0000001F
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#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S))
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#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V 0x1F
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#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S 0
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#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_BASE + 0x07C)
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/* DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP 0x0000001F
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#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S))
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#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V 0x1F
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#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S 0
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#define DPORT_PRO_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_BASE + 0x080)
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/* DPORT_PRO_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_SPI_INTR_1_MAP 0x0000001F
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#define DPORT_PRO_SPI_INTR_1_MAP_M ((DPORT_PRO_SPI_INTR_1_MAP_V)<<(DPORT_PRO_SPI_INTR_1_MAP_S))
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#define DPORT_PRO_SPI_INTR_1_MAP_V 0x1F
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#define DPORT_PRO_SPI_INTR_1_MAP_S 0
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#define DPORT_PRO_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_BASE + 0x084)
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/* DPORT_PRO_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_SPI_INTR_2_MAP 0x0000001F
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#define DPORT_PRO_SPI_INTR_2_MAP_M ((DPORT_PRO_SPI_INTR_2_MAP_V)<<(DPORT_PRO_SPI_INTR_2_MAP_S))
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#define DPORT_PRO_SPI_INTR_2_MAP_V 0x1F
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#define DPORT_PRO_SPI_INTR_2_MAP_S 0
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#define DPORT_PRO_SPI_INTR_3_MAP_REG (DR_REG_INTERRUPT_BASE + 0x088)
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/* DPORT_PRO_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_SPI_INTR_3_MAP 0x0000001F
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#define DPORT_PRO_SPI_INTR_3_MAP_M ((DPORT_PRO_SPI_INTR_3_MAP_V)<<(DPORT_PRO_SPI_INTR_3_MAP_S))
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#define DPORT_PRO_SPI_INTR_3_MAP_V 0x1F
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#define DPORT_PRO_SPI_INTR_3_MAP_S 0
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#define DPORT_PRO_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x08C)
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/* DPORT_PRO_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_I2S0_INT_MAP 0x0000001F
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#define DPORT_PRO_I2S0_INT_MAP_M ((DPORT_PRO_I2S0_INT_MAP_V)<<(DPORT_PRO_I2S0_INT_MAP_S))
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#define DPORT_PRO_I2S0_INT_MAP_V 0x1F
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#define DPORT_PRO_I2S0_INT_MAP_S 0
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#define DPORT_PRO_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x090)
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/* DPORT_PRO_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_I2S1_INT_MAP 0x0000001F
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#define DPORT_PRO_I2S1_INT_MAP_M ((DPORT_PRO_I2S1_INT_MAP_V)<<(DPORT_PRO_I2S1_INT_MAP_S))
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#define DPORT_PRO_I2S1_INT_MAP_V 0x1F
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#define DPORT_PRO_I2S1_INT_MAP_S 0
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#define DPORT_PRO_UART_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x094)
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/* DPORT_PRO_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_UART_INTR_MAP 0x0000001F
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#define DPORT_PRO_UART_INTR_MAP_M ((DPORT_PRO_UART_INTR_MAP_V)<<(DPORT_PRO_UART_INTR_MAP_S))
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#define DPORT_PRO_UART_INTR_MAP_V 0x1F
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#define DPORT_PRO_UART_INTR_MAP_S 0
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#define DPORT_PRO_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x098)
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/* DPORT_PRO_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_UART1_INTR_MAP 0x0000001F
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#define DPORT_PRO_UART1_INTR_MAP_M ((DPORT_PRO_UART1_INTR_MAP_V)<<(DPORT_PRO_UART1_INTR_MAP_S))
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#define DPORT_PRO_UART1_INTR_MAP_V 0x1F
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#define DPORT_PRO_UART1_INTR_MAP_S 0
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#define DPORT_PRO_UART2_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x09C)
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/* DPORT_PRO_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_UART2_INTR_MAP 0x0000001F
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#define DPORT_PRO_UART2_INTR_MAP_M ((DPORT_PRO_UART2_INTR_MAP_V)<<(DPORT_PRO_UART2_INTR_MAP_S))
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#define DPORT_PRO_UART2_INTR_MAP_V 0x1F
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#define DPORT_PRO_UART2_INTR_MAP_S 0
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#define DPORT_PRO_SDIO_HOST_DPORT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0A0)
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/* DPORT_PRO_SDIO_HOST_DPORT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_SDIO_HOST_DPORT_MAP 0x0000001F
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#define DPORT_PRO_SDIO_HOST_DPORT_MAP_M ((DPORT_PRO_SDIO_HOST_DPORT_MAP_V)<<(DPORT_PRO_SDIO_HOST_DPORT_MAP_S))
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#define DPORT_PRO_SDIO_HOST_DPORT_MAP_V 0x1F
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#define DPORT_PRO_SDIO_HOST_DPORT_MAP_S 0
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#define DPORT_PRO_PWM0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0A4)
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/* DPORT_PRO_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_PWM0_INTR_MAP 0x0000001F
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#define DPORT_PRO_PWM0_INTR_MAP_M ((DPORT_PRO_PWM0_INTR_MAP_V)<<(DPORT_PRO_PWM0_INTR_MAP_S))
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#define DPORT_PRO_PWM0_INTR_MAP_V 0x1F
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#define DPORT_PRO_PWM0_INTR_MAP_S 0
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#define DPORT_PRO_PWM1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0A8)
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/* DPORT_PRO_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_PWM1_INTR_MAP 0x0000001F
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#define DPORT_PRO_PWM1_INTR_MAP_M ((DPORT_PRO_PWM1_INTR_MAP_V)<<(DPORT_PRO_PWM1_INTR_MAP_S))
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#define DPORT_PRO_PWM1_INTR_MAP_V 0x1F
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#define DPORT_PRO_PWM1_INTR_MAP_S 0
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#define DPORT_PRO_PWM2_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0AC)
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/* DPORT_PRO_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_PWM2_INTR_MAP 0x0000001F
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#define DPORT_PRO_PWM2_INTR_MAP_M ((DPORT_PRO_PWM2_INTR_MAP_V)<<(DPORT_PRO_PWM2_INTR_MAP_S))
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#define DPORT_PRO_PWM2_INTR_MAP_V 0x1F
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#define DPORT_PRO_PWM2_INTR_MAP_S 0
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#define DPORT_PRO_PWM3_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0B0)
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/* DPORT_PRO_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_PWM3_INTR_MAP 0x0000001F
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#define DPORT_PRO_PWM3_INTR_MAP_M ((DPORT_PRO_PWM3_INTR_MAP_V)<<(DPORT_PRO_PWM3_INTR_MAP_S))
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#define DPORT_PRO_PWM3_INTR_MAP_V 0x1F
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#define DPORT_PRO_PWM3_INTR_MAP_S 0
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#define DPORT_PRO_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0B4)
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/* DPORT_PRO_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_LEDC_INT_MAP 0x0000001F
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#define DPORT_PRO_LEDC_INT_MAP_M ((DPORT_PRO_LEDC_INT_MAP_V)<<(DPORT_PRO_LEDC_INT_MAP_S))
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#define DPORT_PRO_LEDC_INT_MAP_V 0x1F
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#define DPORT_PRO_LEDC_INT_MAP_S 0
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#define DPORT_PRO_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0B8)
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/* DPORT_PRO_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_EFUSE_INT_MAP 0x0000001F
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#define DPORT_PRO_EFUSE_INT_MAP_M ((DPORT_PRO_EFUSE_INT_MAP_V)<<(DPORT_PRO_EFUSE_INT_MAP_S))
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#define DPORT_PRO_EFUSE_INT_MAP_V 0x1F
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#define DPORT_PRO_EFUSE_INT_MAP_S 0
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#define DPORT_PRO_CAN_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0BC)
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/* DPORT_PRO_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_CAN_INT_MAP 0x0000001F
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#define DPORT_PRO_CAN_INT_MAP_M ((DPORT_PRO_CAN_INT_MAP_V)<<(DPORT_PRO_CAN_INT_MAP_S))
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#define DPORT_PRO_CAN_INT_MAP_V 0x1F
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#define DPORT_PRO_CAN_INT_MAP_S 0
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#define DPORT_PRO_USB_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0C0)
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/* DPORT_PRO_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_USB_INTR_MAP 0x0000001F
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#define DPORT_PRO_USB_INTR_MAP_M ((DPORT_PRO_USB_INTR_MAP_V)<<(DPORT_PRO_USB_INTR_MAP_S))
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#define DPORT_PRO_USB_INTR_MAP_V 0x1F
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#define DPORT_PRO_USB_INTR_MAP_S 0
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#define DPORT_PRO_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0C4)
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/* DPORT_PRO_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_RTC_CORE_INTR_MAP 0x0000001F
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#define DPORT_PRO_RTC_CORE_INTR_MAP_M ((DPORT_PRO_RTC_CORE_INTR_MAP_V)<<(DPORT_PRO_RTC_CORE_INTR_MAP_S))
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#define DPORT_PRO_RTC_CORE_INTR_MAP_V 0x1F
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#define DPORT_PRO_RTC_CORE_INTR_MAP_S 0
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#define DPORT_PRO_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0C8)
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/* DPORT_PRO_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_RMT_INTR_MAP 0x0000001F
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#define DPORT_PRO_RMT_INTR_MAP_M ((DPORT_PRO_RMT_INTR_MAP_V)<<(DPORT_PRO_RMT_INTR_MAP_S))
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#define DPORT_PRO_RMT_INTR_MAP_V 0x1F
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#define DPORT_PRO_RMT_INTR_MAP_S 0
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#define DPORT_PRO_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0CC)
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/* DPORT_PRO_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_PCNT_INTR_MAP 0x0000001F
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#define DPORT_PRO_PCNT_INTR_MAP_M ((DPORT_PRO_PCNT_INTR_MAP_V)<<(DPORT_PRO_PCNT_INTR_MAP_S))
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#define DPORT_PRO_PCNT_INTR_MAP_V 0x1F
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#define DPORT_PRO_PCNT_INTR_MAP_S 0
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#define DPORT_PRO_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0D0)
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/* DPORT_PRO_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_I2C_EXT0_INTR_MAP 0x0000001F
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#define DPORT_PRO_I2C_EXT0_INTR_MAP_M ((DPORT_PRO_I2C_EXT0_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT0_INTR_MAP_S))
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#define DPORT_PRO_I2C_EXT0_INTR_MAP_V 0x1F
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#define DPORT_PRO_I2C_EXT0_INTR_MAP_S 0
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#define DPORT_PRO_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0D4)
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/* DPORT_PRO_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_I2C_EXT1_INTR_MAP 0x0000001F
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#define DPORT_PRO_I2C_EXT1_INTR_MAP_M ((DPORT_PRO_I2C_EXT1_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT1_INTR_MAP_S))
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#define DPORT_PRO_I2C_EXT1_INTR_MAP_V 0x1F
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#define DPORT_PRO_I2C_EXT1_INTR_MAP_S 0
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#define DPORT_PRO_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0D8)
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/* DPORT_PRO_RSA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_RSA_INTR_MAP 0x0000001F
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#define DPORT_PRO_RSA_INTR_MAP_M ((DPORT_PRO_RSA_INTR_MAP_V)<<(DPORT_PRO_RSA_INTR_MAP_S))
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#define DPORT_PRO_RSA_INTR_MAP_V 0x1F
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#define DPORT_PRO_RSA_INTR_MAP_S 0
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#define DPORT_PRO_SPI1_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0DC)
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/* DPORT_PRO_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_SPI1_DMA_INT_MAP 0x0000001F
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#define DPORT_PRO_SPI1_DMA_INT_MAP_M ((DPORT_PRO_SPI1_DMA_INT_MAP_V)<<(DPORT_PRO_SPI1_DMA_INT_MAP_S))
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#define DPORT_PRO_SPI1_DMA_INT_MAP_V 0x1F
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#define DPORT_PRO_SPI1_DMA_INT_MAP_S 0
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#define DPORT_PRO_SPI2_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0E0)
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/* DPORT_PRO_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_SPI2_DMA_INT_MAP 0x0000001F
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#define DPORT_PRO_SPI2_DMA_INT_MAP_M ((DPORT_PRO_SPI2_DMA_INT_MAP_V)<<(DPORT_PRO_SPI2_DMA_INT_MAP_S))
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#define DPORT_PRO_SPI2_DMA_INT_MAP_V 0x1F
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#define DPORT_PRO_SPI2_DMA_INT_MAP_S 0
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#define DPORT_PRO_SPI3_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0E4)
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/* DPORT_PRO_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_SPI3_DMA_INT_MAP 0x0000001F
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#define DPORT_PRO_SPI3_DMA_INT_MAP_M ((DPORT_PRO_SPI3_DMA_INT_MAP_V)<<(DPORT_PRO_SPI3_DMA_INT_MAP_S))
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#define DPORT_PRO_SPI3_DMA_INT_MAP_V 0x1F
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#define DPORT_PRO_SPI3_DMA_INT_MAP_S 0
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#define DPORT_PRO_WDG_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0E8)
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/* DPORT_PRO_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_WDG_INT_MAP 0x0000001F
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#define DPORT_PRO_WDG_INT_MAP_M ((DPORT_PRO_WDG_INT_MAP_V)<<(DPORT_PRO_WDG_INT_MAP_S))
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#define DPORT_PRO_WDG_INT_MAP_V 0x1F
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#define DPORT_PRO_WDG_INT_MAP_S 0
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#define DPORT_PRO_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0EC)
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/* DPORT_PRO_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_TIMER_INT1_MAP 0x0000001F
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#define DPORT_PRO_TIMER_INT1_MAP_M ((DPORT_PRO_TIMER_INT1_MAP_V)<<(DPORT_PRO_TIMER_INT1_MAP_S))
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#define DPORT_PRO_TIMER_INT1_MAP_V 0x1F
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#define DPORT_PRO_TIMER_INT1_MAP_S 0
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#define DPORT_PRO_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0F0)
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/* DPORT_PRO_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_TIMER_INT2_MAP 0x0000001F
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#define DPORT_PRO_TIMER_INT2_MAP_M ((DPORT_PRO_TIMER_INT2_MAP_V)<<(DPORT_PRO_TIMER_INT2_MAP_S))
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#define DPORT_PRO_TIMER_INT2_MAP_V 0x1F
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#define DPORT_PRO_TIMER_INT2_MAP_S 0
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#define DPORT_PRO_TG_T0_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0F4)
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/* DPORT_PRO_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_TG_T0_EDGE_INT_MAP 0x0000001F
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#define DPORT_PRO_TG_T0_EDGE_INT_MAP_M ((DPORT_PRO_TG_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T0_EDGE_INT_MAP_S))
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#define DPORT_PRO_TG_T0_EDGE_INT_MAP_V 0x1F
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#define DPORT_PRO_TG_T0_EDGE_INT_MAP_S 0
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#define DPORT_PRO_TG_T1_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0F8)
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/* DPORT_PRO_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_TG_T1_EDGE_INT_MAP 0x0000001F
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#define DPORT_PRO_TG_T1_EDGE_INT_MAP_M ((DPORT_PRO_TG_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T1_EDGE_INT_MAP_S))
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#define DPORT_PRO_TG_T1_EDGE_INT_MAP_V 0x1F
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#define DPORT_PRO_TG_T1_EDGE_INT_MAP_S 0
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#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0FC)
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/* DPORT_PRO_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_TG_WDT_EDGE_INT_MAP 0x0000001F
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#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_M ((DPORT_PRO_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_WDT_EDGE_INT_MAP_S))
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#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_V 0x1F
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#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_S 0
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#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x100)
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/* DPORT_PRO_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_TG_LACT_EDGE_INT_MAP 0x0000001F
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#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_M ((DPORT_PRO_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_LACT_EDGE_INT_MAP_S))
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#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_V 0x1F
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#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_S 0
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#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x104)
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/* DPORT_PRO_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_TG1_T0_EDGE_INT_MAP 0x0000001F
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#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_M ((DPORT_PRO_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T0_EDGE_INT_MAP_S))
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#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_V 0x1F
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#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_S 0
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#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x108)
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/* DPORT_PRO_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_TG1_T1_EDGE_INT_MAP 0x0000001F
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#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_M ((DPORT_PRO_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T1_EDGE_INT_MAP_S))
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#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_V 0x1F
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#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_S 0
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#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x10C)
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/* DPORT_PRO_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP 0x0000001F
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#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_M ((DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S))
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#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V 0x1F
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#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S 0
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#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x110)
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/* DPORT_PRO_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP 0x0000001F
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#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_M ((DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S))
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#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V 0x1F
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#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S 0
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#define DPORT_PRO_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x114)
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/* DPORT_PRO_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_CACHE_IA_INT_MAP 0x0000001F
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#define DPORT_PRO_CACHE_IA_INT_MAP_M ((DPORT_PRO_CACHE_IA_INT_MAP_V)<<(DPORT_PRO_CACHE_IA_INT_MAP_S))
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#define DPORT_PRO_CACHE_IA_INT_MAP_V 0x1F
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#define DPORT_PRO_CACHE_IA_INT_MAP_S 0
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#define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x118)
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/* DPORT_PRO_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP 0x0000001F
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#define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_M ((DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_V)<<(DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_S))
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#define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_V 0x1F
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#define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_S 0
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#define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x11C)
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/* DPORT_PRO_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP 0x0000001F
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#define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_M ((DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_V)<<(DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_S))
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#define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_V 0x1F
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#define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_S 0
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#define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x120)
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/* DPORT_PRO_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP 0x0000001F
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#define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_M ((DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_V)<<(DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_S))
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#define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_V 0x1F
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#define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_S 0
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#define DPORT_PRO_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x124)
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/* DPORT_PRO_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_ASSIST_DEBUG_INTR_MAP 0x0000001F
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#define DPORT_PRO_ASSIST_DEBUG_INTR_MAP_M ((DPORT_PRO_ASSIST_DEBUG_INTR_MAP_V)<<(DPORT_PRO_ASSIST_DEBUG_INTR_MAP_S))
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#define DPORT_PRO_ASSIST_DEBUG_INTR_MAP_V 0x1F
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#define DPORT_PRO_ASSIST_DEBUG_INTR_MAP_S 0
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#define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x128)
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/* DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP 0x0000001F
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#define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_M ((DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_S))
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#define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_V 0x1F
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#define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_S 0
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#define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x12C)
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/* DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP 0x0000001F
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#define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_M ((DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_S))
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#define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_V 0x1F
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#define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_S 0
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#define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x130)
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/* DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP 0x0000001F
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#define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_M ((DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_S))
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#define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_V 0x1F
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#define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_S 0
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#define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x134)
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/* DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP 0x0000001F
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#define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_M ((DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_S))
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#define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_V 0x1F
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#define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_S 0
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#define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x138)
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/* DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP 0x0000001F
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#define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_M ((DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_S))
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#define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_V 0x1F
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#define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_S 0
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#define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x13C)
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/* DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP 0x0000001F
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#define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_M ((DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_S))
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#define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_V 0x1F
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#define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_S 0
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#define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x140)
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/* DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP 0x0000001F
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#define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_M ((DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_S))
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#define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_V 0x1F
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#define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_S 0
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#define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x144)
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/* DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP 0x0000001F
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#define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_M ((DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_S))
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#define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_V 0x1F
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#define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_S 0
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#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x148)
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/* DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP 0x0000001F
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#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_M ((DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_V)<<(DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_S))
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#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_V 0x1F
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#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_S 0
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#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x14C)
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/* DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP 0x0000001F
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#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_M ((DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_V)<<(DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_S))
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#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_V 0x1F
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#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_S 0
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#define DPORT_PRO_DMA_COPY_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x150)
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/* DPORT_PRO_DMA_COPY_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_DMA_COPY_INTR_MAP 0x0000001F
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#define DPORT_PRO_DMA_COPY_INTR_MAP_M ((DPORT_PRO_DMA_COPY_INTR_MAP_V)<<(DPORT_PRO_DMA_COPY_INTR_MAP_S))
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#define DPORT_PRO_DMA_COPY_INTR_MAP_V 0x1F
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#define DPORT_PRO_DMA_COPY_INTR_MAP_S 0
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#define DPORT_PRO_SPI4_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x154)
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/* DPORT_PRO_SPI4_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_SPI4_DMA_INT_MAP 0x0000001F
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#define DPORT_PRO_SPI4_DMA_INT_MAP_M ((DPORT_PRO_SPI4_DMA_INT_MAP_V)<<(DPORT_PRO_SPI4_DMA_INT_MAP_S))
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#define DPORT_PRO_SPI4_DMA_INT_MAP_V 0x1F
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#define DPORT_PRO_SPI4_DMA_INT_MAP_S 0
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#define DPORT_PRO_SPI_INTR_4_MAP_REG (DR_REG_INTERRUPT_BASE + 0x158)
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/* DPORT_PRO_SPI_INTR_4_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
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/*description: */
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#define DPORT_PRO_SPI_INTR_4_MAP 0x0000001F
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#define DPORT_PRO_SPI_INTR_4_MAP_M ((DPORT_PRO_SPI_INTR_4_MAP_V)<<(DPORT_PRO_SPI_INTR_4_MAP_S))
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#define DPORT_PRO_SPI_INTR_4_MAP_V 0x1F
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#define DPORT_PRO_SPI_INTR_4_MAP_S 0
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#define DPORT_PRO_INTR_STATUS_0_REG (DR_REG_INTERRUPT_BASE + 0x15C)
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/* DPORT_PRO_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: */
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#define DPORT_PRO_INTR_STATUS_0 0xFFFFFFFF
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#define DPORT_PRO_INTR_STATUS_0_M ((DPORT_PRO_INTR_STATUS_0_V)<<(DPORT_PRO_INTR_STATUS_0_S))
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#define DPORT_PRO_INTR_STATUS_0_V 0xFFFFFFFF
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#define DPORT_PRO_INTR_STATUS_0_S 0
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#define DPORT_PRO_INTR_STATUS_1_REG (DR_REG_INTERRUPT_BASE + 0x160)
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/* DPORT_PRO_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: */
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#define DPORT_PRO_INTR_STATUS_1 0xFFFFFFFF
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#define DPORT_PRO_INTR_STATUS_1_M ((DPORT_PRO_INTR_STATUS_1_V)<<(DPORT_PRO_INTR_STATUS_1_S))
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#define DPORT_PRO_INTR_STATUS_1_V 0xFFFFFFFF
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#define DPORT_PRO_INTR_STATUS_1_S 0
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#define DPORT_PRO_INTR_STATUS_2_REG (DR_REG_INTERRUPT_BASE + 0x164)
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/* DPORT_PRO_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: */
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#define DPORT_PRO_INTR_STATUS_2 0xFFFFFFFF
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#define DPORT_PRO_INTR_STATUS_2_M ((DPORT_PRO_INTR_STATUS_2_V)<<(DPORT_PRO_INTR_STATUS_2_S))
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#define DPORT_PRO_INTR_STATUS_2_V 0xFFFFFFFF
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#define DPORT_PRO_INTR_STATUS_2_S 0
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#define INTERRUPT_CLOCK_GATE_REG (DR_REG_INTERRUPT_BASE + 0x168)
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/* DPORT_PRO_NMI_MASK_HW : R/W ;bitpos:[1] ;default: 1'b0 ; */
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/*description: */
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#define DPORT_PRO_NMI_MASK_HW (BIT(1))
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#define DPORT_PRO_NMI_MASK_HW_M (BIT(1))
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#define DPORT_PRO_NMI_MASK_HW_V 0x1
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#define DPORT_PRO_NMI_MASK_HW_S 1
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/* INTERRUPT_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
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/*description: */
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#define INTERRUPT_CLK_EN (BIT(0))
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#define INTERRUPT_CLK_EN_M (BIT(0))
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#define INTERRUPT_CLK_EN_V 0x1
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#define INTERRUPT_CLK_EN_S 0
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#define INTERRUPT_DATE_REG (DR_REG_INTERRUPT_BASE + 0xFFC)
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/* INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h1809110 ; */
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/*description: */
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#define INTERRUPT_DATE 0x0FFFFFFF
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#define INTERRUPT_DATE_M ((INTERRUPT_DATE_V)<<(INTERRUPT_DATE_S))
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#define INTERRUPT_DATE_V 0xFFFFFFF
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#define INTERRUPT_DATE_S 0
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#ifdef __cplusplus
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}
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#endif
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#endif /*_SOC_INTERRUPT_REG_H_ */
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