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add esp32s2beta in soc component

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This commit is contained in:
suda-morris 2019-04-03 17:08:02 +08:00
parent cc98b9ef60
commit 91508ca27f
103 changed files with 64354 additions and 62 deletions
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23
components/driver/cas.h Normal file
View file

@ -0,0 +1,23 @@
#ifndef __CAS_H__
#define __CAS_H__
#include "sdkconfig.h"
#include "freertos/FreeRTOS.h"
#include "freertos/portmacro.h"
#define __cas_temp_sync_compare_and_swap_test(ptr, expected, desired) ({\
bool ret = false;\
unsigned state = portENTER_CRITICAL_NESTED(); \
if (*ptr == expected) { \
*ptr = desired; \
ret = true;\
}\
portEXIT_CRITICAL_NESTED(state); \
ret; \
})
#define __sync_bool_compare_and_swap(ptr, expected, desired) __cas_temp_sync_compare_and_swap_test(ptr, expected, desired)
#endif

4
components/lwip/CMakeLists.txt
View file

@ -86,11 +86,7 @@ set(COMPONENT_SRCS "apps/dhcpserver/dhcpserver.c"
"port/esp32/debug/lwip_debug.c"
"port/esp32/freertos/sys_arch.c"
"port/esp32/netif/dhcp_state.c"
<<<<<<< bce8b14e7324423a5caad1c6a240e97fdc45afe2
"port/esp32/netif/ethernetif.c"
"port/esp32/netif/nettestif.c"
=======
>>>>>>> Ethernet peripheral will depend on IDF_TARGET
"port/esp32/netif/wlanif.c")
if(CONFIG_IDF_TARGET_ESP32)

1
components/soc/component.mk
View file

@ -5,4 +5,5 @@ COMPONENT_SRCDIRS := $(SOC_NAME) src src/hal
COMPONENT_ADD_INCLUDEDIRS := $(SOC_NAME)/include include
-include $(COMPONENT_PATH)/$(SOC_NAME)/component.mk
COMPONENT_ADD_LDFRAGMENTS += linker.lf

12
components/soc/esp32/include/soc/dport_reg.h
View file

@ -19,7 +19,7 @@
#ifndef __ASSEMBLER__
#include "dport_access.h"
#endif
/* Registers defined in this header file must be accessed using special macros,
* prefixed with DPORT_. See soc/dport_access.h file for details.
*/
@ -961,7 +961,6 @@
#define DPORT_CAN_CLK_EN (BIT(19))
#define DPORT_I2C_EXT1_CLK_EN (BIT(18))
#define DPORT_PWM0_CLK_EN (BIT(17))
#define DPORT_SPI_CLK_EN_2 (BIT(16)) /** Deprecated, please use DPORT_SPI3_CLK_EN **/
#define DPORT_SPI3_CLK_EN (BIT(16))
#define DPORT_TIMERGROUP1_CLK_EN (BIT(15))
#define DPORT_EFUSE_CLK_EN (BIT(14))
@ -972,13 +971,11 @@
#define DPORT_RMT_CLK_EN (BIT(9))
#define DPORT_UHCI0_CLK_EN (BIT(8))
#define DPORT_I2C_EXT0_CLK_EN (BIT(7))
#define DPORT_SPI_CLK_EN (BIT(6)) /** Deprecated, please use DPORT_SPI2_CLK_EN **/
#define DPORT_SPI2_CLK_EN (BIT(6))
#define DPORT_UART1_CLK_EN (BIT(5))
#define DPORT_I2S0_CLK_EN (BIT(4))
#define DPORT_WDG_CLK_EN (BIT(3))
#define DPORT_UART_CLK_EN (BIT(2))
#define DPORT_SPI_CLK_EN_1 (BIT(1)) /** Deprecated, please use DPORT_SPI01_CLK_EN **/
#define DPORT_SPI01_CLK_EN (BIT(1))
#define DPORT_TIMERS_CLK_EN (BIT(0))
#define DPORT_PERIP_RST_EN_REG (DR_REG_DPORT_BASE + 0x0C4)
@ -998,7 +995,6 @@
#define DPORT_CAN_RST (BIT(19))
#define DPORT_I2C_EXT1_RST (BIT(18))
#define DPORT_PWM0_RST (BIT(17))
#define DPORT_SPI_RST_2 (BIT(16)) /** Deprecated, please use DPORT_SPI3_RST **/
#define DPORT_SPI3_RST (BIT(16))
#define DPORT_TIMERGROUP1_RST (BIT(15))
#define DPORT_EFUSE_RST (BIT(14))
@ -1009,13 +1005,11 @@
#define DPORT_RMT_RST (BIT(9))
#define DPORT_UHCI0_RST (BIT(8))
#define DPORT_I2C_EXT0_RST (BIT(7))
#define DPORT_SPI_RST (BIT(6)) /** Deprecated, please use DPORT_SPI2_RST **/
#define DPORT_SPI2_RST (BIT(6))
#define DPORT_UART1_RST (BIT(5))
#define DPORT_I2S0_RST (BIT(4))
#define DPORT_WDG_RST (BIT(3))
#define DPORT_UART_RST (BIT(2))
#define DPORT_SPI_RST_1 (BIT(1)) /** Deprecated, please use DPORT_SPI01_RST **/
#define DPORT_SPI01_RST (BIT(1))
#define DPORT_TIMERS_RST (BIT(0))
#define DPORT_SLAVE_SPI_CONFIG_REG (DR_REG_DPORT_BASE + 0x0C8)
@ -1090,7 +1084,7 @@
#define DPORT_BT_RST (BIT(3))
#define DPORT_MAC_RST (BIT(2))
#define DPORT_FE_RST (BIT(1))
#define DPORT_BB_RST (BIT(0))
#define DPORT_BB_RST (BIT(0))
#define DPORT_BT_LPCK_DIV_INT_REG (DR_REG_DPORT_BASE + 0x0D4)
/* DPORT_BTEXTWAKEUP_REQ : R/W ;bitpos:[12] ;default: 1'b0 ; */
@ -4283,6 +4277,8 @@
#define DPORT_FLASH_MMU_TABLE_INVALID_VAL 0x100
#define DPORT_MMU_ADDRESS_MASK 0xff
#endif /*_SOC_DPORT_REG_H_ */

14
components/soc/esp32/include/soc/hwcrypto_reg.h
View file

@ -26,16 +26,22 @@
#define RSA_M_DASH_REG (DR_REG_RSA_BASE + 0x800)
#define RSA_MODEXP_MODE_REG (DR_REG_RSA_BASE + 0x804)
#define RSA_START_MODEXP_REG (DR_REG_RSA_BASE + 0x808)
#define RSA_MODEXP_START_REG (DR_REG_RSA_BASE + 0x808)
#define RSA_MULT_MODE_REG (DR_REG_RSA_BASE + 0x80c)
#define RSA_MULT_START_REG (DR_REG_RSA_BASE + 0x810)
#define RSA_INTERRUPT_REG (DR_REG_RSA_BASE + 0x814)
#define RSA_CLEAR_INTERRUPT_REG (DR_REG_RSA_BASE + 0x814)
#define RSA_QUERY_INTERRUPT_REG (DR_REG_RSA_BASE + 0x814) /* same */
#define RSA_CLEAN_REG (DR_REG_RSA_BASE + 0x818)
#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x818)
/* Backwards compatibility register names used pre-ESP32S2 */
#define RSA_CLEAN_REG (RSA_QUERY_CLEAN_REG)
#define RSA_INTERRUPT_REG (RSA_CLEAR_INTERRUPT_REG)
#define RSA_START_MODEXP_REG (RSA_MODEXP_START_REG)
/* SHA acceleration registers */
#define SHA_TEXT_BASE ((DR_REG_SHA_BASE) + 0x00)
#define SHA_TEXT_BASE ((DR_REG_SHA_BASE) + 0x00)
#define SHA_1_START_REG ((DR_REG_SHA_BASE) + 0x80)
#define SHA_1_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x84)

15
components/soc/esp32/include/soc/io_mux_reg.h
View file

@ -79,9 +79,9 @@
/*
* @attention
* The PIN_PULL[UP|DWN]_[EN|DIS]() functions used to exist as macros in previous SDK versions.
* Unfortunately, however, they do not work for some GPIOs on the ESP32 chip, which needs pullups
* and -downs turned on and off through RTC registers. The functions still exist for compatibility
* The PIN_PULL[UP|DWN]_[EN|DIS]() functions used to exist as macros in previous SDK versions.
* Unfortunately, however, they do not work for some GPIOs on the ESP32 chip, which needs pullups
* and -downs turned on and off through RTC registers. The functions still exist for compatibility
* with older code, but are marked as deprecated in order to generate a warning.
* Please replace them in this fashion: (make sure to include driver/gpio.h as well)
* PIN_PULLUP_EN(GPIO_PIN_MUX_REG[x]) -> gpio_pullup_en(x)
@ -90,7 +90,7 @@
* PIN_PULLDWN_DIS(GPIO_PIN_MUX_REG[x]) -> gpio_pulldown_dis(x)
*
*/
static inline void __attribute__ ((deprecated)) PIN_PULLUP_DIS(uint32_t PIN_NAME)
static inline void __attribute__ ((deprecated)) PIN_PULLUP_DIS(uint32_t PIN_NAME)
{
REG_CLR_BIT(PIN_NAME, FUN_PU);
}
@ -115,6 +115,13 @@ static inline void __attribute__ ((deprecated)) PIN_PULLDWN_EN(uint32_t PIN_NAME
#define PIN_FUNC_GPIO 2
#define SPI_CLK_GPIO_NUM 6
#define SPI_CS0_GPIO_NUM 11
#define SPI_Q_GPIO_NUM 7
#define SPI_D_GPIO_NUM 8
#define SPI_WP_GPIO_NUM 10
#define SPI_HD_GPIO_NUM 9
#define PIN_CTRL (DR_REG_IO_MUX_BASE +0x00)
#define CLK_OUT3 0xf
#define CLK_OUT3_V CLK_OUT3

54
components/soc/esp32/include/soc/soc.h
View file

@ -25,19 +25,6 @@
#define PRO_CPU_NUM (0)
#define APP_CPU_NUM (1)
/* Overall memory map */
#define SOC_IROM_LOW 0x400D0000
#define SOC_IROM_HIGH 0x40400000
#define SOC_DROM_LOW 0x3F400000
#define SOC_DROM_HIGH 0x3F800000
#define SOC_DRAM_LOW 0x3FFAE000
#define SOC_DRAM_HIGH 0x40000000
#define SOC_RTC_IRAM_LOW 0x400C0000
#define SOC_RTC_IRAM_HIGH 0x400C2000
#define SOC_RTC_DATA_LOW 0x50000000
#define SOC_RTC_DATA_HIGH 0x50002000
#define SOC_EXTRAM_DATA_LOW 0x3F800000
#define SOC_EXTRAM_DATA_HIGH 0x3FC00000
#define SOC_MAX_CONTIGUOUS_RAM_SIZE 0x400000 ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
@ -246,24 +233,28 @@
//}}
/* Overall memory map */
#define SOC_DROM_LOW 0x3F400000
#define SOC_DROM_HIGH 0x3F800000
#define SOC_IROM_LOW 0x400D0000
#define SOC_IROM_HIGH 0x40400000
#define SOC_IROM_MASK_LOW 0x40000000
#define SOC_IROM_MASK_HIGH 0x40070000
#define SOC_CACHE_PRO_LOW 0x40070000
#define SOC_CACHE_PRO_HIGH 0x40078000
#define SOC_CACHE_APP_LOW 0x40078000
#define SOC_CACHE_APP_HIGH 0x40080000
#define SOC_IRAM_LOW 0x40080000
#define SOC_IRAM_HIGH 0x400A0000
#define SOC_RTC_IRAM_LOW 0x400C0000
#define SOC_RTC_IRAM_HIGH 0x400C2000
#define SOC_RTC_DRAM_LOW 0x3FF80000
#define SOC_RTC_DRAM_HIGH 0x3FF82000
#define SOC_RTC_DATA_LOW 0x50000000
#define SOC_RTC_DATA_HIGH 0x50002000
#define SOC_DROM_LOW 0x3F400000
#define SOC_DROM_HIGH 0x3F800000
#define SOC_DRAM_LOW 0x3FFAE000
#define SOC_DRAM_HIGH 0x40000000
#define SOC_IROM_LOW 0x400D0000
#define SOC_IROM_HIGH 0x40400000
#define SOC_IROM_MASK_LOW 0x40000000
#define SOC_IROM_MASK_HIGH 0x40070000
#define SOC_CACHE_PRO_LOW 0x40070000
#define SOC_CACHE_PRO_HIGH 0x40078000
#define SOC_CACHE_APP_LOW 0x40078000
#define SOC_CACHE_APP_HIGH 0x40080000
#define SOC_IRAM_LOW 0x40080000
#define SOC_IRAM_HIGH 0x400A0000
#define SOC_RTC_IRAM_LOW 0x400C0000
#define SOC_RTC_IRAM_HIGH 0x400C2000
#define SOC_RTC_DRAM_LOW 0x3FF80000
#define SOC_RTC_DRAM_HIGH 0x3FF82000
#define SOC_RTC_DATA_LOW 0x50000000
#define SOC_RTC_DATA_HIGH 0x50002000
#define SOC_EXTRAM_DATA_LOW 0x3F800000
#define SOC_EXTRAM_DATA_HIGH 0x3FC00000
//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
#define SOC_DIRAM_IRAM_LOW 0x400A0000
@ -355,6 +346,7 @@
#define ETS_MMU_IA_INTR_SOURCE 66/**< interrupt of MMU Invalid Access, LEVEL*/
#define ETS_MPU_IA_INTR_SOURCE 67/**< interrupt of MPU Invalid Access, LEVEL*/
#define ETS_CACHE_IA_INTR_SOURCE 68/**< interrupt of Cache Invalied Access, LEVEL*/
#define ETS_MAX_INTR_SOURCE 69/**< total number of interrupt sources*/
//interrupt cpu using table, Please see the core-isa.h
/*************************************************************************************************************

7
components/soc/esp32/include/soc/spi_pins.h
View file

@ -15,6 +15,9 @@
#ifndef _SOC_SPI_PINS_H_
#define _SOC_SPI_PINS_H_
#define SPI_PERIPH_NUM 3
#define SPI_FUNC_NUM 1
#define SPI_IOMUX_PIN_NUM_MISO 7
#define SPI_IOMUX_PIN_NUM_MOSI 8
#define SPI_IOMUX_PIN_NUM_CLK 6
@ -22,6 +25,7 @@
#define SPI_IOMUX_PIN_NUM_WP 10
#define SPI_IOMUX_PIN_NUM_HD 9
#define HSPI_FUNC_NUM 1
#define HSPI_IOMUX_PIN_NUM_MISO 12
#define HSPI_IOMUX_PIN_NUM_MOSI 13
#define HSPI_IOMUX_PIN_NUM_CLK 14
@ -29,6 +33,7 @@
#define HSPI_IOMUX_PIN_NUM_WP 2
#define HSPI_IOMUX_PIN_NUM_HD 4
#define VSPI_FUNC_NUM 1
#define VSPI_IOMUX_PIN_NUM_MISO 19
#define VSPI_IOMUX_PIN_NUM_MOSI 23
#define VSPI_IOMUX_PIN_NUM_CLK 18
@ -36,4 +41,4 @@
#define VSPI_IOMUX_PIN_NUM_WP 22
#define VSPI_IOMUX_PIN_NUM_HD 21
#endif /* _SOC_SPI_PINS_H_ */
#endif /* _SOC_SPI_PINS_H_ */

4
components/soc/esp32/soc_memory_layout.c
View file

@ -76,7 +76,7 @@ from low to high start address.
*/
const soc_memory_region_t soc_memory_regions[] = {
#ifdef CONFIG_ESP32_SPIRAM_SUPPORT
{ 0x3F800000, 0x400000, 15, 0}, //SPI SRAM, if available
{ SOC_EXTRAM_DATA_LOW, CONFIG_SPIRAM_SIZE, 15, 0}, //SPI SRAM, if available
#endif
{ 0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- used for rom code
{ 0x3FFB0000, 0x8000, 0, 0}, //pool 15 <- if BT is enabled, used as BT HW shared memory
@ -167,7 +167,7 @@ SOC_RESERVE_MEMORY_REGION(0x3fffc000, 0x40000000, trace_mem); //Reserve trace me
#endif
#ifdef CONFIG_ESP32_SPIRAM_SUPPORT
SOC_RESERVE_MEMORY_REGION(0x3f800000, 0x3fC00000, spi_ram); //SPI RAM gets added later if needed, in spiram.c; reserve it for now
SOC_RESERVE_MEMORY_REGION(SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_LOW + CONFIG_SPIRAM_SIZE, spi_ram); //SPI RAM gets added later if needed, in spiram.c; reserve it for now
#endif
#endif /* BOOTLOADER_BUILD */

11
components/soc/esp32/spi_periph.c
View file

@ -40,7 +40,8 @@ const spi_signal_conn_t spi_periph_signal[3] = {
.irq = ETS_SPI1_INTR_SOURCE,
.irq_dma = ETS_SPI1_DMA_INTR_SOURCE,
.module = PERIPH_SPI_MODULE,
.hw = &SPI1
.hw = &SPI1,
.func = SPI_FUNC_NUM
}, {
.spiclk_out = HSPICLK_OUT_IDX,
.spiclk_in = HSPICLK_IN_IDX,
@ -63,7 +64,8 @@ const spi_signal_conn_t spi_periph_signal[3] = {
.irq = ETS_SPI2_INTR_SOURCE,
.irq_dma = ETS_SPI2_DMA_INTR_SOURCE,
.module = PERIPH_HSPI_MODULE,
.hw = &SPI2
.hw = &SPI2,
.func = HSPI_FUNC_NUM
}, {
.spiclk_out = VSPICLK_OUT_IDX,
.spiclk_in = VSPICLK_IN_IDX,
@ -86,6 +88,7 @@ const spi_signal_conn_t spi_periph_signal[3] = {
.irq = ETS_SPI3_INTR_SOURCE,
.irq_dma = ETS_SPI3_DMA_INTR_SOURCE,
.module = PERIPH_VSPI_MODULE,
.hw = &SPI3
.hw = &SPI3,
.func = VSPI_FUNC_NUM
}
};
};

1
components/soc/esp32s2beta/component.mk Normal file
View file

@ -0,0 +1 @@
esp32s2beta/rtc_clk.o: CFLAGS += -fno-jump-tables -fno-tree-switch-conversion

63
components/soc/esp32s2beta/cpu_util.c Normal file
View file

@ -0,0 +1,63 @@
// Copyright 2013-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "esp_attr.h"
#include "soc/cpu.h"
#include "soc/soc.h"
#include "soc/rtc_cntl_reg.h"
#include "sdkconfig.h"
void IRAM_ATTR esp_cpu_stall(int cpu_id)
{
if (cpu_id == 1) {
CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_APPCPU_C1_M);
SET_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, 0x21<<RTC_CNTL_SW_STALL_APPCPU_C1_S);
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_APPCPU_C0_M);
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, 2<<RTC_CNTL_SW_STALL_APPCPU_C0_S);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_PROCPU_C1_M);
SET_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, 0x21<<RTC_CNTL_SW_STALL_PROCPU_C1_S);
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_PROCPU_C0_M);
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, 2<<RTC_CNTL_SW_STALL_PROCPU_C0_S);
}
}
void IRAM_ATTR esp_cpu_unstall(int cpu_id)
{
if (cpu_id == 1) {
CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_APPCPU_C1_M);
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_APPCPU_C0_M);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_PROCPU_C1_M);
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_PROCPU_C0_M);
}
}
void IRAM_ATTR esp_cpu_reset(int cpu_id)
{
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
cpu_id == 0 ? RTC_CNTL_SW_PROCPU_RST_M : RTC_CNTL_SW_APPCPU_RST_M);
}
bool IRAM_ATTR esp_cpu_in_ocd_debug_mode()
{
#if CONFIG_ESP32_DEBUG_OCDAWARE
int dcr;
int reg=0x10200C; //DSRSET register
asm("rer %0,%1":"=r"(dcr):"r"(reg));
return (dcr&0x1);
#else
return false; // Always return false if "OCD aware" is disabled
#endif
}

136
components/soc/esp32s2beta/i2c_apll.h Normal file
View file

@ -0,0 +1,136 @@
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
/**
* @file i2c_apll.h
* @brief Register definitions for audio PLL (APLL)
*
* This file lists register fields of APLL, located on an internal configuration
* bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
* rtc_clk_apll_enable function in rtc_clk.c.
*/
#define I2C_APLL 0X6D
#define I2C_APLL_HOSTID 3
#define I2C_APLL_IR_CAL_DELAY 0
#define I2C_APLL_IR_CAL_DELAY_MSB 3
#define I2C_APLL_IR_CAL_DELAY_LSB 0
#define I2C_APLL_IR_CAL_RSTB 0
#define I2C_APLL_IR_CAL_RSTB_MSB 4
#define I2C_APLL_IR_CAL_RSTB_LSB 4
#define I2C_APLL_IR_CAL_START 0
#define I2C_APLL_IR_CAL_START_MSB 5
#define I2C_APLL_IR_CAL_START_LSB 5
#define I2C_APLL_IR_CAL_UNSTOP 0
#define I2C_APLL_IR_CAL_UNSTOP_MSB 6
#define I2C_APLL_IR_CAL_UNSTOP_LSB 6
#define I2C_APLL_OC_ENB_FCAL 0
#define I2C_APLL_OC_ENB_FCAL_MSB 7
#define I2C_APLL_OC_ENB_FCAL_LSB 7
#define I2C_APLL_IR_CAL_EXT_CAP 1
#define I2C_APLL_IR_CAL_EXT_CAP_MSB 4
#define I2C_APLL_IR_CAL_EXT_CAP_LSB 0
#define I2C_APLL_IR_CAL_ENX_CAP 1
#define I2C_APLL_IR_CAL_ENX_CAP_MSB 5
#define I2C_APLL_IR_CAL_ENX_CAP_LSB 5
#define I2C_APLL_OC_LBW 1
#define I2C_APLL_OC_LBW_MSB 6
#define I2C_APLL_OC_LBW_LSB 6
#define I2C_APLL_IR_CAL_CK_DIV 2
#define I2C_APLL_IR_CAL_CK_DIV_MSB 3
#define I2C_APLL_IR_CAL_CK_DIV_LSB 0
#define I2C_APLL_OC_DCHGP 2
#define I2C_APLL_OC_DCHGP_MSB 6
#define I2C_APLL_OC_DCHGP_LSB 4
#define I2C_APLL_OC_ENB_VCON 2
#define I2C_APLL_OC_ENB_VCON_MSB 7
#define I2C_APLL_OC_ENB_VCON_LSB 7
#define I2C_APLL_OR_CAL_CAP 3
#define I2C_APLL_OR_CAL_CAP_MSB 4
#define I2C_APLL_OR_CAL_CAP_LSB 0
#define I2C_APLL_OR_CAL_UDF 3
#define I2C_APLL_OR_CAL_UDF_MSB 5
#define I2C_APLL_OR_CAL_UDF_LSB 5
#define I2C_APLL_OR_CAL_OVF 3
#define I2C_APLL_OR_CAL_OVF_MSB 6
#define I2C_APLL_OR_CAL_OVF_LSB 6
#define I2C_APLL_OR_CAL_END 3
#define I2C_APLL_OR_CAL_END_MSB 7
#define I2C_APLL_OR_CAL_END_LSB 7
#define I2C_APLL_OR_OUTPUT_DIV 4
#define I2C_APLL_OR_OUTPUT_DIV_MSB 4
#define I2C_APLL_OR_OUTPUT_DIV_LSB 0
#define I2C_APLL_OC_TSCHGP 4
#define I2C_APLL_OC_TSCHGP_MSB 6
#define I2C_APLL_OC_TSCHGP_LSB 6
#define I2C_APLL_EN_FAST_CAL 4
#define I2C_APLL_EN_FAST_CAL_MSB 7
#define I2C_APLL_EN_FAST_CAL_LSB 7
#define I2C_APLL_OC_DHREF_SEL 5
#define I2C_APLL_OC_DHREF_SEL_MSB 1
#define I2C_APLL_OC_DHREF_SEL_LSB 0
#define I2C_APLL_OC_DLREF_SEL 5
#define I2C_APLL_OC_DLREF_SEL_MSB 3
#define I2C_APLL_OC_DLREF_SEL_LSB 2
#define I2C_APLL_SDM_DITHER 5
#define I2C_APLL_SDM_DITHER_MSB 4
#define I2C_APLL_SDM_DITHER_LSB 4
#define I2C_APLL_SDM_STOP 5
#define I2C_APLL_SDM_STOP_MSB 5
#define I2C_APLL_SDM_STOP_LSB 5
#define I2C_APLL_SDM_RSTB 5
#define I2C_APLL_SDM_RSTB_MSB 6
#define I2C_APLL_SDM_RSTB_LSB 6
#define I2C_APLL_OC_DVDD 6
#define I2C_APLL_OC_DVDD_MSB 4
#define I2C_APLL_OC_DVDD_LSB 0
#define I2C_APLL_DSDM2 7
#define I2C_APLL_DSDM2_MSB 5
#define I2C_APLL_DSDM2_LSB 0
#define I2C_APLL_DSDM1 8
#define I2C_APLL_DSDM1_MSB 7
#define I2C_APLL_DSDM1_LSB 0
#define I2C_APLL_DSDM0 9
#define I2C_APLL_DSDM0_MSB 7
#define I2C_APLL_DSDM0_LSB 0

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// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
/**
* @file i2c_apll.h
* @brief Register definitions for digital PLL (BBPLL)
*
* This file lists register fields of BBPLL, located on an internal configuration
* bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
* rtc_clk_cpu_freq_set function in rtc_clk.c.
*/
#define I2C_BBPLL 0x66
#define I2C_BBPLL_HOSTID 1
#define I2C_BBPLL_IR_CAL_DELAY 0
#define I2C_BBPLL_IR_CAL_DELAY_MSB 3
#define I2C_BBPLL_IR_CAL_DELAY_LSB 0
#define I2C_BBPLL_IR_CAL_CK_DIV 0
#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7
#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4
#define I2C_BBPLL_IR_CAL_EXT_CAP 1
#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3
#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0
#define I2C_BBPLL_IR_CAL_ENX_CAP 1
#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4
#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4
#define I2C_BBPLL_IR_CAL_RSTB 1
#define I2C_BBPLL_IR_CAL_RSTB_MSB 5
#define I2C_BBPLL_IR_CAL_RSTB_LSB 5
#define I2C_BBPLL_IR_CAL_START 1
#define I2C_BBPLL_IR_CAL_START_MSB 6
#define I2C_BBPLL_IR_CAL_START_LSB 6
#define I2C_BBPLL_IR_CAL_UNSTOP 1
#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7
#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7
#define I2C_BBPLL_OC_REF_DIV 2
#define I2C_BBPLL_OC_REF_DIV_MSB 3
#define I2C_BBPLL_OC_REF_DIV_LSB 0
#define I2C_BBPLL_OC_DCHGP 2
#define I2C_BBPLL_OC_DCHGP_MSB 6
#define I2C_BBPLL_OC_DCHGP_LSB 4
#define I2C_BBPLL_OC_ENB_FCAL 2
#define I2C_BBPLL_OC_ENB_FCAL_MSB 7
#define I2C_BBPLL_OC_ENB_FCAL_LSB 7
#define I2C_BBPLL_OC_DIV_7_0 3
#define I2C_BBPLL_OC_DIV_7_0_MSB 7
#define I2C_BBPLL_OC_DIV_7_0_LSB 0
#define I2C_BBPLL_RSTB_DIV_ADC 4
#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0
#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0
#define I2C_BBPLL_MODE_HF 4
#define I2C_BBPLL_MODE_HF_MSB 1
#define I2C_BBPLL_MODE_HF_LSB 1
#define I2C_BBPLL_DIV_ADC 4
#define I2C_BBPLL_DIV_ADC_MSB 3
#define I2C_BBPLL_DIV_ADC_LSB 2
#define I2C_BBPLL_DIV_DAC 4
#define I2C_BBPLL_DIV_DAC_MSB 4
#define I2C_BBPLL_DIV_DAC_LSB 4
#define I2C_BBPLL_DIV_CPU 4
#define I2C_BBPLL_DIV_CPU_MSB 5
#define I2C_BBPLL_DIV_CPU_LSB 5
#define I2C_BBPLL_OC_ENB_VCON 4
#define I2C_BBPLL_OC_ENB_VCON_MSB 6
#define I2C_BBPLL_OC_ENB_VCON_LSB 6
#define I2C_BBPLL_OC_TSCHGP 4
#define I2C_BBPLL_OC_TSCHGP_MSB 7
#define I2C_BBPLL_OC_TSCHGP_LSB 7
#define I2C_BBPLL_OC_DR1 5
#define I2C_BBPLL_OC_DR1_MSB 2
#define I2C_BBPLL_OC_DR1_LSB 0
#define I2C_BBPLL_OC_DR3 5
#define I2C_BBPLL_OC_DR3_MSB 6
#define I2C_BBPLL_OC_DR3_LSB 4
#define I2C_BBPLL_EN_USB 5
#define I2C_BBPLL_EN_USB_MSB 7
#define I2C_BBPLL_EN_USB_LSB 7
#define I2C_BBPLL_OC_DCUR 6
#define I2C_BBPLL_OC_DCUR_MSB 2
#define I2C_BBPLL_OC_DCUR_LSB 0
#define I2C_BBPLL_INC_CUR 6
#define I2C_BBPLL_INC_CUR_MSB 3
#define I2C_BBPLL_INC_CUR_LSB 3
#define I2C_BBPLL_OC_DHREF_SEL 6
#define I2C_BBPLL_OC_DHREF_SEL_MSB 5
#define I2C_BBPLL_OC_DHREF_SEL_LSB 4
#define I2C_BBPLL_OC_DLREF_SEL 6
#define I2C_BBPLL_OC_DLREF_SEL_MSB 7
#define I2C_BBPLL_OC_DLREF_SEL_LSB 6
#define I2C_BBPLL_OR_CAL_CAP 8
#define I2C_BBPLL_OR_CAL_CAP_MSB 3
#define I2C_BBPLL_OR_CAL_CAP_LSB 0
#define I2C_BBPLL_OR_CAL_UDF 8
#define I2C_BBPLL_OR_CAL_UDF_MSB 4
#define I2C_BBPLL_OR_CAL_UDF_LSB 4
#define I2C_BBPLL_OR_CAL_OVF 8
#define I2C_BBPLL_OR_CAL_OVF_MSB 5
#define I2C_BBPLL_OR_CAL_OVF_LSB 5
#define I2C_BBPLL_OR_CAL_END 8
#define I2C_BBPLL_OR_CAL_END_MSB 6
#define I2C_BBPLL_OR_CAL_END_LSB 6
#define I2C_BBPLL_OR_LOCK 8
#define I2C_BBPLL_OR_LOCK_MSB 7
#define I2C_BBPLL_OR_LOCK_LSB 7
#define I2C_BBPLL_BBADC_DELAY1 9
#define I2C_BBPLL_BBADC_DELAY1_MSB 1
#define I2C_BBPLL_BBADC_DELAY1_LSB 0
#define I2C_BBPLL_BBADC_DELAY2 9
#define I2C_BBPLL_BBADC_DELAY2_MSB 3
#define I2C_BBPLL_BBADC_DELAY2_LSB 2
#define I2C_BBPLL_BBADC_DVDD 9
#define I2C_BBPLL_BBADC_DVDD_MSB 5
#define I2C_BBPLL_BBADC_DVDD_LSB 4
#define I2C_BBPLL_BBADC_DREF 9
#define I2C_BBPLL_BBADC_DREF_MSB 7
#define I2C_BBPLL_BBADC_DREF_LSB 6
#define I2C_BBPLL_BBADC_DCUR 10
#define I2C_BBPLL_BBADC_DCUR_MSB 1
#define I2C_BBPLL_BBADC_DCUR_LSB 0
#define I2C_BBPLL_BBADC_INPUT_SHORT 10
#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2
#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2
#define I2C_BBPLL_ENT_PLL 10
#define I2C_BBPLL_ENT_PLL_MSB 3
#define I2C_BBPLL_ENT_PLL_LSB 3
#define I2C_BBPLL_DTEST 10
#define I2C_BBPLL_DTEST_MSB 5
#define I2C_BBPLL_DTEST_LSB 4
#define I2C_BBPLL_ENT_ADC 10
#define I2C_BBPLL_ENT_ADC_MSB 7
#define I2C_BBPLL_ENT_ADC_LSB 6

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// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include "i2c_apll.h"
#include "i2c_bbpll.h"
/* Analog function control register */
#define ANA_CONFIG_REG 0x6000E044
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)
/* Clear to enable APLL */
#define I2C_APLL_M (BIT(14))
/* Clear to enable BBPLL */
#define I2C_BBPLL_M (BIT(17))
/* ROM functions which read/write internal control bus */
uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
uint8_t rom_i2c_readReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
/* Convenience macros for the above functions, these use register definitions
* from i2c_apll.h/i2c_bbpll.h header files.
*/
#define I2C_WRITEREG_MASK_RTC(block, reg_add, indata) \
rom_i2c_writeReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata)
#define I2C_READREG_MASK_RTC(block, reg_add) \
rom_i2c_readReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB)
#define I2C_WRITEREG_RTC(block, reg_add, indata) \
rom_i2c_writeReg(block, block##_HOSTID, reg_add, indata)
#define I2C_READREG_RTC(block, reg_add) \
rom_i2c_readReg(block, block##_HOSTID, reg_add)

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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_ADC_CHANNEL_H
#define _SOC_ADC_CHANNEL_H
#define ADC1_GPIO1_CHANNEL ADC1_CHANNEL_0
#define ADC1_CHANNEL_0_GPIO_NUM 1
#define ADC1_GPIO2_CHANNEL ADC1_CHANNEL_1
#define ADC1_CHANNEL_1_GPIO_NUM 2
#define ADC1_GPIO3_CHANNEL ADC1_CHANNEL_2
#define ADC1_CHANNEL_2_GPIO_NUM 3
#define ADC1_GPIO4_CHANNEL ADC1_CHANNEL_3
#define ADC1_CHANNEL_3_GPIO_NUM 4
#define ADC1_GPIO5_CHANNEL ADC1_CHANNEL_4
#define ADC1_CHANNEL_4_GPIO_NUM 5
#define ADC1_GPIO6_CHANNEL ADC1_CHANNEL_5
#define ADC1_CHANNEL_5_GPIO_NUM 6
#define ADC1_GPIO7_CHANNEL ADC1_CHANNEL_6
#define ADC1_CHANNEL_6_GPIO_NUM 7
#define ADC1_GPIO8_CHANNEL ADC1_CHANNEL_7
#define ADC1_CHANNEL_7_GPIO_NUM 8
#define ADC1_GPIO9_CHANNEL ADC1_CHANNEL_8
#define ADC1_CHANNEL_8_GPIO_NUM 9
#define ADC1_GPIO10_CHANNEL ADC1_CHANNEL_9
#define ADC1_CHANNEL_9_GPIO_NUM 10
#define ADC2_GPIO11_CHANNEL ADC2_CHANNEL_0
#define ADC2_CHANNEL_0_GPIO_NUM 11
#define ADC2_GPIO12_CHANNEL ADC2_CHANNEL_1
#define ADC2_CHANNEL_1_GPIO_NUM 12
#define ADC2_GPIO13_CHANNEL ADC2_CHANNEL_2
#define ADC2_CHANNEL_2_GPIO_NUM 13
#define ADC2_GPIO14_CHANNEL ADC2_CHANNEL_3
#define ADC2_CHANNEL_3_GPIO_NUM 14
#define ADC2_GPIO15_CHANNEL ADC2_CHANNEL_4
#define ADC2_CHANNEL_4_GPIO_NUM 15
#define ADC2_GPIO16_CHANNEL ADC2_CHANNEL_5
#define ADC2_CHANNEL_5_GPIO_NUM 16
#define ADC2_GPIO17_CHANNEL ADC2_CHANNEL_6
#define ADC2_CHANNEL_6_GPIO_NUM 17
#define ADC2_GPIO18_CHANNEL ADC2_CHANNEL_7
#define ADC2_CHANNEL_7_GPIO_NUM 18
#define ADC2_GPIO19_CHANNEL ADC2_CHANNEL_8
#define ADC2_CHANNEL_8_GPIO_NUM 19
#define ADC2_GPIO20_CHANNEL ADC2_CHANNEL_9
#define ADC2_CHANNEL_9_GPIO_NUM 20
#endif

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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_APB_CTRL_REG_H_
#define _SOC_APB_CTRL_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x000)
/* APB_CTRL_SOC_CLK_SEL : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
/*description: */
#define APB_CTRL_SOC_CLK_SEL 0x00000003
#define APB_CTRL_SOC_CLK_SEL_M ((APB_CTRL_SOC_CLK_SEL_V)<<(APB_CTRL_SOC_CLK_SEL_S))
#define APB_CTRL_SOC_CLK_SEL_V 0x3
#define APB_CTRL_SOC_CLK_SEL_S 14
#define APB_CTRL_SOC_CLK_SEL_XTL 0
#define APB_CTRL_SOC_CLK_SEL_PLL 1
#define APB_CTRL_SOC_CLK_SEL_8M 2
#define APB_CTRL_SOC_CLK_SEL_APLL 3
/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_RST_TICK_CNT (BIT(12))
#define APB_CTRL_RST_TICK_CNT_M (BIT(12))
#define APB_CTRL_RST_TICK_CNT_V 0x1
#define APB_CTRL_RST_TICK_CNT_S 12
/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_CLK_EN (BIT(11))
#define APB_CTRL_CLK_EN_M (BIT(11))
#define APB_CTRL_CLK_EN_V 0x1
#define APB_CTRL_CLK_EN_S 11
/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_CLK_320M_EN (BIT(10))
#define APB_CTRL_CLK_320M_EN_M (BIT(10))
#define APB_CTRL_CLK_320M_EN_V 0x1
#define APB_CTRL_CLK_320M_EN_S 10
/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
/*description: */
#define APB_CTRL_PRE_DIV_CNT 0x000003FF
#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S))
#define APB_CTRL_PRE_DIV_CNT_V 0x3FF
#define APB_CTRL_PRE_DIV_CNT_S 0
#define APB_CTRL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x004)
/* APB_CTRL_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
/*description: */
#define APB_CTRL_TICK_ENABLE (BIT(16))
#define APB_CTRL_TICK_ENABLE_M (BIT(16))
#define APB_CTRL_TICK_ENABLE_V 0x1
#define APB_CTRL_TICK_ENABLE_S 16
/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
/*description: */
#define APB_CTRL_CK8M_TICK_NUM 0x000000FF
#define APB_CTRL_CK8M_TICK_NUM_M ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S))
#define APB_CTRL_CK8M_TICK_NUM_V 0xFF
#define APB_CTRL_CK8M_TICK_NUM_S 8
/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
/*description: */
#define APB_CTRL_XTAL_TICK_NUM 0x000000FF
#define APB_CTRL_XTAL_TICK_NUM_M ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S))
#define APB_CTRL_XTAL_TICK_NUM_V 0xFF
#define APB_CTRL_XTAL_TICK_NUM_S 0
#define APB_CTRL_SARADC_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x008)
/* APB_CTRL_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
/*description: force option to xpd sar blocks*/
#define APB_CTRL_SARADC_XPD_SAR_FORCE 0x00000003
#define APB_CTRL_SARADC_XPD_SAR_FORCE_M ((APB_CTRL_SARADC_XPD_SAR_FORCE_V)<<(APB_CTRL_SARADC_XPD_SAR_FORCE_S))
#define APB_CTRL_SARADC_XPD_SAR_FORCE_V 0x3
#define APB_CTRL_SARADC_XPD_SAR_FORCE_S 27
/* APB_CTRL_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data
is from GPIO matrix*/
#define APB_CTRL_SARADC_DATA_TO_I2S (BIT(26))
#define APB_CTRL_SARADC_DATA_TO_I2S_M (BIT(26))
#define APB_CTRL_SARADC_DATA_TO_I2S_V 0x1
#define APB_CTRL_SARADC_DATA_TO_I2S_S 26
/* APB_CTRL_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data
in this case the resolution should not be larger than 11 bits.*/
#define APB_CTRL_SARADC_DATA_SAR_SEL (BIT(25))
#define APB_CTRL_SARADC_DATA_SAR_SEL_M (BIT(25))
#define APB_CTRL_SARADC_DATA_SAR_SEL_V 0x1
#define APB_CTRL_SARADC_DATA_SAR_SEL_S 25
/* APB_CTRL_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */
/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/
#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR (BIT(24))
#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24))
#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_V 0x1
#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_S 24
/* APB_CTRL_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/
#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR (BIT(23))
#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_M (BIT(23))
#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_V 0x1
#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_S 23
/* APB_CTRL_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */
/*description: 0 ~ 15 means length 1 ~ 16*/
#define APB_CTRL_SARADC_SAR2_PATT_LEN 0x0000000F
#define APB_CTRL_SARADC_SAR2_PATT_LEN_M ((APB_CTRL_SARADC_SAR2_PATT_LEN_V)<<(APB_CTRL_SARADC_SAR2_PATT_LEN_S))
#define APB_CTRL_SARADC_SAR2_PATT_LEN_V 0xF
#define APB_CTRL_SARADC_SAR2_PATT_LEN_S 19
/* APB_CTRL_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */
/*description: 0 ~ 15 means length 1 ~ 16*/
#define APB_CTRL_SARADC_SAR1_PATT_LEN 0x0000000F
#define APB_CTRL_SARADC_SAR1_PATT_LEN_M ((APB_CTRL_SARADC_SAR1_PATT_LEN_V)<<(APB_CTRL_SARADC_SAR1_PATT_LEN_S))
#define APB_CTRL_SARADC_SAR1_PATT_LEN_V 0xF
#define APB_CTRL_SARADC_SAR1_PATT_LEN_S 15
/* APB_CTRL_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
/*description: SAR clock divider*/
#define APB_CTRL_SARADC_SAR_CLK_DIV 0x000000FF
#define APB_CTRL_SARADC_SAR_CLK_DIV_M ((APB_CTRL_SARADC_SAR_CLK_DIV_V)<<(APB_CTRL_SARADC_SAR_CLK_DIV_S))
#define APB_CTRL_SARADC_SAR_CLK_DIV_V 0xFF
#define APB_CTRL_SARADC_SAR_CLK_DIV_S 7
/* APB_CTRL_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_SARADC_SAR_CLK_GATED (BIT(6))
#define APB_CTRL_SARADC_SAR_CLK_GATED_M (BIT(6))
#define APB_CTRL_SARADC_SAR_CLK_GATED_V 0x1
#define APB_CTRL_SARADC_SAR_CLK_GATED_S 6
/* APB_CTRL_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */
/*description: 0: SAR1 1: SAR2 only work for single SAR mode*/
#define APB_CTRL_SARADC_SAR_SEL (BIT(5))
#define APB_CTRL_SARADC_SAR_SEL_M (BIT(5))
#define APB_CTRL_SARADC_SAR_SEL_V 0x1
#define APB_CTRL_SARADC_SAR_SEL_S 5
/* APB_CTRL_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
/*description: 0: single mode 1: double mode 2: alternate mode*/
#define APB_CTRL_SARADC_WORK_MODE 0x00000003
#define APB_CTRL_SARADC_WORK_MODE_M ((APB_CTRL_SARADC_WORK_MODE_V)<<(APB_CTRL_SARADC_WORK_MODE_S))
#define APB_CTRL_SARADC_WORK_MODE_V 0x3
#define APB_CTRL_SARADC_WORK_MODE_S 3
/* APB_CTRL_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
/*description: */
#define APB_CTRL_SARADC_START (BIT(1))
#define APB_CTRL_SARADC_START_M (BIT(1))
#define APB_CTRL_SARADC_START_V 0x1
#define APB_CTRL_SARADC_START_S 1
/* APB_CTRL_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: */
#define APB_CTRL_SARADC_START_FORCE (BIT(0))
#define APB_CTRL_SARADC_START_FORCE_M (BIT(0))
#define APB_CTRL_SARADC_START_FORCE_V 0x1
#define APB_CTRL_SARADC_START_FORCE_S 0
#define APB_CTRL_SARADC_CTRL2_REG (DR_REG_APB_CTRL_BASE + 0x00C)
/* APB_CTRL_SARADC_TIMER_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
/*description: to enable saradc timer trigger*/
#define APB_CTRL_SARADC_TIMER_EN (BIT(20))
#define APB_CTRL_SARADC_TIMER_EN_M (BIT(20))
#define APB_CTRL_SARADC_TIMER_EN_V 0x1
#define APB_CTRL_SARADC_TIMER_EN_S 20
/* APB_CTRL_SARADC_TIMER_TARGET : R/W ;bitpos:[19:12] ;default: 8'd10 ; */
/*description: to set saradc timer target*/
#define APB_CTRL_SARADC_TIMER_TARGET 0x000000FF
#define APB_CTRL_SARADC_TIMER_TARGET_M ((APB_CTRL_SARADC_TIMER_TARGET_V)<<(APB_CTRL_SARADC_TIMER_TARGET_S))
#define APB_CTRL_SARADC_TIMER_TARGET_V 0xFF
#define APB_CTRL_SARADC_TIMER_TARGET_S 12
/* APB_CTRL_SARADC_TIMER_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
/*description: 1: select saradc timer 0: i2s_ws trigger*/
#define APB_CTRL_SARADC_TIMER_SEL (BIT(11))
#define APB_CTRL_SARADC_TIMER_SEL_M (BIT(11))
#define APB_CTRL_SARADC_TIMER_SEL_V 0x1
#define APB_CTRL_SARADC_TIMER_SEL_S 11
/* APB_CTRL_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
/*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/
#define APB_CTRL_SARADC_SAR2_INV (BIT(10))
#define APB_CTRL_SARADC_SAR2_INV_M (BIT(10))
#define APB_CTRL_SARADC_SAR2_INV_V 0x1
#define APB_CTRL_SARADC_SAR2_INV_S 10
/* APB_CTRL_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
/*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/
#define APB_CTRL_SARADC_SAR1_INV (BIT(9))
#define APB_CTRL_SARADC_SAR1_INV_M (BIT(9))
#define APB_CTRL_SARADC_SAR1_INV_V 0x1
#define APB_CTRL_SARADC_SAR1_INV_S 9
/* APB_CTRL_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
/*description: max conversion number*/
#define APB_CTRL_SARADC_MAX_MEAS_NUM 0x000000FF
#define APB_CTRL_SARADC_MAX_MEAS_NUM_M ((APB_CTRL_SARADC_MAX_MEAS_NUM_V)<<(APB_CTRL_SARADC_MAX_MEAS_NUM_S))
#define APB_CTRL_SARADC_MAX_MEAS_NUM_V 0xFF
#define APB_CTRL_SARADC_MAX_MEAS_NUM_S 1
/* APB_CTRL_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: */
#define APB_CTRL_SARADC_MEAS_NUM_LIMIT (BIT(0))
#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_M (BIT(0))
#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_V 0x1
#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_S 0
#define APB_CTRL_SARADC_FSM_REG (DR_REG_APB_CTRL_BASE + 0x010)
/* APB_CTRL_SARADC_SAMPLE_CYCLE : R/W ;bitpos:[31:24] ;default: 8'd2 ; */
/*description: sample cycles*/
#define APB_CTRL_SARADC_SAMPLE_CYCLE 0x000000FF
#define APB_CTRL_SARADC_SAMPLE_CYCLE_M ((APB_CTRL_SARADC_SAMPLE_CYCLE_V)<<(APB_CTRL_SARADC_SAMPLE_CYCLE_S))
#define APB_CTRL_SARADC_SAMPLE_CYCLE_V 0xFF
#define APB_CTRL_SARADC_SAMPLE_CYCLE_S 24
/* APB_CTRL_SARADC_SAMPLE_NUM : R/W ;bitpos:[23:16] ;default: 8'd0 ; */
/*description: sample number*/
#define APB_CTRL_SARADC_SAMPLE_NUM 0x000000FF
#define APB_CTRL_SARADC_SAMPLE_NUM_M ((APB_CTRL_SARADC_SAMPLE_NUM_V)<<(APB_CTRL_SARADC_SAMPLE_NUM_S))
#define APB_CTRL_SARADC_SAMPLE_NUM_V 0xFF
#define APB_CTRL_SARADC_SAMPLE_NUM_S 16
#define APB_CTRL_SARADC_FSM_WAIT_REG (DR_REG_APB_CTRL_BASE + 0x014)
/* APB_CTRL_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */
/*description: */
#define APB_CTRL_SARADC_STANDBY_WAIT 0x000000FF
#define APB_CTRL_SARADC_STANDBY_WAIT_M ((APB_CTRL_SARADC_STANDBY_WAIT_V)<<(APB_CTRL_SARADC_STANDBY_WAIT_S))
#define APB_CTRL_SARADC_STANDBY_WAIT_V 0xFF
#define APB_CTRL_SARADC_STANDBY_WAIT_S 16
/* APB_CTRL_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */
/*description: */
#define APB_CTRL_SARADC_RSTB_WAIT 0x000000FF
#define APB_CTRL_SARADC_RSTB_WAIT_M ((APB_CTRL_SARADC_RSTB_WAIT_V)<<(APB_CTRL_SARADC_RSTB_WAIT_S))
#define APB_CTRL_SARADC_RSTB_WAIT_V 0xFF
#define APB_CTRL_SARADC_RSTB_WAIT_S 8
/* APB_CTRL_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
/*description: */
#define APB_CTRL_SARADC_XPD_WAIT 0x000000FF
#define APB_CTRL_SARADC_XPD_WAIT_M ((APB_CTRL_SARADC_XPD_WAIT_V)<<(APB_CTRL_SARADC_XPD_WAIT_S))
#define APB_CTRL_SARADC_XPD_WAIT_V 0xFF
#define APB_CTRL_SARADC_XPD_WAIT_S 0
#define APB_CTRL_SARADC_SAR1_STATUS_REG (DR_REG_APB_CTRL_BASE + 0x018)
/* APB_CTRL_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define APB_CTRL_SARADC_SAR1_STATUS 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR1_STATUS_M ((APB_CTRL_SARADC_SAR1_STATUS_V)<<(APB_CTRL_SARADC_SAR1_STATUS_S))
#define APB_CTRL_SARADC_SAR1_STATUS_V 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR1_STATUS_S 0
#define APB_CTRL_SARADC_SAR2_STATUS_REG (DR_REG_APB_CTRL_BASE + 0x01C)
/* APB_CTRL_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define APB_CTRL_SARADC_SAR2_STATUS 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR2_STATUS_M ((APB_CTRL_SARADC_SAR2_STATUS_V)<<(APB_CTRL_SARADC_SAR2_STATUS_S))
#define APB_CTRL_SARADC_SAR2_STATUS_V 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR2_STATUS_S 0
#define APB_CTRL_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_CTRL_BASE + 0x020)
/* APB_CTRL_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/
#define APB_CTRL_SARADC_SAR1_PATT_TAB1 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR1_PATT_TAB1_M ((APB_CTRL_SARADC_SAR1_PATT_TAB1_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB1_S))
#define APB_CTRL_SARADC_SAR1_PATT_TAB1_V 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR1_PATT_TAB1_S 0
#define APB_CTRL_SARADC_SAR1_PATT_TAB2_REG (DR_REG_APB_CTRL_BASE + 0x024)
/* APB_CTRL_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/
#define APB_CTRL_SARADC_SAR1_PATT_TAB2 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR1_PATT_TAB2_M ((APB_CTRL_SARADC_SAR1_PATT_TAB2_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB2_S))
#define APB_CTRL_SARADC_SAR1_PATT_TAB2_V 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR1_PATT_TAB2_S 0
#define APB_CTRL_SARADC_SAR1_PATT_TAB3_REG (DR_REG_APB_CTRL_BASE + 0x028)
/* APB_CTRL_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/
#define APB_CTRL_SARADC_SAR1_PATT_TAB3 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR1_PATT_TAB3_M ((APB_CTRL_SARADC_SAR1_PATT_TAB3_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB3_S))
#define APB_CTRL_SARADC_SAR1_PATT_TAB3_V 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR1_PATT_TAB3_S 0
#define APB_CTRL_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_CTRL_BASE + 0x02C)
/* APB_CTRL_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/
#define APB_CTRL_SARADC_SAR1_PATT_TAB4 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR1_PATT_TAB4_M ((APB_CTRL_SARADC_SAR1_PATT_TAB4_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB4_S))
#define APB_CTRL_SARADC_SAR1_PATT_TAB4_V 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR1_PATT_TAB4_S 0
#define APB_CTRL_SARADC_SAR2_PATT_TAB1_REG (DR_REG_APB_CTRL_BASE + 0x030)
/* APB_CTRL_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/
#define APB_CTRL_SARADC_SAR2_PATT_TAB1 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR2_PATT_TAB1_M ((APB_CTRL_SARADC_SAR2_PATT_TAB1_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB1_S))
#define APB_CTRL_SARADC_SAR2_PATT_TAB1_V 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR2_PATT_TAB1_S 0
#define APB_CTRL_SARADC_SAR2_PATT_TAB2_REG (DR_REG_APB_CTRL_BASE + 0x034)
/* APB_CTRL_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/
#define APB_CTRL_SARADC_SAR2_PATT_TAB2 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR2_PATT_TAB2_M ((APB_CTRL_SARADC_SAR2_PATT_TAB2_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB2_S))
#define APB_CTRL_SARADC_SAR2_PATT_TAB2_V 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR2_PATT_TAB2_S 0
#define APB_CTRL_SARADC_SAR2_PATT_TAB3_REG (DR_REG_APB_CTRL_BASE + 0x038)
/* APB_CTRL_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/
#define APB_CTRL_SARADC_SAR2_PATT_TAB3 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR2_PATT_TAB3_M ((APB_CTRL_SARADC_SAR2_PATT_TAB3_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB3_S))
#define APB_CTRL_SARADC_SAR2_PATT_TAB3_V 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR2_PATT_TAB3_S 0
#define APB_CTRL_SARADC_SAR2_PATT_TAB4_REG (DR_REG_APB_CTRL_BASE + 0x03C)
/* APB_CTRL_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/
#define APB_CTRL_SARADC_SAR2_PATT_TAB4 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR2_PATT_TAB4_M ((APB_CTRL_SARADC_SAR2_PATT_TAB4_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB4_S))
#define APB_CTRL_SARADC_SAR2_PATT_TAB4_V 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR2_PATT_TAB4_S 0
#define APB_CTRL_ADC_ARB_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x040)
/* APB_CTRL_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: adc2 arbiter uses fixed priority*/
#define APB_CTRL_ADC_ARB_FIX_PRIORITY (BIT(12))
#define APB_CTRL_ADC_ARB_FIX_PRIORITY_M (BIT(12))
#define APB_CTRL_ADC_ARB_FIX_PRIORITY_V 0x1
#define APB_CTRL_ADC_ARB_FIX_PRIORITY_S 12
/* APB_CTRL_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */
/*description: Set adc2 arbiter wifi priority*/
#define APB_CTRL_ADC_ARB_WIFI_PRIORITY 0x00000003
#define APB_CTRL_ADC_ARB_WIFI_PRIORITY_M ((APB_CTRL_ADC_ARB_WIFI_PRIORITY_V)<<(APB_CTRL_ADC_ARB_WIFI_PRIORITY_S))
#define APB_CTRL_ADC_ARB_WIFI_PRIORITY_V 0x3
#define APB_CTRL_ADC_ARB_WIFI_PRIORITY_S 10
/* APB_CTRL_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */
/*description: Set adc2 arbiter rtc priority*/
#define APB_CTRL_ADC_ARB_RTC_PRIORITY 0x00000003
#define APB_CTRL_ADC_ARB_RTC_PRIORITY_M ((APB_CTRL_ADC_ARB_RTC_PRIORITY_V)<<(APB_CTRL_ADC_ARB_RTC_PRIORITY_S))
#define APB_CTRL_ADC_ARB_RTC_PRIORITY_V 0x3
#define APB_CTRL_ADC_ARB_RTC_PRIORITY_S 8
/* APB_CTRL_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
/*description: Set adc2 arbiter apb priority*/
#define APB_CTRL_ADC_ARB_APB_PRIORITY 0x00000003
#define APB_CTRL_ADC_ARB_APB_PRIORITY_M ((APB_CTRL_ADC_ARB_APB_PRIORITY_V)<<(APB_CTRL_ADC_ARB_APB_PRIORITY_S))
#define APB_CTRL_ADC_ARB_APB_PRIORITY_V 0x3
#define APB_CTRL_ADC_ARB_APB_PRIORITY_S 6
/* APB_CTRL_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: adc2 arbiter force grant*/
#define APB_CTRL_ADC_ARB_GRANT_FORCE (BIT(5))
#define APB_CTRL_ADC_ARB_GRANT_FORCE_M (BIT(5))
#define APB_CTRL_ADC_ARB_GRANT_FORCE_V 0x1
#define APB_CTRL_ADC_ARB_GRANT_FORCE_S 5
/* APB_CTRL_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enable wifi controller*/
#define APB_CTRL_ADC_ARB_WIFI_FORCE (BIT(4))
#define APB_CTRL_ADC_ARB_WIFI_FORCE_M (BIT(4))
#define APB_CTRL_ADC_ARB_WIFI_FORCE_V 0x1
#define APB_CTRL_ADC_ARB_WIFI_FORCE_S 4
/* APB_CTRL_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enable rtc controller*/
#define APB_CTRL_ADC_ARB_RTC_FORCE (BIT(3))
#define APB_CTRL_ADC_ARB_RTC_FORCE_M (BIT(3))
#define APB_CTRL_ADC_ARB_RTC_FORCE_V 0x1
#define APB_CTRL_ADC_ARB_RTC_FORCE_S 3
/* APB_CTRL_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enable apb controller*/
#define APB_CTRL_ADC_ARB_APB_FORCE (BIT(2))
#define APB_CTRL_ADC_ARB_APB_FORCE_M (BIT(2))
#define APB_CTRL_ADC_ARB_APB_FORCE_V 0x1
#define APB_CTRL_ADC_ARB_APB_FORCE_S 2
#define APB_CTRL_CLK_OUT_EN_REG (DR_REG_APB_CTRL_BASE + 0x044)
/* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK_XTAL_OEN (BIT(10))
#define APB_CTRL_CLK_XTAL_OEN_M (BIT(10))
#define APB_CTRL_CLK_XTAL_OEN_V 0x1
#define APB_CTRL_CLK_XTAL_OEN_S 10
/* APB_CTRL_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK40X_BB_OEN (BIT(9))
#define APB_CTRL_CLK40X_BB_OEN_M (BIT(9))
#define APB_CTRL_CLK40X_BB_OEN_V 0x1
#define APB_CTRL_CLK40X_BB_OEN_S 9
/* APB_CTRL_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK_DAC_CPU_OEN (BIT(8))
#define APB_CTRL_CLK_DAC_CPU_OEN_M (BIT(8))
#define APB_CTRL_CLK_DAC_CPU_OEN_V 0x1
#define APB_CTRL_CLK_DAC_CPU_OEN_S 8
/* APB_CTRL_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK_ADC_INF_OEN (BIT(7))
#define APB_CTRL_CLK_ADC_INF_OEN_M (BIT(7))
#define APB_CTRL_CLK_ADC_INF_OEN_V 0x1
#define APB_CTRL_CLK_ADC_INF_OEN_S 7
/* APB_CTRL_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK_320M_OEN (BIT(6))
#define APB_CTRL_CLK_320M_OEN_M (BIT(6))
#define APB_CTRL_CLK_320M_OEN_V 0x1
#define APB_CTRL_CLK_320M_OEN_S 6
/* APB_CTRL_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK160_OEN (BIT(5))
#define APB_CTRL_CLK160_OEN_M (BIT(5))
#define APB_CTRL_CLK160_OEN_V 0x1
#define APB_CTRL_CLK160_OEN_S 5
/* APB_CTRL_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK80_OEN (BIT(4))
#define APB_CTRL_CLK80_OEN_M (BIT(4))
#define APB_CTRL_CLK80_OEN_V 0x1
#define APB_CTRL_CLK80_OEN_S 4
/* APB_CTRL_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK_BB_OEN (BIT(3))
#define APB_CTRL_CLK_BB_OEN_M (BIT(3))
#define APB_CTRL_CLK_BB_OEN_V 0x1
#define APB_CTRL_CLK_BB_OEN_S 3
/* APB_CTRL_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK44_OEN (BIT(2))
#define APB_CTRL_CLK44_OEN_M (BIT(2))
#define APB_CTRL_CLK44_OEN_V 0x1
#define APB_CTRL_CLK44_OEN_S 2
/* APB_CTRL_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK22_OEN (BIT(1))
#define APB_CTRL_CLK22_OEN_M (BIT(1))
#define APB_CTRL_CLK22_OEN_V 0x1
#define APB_CTRL_CLK22_OEN_S 1
/* APB_CTRL_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK20_OEN (BIT(0))
#define APB_CTRL_CLK20_OEN_M (BIT(0))
#define APB_CTRL_CLK20_OEN_V 0x1
#define APB_CTRL_CLK20_OEN_S 0
#define APB_CTRL_HOST_INF_SEL_REG (DR_REG_APB_CTRL_BASE + 0x048)
/* APB_CTRL_SPI_PRIOR : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_SPI_PRIOR (BIT(13))
#define APB_CTRL_SPI_PRIOR_M (BIT(13))
#define APB_CTRL_SPI_PRIOR_V 0x1
#define APB_CTRL_SPI_PRIOR_S 13
/* APB_CTRL_SPI1_HOLD : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_SPI1_HOLD (BIT(9))
#define APB_CTRL_SPI1_HOLD_M (BIT(9))
#define APB_CTRL_SPI1_HOLD_V 0x1
#define APB_CTRL_SPI1_HOLD_S 9
/* APB_CTRL_SPI0_HOLD : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_SPI0_HOLD (BIT(8))
#define APB_CTRL_SPI0_HOLD_M (BIT(8))
#define APB_CTRL_SPI0_HOLD_V 0x1
#define APB_CTRL_SPI0_HOLD_S 8
/* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define APB_CTRL_PERI_IO_SWAP 0x000000FF
#define APB_CTRL_PERI_IO_SWAP_M ((APB_CTRL_PERI_IO_SWAP_V)<<(APB_CTRL_PERI_IO_SWAP_S))
#define APB_CTRL_PERI_IO_SWAP_V 0xFF
#define APB_CTRL_PERI_IO_SWAP_S 0
#define APB_CTRL_EXT_MEM_PMS_LOCK_REG (DR_REG_APB_CTRL_BASE + 0x04C)
/* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_EXT_MEM_PMS_LOCK (BIT(0))
#define APB_CTRL_EXT_MEM_PMS_LOCK_M (BIT(0))
#define APB_CTRL_EXT_MEM_PMS_LOCK_V 0x1
#define APB_CTRL_EXT_MEM_PMS_LOCK_S 0
#define APB_CTRL_FLASH_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x050)
/* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_FLASH_ACE0_ATTR 0x00000007
#define APB_CTRL_FLASH_ACE0_ATTR_M ((APB_CTRL_FLASH_ACE0_ATTR_V)<<(APB_CTRL_FLASH_ACE0_ATTR_S))
#define APB_CTRL_FLASH_ACE0_ATTR_V 0x7
#define APB_CTRL_FLASH_ACE0_ATTR_S 0
#define APB_CTRL_FLASH_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x054)
/* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_FLASH_ACE1_ATTR 0x00000007
#define APB_CTRL_FLASH_ACE1_ATTR_M ((APB_CTRL_FLASH_ACE1_ATTR_V)<<(APB_CTRL_FLASH_ACE1_ATTR_S))
#define APB_CTRL_FLASH_ACE1_ATTR_V 0x7
#define APB_CTRL_FLASH_ACE1_ATTR_S 0
#define APB_CTRL_FLASH_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x058)
/* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_FLASH_ACE2_ATTR 0x00000007
#define APB_CTRL_FLASH_ACE2_ATTR_M ((APB_CTRL_FLASH_ACE2_ATTR_V)<<(APB_CTRL_FLASH_ACE2_ATTR_S))
#define APB_CTRL_FLASH_ACE2_ATTR_V 0x7
#define APB_CTRL_FLASH_ACE2_ATTR_S 0
#define APB_CTRL_FLASH_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x05C)
/* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_FLASH_ACE3_ATTR 0x00000007
#define APB_CTRL_FLASH_ACE3_ATTR_M ((APB_CTRL_FLASH_ACE3_ATTR_V)<<(APB_CTRL_FLASH_ACE3_ATTR_S))
#define APB_CTRL_FLASH_ACE3_ATTR_V 0x7
#define APB_CTRL_FLASH_ACE3_ATTR_S 0
#define APB_CTRL_FLASH_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x060)
/* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_FLASH_ACE0_ADDR_S 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE0_ADDR_S_M ((APB_CTRL_FLASH_ACE0_ADDR_S_V)<<(APB_CTRL_FLASH_ACE0_ADDR_S_S))
#define APB_CTRL_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE0_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x064)
/* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE1_ADDR_S 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE1_ADDR_S_M ((APB_CTRL_FLASH_ACE1_ADDR_S_V)<<(APB_CTRL_FLASH_ACE1_ADDR_S_S))
#define APB_CTRL_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE1_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x068)
/* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE2_ADDR_S 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE2_ADDR_S_M ((APB_CTRL_FLASH_ACE2_ADDR_S_V)<<(APB_CTRL_FLASH_ACE2_ADDR_S_S))
#define APB_CTRL_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE2_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x06C)
/* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE3_ADDR_S 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE3_ADDR_S_M ((APB_CTRL_FLASH_ACE3_ADDR_S_V)<<(APB_CTRL_FLASH_ACE3_ADDR_S_S))
#define APB_CTRL_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE3_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x070)
/* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE0_SIZE 0x0000FFFF
#define APB_CTRL_FLASH_ACE0_SIZE_M ((APB_CTRL_FLASH_ACE0_SIZE_V)<<(APB_CTRL_FLASH_ACE0_SIZE_S))
#define APB_CTRL_FLASH_ACE0_SIZE_V 0xFFFF
#define APB_CTRL_FLASH_ACE0_SIZE_S 0
#define APB_CTRL_FLASH_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x074)
/* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE1_SIZE 0x0000FFFF
#define APB_CTRL_FLASH_ACE1_SIZE_M ((APB_CTRL_FLASH_ACE1_SIZE_V)<<(APB_CTRL_FLASH_ACE1_SIZE_S))
#define APB_CTRL_FLASH_ACE1_SIZE_V 0xFFFF
#define APB_CTRL_FLASH_ACE1_SIZE_S 0
#define APB_CTRL_FLASH_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x078)
/* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE2_SIZE 0x0000FFFF
#define APB_CTRL_FLASH_ACE2_SIZE_M ((APB_CTRL_FLASH_ACE2_SIZE_V)<<(APB_CTRL_FLASH_ACE2_SIZE_S))
#define APB_CTRL_FLASH_ACE2_SIZE_V 0xFFFF
#define APB_CTRL_FLASH_ACE2_SIZE_S 0
#define APB_CTRL_FLASH_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x07C)
/* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE3_SIZE 0x0000FFFF
#define APB_CTRL_FLASH_ACE3_SIZE_M ((APB_CTRL_FLASH_ACE3_SIZE_V)<<(APB_CTRL_FLASH_ACE3_SIZE_S))
#define APB_CTRL_FLASH_ACE3_SIZE_V 0xFFFF
#define APB_CTRL_FLASH_ACE3_SIZE_S 0
#define APB_CTRL_SRAM_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x080)
/* APB_CTRL_SRAM_ACE0_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_SRAM_ACE0_ATTR 0x00000007
#define APB_CTRL_SRAM_ACE0_ATTR_M ((APB_CTRL_SRAM_ACE0_ATTR_V)<<(APB_CTRL_SRAM_ACE0_ATTR_S))
#define APB_CTRL_SRAM_ACE0_ATTR_V 0x7
#define APB_CTRL_SRAM_ACE0_ATTR_S 0
#define APB_CTRL_SRAM_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x084)
/* APB_CTRL_SRAM_ACE1_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_SRAM_ACE1_ATTR 0x00000007
#define APB_CTRL_SRAM_ACE1_ATTR_M ((APB_CTRL_SRAM_ACE1_ATTR_V)<<(APB_CTRL_SRAM_ACE1_ATTR_S))
#define APB_CTRL_SRAM_ACE1_ATTR_V 0x7
#define APB_CTRL_SRAM_ACE1_ATTR_S 0
#define APB_CTRL_SRAM_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x088)
/* APB_CTRL_SRAM_ACE2_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_SRAM_ACE2_ATTR 0x00000007
#define APB_CTRL_SRAM_ACE2_ATTR_M ((APB_CTRL_SRAM_ACE2_ATTR_V)<<(APB_CTRL_SRAM_ACE2_ATTR_S))
#define APB_CTRL_SRAM_ACE2_ATTR_V 0x7
#define APB_CTRL_SRAM_ACE2_ATTR_S 0
#define APB_CTRL_SRAM_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x08C)
/* APB_CTRL_SRAM_ACE3_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_SRAM_ACE3_ATTR 0x00000007
#define APB_CTRL_SRAM_ACE3_ATTR_M ((APB_CTRL_SRAM_ACE3_ATTR_V)<<(APB_CTRL_SRAM_ACE3_ATTR_S))
#define APB_CTRL_SRAM_ACE3_ATTR_V 0x7
#define APB_CTRL_SRAM_ACE3_ATTR_S 0
#define APB_CTRL_SRAM_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x090)
/* APB_CTRL_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_SRAM_ACE0_ADDR_S 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE0_ADDR_S_M ((APB_CTRL_SRAM_ACE0_ADDR_S_V)<<(APB_CTRL_SRAM_ACE0_ADDR_S_S))
#define APB_CTRL_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE0_ADDR_S_S 0
#define APB_CTRL_SRAM_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x094)
/* APB_CTRL_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
/*description: */
#define APB_CTRL_SRAM_ACE1_ADDR_S 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE1_ADDR_S_M ((APB_CTRL_SRAM_ACE1_ADDR_S_V)<<(APB_CTRL_SRAM_ACE1_ADDR_S_S))
#define APB_CTRL_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE1_ADDR_S_S 0
#define APB_CTRL_SRAM_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x098)
/* APB_CTRL_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
/*description: */
#define APB_CTRL_SRAM_ACE2_ADDR_S 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE2_ADDR_S_M ((APB_CTRL_SRAM_ACE2_ADDR_S_V)<<(APB_CTRL_SRAM_ACE2_ADDR_S_S))
#define APB_CTRL_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE2_ADDR_S_S 0
#define APB_CTRL_SRAM_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x09C)
/* APB_CTRL_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
/*description: */
#define APB_CTRL_SRAM_ACE3_ADDR_S 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE3_ADDR_S_M ((APB_CTRL_SRAM_ACE3_ADDR_S_V)<<(APB_CTRL_SRAM_ACE3_ADDR_S_S))
#define APB_CTRL_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE3_ADDR_S_S 0
#define APB_CTRL_SRAM_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x0A0)
/* APB_CTRL_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_SRAM_ACE0_SIZE 0x0000FFFF
#define APB_CTRL_SRAM_ACE0_SIZE_M ((APB_CTRL_SRAM_ACE0_SIZE_V)<<(APB_CTRL_SRAM_ACE0_SIZE_S))
#define APB_CTRL_SRAM_ACE0_SIZE_V 0xFFFF
#define APB_CTRL_SRAM_ACE0_SIZE_S 0
#define APB_CTRL_SRAM_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x0A4)
/* APB_CTRL_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_SRAM_ACE1_SIZE 0x0000FFFF
#define APB_CTRL_SRAM_ACE1_SIZE_M ((APB_CTRL_SRAM_ACE1_SIZE_V)<<(APB_CTRL_SRAM_ACE1_SIZE_S))
#define APB_CTRL_SRAM_ACE1_SIZE_V 0xFFFF
#define APB_CTRL_SRAM_ACE1_SIZE_S 0
#define APB_CTRL_SRAM_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x0A8)
/* APB_CTRL_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_SRAM_ACE2_SIZE 0x0000FFFF
#define APB_CTRL_SRAM_ACE2_SIZE_M ((APB_CTRL_SRAM_ACE2_SIZE_V)<<(APB_CTRL_SRAM_ACE2_SIZE_S))
#define APB_CTRL_SRAM_ACE2_SIZE_V 0xFFFF
#define APB_CTRL_SRAM_ACE2_SIZE_S 0
#define APB_CTRL_SRAM_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x0AC)
/* APB_CTRL_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_SRAM_ACE3_SIZE 0x0000FFFF
#define APB_CTRL_SRAM_ACE3_SIZE_M ((APB_CTRL_SRAM_ACE3_SIZE_V)<<(APB_CTRL_SRAM_ACE3_SIZE_S))
#define APB_CTRL_SRAM_ACE3_SIZE_V 0xFFFF
#define APB_CTRL_SRAM_ACE3_SIZE_S 0
#define APB_CTRL_SPI0_PMS_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x0B0)
/* APB_CTRL_SPI0_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
/*description: */
#define APB_CTRL_SPI0_REJECT_CDE 0x0000001F
#define APB_CTRL_SPI0_REJECT_CDE_M ((APB_CTRL_SPI0_REJECT_CDE_V)<<(APB_CTRL_SPI0_REJECT_CDE_S))
#define APB_CTRL_SPI0_REJECT_CDE_V 0x1F
#define APB_CTRL_SPI0_REJECT_CDE_S 2
/* APB_CTRL_SPI0_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_SPI0_REJECT_CLR (BIT(1))
#define APB_CTRL_SPI0_REJECT_CLR_M (BIT(1))
#define APB_CTRL_SPI0_REJECT_CLR_V 0x1
#define APB_CTRL_SPI0_REJECT_CLR_S 1
/* APB_CTRL_SPI0_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_SPI0_REJECT_INT (BIT(0))
#define APB_CTRL_SPI0_REJECT_INT_M (BIT(0))
#define APB_CTRL_SPI0_REJECT_INT_V 0x1
#define APB_CTRL_SPI0_REJECT_INT_S 0
#define APB_CTRL_SPI0_REJECT_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x0B4)
/* APB_CTRL_SPI0_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_SPI0_REJECT_ADDR 0xFFFFFFFF
#define APB_CTRL_SPI0_REJECT_ADDR_M ((APB_CTRL_SPI0_REJECT_ADDR_V)<<(APB_CTRL_SPI0_REJECT_ADDR_S))
#define APB_CTRL_SPI0_REJECT_ADDR_V 0xFFFFFFFF
#define APB_CTRL_SPI0_REJECT_ADDR_S 0
#define APB_CTRL_SPI1_PMS_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x0B8)
/* APB_CTRL_SPI1_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
/*description: */
#define APB_CTRL_SPI1_REJECT_CDE 0x0000001F
#define APB_CTRL_SPI1_REJECT_CDE_M ((APB_CTRL_SPI1_REJECT_CDE_V)<<(APB_CTRL_SPI1_REJECT_CDE_S))
#define APB_CTRL_SPI1_REJECT_CDE_V 0x1F
#define APB_CTRL_SPI1_REJECT_CDE_S 2
/* APB_CTRL_SPI1_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_SPI1_REJECT_CLR (BIT(1))
#define APB_CTRL_SPI1_REJECT_CLR_M (BIT(1))
#define APB_CTRL_SPI1_REJECT_CLR_V 0x1
#define APB_CTRL_SPI1_REJECT_CLR_S 1
/* APB_CTRL_SPI1_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_SPI1_REJECT_INT (BIT(0))
#define APB_CTRL_SPI1_REJECT_INT_M (BIT(0))
#define APB_CTRL_SPI1_REJECT_INT_V 0x1
#define APB_CTRL_SPI1_REJECT_INT_S 0
#define APB_CTRL_SPI1_REJECT_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x0BC)
/* APB_CTRL_SPI1_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_SPI1_REJECT_ADDR 0xFFFFFFFF
#define APB_CTRL_SPI1_REJECT_ADDR_M ((APB_CTRL_SPI1_REJECT_ADDR_V)<<(APB_CTRL_SPI1_REJECT_ADDR_S))
#define APB_CTRL_SPI1_REJECT_ADDR_V 0xFFFFFFFF
#define APB_CTRL_SPI1_REJECT_ADDR_S 0
#define APB_CTRL_SDIO_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x0C0)
/* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define APB_CTRL_SDIO_WIN_ACCESS_EN (BIT(0))
#define APB_CTRL_SDIO_WIN_ACCESS_EN_M (BIT(0))
#define APB_CTRL_SDIO_WIN_ACCESS_EN_V 0x1
#define APB_CTRL_SDIO_WIN_ACCESS_EN_S 0
#define APB_CTRL_REDCY_SIG0_REG (DR_REG_APB_CTRL_BASE + 0x0C4)
/* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define APB_CTRL_REDCY_ANDOR (BIT(31))
#define APB_CTRL_REDCY_ANDOR_M (BIT(31))
#define APB_CTRL_REDCY_ANDOR_V 0x1
#define APB_CTRL_REDCY_ANDOR_S 31
/* APB_CTRL_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
/*description: */
#define APB_CTRL_REDCY_SIG0 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG0_M ((APB_CTRL_REDCY_SIG0_V)<<(APB_CTRL_REDCY_SIG0_S))
#define APB_CTRL_REDCY_SIG0_V 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG0_S 0
#define APB_CTRL_REDCY_SIG1_REG (DR_REG_APB_CTRL_BASE + 0x0C8)
/* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define APB_CTRL_REDCY_NANDOR (BIT(31))
#define APB_CTRL_REDCY_NANDOR_M (BIT(31))
#define APB_CTRL_REDCY_NANDOR_V 0x1
#define APB_CTRL_REDCY_NANDOR_S 31
/* APB_CTRL_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
/*description: */
#define APB_CTRL_REDCY_SIG1 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG1_M ((APB_CTRL_REDCY_SIG1_V)<<(APB_CTRL_REDCY_SIG1_S))
#define APB_CTRL_REDCY_SIG1_V 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG1_S 0
#define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_APB_CTRL_BASE + 0x0CC)
/* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_WIFI_BB_CFG 0xFFFFFFFF
#define APB_CTRL_WIFI_BB_CFG_M ((APB_CTRL_WIFI_BB_CFG_V)<<(APB_CTRL_WIFI_BB_CFG_S))
#define APB_CTRL_WIFI_BB_CFG_V 0xFFFFFFFF
#define APB_CTRL_WIFI_BB_CFG_S 0
#define APB_CTRL_WIFI_BB_CFG_2_REG (DR_REG_APB_CTRL_BASE + 0x0D0)
/* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_WIFI_BB_CFG_2 0xFFFFFFFF
#define APB_CTRL_WIFI_BB_CFG_2_M ((APB_CTRL_WIFI_BB_CFG_2_V)<<(APB_CTRL_WIFI_BB_CFG_2_S))
#define APB_CTRL_WIFI_BB_CFG_2_V 0xFFFFFFFF
#define APB_CTRL_WIFI_BB_CFG_2_S 0
#define APB_CTRL_WIFI_CLK_EN_REG (DR_REG_APB_CTRL_BASE + 0x0D4)
/* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
/*description: */
#define APB_CTRL_WIFI_CLK_EN 0xFFFFFFFF
#define APB_CTRL_WIFI_CLK_EN_M ((APB_CTRL_WIFI_CLK_EN_V)<<(APB_CTRL_WIFI_CLK_EN_S))
#define APB_CTRL_WIFI_CLK_EN_V 0xFFFFFFFF
#define APB_CTRL_WIFI_CLK_EN_S 0
#define APB_CTRL_WIFI_RST_EN_REG (DR_REG_APB_CTRL_BASE + 0x0D8)
/* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_WIFI_RST 0xFFFFFFFF
#define APB_CTRL_WIFI_RST_M ((APB_CTRL_WIFI_RST_V)<<(APB_CTRL_WIFI_RST_S))
#define APB_CTRL_WIFI_RST_V 0xFFFFFFFF
#define APB_CTRL_WIFI_RST_S 0
#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_APB_CTRL_BASE + 0x0DC)
/* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_DC_MEM_FORCE_PD (BIT(5))
#define APB_CTRL_DC_MEM_FORCE_PD_M (BIT(5))
#define APB_CTRL_DC_MEM_FORCE_PD_V 0x1
#define APB_CTRL_DC_MEM_FORCE_PD_S 5
/* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_DC_MEM_FORCE_PU (BIT(4))
#define APB_CTRL_DC_MEM_FORCE_PU_M (BIT(4))
#define APB_CTRL_DC_MEM_FORCE_PU_V 0x1
#define APB_CTRL_DC_MEM_FORCE_PU_S 4
/* APB_CTRL_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_PBUS_MEM_FORCE_PD (BIT(3))
#define APB_CTRL_PBUS_MEM_FORCE_PD_M (BIT(3))
#define APB_CTRL_PBUS_MEM_FORCE_PD_V 0x1
#define APB_CTRL_PBUS_MEM_FORCE_PD_S 3
/* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_PBUS_MEM_FORCE_PU (BIT(2))
#define APB_CTRL_PBUS_MEM_FORCE_PU_M (BIT(2))
#define APB_CTRL_PBUS_MEM_FORCE_PU_V 0x1
#define APB_CTRL_PBUS_MEM_FORCE_PU_S 2
/* APB_CTRL_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_AGC_MEM_FORCE_PD (BIT(1))
#define APB_CTRL_AGC_MEM_FORCE_PD_M (BIT(1))
#define APB_CTRL_AGC_MEM_FORCE_PD_V 0x1
#define APB_CTRL_AGC_MEM_FORCE_PD_S 1
/* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_AGC_MEM_FORCE_PU (BIT(0))
#define APB_CTRL_AGC_MEM_FORCE_PU_M (BIT(0))
#define APB_CTRL_AGC_MEM_FORCE_PU_V 0x1
#define APB_CTRL_AGC_MEM_FORCE_PU_S 0
#define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x3FC)
/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h18102500 ; */
/*description: */
#define APB_CTRL_DATE 0xFFFFFFFF
#define APB_CTRL_DATE_M ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S))
#define APB_CTRL_DATE_V 0xFFFFFFFF
#define APB_CTRL_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_APB_CTRL_REG_H_ */

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components/soc/esp32s2beta/include/soc/apb_ctrl_struct.h Normal file
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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_APB_CTRL_STRUCT_H_
#define _SOC_APB_CTRL_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t pre_div: 10;
uint32_t clk_320m_en: 1;
uint32_t clk_en: 1;
uint32_t rst_tick: 1;
uint32_t reserved13: 1;
uint32_t soc_clk_sel: 2;
uint32_t reserved16: 16;
};
uint32_t val;
} clk_conf;
union {
struct {
uint32_t xtal_tick: 8;
uint32_t ck8m_tick: 8;
uint32_t tick_enable: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} tick_conf;
union {
struct {
uint32_t start_force: 1;
uint32_t start: 1;
uint32_t reserved2: 1;
uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/
uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/
uint32_t sar_clk_gated: 1;
uint32_t sar_clk_div: 8; /*SAR clock divider*/
uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/
uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/
uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/
uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/
uint32_t xpd_sar_force: 2; /*force option to xpd sar blocks*/
uint32_t reserved29: 3;
};
uint32_t val;
} saradc_ctrl;
union {
struct {
uint32_t meas_num_limit: 1;
uint32_t max_meas_num: 8; /*max conversion number*/
uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/
uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/
uint32_t timer_sel: 1; /*1: select saradc timer 0: i2s_ws trigger*/
uint32_t timer_target: 8; /*to set saradc timer target*/
uint32_t timer_en: 1; /*to enable saradc timer trigger*/
uint32_t reserved21: 11;
};
uint32_t val;
} saradc_ctrl2;
union {
struct {
uint32_t reserved0: 16;
uint32_t sample_num: 8; /*sample number*/
uint32_t sample_cycle: 8; /*sample cycles*/
};
uint32_t val;
} saradc_fsm;
union {
struct {
uint32_t xpd_wait: 8;
uint32_t rstb_wait: 8;
uint32_t standby_wait: 8;
uint32_t reserved24: 8;
};
uint32_t val;
} saradc_fsm_wait;
uint32_t saradc_sar1_status; /**/
uint32_t saradc_sar2_status; /**/
uint32_t saradc_sar1_patt_tab1; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/
uint32_t saradc_sar1_patt_tab2; /*Item 4 ~ 7 for pattern table 1 (each item one byte)*/
uint32_t saradc_sar1_patt_tab3; /*Item 8 ~ 11 for pattern table 1 (each item one byte)*/
uint32_t saradc_sar1_patt_tab4; /*Item 12 ~ 15 for pattern table 1 (each item one byte)*/
uint32_t saradc_sar2_patt_tab1; /*item 0 ~ 3 for pattern table 2 (each item one byte)*/
uint32_t saradc_sar2_patt_tab2; /*Item 4 ~ 7 for pattern table 2 (each item one byte)*/
uint32_t saradc_sar2_patt_tab3; /*Item 8 ~ 11 for pattern table 2 (each item one byte)*/
uint32_t saradc_sar2_patt_tab4; /*Item 12 ~ 15 for pattern table 2 (each item one byte)*/
union {
struct {
uint32_t reserved0: 2;
uint32_t adc_arb_apb_force: 1; /*adc2 arbiter force to enableapb controller*/
uint32_t adc_arb_rtc_force: 1; /*adc2 arbiter force to enable rtc controller*/
uint32_t adc_arb_wifi_force: 1; /*adc2 arbiter force to enable wifi controller*/
uint32_t adc_arb_grant_force: 1; /*adc2 arbiter force grant*/
uint32_t adc_arb_apb_priority: 2; /*Set adc2 arbiterapb priority*/
uint32_t adc_arb_rtc_priority: 2; /*Set adc2 arbiter rtc priority*/
uint32_t adc_arb_wifi_priority: 2; /*Set adc2 arbiter wifi priority*/
uint32_t adc_arb_fix_priority: 1; /*adc2 arbiter uses fixed priority*/
uint32_t reserved13: 19;
};
uint32_t val;
} adc_arb_ctrl;
union {
struct {
uint32_t clk20_oen: 1;
uint32_t clk22_oen: 1;
uint32_t clk44_oen: 1;
uint32_t clk_bb_oen: 1;
uint32_t clk80_oen: 1;
uint32_t clk160_oen: 1;
uint32_t clk_320m_oen: 1;
uint32_t clk_adc_inf_oen: 1;
uint32_t clk_dac_cpu_oen: 1;
uint32_t clk40x_bb_oen: 1;
uint32_t clk_xtal_oen: 1;
uint32_t reserved11: 21;
};
uint32_t val;
} clk_out_en;
union {
struct {
uint32_t peri_io_swap: 8;
uint32_t spi0_hold: 1;
uint32_t spi1_hold: 1;
uint32_t reserved10: 3;
uint32_t spi_prior: 1;
uint32_t reserved14: 18;
};
uint32_t val;
} host_inf_sel;
union {
struct {
uint32_t ext_mem_pms_lock: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} ext_mem_pms_lock;
union {
struct {
uint32_t flash_ace0_attr: 3;
uint32_t reserved3: 29;
};
uint32_t val;
} flash_ace0_attr;
union {
struct {
uint32_t flash_ace1_attr: 3;
uint32_t reserved3: 29;
};
uint32_t val;
} flash_ace1_attr;
union {
struct {
uint32_t flash_ace2_attr: 3;
uint32_t reserved3: 29;
};
uint32_t val;
} flash_ace2_attr;
union {
struct {
uint32_t flash_ace3_attr: 3;
uint32_t reserved3: 29;
};
uint32_t val;
} flash_ace3_attr;
uint32_t flash_ace0_addr; /**/
uint32_t flash_ace1_addr; /**/
uint32_t flash_ace2_addr; /**/
uint32_t flash_ace3_addr; /**/
union {
struct {
uint32_t flash_ace0_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
} flash_ace0_size;
union {
struct {
uint32_t flash_ace1_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
} flash_ace1_size;
union {
struct {
uint32_t flash_ace2_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
} flash_ace2_size;
union {
struct {
uint32_t flash_ace3_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
} flash_ace3_size;
union {
struct {
uint32_t sram_ace0_attr: 3;
uint32_t reserved3: 29;
};
uint32_t val;
} sram_ace0_attr;
union {
struct {
uint32_t sram_ace1_attr: 3;
uint32_t reserved3: 29;
};
uint32_t val;
} sram_ace1_attr;
union {
struct {
uint32_t sram_ace2_attr: 3;
uint32_t reserved3: 29;
};
uint32_t val;
} sram_ace2_attr;
union {
struct {
uint32_t sram_ace3_attr: 3;
uint32_t reserved3: 29;
};
uint32_t val;
} sram_ace3_attr;
uint32_t sram_ace0_addr; /**/
uint32_t sram_ace1_addr; /**/
uint32_t sram_ace2_addr; /**/
uint32_t sram_ace3_addr; /**/
union {
struct {
uint32_t sram_ace0_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
} sram_ace0_size;
union {
struct {
uint32_t sram_ace1_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
} sram_ace1_size;
union {
struct {
uint32_t sram_ace2_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
} sram_ace2_size;
union {
struct {
uint32_t sram_ace3_size:16;
uint32_t reserved16: 16;
};
uint32_t val;
} sram_ace3_size;
union {
struct {
uint32_t spi0_reject_int: 1;
uint32_t spi0_reject_clr: 1;
uint32_t spi0_reject_cde: 5;
uint32_t reserved7: 25;
};
uint32_t val;
} spi0_pms_ctrl;
uint32_t spi0_reject_addr; /**/
union {
struct {
uint32_t spi1_reject_int: 1;
uint32_t spi1_reject_clr: 1;
uint32_t spi1_reject_cde: 5;
uint32_t reserved7: 25;
};
uint32_t val;
} spi1_pms_ctrl;
uint32_t spi1_reject_addr; /**/
union {
struct {
uint32_t sdio_win_access_en: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} sdio_ctrl;
union {
struct {
uint32_t redcy_sig0: 31;
uint32_t redcy_andor: 1;
};
uint32_t val;
} redcy_sig0;
union {
struct {
uint32_t redcy_sig1: 31;
uint32_t redcy_nandor: 1;
};
uint32_t val;
} redcy_sig1;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t reserved_fc;
uint32_t reserved_100;
uint32_t reserved_104;
uint32_t reserved_108;
uint32_t reserved_10c;
uint32_t reserved_110;
uint32_t reserved_114;
uint32_t reserved_118;
uint32_t reserved_11c;
uint32_t reserved_120;
uint32_t reserved_124;
uint32_t reserved_128;
uint32_t reserved_12c;
uint32_t reserved_130;
uint32_t reserved_134;
uint32_t reserved_138;
uint32_t reserved_13c;
uint32_t reserved_140;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
uint32_t reserved_1fc;
uint32_t reserved_200;
uint32_t reserved_204;
uint32_t reserved_208;
uint32_t reserved_20c;
uint32_t reserved_210;
uint32_t reserved_214;
uint32_t reserved_218;
uint32_t reserved_21c;
uint32_t reserved_220;
uint32_t reserved_224;
uint32_t reserved_228;
uint32_t reserved_22c;
uint32_t reserved_230;
uint32_t reserved_234;
uint32_t reserved_238;
uint32_t reserved_23c;
uint32_t reserved_240;
uint32_t reserved_244;
uint32_t reserved_248;
uint32_t reserved_24c;
uint32_t reserved_250;
uint32_t reserved_254;
uint32_t reserved_258;
uint32_t reserved_25c;
uint32_t reserved_260;
uint32_t reserved_264;
uint32_t reserved_268;
uint32_t reserved_26c;
uint32_t reserved_270;
uint32_t reserved_274;
uint32_t reserved_278;
uint32_t reserved_27c;
uint32_t reserved_280;
uint32_t reserved_284;
uint32_t reserved_288;
uint32_t reserved_28c;
uint32_t reserved_290;
uint32_t reserved_294;
uint32_t reserved_298;
uint32_t reserved_29c;
uint32_t reserved_2a0;
uint32_t reserved_2a4;
uint32_t reserved_2a8;
uint32_t reserved_2ac;
uint32_t reserved_2b0;
uint32_t reserved_2b4;
uint32_t reserved_2b8;
uint32_t reserved_2bc;
uint32_t reserved_2c0;
uint32_t reserved_2c4;
uint32_t reserved_2c8;
uint32_t reserved_2cc;
uint32_t reserved_2d0;
uint32_t reserved_2d4;
uint32_t reserved_2d8;
uint32_t reserved_2dc;
uint32_t reserved_2e0;
uint32_t reserved_2e4;
uint32_t reserved_2e8;
uint32_t reserved_2ec;
uint32_t reserved_2f0;
uint32_t reserved_2f4;
uint32_t reserved_2f8;
uint32_t reserved_2fc;
uint32_t reserved_300;
uint32_t reserved_304;
uint32_t reserved_308;
uint32_t reserved_30c;
uint32_t reserved_310;
uint32_t reserved_314;
uint32_t reserved_318;
uint32_t reserved_31c;
uint32_t reserved_320;
uint32_t reserved_324;
uint32_t reserved_328;
uint32_t reserved_32c;
uint32_t reserved_330;
uint32_t reserved_334;
uint32_t reserved_338;
uint32_t reserved_33c;
uint32_t reserved_340;
uint32_t reserved_344;
uint32_t reserved_348;
uint32_t reserved_34c;
uint32_t reserved_350;
uint32_t reserved_354;
uint32_t reserved_358;
uint32_t reserved_35c;
uint32_t reserved_360;
uint32_t reserved_364;
uint32_t reserved_368;
uint32_t reserved_36c;
uint32_t reserved_370;
uint32_t reserved_374;
uint32_t reserved_378;
uint32_t reserved_37c;
uint32_t reserved_380;
uint32_t reserved_384;
uint32_t reserved_388;
uint32_t reserved_38c;
uint32_t reserved_390;
uint32_t reserved_394;
uint32_t reserved_398;
uint32_t reserved_39c;
uint32_t reserved_3a0;
uint32_t reserved_3a4;
uint32_t reserved_3a8;
uint32_t reserved_3ac;
uint32_t reserved_3b0;
uint32_t reserved_3b4;
uint32_t reserved_3b8;
uint32_t reserved_3bc;
uint32_t reserved_3c0;
uint32_t reserved_3c4;
uint32_t reserved_3c8;
uint32_t reserved_3cc;
uint32_t reserved_3d0;
uint32_t reserved_3d4;
uint32_t reserved_3d8;
uint32_t reserved_3dc;
uint32_t reserved_3e0;
uint32_t reserved_3e4;
uint32_t reserved_3e8;
uint32_t reserved_3ec;
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
uint32_t date; /**/
} apb_ctrl_dev_t;
extern apb_ctrl_dev_t APB_CTRL;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_APB_CTRL_STRUCT_H_ */

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#define ASSIST_DEBUG_BASE DR_REG_ASSIST_DEBUG_BASE
#define ASSIST_DEBUG_INTERRUPT_ENA ((ASSIST_DEBUG_BASE) +0x00)
#define ASSIST_DEBUG_INTERRUPT_RAW ((ASSIST_DEBUG_BASE) +0x04)
#define ASSIST_DEBUG_INTERRUPT_RLS ((ASSIST_DEBUG_BASE) +0x08)
#define ASSIST_DEBUG_INTERRUPT_CLR ((ASSIST_DEBUG_BASE) +0x0C)
#define ASSIST_DEBUG_INTERRUPT_AREA_0_TOUCH_PRO_RD BIT(0)
#define ASSIST_DEBUG_INTERRUPT_AREA_0_TOUCH_PRO_WR BIT(1)
#define ASSIST_DEBUG_INTERRUPT_AREA_1_TOUCH_PRO_RD BIT(2)
#define ASSIST_DEBUG_INTERRUPT_AREA_1_TOUCH_PRO_WR BIT(3)
#define ASSIST_DEBUG_INTERRUPT_PRO_SP_SPILL_MIN BIT(4)
#define ASSIST_DEBUG_INTERRUPT_PRO_SP_SPILL_MAX BIT(5)
#define ASSIST_DEBUG_AREA_0_MIN ((ASSIST_DEBUG_BASE) +0x10)
#define ASSIST_DEBUG_AREA_0_MAX ((ASSIST_DEBUG_BASE) +0x14)
#define ASSIST_DEBUG_AREA_0_PC ((ASSIST_DEBUG_BASE) +0x18)
#define ASSIST_DEBUG_AREA_0_SP ((ASSIST_DEBUG_BASE) +0x1C)
#define ASSIST_DEBUG_AREA_1_MIN ((ASSIST_DEBUG_BASE) +0x20)
#define ASSIST_DEBUG_AREA_1_MAX ((ASSIST_DEBUG_BASE) +0x24)
#define ASSIST_DEBUG_AREA_1_PC ((ASSIST_DEBUG_BASE) +0x28)
#define ASSIST_DEBUG_AREA_1_SP ((ASSIST_DEBUG_BASE) +0x2C)
#define ASSIST_DEBUG_PRO_SP_UNSTABLE ((ASSIST_DEBUG_BASE) +0x30)
#define ASSIST_DEBUG_PRO_SP_MIN ((ASSIST_DEBUG_BASE) +0x34)
#define ASSIST_DEBUG_PRO_SP_MAX ((ASSIST_DEBUG_BASE) +0x38)
#define ASSIST_DEBUG_PRO_SP_PC ((ASSIST_DEBUG_BASE) +0x3C)
#define ASSIST_DEBUG_PRO_PDEBUGENABLE ((ASSIST_DEBUG_BASE) +0x40)
#define ASSIST_DEBUG_PRO_RCD_RECORDING ((ASSIST_DEBUG_BASE) +0x44)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGINST ((ASSIST_DEBUG_BASE) +0x48)
/* register layout:
* SIZE [7..0] : Instructions normally complete in the W stage. The size of the instruction in the W is given
* by this field in number of bytes. If it is 8’b0 in a given cycle the W stage has no completing
* instruction. This is also known as a bubble cycle. Also see DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG.
* ISRC [14..12] : Instruction source.
** LOOP [23..20] : Loopback status.
** CINTLEVEL [27..24]: CINTLEVEL.
*/
#define DPORT_RECORD_PDEBUGINST_SZ_M ((DPORT_RECORD_PDEBUGINST_SZ_V)<<(DPORT_RECORD_PDEBUGINST_SZ_S))
#define DPORT_RECORD_PDEBUGINST_SZ_V 0xFF
#define DPORT_RECORD_PDEBUGINST_SZ_S 0
#define DPORT_RECORD_PDEBUGINST_SZ(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_SZ_S) & DPORT_RECORD_PDEBUGINST_SZ_V)
#define DPORT_RECORD_PDEBUGINST_ISRC_M ((DPORT_RECORD_PDEBUGINST_ISRC_V)<<(DPORT_RECORD_PDEBUGINST_ISRC_S))
#define DPORT_RECORD_PDEBUGINST_ISRC_V 0x07
#define DPORT_RECORD_PDEBUGINST_ISRC_S 12
#define DPORT_RECORD_PDEBUGINST_ISRC(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_ISRC_S) & DPORT_RECORD_PDEBUGINST_ISRC_V)
// #define DPORT_RECORD_PDEBUGINST_LOOP_M ((DPORT_RECORD_PDEBUGINST_LOOP_V)<<(DPORT_RECORD_PDEBUGINST_LOOP_S))
// #define DPORT_RECORD_PDEBUGINST_LOOP_V 0x0F
// #define DPORT_RECORD_PDEBUGINST_LOOP_S 20
// #define DPORT_RECORD_PDEBUGINST_LOOP(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_LOOP_S) & DPORT_RECORD_PDEBUGINST_LOOP_V)
#define DPORT_RECORD_PDEBUGINST_LOOP_REP (BIT(20)) /* loopback will occur */
#define DPORT_RECORD_PDEBUGINST_LOOP (BIT(21)) /* last inst of loop */
#define DPORT_RECORD_PDEBUGINST_CINTL_M ((DPORT_RECORD_PDEBUGINST_CINTL_V)<<(DPORT_RECORD_PDEBUGINST_CINTL_S))
#define DPORT_RECORD_PDEBUGINST_CINTL_V 0x0F
#define DPORT_RECORD_PDEBUGINST_CINTL_S 24
#define DPORT_RECORD_PDEBUGINST_CINTL(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_CINTL_S) & DPORT_RECORD_PDEBUGINST_CINTL_V)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGSTATUS ((ASSIST_DEBUG_BASE) +0x4C)
/* register layout:
* BBCAUSE [5..0]: Indicates cause for bubble cycle. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ == 0
* INSNTYPE[5..0]: Indicates type of instruction retiring in the W stage. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ > 0
*/
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_M ((DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V)<<(DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S))
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V 0x3F
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S 0
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S) & DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V)
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_PSO 0x00 /* Power shut off */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DEP 0x02 /* Register dependency or resource conflict. See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_CTL 0x04 /* Control transfer bubble */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ICM 0x08 /* I-cache miss (incl uncached miss) */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DCM 0x0C /* D-cache miss (excl uncached miss) */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXC0 0x10 /* Exception or interrupt (W stage). See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info.
The virtual address of the instruction that was killed appears on DPORT_PRO_CPU_RECORD_PDEBUGPC_REG[31:0] */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXC1 0x11 /* Exception or interrupt (W+1 stage). See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_RPL 0x14 /* Instruction replay (other). DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG has the PC of the replaying instruction. */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLB 0x18 /* HW ITLB refill. The refill address and data are available on
DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG and DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG. */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLBM 0x1A /* ITLB miss */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DTLB 0x1C /* HW DTLB refill. The refill address and data are available on
DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG and DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG. */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DTLBM 0x1E /* DTLB miss */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_STALL 0x20 /* Stall . The cause of the global stall is further classified in the DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG. */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_HWMEC 0x24 /* HW-corrected memory error */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI 0x28 /* WAITI mode */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_OTHER 0x3C /* all other bubbles */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_M ((DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V)<<(DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S))
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V 0x3F
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S 0
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S) & DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V)
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_JX 0x00 /* JX */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CALLX 0x04 /* CALLX */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CRET 0x08 /* All call returns */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_ERET 0x0C /* All exception returns */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_B 0x10 /* Branch taken or loop not taken */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_J 0x14 /* J */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CALL 0x18 /* CALL */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_BN 0x1C /* Branch not taken */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_LOOP 0x20 /* Loop instruction (taken) */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S32C1I 0x24 /* S32C1I. The address and load data (before the conditional store) are available on the LS signals*/
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WXSR2LB 0x28 /* WSR/XSR to LBEGIN */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WSR2MMID 0x2C /* WSR to MMID */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWXSR 0x30 /* RSR or WSR (except MMID and LBEGIN) or XSR (except LBEGIN) */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWER 0x34 /* RER or WER */
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_DEF 0x3C /* Default */
#define ASSIST_DEBUG_PRO_RCD_PDEBUGDATA ((ASSIST_DEBUG_BASE) +0x50)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGPC ((ASSIST_DEBUG_BASE) +0x54)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGLS0STAT ((ASSIST_DEBUG_BASE) +0x58)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGLS0ADDR ((ASSIST_DEBUG_BASE) +0x5C)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGLS0DATA ((ASSIST_DEBUG_BASE) +0x60)
#define ASSIST_DEBUG_PRO_RCD_SP ((ASSIST_DEBUG_BASE) +0x64)

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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_BB_REG_H_
#define _SOC_BB_REG_H_
/* Some of the baseband control registers.
* PU/PD fields defined here are used in sleep related functions.
*/
#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054)
#define BB_FFT_FORCE_PU (BIT(3))
#define BB_FFT_FORCE_PU_M (BIT(3))
#define BB_FFT_FORCE_PU_V 1
#define BB_FFT_FORCE_PU_S 3
#define BB_FFT_FORCE_PD (BIT(2))
#define BB_FFT_FORCE_PD_M (BIT(2))
#define BB_FFT_FORCE_PD_V 1
#define BB_FFT_FORCE_PD_S 2
#define BB_DC_EST_FORCE_PU (BIT(1))
#define BB_DC_EST_FORCE_PU_M (BIT(1))
#define BB_DC_EST_FORCE_PU_V 1
#define BB_DC_EST_FORCE_PU_S 1
#define BB_DC_EST_FORCE_PD (BIT(0))
#define BB_DC_EST_FORCE_PD_M (BIT(0))
#define BB_DC_EST_FORCE_PD_V 1
#define BB_DC_EST_FORCE_PD_S 0
#endif /* _SOC_BB_REG_H_ */

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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_BOOT_MODE_H_
#define _SOC_BOOT_MODE_H_
#include "soc.h"
/*SPI Boot*/
#define IS_1XXX(v) (((v)&0x08)==0x08)
/*Download Boot, USB/SDIO/UART0/UART1*/
#define IS_00XX(v) (((v)&0x0c)==0x00)
/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/
#define IS_0000(v) (((v)&0x0f)==0x00)
/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/
#define IS_0001(v) (((v)&0x0f)==0x01)
/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/
#define IS_0010(v) (((v)&0x0f)==0x02)
/*Download Boot, SDIO/UART0/UART1,REI_REO V2*/
#define IS_0011(v) (((v)&0x0f)==0x03)
/*ATE/ANALOG Mode*/
#define IS_0101(v) (((v)&0x0f)==0x05)
/*Diagnostic Mode+UART0 download Mode*/
#define IS_0111(v) (((v)&0x0f)==0x07)
/*legacy SPI Boot*/
#define IS_0100(v) (((v)&0x0f)==0x04)
/*SDIO_Slave download Mode V1.1*/
#define IS_0110(v) (((v)&0x0f)==0x06)
#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG))
/*do not include download mode*/
#define ETS_IS_UART_BOOT() IS_0111(BOOT_MODE_GET())
/*all spi boot including spi/legacy*/
#define ETS_IS_FLASH_BOOT() (IS_1XXX(BOOT_MODE_GET()) || IS_0100(BOOT_MODE_GET()))
/*all faster spi boot including spi*/
#define ETS_IS_FAST_FLASH_BOOT() IS_1XXX(BOOT_MODE_GET())
/*all sdio V2 of failing edge input, failing edge output*/
#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_0000(BOOT_MODE_GET())
/*all sdio V2 of failing edge input, raising edge output*/
#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_0001(BOOT_MODE_GET())
/*all sdio V2 of raising edge input, failing edge output*/
#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_0010(BOOT_MODE_GET())
/*all sdio V2 of raising edge input, raising edge output*/
#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_0011(BOOT_MODE_GET())
/*all sdio V1 of raising edge input, failing edge output*/
#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_0110(BOOT_MODE_GET())
/*do not include download mode*/
#define ETS_IS_SDIO_BOOT() IS_0110(BOOT_MODE_GET())
/*joint download boot*/
#define ETS_IS_USB_SDIO_UART_BOOT() IS_00XX(BOOT_MODE_GET())
/*ATE mode*/
#define ETS_IS_ATE_BOOT() IS_0101(BOOT_MODE_GET())
/*used by ETS_IS_SDIO_UART_BOOT*/
#define SEL_NO_BOOT 0
#define SEL_SDIO_BOOT BIT0
#define SEL_UART_BOOT BIT1
#endif /* _SOC_BOOT_MODE_H_ */

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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_CLKOUT_CHANNEL_H
#define _SOC_CLKOUT_CHANNEL_H
//CLKOUT channels
#define CLKOUT_GPIO20_DIRECT_CHANNEL CLKOUT_CHANNEL_1
#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM 20
#define CLKOUT_GPIO19_DIRECT_CHANNEL CLKOUT_CHANNEL_2
#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM 19
#define CLKOUT_GPIO18_DIRECT_CHANNEL CLKOUT_CHANNEL_3
#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM 18
#endif

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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_CPU_H
#define _SOC_CPU_H
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#include "xtensa/corebits.h"
/* C macros for xtensa special register read/write/exchange */
#define RSR(reg, curval) asm volatile ("rsr %0, " #reg : "=r" (curval));
#define WSR(reg, newval) asm volatile ("wsr %0, " #reg : : "r" (newval));
#define XSR(reg, swapval) asm volatile ("xsr %0, " #reg : "+r" (swapval));
/** @brief Read current stack pointer address
*
*/
static inline void *get_sp()
{
void *sp;
asm volatile ("mov %0, sp;" : "=r" (sp));
return sp;
}
/* Functions to set page attributes for Region Protection option in the CPU.
* See Xtensa ISA Reference manual for explanation of arguments (section 4.6.3.2).
*/
static inline void cpu_write_dtlb(uint32_t vpn, unsigned attr)
{
asm volatile ("wdtlb %1, %0; dsync\n" :: "r" (vpn), "r" (attr));
}
static inline void cpu_write_itlb(unsigned vpn, unsigned attr)
{
asm volatile ("witlb %1, %0; isync\n" :: "r" (vpn), "r" (attr));
}
/**
* @brief Configure memory region protection
*
* Make page 0 access raise an exception.
* Also protect some other unused pages so we can catch weirdness.
* Useful attribute values:
* 0 — cached, RW
* 2 — bypass cache, RWX (default value after CPU reset)
* 15 — no access, raise exception
*/
static inline void cpu_configure_region_protection()
{
const uint32_t pages_to_protect[] = {0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000};
for (int i = 0; i < sizeof(pages_to_protect)/sizeof(pages_to_protect[0]); ++i) {
cpu_write_dtlb(pages_to_protect[i], 0xf);
cpu_write_itlb(pages_to_protect[i], 0xf);
}
cpu_write_dtlb(0x20000000, 0);
cpu_write_itlb(0x20000000, 0);
}
/**
* @brief Stall CPU using RTC controller
* @param cpu_id ID of the CPU to stall (0 = PRO, 1 = APP)
*/
void esp_cpu_stall(int cpu_id);
/**
* @brief Un-stall CPU using RTC controller
* @param cpu_id ID of the CPU to un-stall (0 = PRO, 1 = APP)
*/
void esp_cpu_unstall(int cpu_id);
/**
* @brief Reset CPU using RTC controller
* @param cpu_id ID of the CPU to reset (0 = PRO, 1 = APP)
*/
void esp_cpu_reset(int cpu_id);
/**
* @brief Returns true if a JTAG debugger is attached to CPU
* OCD (on chip debug) port.
*
* @note If "Make exception and panic handlers JTAG/OCD aware"
* is disabled, this function always returns false.
*/
bool esp_cpu_in_ocd_debug_mode();
#endif

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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_DAC_CHANNEL_H
#define _SOC_DAC_CHANNEL_H
#define DAC_GPIO17_CHANNEL DAC_CHANNEL_1
#define DAC_CHANNEL_1_GPIO_NUM 17
#define DAC_GPIO18_CHANNEL DAC_CHANNEL_2
#define DAC_CHANNEL_2_GPIO_NUM 18
#endif

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// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _DPORT_ACCESS_H_
#define _DPORT_ACCESS_H_
#include <stdint.h>
#include "esp_attr.h"
#include "esp_dport_access.h"
#include "soc.h"
#include "uart_reg.h"
#include "xtensa/xtruntime.h"
#ifdef __cplusplus
extern "C" {
#endif
// ESP32C is single core and does not have DPORT bug, so these macros are all same as the non-DPORT versions
// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent.
#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r))
#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
// Write value to DPORT register (does not require protecting)
#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v))
#define DPORT_REG_READ(_r) _DPORT_REG_READ(_r)
#define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r)
//get bit or get bits from register
#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b))
//set bit or set bits to register
#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b)))
//clear bit or clear bits of register
#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b))))
//set bits of register controlled by mask
#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m))))
//get field from register, uses field _S & _V to determine mask
#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
//set field to register, used when _f is not left shifted by _f##_S
#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S))))
//get field value from a variable, used when _f is not left shifted by _f##_S
#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
//get field value from a variable, used when _f is left shifted by _f##_S
#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
//set field value to a variable, used when _f is not left shifted by _f##_S
#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
//set field value to a variable, used when _f is left shifted by _f##_S
#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
//generate a value from a field value, used when _f is not left shifted by _f##_S
#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
//generate a value from a field value, used when _f is left shifted by _f##_S
#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe.
#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr)))
#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
#define DPORT_READ_PERI_REG(addr) _DPORT_READ_PERI_REG(addr)
//write value to register
#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val))
//clear bits of register controlled by mask
#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask))))
//set bits of register controlled by mask
#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask)))
//get bits of register controlled by mask
#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask))
//get bits of register controlled by highest bit and lowest bit
#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
//set bits of register controlled by mask and shift
#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift))))
//get field of register
#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask))
//}}
#ifdef __cplusplus
}
#endif
#endif /* _DPORT_ACCESS_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_DPORT_REG_H_
#define _SOC_DPORT_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include"extmem_reg.h"
#include"interrupt_reg.h"
#include"system_reg.h"
#include "sensitive_reg.h"
#include "soc.h"
/*IRAM0 connected with Cache IBUS0*/
#define IRAM0_ADDRESS_LOW 0x40000000
#define IRAM0_ADDRESS_HIGH 0x40400000
#define IRAM0_CACHE_ADDRESS_LOW 0x40080000
#define IRAM0_CACHE_ADDRESS_HIGH 0x40400000
/*IRAM1 and AHB_IBUS1 connected with Cache IBUS1, alternative*/
#define IRAM1_ADDRESS_LOW 0x40400000
#define IRAM1_ADDRESS_HIGH 0x40800000
#define AHB_IBUS1_ADDRESS_LOW 0x60400000
#define AHB_IBUS1_ADDRESS_HIGH 0x60800000
/*IROM0 and AHB_IBUS2 connected with Cache IBUS2, alternative*/
#define IROM0_ADDRESS_LOW 0x40800000
#define IROM0_ADDRESS_HIGH 0x40c00000
#define AHB_IBUS2_ADDRESS_LOW 0x60800000
#define AHB_IBUS2_ADDRESS_HIGH 0x60c00000
/*DROM0 and AHB_IBUS2 connected with Cache IBUS3, alternative*/
/*DROM0 and AHB_DBUS2 connected with Cache DBUS3, alternative*/
#define DROM0_ADDRESS_LOW 0x3f000000
#define DROM0_ADDRESS_HIGH 0x3f400000
#define AHB_IBUS3_ADDRESS_LOW 0x60c00000
#define AHB_IBUS3_ADDRESS_HIGH 0x61000000
#define AHB_DBUS3_ADDRESS_LOW 0x61800000
#define AHB_DBUS3_ADDRESS_HIGH 0x61c00000
/*DRAM0 and AHB_DBUS2 connected with Cache DBUS0, alternative*/
#define DRAM0_ADDRESS_LOW 0x3fc00000
#define DRAM0_ADDRESS_HIGH 0x40000000
#define DRAM0_CACHE_ADDRESS_LOW 0x3fc00000
#define DRAM0_CACHE_ADDRESS_HIGH 0x3ff90000
#define AHB_DBUS0_ADDRESS_LOW 0x61000000
#define AHB_DBUS0_ADDRESS_HIGH 0x61400000
/*DRAM1 connected with Cache DBUS1*/
#define DRAM1_ADDRESS_LOW 0x3f800000
#define DRAM1_ADDRESS_HIGH 0x3fc00000
/*DPORT and AHB_DBUS2 connected with Cache DBUS2, alternative*/
#define DPORT_ADDRESS_LOW 0x3f400000
#define DPORT_ADDRESS_HIGH 0x3f800000
#define DPORT_CACHE_ADDRESS_LOW 0x3f500000
#define DPORT_CACHE_ADDRESS_HIGH 0x3f800000
#define AHB_DBUS2_ADDRESS_LOW 0x61400000
#define AHB_DBUS2_ADDRESS_HIGH 0x61800000
#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
#define ADDRESS_IN_IRAM1(vaddr) ADDRESS_IN_BUS(IRAM1, vaddr)
#define ADDRESS_IN_AHB_IBUS1(vaddr) ADDRESS_IN_BUS(AHB_IBUS1, vaddr)
#define ADDRESS_IN_IROM0(vaddr) ADDRESS_IN_BUS(IROM0, vaddr)
#define ADDRESS_IN_AHB_IBUS2(vaddr) ADDRESS_IN_BUS(AHB_IBUS2, vaddr)
#define ADDRESS_IN_DROM0(vaddr) ADDRESS_IN_BUS(DROM0, vaddr)
#define ADDRESS_IN_AHB_IBUS3(vaddr) ADDRESS_IN_BUS(AHB_IBUS3, vaddr)
#define ADDRESS_IN_AHB_DBUS3(vaddr) ADDRESS_IN_BUS(AHB_DBUS3, vaddr)
#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
#define ADDRESS_IN_AHB_DBUS0(vaddr) ADDRESS_IN_BUS(AHB_DBUS0, vaddr)
#define ADDRESS_IN_DRAM1(vaddr) ADDRESS_IN_BUS(DRAM1, vaddr)
#define ADDRESS_IN_DPORT(vaddr) ADDRESS_IN_BUS(DPORT, vaddr)
#define ADDRESS_IN_DPORT_CACHE(vaddr) ADDRESS_IN_BUS(DPORT_CACHE, vaddr)
#define ADDRESS_IN_AHB_DBUS2(vaddr) ADDRESS_IN_BUS(AHB_DBUS2, vaddr)
#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
#define BUS_IRAM1_CACHE_SIZE BUS_SIZE(IRAM1)
#define BUS_IROM0_CACHE_SIZE BUS_SIZE(IROM0)
#define BUS_DROM0_CACHE_SIZE BUS_SIZE(DROM0)
#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
#define BUS_DRAM1_CACHE_SIZE BUS_SIZE(DRAM1)
#define BUS_DPORT_CACHE_SIZE BUS_SIZE(DPORT)
#define BUS_AHB_IBUS1_CACHE_SIZE BUS_SIZE(AHB_IBUS1)
#define BUS_AHB_IBUS2_CACHE_SIZE BUS_SIZE(AHB_IBUS2)
#define BUS_AHB_IBUS3_CACHE_SIZE BUS_SIZE(AHB_IBUS3)
#define BUS_AHB_DBUS0_CACHE_SIZE BUS_SIZE(AHB_DBUS0)
#define BUS_AHB_DBUS2_CACHE_SIZE BUS_SIZE(AHB_DBUS2)
#define BUS_AHB_DBUS3_CACHE_SIZE BUS_SIZE(AHB_DBUS3)
#define PRO_CACHE_IBUS0 0
#define PRO_CACHE_IBUS0_MMU_START 0
#define PRO_CACHE_IBUS0_MMU_END 0x100
#define PRO_CACHE_IBUS1 1
#define PRO_CACHE_IBUS1_MMU_START 0x100
#define PRO_CACHE_IBUS1_MMU_END 0x200
#define PRO_CACHE_IBUS2 2
#define PRO_CACHE_IBUS2_MMU_START 0x200
#define PRO_CACHE_IBUS2_MMU_END 0x300
#define PRO_CACHE_IBUS3 3
#define PRO_CACHE_IBUS3_MMU_START 0x300
#define PRO_CACHE_IBUS3_MMU_END 0x400
#define PRO_CACHE_DBUS0 4
#define PRO_CACHE_DBUS0_MMU_START 0x400
#define PRO_CACHE_DBUS0_MMU_END 0x500
#define PRO_CACHE_DBUS1 5
#define PRO_CACHE_DBUS1_MMU_START 0x500
#define PRO_CACHE_DBUS1_MMU_END 0x600
#define PRO_CACHE_DBUS2 6
#define PRO_CACHE_DBUS2_MMU_START 0x600
#define PRO_CACHE_DBUS2_MMU_END 0x700
#define PRO_CACHE_DBUS3 7
#define PRO_CACHE_DBUS3_MMU_START 0x700
#define PRO_CACHE_DBUS3_MMU_END 0x800
#define DPORT_MMU_SIZE 0x800
#define DPORT_ICACHE_MMU_SIZE 0x400
#define DPORT_DCACHE_MMU_SIZE 0x400
#define DPORT_MMU_BUS_START(i) ((i) * 0x100)
#define DPORT_MMU_BUS_SIZE 0x100
#define DPORT_MMU_INVALID BIT(14)
#define DPORT_MMU_ACCESS_FLASH BIT(15)
#define DPORT_MMU_ACCESS_SPIRAM BIT(16)
/* Flash MMU table for PRO CPU */
#define DPORT_PRO_FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
#define DPORT_FLASH_MMU_TABLE_SIZE (DPORT_ICACHE_MMU_SIZE/sizeof(uint32_t))
#define DPORT_MMU_TABLE_INVALID_VAL 0x4000
#define DPORT_FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
#define DPORT_MMU_ADDRESS_MASK 0x3fff
#define BUS_ADDR_SIZE 0x400000
#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
#define BUS_NUM_MASK 0x3
#define CACHE_MEMORY_BLOCK_SIZE 8192
#define CACHE_MEMORY_BLOCK_NUM 4
#define CACHE_MEMORY_BLOCK_NUM_MASK 0x3
#define CACHE_MEMORY_LAYOUT_SHIFT 4
#define CACHE_MEMORY_LAYOUT_SHIFT0 0
#define CACHE_MEMORY_LAYOUT_SHIFT1 4
#define CACHE_MEMORY_LAYOUT_SHIFT2 8
#define CACHE_MEMORY_LAYOUT_SHIFT3 12
#define CACHE_MEMORY_LAYOUT_MASK 0xf
#define CACHE_MEMORY_BLOCK0_ADDR 0x40020000
#define CACHE_MEMORY_BLOCK1_ADDR 0x40022000
#define CACHE_MEMORY_BLOCK2_ADDR 0x40024000
#define CACHE_MEMORY_BLOCK3_ADDR 0x40026000
#define DPORT_DATE_REG SYSTEM_DATE_REG
#ifndef __ASSEMBLER__
#include "dport_access.h"
#endif
#ifdef __cplusplus
}
#endif
#endif /*_SOC_DPORT_REG_H_ */

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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_EFUSE_STRUCT_H_
#define _SOC_EFUSE_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t rd_efuse_wr_dis: 16;
uint32_t rd_efuse_rd_dis: 4;
uint32_t rd_flash_crypt_cnt: 8;
uint32_t reserved28: 4;
};
uint32_t val;
} blk0_rdata0;
uint32_t blk0_rdata1; /**/
union {
struct {
uint32_t rd_wifi_mac_crc_high:24;
uint32_t reserved24: 8;
};
uint32_t val;
} blk0_rdata2;
union {
struct {
uint32_t rd_soft_disable_jtag: 1;
uint32_t rd_chip_ver_dis_bt: 1;
uint32_t rd_chip_ver_32pad: 1;
uint32_t rd_chip_ver_dis_cache: 1;
uint32_t rd_chip_ver_reserve: 13;
uint32_t reserved17: 15;
};
uint32_t val;
} blk0_rdata3;
union {
struct {
uint32_t rd_ck8m_freq: 8;
uint32_t rd_sdio_drefh: 2;
uint32_t rd_sdio_drefm: 2;
uint32_t rd_sdio_drefl: 2;
uint32_t rd_xpd_sdio: 1;
uint32_t rd_sdio_tieh: 1;
uint32_t rd_sdio_force: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} blk0_rdata4;
union {
struct {
uint32_t rd_spi_pad_config: 20;
uint32_t rd_tsens_dos: 4;
uint32_t rd_reserve_use1: 4;
uint32_t rd_flash_crypt_config: 4;
};
uint32_t val;
} blk0_rdata5;
union {
struct {
uint32_t rd_coding_scheme: 2;
uint32_t rd_dig_reserve: 1;
uint32_t rd_disable_sdio_host: 1;
uint32_t rd_abs_done_0: 1;
uint32_t rd_abs_done_1: 1;
uint32_t rd_hard_disable_jtag: 1;
uint32_t rd_disable_dl_encrypt: 1;
uint32_t rd_disable_dl_decrypt: 1;
uint32_t rd_disable_dl_cache: 1;
uint32_t rd_key_status: 1;
uint32_t reserved11: 21;
};
uint32_t val;
} blk0_rdata6;
union {
struct {
uint32_t wr_dis: 16;
uint32_t rd_dis: 4;
uint32_t flash_crypt_cnt: 8;
uint32_t reserved28: 4;
};
uint32_t val;
} blk0_wdata0;
uint32_t blk0_wdata1; /**/
union {
struct {
uint32_t wifi_mac_crc_high:24;
uint32_t reserved24: 8;
};
uint32_t val;
} blk0_wdata2;
union {
struct {
uint32_t soft_disable_jtag: 1;
uint32_t chip_ver_dis_bt: 1;
uint32_t chip_ver_32pad: 1;
uint32_t chip_ver_dis_cache: 1;
uint32_t chip_ver_reserve: 13;
uint32_t reserved17: 15;
};
uint32_t val;
} blk0_wdata3;
union {
struct {
uint32_t ck8m_freq: 8;
uint32_t sdio_drefh: 2;
uint32_t sdio_drefm: 2;
uint32_t sdio_drefl: 2;
uint32_t xpd_sdio: 1;
uint32_t sdio_tieh: 1;
uint32_t sdio_force: 1;
uint32_t reserved17:15;
};
uint32_t val;
} blk0_wdata4;
union {
struct {
uint32_t spi_pad_config: 20;
uint32_t tsens_dos: 4;
uint32_t reserve_use1: 4;
uint32_t flash_crypt_config: 4;
};
uint32_t val;
} blk0_wdata5;
union {
struct {
uint32_t coding_scheme: 2;
uint32_t dig_reserve: 1;
uint32_t disable_sdio_host: 1;
uint32_t abs_done_0: 1;
uint32_t abs_done_1: 1;
uint32_t hard_disable_jtag: 1;
uint32_t disable_dl_encrypt: 1;
uint32_t disable_dl_decrypt: 1;
uint32_t disable_dl_cache: 1;
uint32_t key_status: 1;
uint32_t reserved11: 21;
};
uint32_t val;
} blk0_wdata6;
uint32_t blk1_rdata0; /**/
uint32_t blk1_rdata1; /**/
uint32_t blk1_rdata2; /**/
uint32_t blk1_rdata3; /**/
uint32_t blk1_rdata4; /**/
uint32_t blk1_rdata5; /**/
uint32_t blk1_rdata6; /**/
uint32_t blk1_rdata7; /**/
uint32_t blk2_rdata0; /**/
uint32_t blk2_rdata1; /**/
uint32_t blk2_rdata2; /**/
uint32_t blk2_rdata3; /**/
uint32_t blk2_rdata4; /**/
uint32_t blk2_rdata5; /**/
uint32_t blk2_rdata6; /**/
uint32_t blk2_rdata7; /**/
uint32_t blk3_rdata0; /**/
uint32_t blk3_rdata1; /**/
uint32_t blk3_rdata2; /**/
uint32_t blk3_rdata3; /**/
uint32_t blk3_rdata4; /**/
uint32_t blk3_rdata5; /**/
uint32_t blk3_rdata6; /**/
uint32_t blk3_rdata7; /**/
uint32_t blk1_wdata0; /**/
uint32_t blk1_wdata1; /**/
uint32_t blk1_wdata2; /**/
uint32_t blk1_wdata3; /**/
uint32_t blk1_wdata4; /**/
uint32_t blk1_wdata5; /**/
uint32_t blk1_wdata6; /**/
uint32_t blk1_wdata7; /**/
uint32_t blk2_wdata0; /**/
uint32_t blk2_wdata1; /**/
uint32_t blk2_wdata2; /**/
uint32_t blk2_wdata3; /**/
uint32_t blk2_wdata4; /**/
uint32_t blk2_wdata5; /**/
uint32_t blk2_wdata6; /**/
uint32_t blk2_wdata7; /**/
uint32_t blk3_wdata0; /**/
uint32_t blk3_wdata1; /**/
uint32_t blk3_wdata2; /**/
uint32_t blk3_wdata3; /**/
uint32_t blk3_wdata4; /**/
uint32_t blk3_wdata5; /**/
uint32_t blk3_wdata6; /**/
uint32_t blk3_wdata7; /**/
union {
struct {
uint32_t reserved0: 16;
uint32_t clk_en: 1;
uint32_t reserved17:15;
};
uint32_t val;
} clk;
union {
struct {
uint32_t op_code: 16;
uint32_t force_no_wr_rd_dis: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} conf;
uint32_t status; /**/
union {
struct {
uint32_t read_cmd: 1;
uint32_t pgm_cmd: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} cmd;
union {
struct {
uint32_t read_done: 1;
uint32_t pgm_done: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t read_done: 1;
uint32_t pgm_done: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t read_done: 1;
uint32_t pgm_done: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t read_done: 1;
uint32_t pgm_done: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t dac_clk_div: 8;
uint32_t dac_clk_pad_sel: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} dac_conf;
union {
struct {
uint32_t dec_warnings:12;
uint32_t reserved12: 20;
};
uint32_t val;
} dec_status;
union {
struct {
uint32_t thr_a: 8;
uint32_t trd: 8;
uint32_t tsur_a: 8;
uint32_t read_init_num: 8;
};
uint32_t val;
} rd_tim_conf;
union {
struct {
uint32_t thp_a: 8;
uint32_t tpgm_inactive: 8;
uint32_t tpgm: 16;
};
uint32_t val;
} wr_tim_conf0;
union {
struct {
uint32_t tsup_a: 8;
uint32_t pwr_on_num:16;
uint32_t reserved24: 8;
};
uint32_t val;
} wr_tim_conf1;
union {
struct {
uint32_t rd_dis_err: 4;
uint32_t chip_ver_reserve_err:13;
uint32_t ck8m_freq_err: 8;
uint32_t sdio_drefh_err: 2;
uint32_t sdio_drefm_err: 2;
uint32_t sdio_drefl_err: 2;
uint32_t key_status_err: 1;
};
uint32_t val;
} repeat_err0;
union {
struct {
uint32_t spi_pad_config_err: 20;
uint32_t flash_crypt_config_err: 4;
uint32_t tsens_dos_err: 4;
uint32_t reserve_use1_err: 4;
};
uint32_t val;
} repeat_err1;
union {
struct {
uint32_t abs_done_0_err: 1;
uint32_t abs_done_1_err: 1;
uint32_t hard_disable_jtag_err: 1;
uint32_t disable_dl_encrypt_err: 1;
uint32_t disable_dl_decrypt_err: 1;
uint32_t disable_dl_cache_err: 1;
uint32_t disable_sdio_host_err: 1;
uint32_t dig_reserve_err: 1;
uint32_t soft_disable_jtag_err: 1;
uint32_t chip_ver_dis_bt_err: 1;
uint32_t chip_ver_32pad_err: 1;
uint32_t chip_ver_dis_cache_err: 1;
uint32_t xpd_sdio_err: 1;
uint32_t sdio_tieh_err: 1;
uint32_t sdio_force_err: 1;
uint32_t reserved15: 17;
};
uint32_t val;
} repeat_err2;
uint32_t repeat_blk1_err0; /**/
uint32_t repeat_blk1_err1; /**/
uint32_t repeat_blk1_err2; /**/
uint32_t repeat_blk1_err3; /**/
uint32_t repeat_blk2_err0; /**/
uint32_t repeat_blk2_err1; /**/
uint32_t repeat_blk2_err2; /**/
uint32_t repeat_blk2_err3; /**/
uint32_t repeat_blk3_err0; /**/
uint32_t repeat_blk3_err1; /**/
uint32_t repeat_blk3_err2; /**/
uint32_t repeat_blk3_err3; /**/
union {
struct {
uint32_t rs_errornum_blk1: 4;
uint32_t rs_fail_blk1: 1;
uint32_t rs_errornum_blk2: 4;
uint32_t rs_fail_blk2: 1;
uint32_t rs_errornum_blk3: 4;
uint32_t rs_fail_blk3: 1;
uint32_t reserved15: 17;
};
uint32_t val;
} rs_state;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
uint32_t date; /**/
} efuse_dev_t;
extern efuse_dev_t EFUSE;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_EFUSE_STRUCT_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include "soc/soc.h"
/* Some of the RF frontend control registers.
* PU/PD fields defined here are used in sleep related functions.
*/
#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090)
#define FE_IQ_EST_FORCE_PU (BIT(5))
#define FE_IQ_EST_FORCE_PU_M (BIT(5))
#define FE_IQ_EST_FORCE_PU_V 1
#define FE_IQ_EST_FORCE_PU_S 5
#define FE_IQ_EST_FORCE_PD (BIT(4))
#define FE_IQ_EST_FORCE_PD_M (BIT(4))
#define FE_IQ_EST_FORCE_PD_V 1
#define FE_IQ_EST_FORCE_PD_S 4
#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0)
#define FE2_TX_INF_FORCE_PU (BIT(10))
#define FE2_TX_INF_FORCE_PU_M (BIT(10))
#define FE2_TX_INF_FORCE_PU_V 1
#define FE2_TX_INF_FORCE_PU_S 10
#define FE2_TX_INF_FORCE_PD (BIT(9))
#define FE2_TX_INF_FORCE_PD_M (BIT(9))
#define FE2_TX_INF_FORCE_PD_V 1
#define FE2_TX_INF_FORCE_PD_S 9

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_FRC_TIMER_REG_H_
#define _SOC_FRC_TIMER_REG_H_
#include "soc.h"
/**
* These are the register definitions for "legacy" timers
*/
#define REG_FRC_TIMER_BASE(i) (DR_REG_FRC_TIMER_BASE + i*0x20)
#define FRC_TIMER_LOAD_REG(i) (REG_FRC_TIMER_BASE(i) + 0x0) // timer load value (23 bit for i==0, 32 bit for i==1)
#define FRC_TIMER_LOAD_VALUE(i) ((i == 0)?0x007FFFFF:0xffffffff)
#define FRC_TIMER_LOAD_VALUE_S 0
#define FRC_TIMER_COUNT_REG(i) (REG_FRC_TIMER_BASE(i) + 0x4) // timer count value (23 bit for i==0, 32 bit for i==1)
#define FRC_TIMER_COUNT ((i == 0)?0x007FFFFF:0xffffffff)
#define FRC_TIMER_COUNT_S 0
#define FRC_TIMER_CTRL_REG(i) (REG_FRC_TIMER_BASE(i) + 0x8)
#define FRC_TIMER_INT_STATUS (BIT(8)) // interrupt status (RO)
#define FRC_TIMER_ENABLE (BIT(7)) // enable timer
#define FRC_TIMER_AUTOLOAD (BIT(6)) // enable autoload
#define FRC_TIMER_PRESCALER 0x00000007
#define FRC_TIMER_PRESCALER_S 1
#define FRC_TIMER_PRESCALER_1 (0 << FRC_TIMER_PRESCALER_S)
#define FRC_TIMER_PRESCALER_16 (2 << FRC_TIMER_PRESCALER_S)
#define FRC_TIMER_PRESCALER_256 (4 << FRC_TIMER_PRESCALER_S)
#define FRC_TIMER_LEVEL_INT (BIT(0)) // 1: level, 0: edge
#define FRC_TIMER_INT_REG(i) (REG_FRC_TIMER_BASE(i) + 0xC)
#define FRC_TIMER_INT_CLR (BIT(0)) // clear interrupt
#define FRC_TIMER_ALARM_REG(i) (REG_FRC_TIMER_BASE(i) + 0x10) // timer alarm value; register only present for i == 1
#define FRC_TIMER_ALARM 0xFFFFFFFF
#define FRC_TIMER_ALARM_S 0
#endif //_SOC_FRC_TIMER_REG_H_

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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_GPIO_SD_REG_H_
#define _SOC_GPIO_SD_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0000)
/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD0_PRESCALE 0x000000FF
#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S))
#define GPIO_SD0_PRESCALE_V 0xFF
#define GPIO_SD0_PRESCALE_S 8
/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD0_IN 0x000000FF
#define GPIO_SD0_IN_M ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S))
#define GPIO_SD0_IN_V 0xFF
#define GPIO_SD0_IN_S 0
#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x0004)
/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD1_PRESCALE 0x000000FF
#define GPIO_SD1_PRESCALE_M ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S))
#define GPIO_SD1_PRESCALE_V 0xFF
#define GPIO_SD1_PRESCALE_S 8
/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD1_IN 0x000000FF
#define GPIO_SD1_IN_M ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S))
#define GPIO_SD1_IN_V 0xFF
#define GPIO_SD1_IN_S 0
#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x0008)
/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD2_PRESCALE 0x000000FF
#define GPIO_SD2_PRESCALE_M ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S))
#define GPIO_SD2_PRESCALE_V 0xFF
#define GPIO_SD2_PRESCALE_S 8
/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD2_IN 0x000000FF
#define GPIO_SD2_IN_M ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S))
#define GPIO_SD2_IN_V 0xFF
#define GPIO_SD2_IN_S 0
#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0x000c)
/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD3_PRESCALE 0x000000FF
#define GPIO_SD3_PRESCALE_M ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S))
#define GPIO_SD3_PRESCALE_V 0xFF
#define GPIO_SD3_PRESCALE_S 8
/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD3_IN 0x000000FF
#define GPIO_SD3_IN_M ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S))
#define GPIO_SD3_IN_V 0xFF
#define GPIO_SD3_IN_S 0
#define GPIO_SIGMADELTA4_REG (DR_REG_GPIO_SD_BASE + 0x0010)
/* GPIO_SD4_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD4_PRESCALE 0x000000FF
#define GPIO_SD4_PRESCALE_M ((GPIO_SD4_PRESCALE_V)<<(GPIO_SD4_PRESCALE_S))
#define GPIO_SD4_PRESCALE_V 0xFF
#define GPIO_SD4_PRESCALE_S 8
/* GPIO_SD4_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD4_IN 0x000000FF
#define GPIO_SD4_IN_M ((GPIO_SD4_IN_V)<<(GPIO_SD4_IN_S))
#define GPIO_SD4_IN_V 0xFF
#define GPIO_SD4_IN_S 0
#define GPIO_SIGMADELTA5_REG (DR_REG_GPIO_SD_BASE + 0x0014)
/* GPIO_SD5_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD5_PRESCALE 0x000000FF
#define GPIO_SD5_PRESCALE_M ((GPIO_SD5_PRESCALE_V)<<(GPIO_SD5_PRESCALE_S))
#define GPIO_SD5_PRESCALE_V 0xFF
#define GPIO_SD5_PRESCALE_S 8
/* GPIO_SD5_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD5_IN 0x000000FF
#define GPIO_SD5_IN_M ((GPIO_SD5_IN_V)<<(GPIO_SD5_IN_S))
#define GPIO_SD5_IN_V 0xFF
#define GPIO_SD5_IN_S 0
#define GPIO_SIGMADELTA6_REG (DR_REG_GPIO_SD_BASE + 0x0018)
/* GPIO_SD6_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD6_PRESCALE 0x000000FF
#define GPIO_SD6_PRESCALE_M ((GPIO_SD6_PRESCALE_V)<<(GPIO_SD6_PRESCALE_S))
#define GPIO_SD6_PRESCALE_V 0xFF
#define GPIO_SD6_PRESCALE_S 8
/* GPIO_SD6_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD6_IN 0x000000FF
#define GPIO_SD6_IN_M ((GPIO_SD6_IN_V)<<(GPIO_SD6_IN_S))
#define GPIO_SD6_IN_V 0xFF
#define GPIO_SD6_IN_S 0
#define GPIO_SIGMADELTA7_REG (DR_REG_GPIO_SD_BASE + 0x001c)
/* GPIO_SD7_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD7_PRESCALE 0x000000FF
#define GPIO_SD7_PRESCALE_M ((GPIO_SD7_PRESCALE_V)<<(GPIO_SD7_PRESCALE_S))
#define GPIO_SD7_PRESCALE_V 0xFF
#define GPIO_SD7_PRESCALE_S 8
/* GPIO_SD7_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define GPIO_SD7_IN 0x000000FF
#define GPIO_SD7_IN_M ((GPIO_SD7_IN_V)<<(GPIO_SD7_IN_S))
#define GPIO_SD7_IN_V 0xFF
#define GPIO_SD7_IN_S 0
#define GPIO_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x0020)
/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define GPIO_SD_CLK_EN (BIT(31))
#define GPIO_SD_CLK_EN_M (BIT(31))
#define GPIO_SD_CLK_EN_V 0x1
#define GPIO_SD_CLK_EN_S 31
#define GPIO_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x0024)
/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define GPIO_SPI_SWAP (BIT(31))
#define GPIO_SPI_SWAP_M (BIT(31))
#define GPIO_SPI_SWAP_V 0x1
#define GPIO_SPI_SWAP_S 31
/* GPIO_FUNCTION_CLK_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */
/*description: */
#define GPIO_FUNCTION_CLK_EN (BIT(30))
#define GPIO_FUNCTION_CLK_EN_M (BIT(30))
#define GPIO_FUNCTION_CLK_EN_V 0x1
#define GPIO_FUNCTION_CLK_EN_S 30
#define GPIO_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0x0028)
/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h1802260 ; */
/*description: */
#define GPIO_SD_DATE 0x0FFFFFFF
#define GPIO_SD_DATE_M ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S))
#define GPIO_SD_DATE_V 0xFFFFFFF
#define GPIO_SD_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_GPIO_SD_REG_H_ */

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components/soc/esp32s2beta/include/soc/gpio_sd_struct.h Normal file
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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_GPIO_SD_STRUCT_H_
#define _SOC_GPIO_SD_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t duty: 8;
uint32_t prescale: 8;
uint32_t reserved16: 16;
};
uint32_t val;
} channel[8];
union {
struct {
uint32_t reserved0: 31;
uint32_t clk_en: 1;
};
uint32_t val;
} cg;
union {
struct {
uint32_t reserved0: 30;
uint32_t function_clk_en: 1;
uint32_t spi_swap: 1;
};
uint32_t val;
} misc;
union {
struct {
uint32_t date: 28;
uint32_t reserved28: 4;
};
uint32_t val;
} version;
} gpio_sd_dev_t;
extern gpio_sd_dev_t SIGMADELTA;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_GPIO_SD_STRUCT_H_ */

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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
#define SPICLK_OUT_IDX SPICLK_OUT_MUX_IDX
#define CLK_I2S_IDX CLK_I2S_MUX_IDX
#define SPIQ_IN_IDX 0
#define SPIQ_OUT_IDX 0
#define SPID_IN_IDX 1
#define SPID_OUT_IDX 1
#define SPIHD_IN_IDX 2
#define SPIHD_OUT_IDX 2
#define SPIWP_IN_IDX 3
#define SPIWP_OUT_IDX 3
#define SPICLK_OUT_MUX_IDX 4
#define SPICS0_OUT_IDX 5
#define SPICS1_OUT_IDX 6
#define FSPICD_OUT_IDX 9
#define SPI3_CD_OUT_IDX 10
#define SPI4_CD_OUT_IDX 11
#define U0RXD_IN_IDX 14
#define U0TXD_OUT_IDX 14
#define U0CTS_IN_IDX 15
#define U0RTS_OUT_IDX 15
#define U0DSR_IN_IDX 16
#define U0DTR_OUT_IDX 16
#define U1RXD_IN_IDX 17
#define U1TXD_OUT_IDX 17
#define U1CTS_IN_IDX 18
#define U1RTS_OUT_IDX 18
#define U1DSR_IN_IDX 21
#define U1DTR_OUT_IDX 21
#define I2S0O_BCK_IN_IDX 23
#define I2S0O_BCK_OUT_IDX 23
#define I2S0O_WS_IN_IDX 25
#define I2S0O_WS_OUT_IDX 25
#define I2S0I_BCK_IN_IDX 27
#define I2S0I_BCK_OUT_IDX 27
#define I2S0I_WS_IN_IDX 28
#define I2S0I_WS_OUT_IDX 28
#define I2CEXT0_SCL_IN_IDX 29
#define I2CEXT0_SCL_OUT_IDX 29
#define I2CEXT0_SDA_IN_IDX 30
#define I2CEXT0_SDA_OUT_IDX 30
#define SDIO_TOHOST_INT_OUT_IDX 31
#define GPIO_BT_ACTIVE_IDX 37
#define GPIO_BT_PRIORITY_IDX 38
#define PCNT_SIG_CH0_IN0_IDX 39
#define GPIO_WLAN_PRIO_IDX 39
#define PCNT_SIG_CH1_IN0_IDX 40
#define GPIO_WLAN_ACTIVE_IDX 40
#define PCNT_CTRL_CH0_IN0_IDX 41
#define BB_DIAG0_IDX 41
#define PCNT_CTRL_CH1_IN0_IDX 42
#define BB_DIAG1_IDX 42
#define PCNT_SIG_CH0_IN1_IDX 43
#define BB_DIAG2_IDX 43
#define PCNT_SIG_CH1_IN1_IDX 44
#define BB_DIAG3_IDX 44
#define PCNT_CTRL_CH0_IN1_IDX 45
#define BB_DIAG4_IDX 45
#define PCNT_CTRL_CH1_IN1_IDX 46
#define BB_DIAG5_IDX 46
#define PCNT_SIG_CH0_IN2_IDX 47
#define BB_DIAG6_IDX 47
#define PCNT_SIG_CH1_IN2_IDX 48
#define BB_DIAG7_IDX 48
#define PCNT_CTRL_CH0_IN2_IDX 49
#define BB_DIAG8_IDX 49
#define PCNT_CTRL_CH1_IN2_IDX 50
#define BB_DIAG9_IDX 50
#define PCNT_SIG_CH0_IN3_IDX 51
#define BB_DIAG10_IDX 51
#define PCNT_SIG_CH1_IN3_IDX 52
#define BB_DIAG11_IDX 52
#define PCNT_CTRL_CH0_IN3_IDX 53
#define BB_DIAG12_IDX 53
#define PCNT_CTRL_CH1_IN3_IDX 54
#define BB_DIAG13_IDX 54
#define BB_DIAG14_IDX 55
#define BB_DIAG15_IDX 56
#define BB_DIAG16_IDX 57
#define BB_DIAG17_IDX 58
#define BB_DIAG18_IDX 59
#define BB_DIAG19_IDX 60
#define USB_EXTPHY_VP_IDX 61
#define USB_EXTPHY_OEN_IDX 61
#define USB_EXTPHY_VM_IDX 62
#define USB_EXTPHY_SPEED_IDX 62
#define USB_EXTPHY_RCV_IDX 63
#define USB_EXTPHY_VPO_IDX 63
#define USB_OTG_IDDIG_IN_IDX 64
#define USB_EXTPHY_VMO_IDX 64
#define USB_OTG_AVALID_IN_IDX 65
#define USB_EXTPHY_SUSPND_IDX 65
#define USB_SRP_BVALID_IN_IDX 66
#define USB_OTG_IDPULLUP_IDX 66
#define USB_OTG_VBUSVALID_IN_IDX 67
#define USB_OTG_DPPULLDOWN_IDX 67
#define USB_SRP_SESSEND_IN_IDX 68
#define USB_OTG_DMPULLDOWN_IDX 68
#define USB_OTG_DRVVBUS_IDX 69
#define USB_SRP_CHRGVBUS_IDX 70
#define USB_SRP_DISCHRGVBUS_IDX 71
#define SPI3_CLK_IN_IDX 72
#define SPI3_CLK_OUT_MUX_IDX 72
#define SPI3_Q_IN_IDX 73
#define SPI3_Q_OUT_IDX 73
#define SPI3_D_IN_IDX 74
#define SPI3_D_OUT_IDX 74
#define SPI3_HD_IN_IDX 75
#define SPI3_HD_OUT_IDX 75
#define SPI3_CS0_IN_IDX 76
#define SPI3_CS0_OUT_IDX 76
#define SPI3_CS1_OUT_IDX 77
#define SPI3_CS2_OUT_IDX 78
#define LEDC_LS_SIG_OUT0_IDX 79
#define LEDC_LS_SIG_OUT1_IDX 80
#define LEDC_LS_SIG_OUT2_IDX 81
#define LEDC_LS_SIG_OUT3_IDX 82
#define RMT_SIG_IN0_IDX 83
#define LEDC_LS_SIG_OUT4_IDX 83
#define RMT_SIG_IN1_IDX 84
#define LEDC_LS_SIG_OUT5_IDX 84
#define RMT_SIG_IN2_IDX 85
#define LEDC_LS_SIG_OUT6_IDX 85
#define RMT_SIG_IN3_IDX 86
#define LEDC_LS_SIG_OUT7_IDX 86
#define RMT_SIG_OUT0_IDX 87
#define RMT_SIG_OUT1_IDX 88
#define RMT_SIG_OUT2_IDX 89
#define RMT_SIG_OUT3_IDX 90
#define EXT_ADC_START_IDX 93
#define I2CEXT1_SCL_IN_IDX 95
#define I2CEXT1_SCL_OUT_IDX 95
#define I2CEXT1_SDA_IN_IDX 96
#define I2CEXT1_SDA_OUT_IDX 96
#define GPIO_SD0_OUT_IDX 100
#define GPIO_SD1_OUT_IDX 101
#define GPIO_SD2_OUT_IDX 102
#define GPIO_SD3_OUT_IDX 103
#define GPIO_SD4_OUT_IDX 104
#define GPIO_SD5_OUT_IDX 105
#define GPIO_SD6_OUT_IDX 106
#define GPIO_SD7_OUT_IDX 107
#define SPI4_CLK_IN_IDX 108
#define SPI4_CLK_OUT_MUX_IDX 108
#define SPI4_Q_IN_IDX 109
#define SPI4_Q_OUT_IDX 109
#define SPI4_D_IN_IDX 110
#define SPI4_D_OUT_IDX 110
#define SPI4_HD_IN_IDX 111
#define SPI4_HD_OUT_IDX 111
#define SPI4_CS0_IN_IDX 112
#define SPI4_CS0_OUT_IDX 112
#define SPI4_CS1_OUT_IDX 113
#define SPI4_CS2_OUT_IDX 114
#define FSPICLK_IN_IDX 115
#define FSPICLK_OUT_MUX_IDX 115
#define FSPIQ_IN_IDX 116
#define FSPIQ_OUT_IDX 116
#define FSPID_IN_IDX 117
#define FSPID_OUT_IDX 117
#define FSPIHD_IN_IDX 118
#define FSPIHD_OUT_IDX 118
#define FSPIWP_IN_IDX 119
#define FSPIWP_OUT_IDX 119
#define FSPICS0_IN_IDX 120
#define FSPICS0_OUT_IDX 120
#define FSPICS1_OUT_IDX 121
#define FSPICS2_OUT_IDX 122
#define CAN_RX_IDX 123
#define CAN_TX_IDX 123
#define CAN_BUS_OFF_ON_IDX 124
#define CAN_CLKOUT_IDX 125
#define SUBSPICLK_OUT_MUX_IDX 126
#define SUBSPIQ_IN_IDX 127
#define SUBSPIQ_OUT_IDX 127
#define SUBSPID_IN_IDX 128
#define SUBSPID_OUT_IDX 128
#define SUBSPIHD_IN_IDX 129
#define SUBSPIHD_OUT_IDX 129
#define SUBSPIWP_IN_IDX 130
#define SUBSPIWP_OUT_IDX 130
#define SUBSPICS0_OUT_IDX 131
#define SUBSPICS1_OUT_IDX 132
#define FSPIDQS_OUT_IDX 133
#define SPI3_DQS_OUT_IDX 134
#define SPI4_DQS_OUT_IDX 135
#define I2S0I_DATA_IN0_IDX 143
#define I2S0O_DATA_OUT0_IDX 143
#define I2S0I_DATA_IN1_IDX 144
#define I2S0O_DATA_OUT1_IDX 144
#define I2S0I_DATA_IN2_IDX 145
#define I2S0O_DATA_OUT2_IDX 145
#define I2S0I_DATA_IN3_IDX 146
#define I2S0O_DATA_OUT3_IDX 146
#define I2S0I_DATA_IN4_IDX 147
#define I2S0O_DATA_OUT4_IDX 147
#define I2S0I_DATA_IN5_IDX 148
#define I2S0O_DATA_OUT5_IDX 148
#define I2S0I_DATA_IN6_IDX 149
#define I2S0O_DATA_OUT6_IDX 149
#define I2S0I_DATA_IN7_IDX 150
#define I2S0O_DATA_OUT7_IDX 150
#define I2S0I_DATA_IN8_IDX 151
#define I2S0O_DATA_OUT8_IDX 151
#define I2S0I_DATA_IN9_IDX 152
#define I2S0O_DATA_OUT9_IDX 152
#define I2S0I_DATA_IN10_IDX 153
#define I2S0O_DATA_OUT10_IDX 153
#define I2S0I_DATA_IN11_IDX 154
#define I2S0O_DATA_OUT11_IDX 154
#define I2S0I_DATA_IN12_IDX 155
#define I2S0O_DATA_OUT12_IDX 155
#define I2S0I_DATA_IN13_IDX 156
#define I2S0O_DATA_OUT13_IDX 156
#define I2S0I_DATA_IN14_IDX 157
#define I2S0O_DATA_OUT14_IDX 157
#define I2S0I_DATA_IN15_IDX 158
#define I2S0O_DATA_OUT15_IDX 158
#define I2S0O_DATA_OUT16_IDX 159
#define I2S0O_DATA_OUT17_IDX 160
#define I2S0O_DATA_OUT18_IDX 161
#define I2S0O_DATA_OUT19_IDX 162
#define I2S0O_DATA_OUT20_IDX 163
#define I2S0O_DATA_OUT21_IDX 164
#define I2S0O_DATA_OUT22_IDX 165
#define I2S0O_DATA_OUT23_IDX 166
#define I2S0I_H_SYNC_IDX 193
#define I2S0I_V_SYNC_IDX 194
#define I2S0I_H_ENABLE_IDX 195
#define PCMFSYNC_IN_IDX 203
#define BT_AUDIO0_IRQ_IDX 203
#define PCMCLK_IN_IDX 204
#define BT_AUDIO1_IRQ_IDX 204
#define PCMDIN_IDX 205
#define BT_AUDIO2_IRQ_IDX 205
#define RW_WAKEUP_REQ_IDX 206
#define BLE_AUDIO0_IRQ_IDX 206
#define BLE_AUDIO1_IRQ_IDX 207
#define BLE_AUDIO2_IRQ_IDX 208
#define PCMFSYNC_OUT_IDX 209
#define PCMCLK_OUT_IDX 210
#define PCMDOUT_IDX 211
#define BLE_AUDIO_SYNC0_P_IDX 212
#define BLE_AUDIO_SYNC1_P_IDX 213
#define BLE_AUDIO_SYNC2_P_IDX 214
#define ANT_SEL0_IDX 215
#define ANT_SEL1_IDX 216
#define ANT_SEL2_IDX 217
#define ANT_SEL3_IDX 218
#define ANT_SEL4_IDX 219
#define ANT_SEL5_IDX 220
#define ANT_SEL6_IDX 221
#define ANT_SEL7_IDX 222
#define SIG_IN_FUNC_223_IDX 223
#define SIG_IN_FUNC223_IDX 223
#define SIG_IN_FUNC_224_IDX 224
#define SIG_IN_FUNC224_IDX 224
#define SIG_IN_FUNC_225_IDX 225
#define SIG_IN_FUNC225_IDX 225
#define SIG_IN_FUNC_226_IDX 226
#define SIG_IN_FUNC226_IDX 226
#define SIG_IN_FUNC_227_IDX 227
#define SIG_IN_FUNC227_IDX 227
#define PRO_ALONEGPIO_IN0_IDX 235
#define PRO_ALONEGPIO_OUT0_IDX 235
#define PRO_ALONEGPIO_IN1_IDX 236
#define PRO_ALONEGPIO_OUT1_IDX 236
#define PRO_ALONEGPIO_IN2_IDX 237
#define PRO_ALONEGPIO_OUT2_IDX 237
#define PRO_ALONEGPIO_IN3_IDX 238
#define PRO_ALONEGPIO_OUT3_IDX 238
#define PRO_ALONEGPIO_IN4_IDX 239
#define PRO_ALONEGPIO_OUT4_IDX 239
#define PRO_ALONEGPIO_IN5_IDX 240
#define PRO_ALONEGPIO_OUT5_IDX 240
#define PRO_ALONEGPIO_IN6_IDX 241
#define PRO_ALONEGPIO_OUT6_IDX 241
#define PRO_ALONEGPIO_IN7_IDX 242
#define PRO_ALONEGPIO_OUT7_IDX 242
#define CLK_I2S_MUX_IDX 251
#define SIG_GPIO_OUT_IDX 256
#define GPIO_MAP_DATE_IDX 0x18102600

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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_GPIO_STRUCT_H_
#define _SOC_GPIO_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
uint32_t bt_select; /**/
uint32_t out; /**/
uint32_t out_w1ts; /**/
uint32_t out_w1tc; /**/
union {
struct {
uint32_t data: 22;
uint32_t reserved22:10;
};
uint32_t val;
} out1;
union {
struct {
uint32_t data: 22;
uint32_t reserved22:10;
};
uint32_t val;
} out1_w1ts;
union {
struct {
uint32_t data: 22;
uint32_t reserved22:10;
};
uint32_t val;
} out1_w1tc;
union {
struct {
uint32_t sel: 8;
uint32_t reserved8: 24;
};
uint32_t val;
} sdio_select;
uint32_t enable; /**/
uint32_t enable_w1ts; /**/
uint32_t enable_w1tc; /**/
union {
struct {
uint32_t data: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} enable1;
union {
struct {
uint32_t data: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} enable1_w1ts;
union {
struct {
uint32_t data: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} enable1_w1tc;
union {
struct {
uint32_t strapping: 16;
uint32_t reserved16:16;
};
uint32_t val;
} strap;
uint32_t in; /**/
union {
struct {
uint32_t data: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} in1;
uint32_t status; /**/
uint32_t status_w1ts; /**/
uint32_t status_w1tc; /**/
union {
struct {
uint32_t intr_st: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} status1;
union {
struct {
uint32_t intr_st: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} status1_w1ts;
union {
struct {
uint32_t intr_st: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} status1_w1tc;
uint32_t pcpu_int; /**/
uint32_t pcpu_nmi_int; /**/
uint32_t cpusdio_int; /**/
union {
struct {
uint32_t intr: 22;
uint32_t reserved22:10;
};
uint32_t val;
} pcpu_int1;
union {
struct {
uint32_t intr: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} pcpu_nmi_int1;
union {
struct {
uint32_t intr: 22;
uint32_t reserved22:10;
};
uint32_t val;
} cpusdio_int1;
union {
struct {
uint32_t sync2_bypass: 2;
uint32_t pad_driver: 1;
uint32_t sync1_bypass: 2;
uint32_t reserved5: 2;
uint32_t int_type: 3;
uint32_t wakeup_enable: 1;
uint32_t config: 2;
uint32_t int_ena: 5;
uint32_t reserved18: 14;
};
uint32_t val;
} pin[54];
union {
struct {
uint32_t rtc_max: 10;
uint32_t reserved10: 21;
uint32_t start: 1;
};
uint32_t val;
} cali_conf;
union {
struct {
uint32_t value_sync2: 20;
uint32_t reserved20: 10;
uint32_t rdy_real: 1;
uint32_t rdy_sync2: 1;
};
uint32_t val;
} cali_data;
union {
struct {
uint32_t func_sel: 6;
uint32_t sig_in_inv: 1;
uint32_t sig_in_sel: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} func_in_sel_cfg[256];
union {
struct {
uint32_t func_sel: 9;
uint32_t inv_sel: 1;
uint32_t oen_sel: 1;
uint32_t oen_inv_sel: 1;
uint32_t reserved12: 20;
};
uint32_t val;
} func_out_sel_cfg[54];
} gpio_dev_t;
extern gpio_dev_t GPIO;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_GPIO_STRUCT_H_ */

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// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_HINF_REG_H_
#define _SOC_HINF_REG_H_
#include "soc.h"
#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0)
/* HINF_DEVICE_ID_FN1 : R/W ;bitpos:[31:16] ;default: 16'h2222 ; */
/*description: */
#define HINF_DEVICE_ID_FN1 0x0000FFFF
#define HINF_DEVICE_ID_FN1_M ((HINF_DEVICE_ID_FN1_V)<<(HINF_DEVICE_ID_FN1_S))
#define HINF_DEVICE_ID_FN1_V 0xFFFF
#define HINF_DEVICE_ID_FN1_S 16
/* HINF_USER_ID_FN1 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */
/*description: */
#define HINF_USER_ID_FN1 0x0000FFFF
#define HINF_USER_ID_FN1_M ((HINF_USER_ID_FN1_V)<<(HINF_USER_ID_FN1_S))
#define HINF_USER_ID_FN1_V 0xFFFF
#define HINF_USER_ID_FN1_S 0
#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4)
/* HINF_SDIO20_CONF1 : R/W ;bitpos:[31:29] ;default: 3'h0 ; */
/*description: */
#define HINF_SDIO20_CONF1 0x00000007
#define HINF_SDIO20_CONF1_M ((HINF_SDIO20_CONF1_V)<<(HINF_SDIO20_CONF1_S))
#define HINF_SDIO20_CONF1_V 0x7
#define HINF_SDIO20_CONF1_S 29
/* HINF_FUNC2_EPS : RO ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
#define HINF_FUNC2_EPS (BIT(28))
#define HINF_FUNC2_EPS_M (BIT(28))
#define HINF_FUNC2_EPS_V 0x1
#define HINF_FUNC2_EPS_S 28
/* HINF_SDIO_VER : R/W ;bitpos:[27:16] ;default: 12'h111 ; */
/*description: */
#define HINF_SDIO_VER 0x00000FFF
#define HINF_SDIO_VER_M ((HINF_SDIO_VER_V)<<(HINF_SDIO_VER_S))
#define HINF_SDIO_VER_V 0xFFF
#define HINF_SDIO_VER_S 16
/* HINF_SDIO20_CONF0 : R/W ;bitpos:[15:12] ;default: 4'b0 ; */
/*description: */
#define HINF_SDIO20_CONF0 0x0000000F
#define HINF_SDIO20_CONF0_M ((HINF_SDIO20_CONF0_V)<<(HINF_SDIO20_CONF0_S))
#define HINF_SDIO20_CONF0_V 0xF
#define HINF_SDIO20_CONF0_S 12
/* HINF_IOENABLE1 : RO ;bitpos:[11] ;default: 1'b0 ; */
/*description: */
#define HINF_IOENABLE1 (BIT(11))
#define HINF_IOENABLE1_M (BIT(11))
#define HINF_IOENABLE1_V 0x1
#define HINF_IOENABLE1_S 11
/* HINF_EMP : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: */
#define HINF_EMP (BIT(10))
#define HINF_EMP_M (BIT(10))
#define HINF_EMP_V 0x1
#define HINF_EMP_S 10
/* HINF_FUNC1_EPS : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: */
#define HINF_FUNC1_EPS (BIT(9))
#define HINF_FUNC1_EPS_M (BIT(9))
#define HINF_FUNC1_EPS_V 0x1
#define HINF_FUNC1_EPS_S 9
/* HINF_CD_DISABLE : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: */
#define HINF_CD_DISABLE (BIT(8))
#define HINF_CD_DISABLE_M (BIT(8))
#define HINF_CD_DISABLE_V 0x1
#define HINF_CD_DISABLE_S 8
/* HINF_IOENABLE2 : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: */
#define HINF_IOENABLE2 (BIT(7))
#define HINF_IOENABLE2_M (BIT(7))
#define HINF_IOENABLE2_V 0x1
#define HINF_IOENABLE2_S 7
/* HINF_SDIO_INT_MASK : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: */
#define HINF_SDIO_INT_MASK (BIT(6))
#define HINF_SDIO_INT_MASK_M (BIT(6))
#define HINF_SDIO_INT_MASK_V 0x1
#define HINF_SDIO_INT_MASK_S 6
/* HINF_SDIO_IOREADY2 : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
#define HINF_SDIO_IOREADY2 (BIT(5))
#define HINF_SDIO_IOREADY2_M (BIT(5))
#define HINF_SDIO_IOREADY2_V 0x1
#define HINF_SDIO_IOREADY2_S 5
/* HINF_SDIO_CD_ENABLE : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: */
#define HINF_SDIO_CD_ENABLE (BIT(4))
#define HINF_SDIO_CD_ENABLE_M (BIT(4))
#define HINF_SDIO_CD_ENABLE_V 0x1
#define HINF_SDIO_CD_ENABLE_S 4
/* HINF_HIGHSPEED_MODE : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define HINF_HIGHSPEED_MODE (BIT(3))
#define HINF_HIGHSPEED_MODE_M (BIT(3))
#define HINF_HIGHSPEED_MODE_V 0x1
#define HINF_HIGHSPEED_MODE_S 3
/* HINF_HIGHSPEED_ENABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define HINF_HIGHSPEED_ENABLE (BIT(2))
#define HINF_HIGHSPEED_ENABLE_M (BIT(2))
#define HINF_HIGHSPEED_ENABLE_V 0x1
#define HINF_HIGHSPEED_ENABLE_S 2
/* HINF_SDIO_IOREADY1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define HINF_SDIO_IOREADY1 (BIT(1))
#define HINF_SDIO_IOREADY1_M (BIT(1))
#define HINF_SDIO_IOREADY1_V 0x1
#define HINF_SDIO_IOREADY1_S 1
/* HINF_SDIO_ENABLE : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define HINF_SDIO_ENABLE (BIT(0))
#define HINF_SDIO_ENABLE_M (BIT(0))
#define HINF_SDIO_ENABLE_V 0x1
#define HINF_SDIO_ENABLE_S 0
#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1C)
/* HINF_SDIO_IOREADY0 : R/W ;bitpos:[17] ;default: 1'b1 ; */
/*description: */
#define HINF_SDIO_IOREADY0 (BIT(17))
#define HINF_SDIO_IOREADY0_M (BIT(17))
#define HINF_SDIO_IOREADY0_V 0x1
#define HINF_SDIO_IOREADY0_S 17
/* HINF_SDIO_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: */
#define HINF_SDIO_RST (BIT(16))
#define HINF_SDIO_RST_M (BIT(16))
#define HINF_SDIO_RST_V 0x1
#define HINF_SDIO_RST_S 16
/* HINF_CHIP_STATE : R/W ;bitpos:[15:8] ;default: 8'b0 ; */
/*description: */
#define HINF_CHIP_STATE 0x000000FF
#define HINF_CHIP_STATE_M ((HINF_CHIP_STATE_V)<<(HINF_CHIP_STATE_S))
#define HINF_CHIP_STATE_V 0xFF
#define HINF_CHIP_STATE_S 8
/* HINF_PIN_STATE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
/*description: */
#define HINF_PIN_STATE 0x000000FF
#define HINF_PIN_STATE_M ((HINF_PIN_STATE_V)<<(HINF_PIN_STATE_S))
#define HINF_PIN_STATE_V 0xFF
#define HINF_PIN_STATE_S 0
#define HINF_CIS_CONF0_REG (DR_REG_HINF_BASE + 0x20)
/* HINF_CIS_CONF_W0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: */
#define HINF_CIS_CONF_W0 0xFFFFFFFF
#define HINF_CIS_CONF_W0_M ((HINF_CIS_CONF_W0_V)<<(HINF_CIS_CONF_W0_S))
#define HINF_CIS_CONF_W0_V 0xFFFFFFFF
#define HINF_CIS_CONF_W0_S 0
#define HINF_CIS_CONF1_REG (DR_REG_HINF_BASE + 0x24)
/* HINF_CIS_CONF_W1 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: */
#define HINF_CIS_CONF_W1 0xFFFFFFFF
#define HINF_CIS_CONF_W1_M ((HINF_CIS_CONF_W1_V)<<(HINF_CIS_CONF_W1_S))
#define HINF_CIS_CONF_W1_V 0xFFFFFFFF
#define HINF_CIS_CONF_W1_S 0
#define HINF_CIS_CONF2_REG (DR_REG_HINF_BASE + 0x28)
/* HINF_CIS_CONF_W2 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: */
#define HINF_CIS_CONF_W2 0xFFFFFFFF
#define HINF_CIS_CONF_W2_M ((HINF_CIS_CONF_W2_V)<<(HINF_CIS_CONF_W2_S))
#define HINF_CIS_CONF_W2_V 0xFFFFFFFF
#define HINF_CIS_CONF_W2_S 0
#define HINF_CIS_CONF3_REG (DR_REG_HINF_BASE + 0x2C)
/* HINF_CIS_CONF_W3 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: */
#define HINF_CIS_CONF_W3 0xFFFFFFFF
#define HINF_CIS_CONF_W3_M ((HINF_CIS_CONF_W3_V)<<(HINF_CIS_CONF_W3_S))
#define HINF_CIS_CONF_W3_V 0xFFFFFFFF
#define HINF_CIS_CONF_W3_S 0
#define HINF_CIS_CONF4_REG (DR_REG_HINF_BASE + 0x30)
/* HINF_CIS_CONF_W4 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: */
#define HINF_CIS_CONF_W4 0xFFFFFFFF
#define HINF_CIS_CONF_W4_M ((HINF_CIS_CONF_W4_V)<<(HINF_CIS_CONF_W4_S))
#define HINF_CIS_CONF_W4_V 0xFFFFFFFF
#define HINF_CIS_CONF_W4_S 0
#define HINF_CIS_CONF5_REG (DR_REG_HINF_BASE + 0x34)
/* HINF_CIS_CONF_W5 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: */
#define HINF_CIS_CONF_W5 0xFFFFFFFF
#define HINF_CIS_CONF_W5_M ((HINF_CIS_CONF_W5_V)<<(HINF_CIS_CONF_W5_S))
#define HINF_CIS_CONF_W5_V 0xFFFFFFFF
#define HINF_CIS_CONF_W5_S 0
#define HINF_CIS_CONF6_REG (DR_REG_HINF_BASE + 0x38)
/* HINF_CIS_CONF_W6 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: */
#define HINF_CIS_CONF_W6 0xFFFFFFFF
#define HINF_CIS_CONF_W6_M ((HINF_CIS_CONF_W6_V)<<(HINF_CIS_CONF_W6_S))
#define HINF_CIS_CONF_W6_V 0xFFFFFFFF
#define HINF_CIS_CONF_W6_S 0
#define HINF_CIS_CONF7_REG (DR_REG_HINF_BASE + 0x3C)
/* HINF_CIS_CONF_W7 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: */
#define HINF_CIS_CONF_W7 0xFFFFFFFF
#define HINF_CIS_CONF_W7_M ((HINF_CIS_CONF_W7_V)<<(HINF_CIS_CONF_W7_S))
#define HINF_CIS_CONF_W7_V 0xFFFFFFFF
#define HINF_CIS_CONF_W7_S 0
#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40)
/* HINF_DEVICE_ID_FN2 : R/W ;bitpos:[31:16] ;default: 16'h3333 ; */
/*description: */
#define HINF_DEVICE_ID_FN2 0x0000FFFF
#define HINF_DEVICE_ID_FN2_M ((HINF_DEVICE_ID_FN2_V)<<(HINF_DEVICE_ID_FN2_S))
#define HINF_DEVICE_ID_FN2_V 0xFFFF
#define HINF_DEVICE_ID_FN2_S 16
/* HINF_USER_ID_FN2 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */
/*description: */
#define HINF_USER_ID_FN2 0x0000FFFF
#define HINF_USER_ID_FN2_M ((HINF_USER_ID_FN2_V)<<(HINF_USER_ID_FN2_S))
#define HINF_USER_ID_FN2_V 0xFFFF
#define HINF_USER_ID_FN2_S 0
#define HINF_DATE_REG (DR_REG_HINF_BASE + 0xFC)
/* HINF_SDIO_DATE : R/W ;bitpos:[31:0] ;default: 32'h15030200 ; */
/*description: */
#define HINF_SDIO_DATE 0xFFFFFFFF
#define HINF_SDIO_DATE_M ((HINF_SDIO_DATE_V)<<(HINF_SDIO_DATE_S))
#define HINF_SDIO_DATE_V 0xFFFFFFFF
#define HINF_SDIO_DATE_S 0
#endif /*_SOC_HINF_REG_H_ */

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// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_HINF_STRUCT_H_
#define _SOC_HINF_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t user_id_fn1: 16;
uint32_t device_id_fn1:16;
};
uint32_t val;
} cfg_data0;
union {
struct {
uint32_t sdio_enable: 1;
uint32_t sdio_ioready1: 1;
uint32_t highspeed_enable: 1;
uint32_t highspeed_mode: 1;
uint32_t sdio_cd_enable: 1;
uint32_t sdio_ioready2: 1;
uint32_t sdio_int_mask: 1;
uint32_t ioenable2: 1;
uint32_t cd_disable: 1;
uint32_t func1_eps: 1;
uint32_t emp: 1;
uint32_t ioenable1: 1;
uint32_t sdio20_conf0: 4;
uint32_t sdio_ver: 12;
uint32_t func2_eps: 1;
uint32_t sdio20_conf1: 3;
};
uint32_t val;
} cfg_data1;
uint32_t reserved_8;
uint32_t reserved_c;
uint32_t reserved_10;
uint32_t reserved_14;
uint32_t reserved_18;
union {
struct {
uint32_t pin_state: 8;
uint32_t chip_state: 8;
uint32_t sdio_rst: 1;
uint32_t sdio_ioready0: 1;
uint32_t reserved18: 14;
};
uint32_t val;
} cfg_data7;
uint32_t cis_conf0; /**/
uint32_t cis_conf1; /**/
uint32_t cis_conf2; /**/
uint32_t cis_conf3; /**/
uint32_t cis_conf4; /**/
uint32_t cis_conf5; /**/
uint32_t cis_conf6; /**/
uint32_t cis_conf7; /**/
union {
struct {
uint32_t user_id_fn2: 16;
uint32_t device_id_fn2:16;
};
uint32_t val;
} cfg_data16;
uint32_t reserved_44;
uint32_t reserved_48;
uint32_t reserved_4c;
uint32_t reserved_50;
uint32_t reserved_54;
uint32_t reserved_58;
uint32_t reserved_5c;
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t date; /**/
} hinf_dev_t;
extern hinf_dev_t HINF;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_HINF_STRUCT_H_ */

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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_HOST_STRUCT_H_
#define _SOC_HOST_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
uint32_t reserved_0;
uint32_t reserved_4;
uint32_t reserved_8;
uint32_t reserved_c;
uint32_t reserved_10;
uint32_t reserved_14;
uint32_t reserved_18;
uint32_t reserved_1c;
union {
struct {
uint32_t func1_mdstat: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} func2_2;
uint32_t reserved_24;
uint32_t reserved_28;
uint32_t reserved_2c;
uint32_t reserved_30;
uint32_t gpio_status0; /**/
union {
struct {
uint32_t sdio_int1: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} gpio_status1;
uint32_t gpio_in0; /**/
union {
struct {
uint32_t sdio_in1: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} gpio_in1;
union {
struct {
uint32_t token0: 12;
uint32_t rx_pf_valid: 1;
uint32_t reserved13: 3;
uint32_t reg_token1: 12;
uint32_t rx_pf_eof: 4;
};
uint32_t val;
} slc0_token_rdata;
uint32_t slc0_pf; /**/
uint32_t reserved_4c;
union {
struct {
uint32_t tohost_bit0: 1;
uint32_t tohost_bit1: 1;
uint32_t tohost_bit2: 1;
uint32_t tohost_bit3: 1;
uint32_t tohost_bit4: 1;
uint32_t tohost_bit5: 1;
uint32_t tohost_bit6: 1;
uint32_t tohost_bit7: 1;
uint32_t token0_1to0: 1;
uint32_t token1_1to0: 1;
uint32_t token0_0to1: 1;
uint32_t token1_0to1: 1;
uint32_t rx_sof: 1;
uint32_t rx_eof: 1;
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_udf: 1;
uint32_t tx_ovf: 1;
uint32_t rx_pf_valid: 1;
uint32_t ext_bit0: 1;
uint32_t ext_bit1: 1;
uint32_t ext_bit2: 1;
uint32_t ext_bit3: 1;
uint32_t rx_new_packet: 1;
uint32_t rd_retry: 1;
uint32_t gpio_sdio: 1;
uint32_t reserved26: 6;
};
uint32_t val;
} slc0_int_raw;
uint32_t reserved_54;
union {
struct {
uint32_t tohost_bit0: 1;
uint32_t tohost_bit1: 1;
uint32_t tohost_bit2: 1;
uint32_t tohost_bit3: 1;
uint32_t tohost_bit4: 1;
uint32_t tohost_bit5: 1;
uint32_t tohost_bit6: 1;
uint32_t tohost_bit7: 1;
uint32_t token0_1to0: 1;
uint32_t token1_1to0: 1;
uint32_t token0_0to1: 1;
uint32_t token1_0to1: 1;
uint32_t rx_sof: 1;
uint32_t rx_eof: 1;
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_udf: 1;
uint32_t tx_ovf: 1;
uint32_t rx_pf_valid: 1;
uint32_t ext_bit0: 1;
uint32_t ext_bit1: 1;
uint32_t ext_bit2: 1;
uint32_t ext_bit3: 1;
uint32_t rx_new_packet: 1;
uint32_t rd_retry: 1;
uint32_t gpio_sdio: 1;
uint32_t reserved26: 6;
};
uint32_t val;
} slc0_int_st;
uint32_t reserved_5c;
union {
struct {
uint32_t reg_slc0_len: 20;
uint32_t reg_slc0_len_check:12;
};
uint32_t val;
} pkt_len;
union {
struct {
uint32_t state0: 8;
uint32_t state1: 8;
uint32_t state2: 8;
uint32_t state3: 8;
};
uint32_t val;
} state_w0;
union {
struct {
uint32_t state4: 8;
uint32_t state5: 8;
uint32_t state6: 8;
uint32_t state7: 8;
};
uint32_t val;
} state_w1;
union {
struct {
uint32_t conf0: 8;
uint32_t conf1: 8;
uint32_t conf2: 8;
uint32_t conf3: 8;
};
uint32_t val;
} conf_w0;
union {
struct {
uint32_t conf4: 8;
uint32_t conf5: 8;
uint32_t conf6: 8;
uint32_t conf7: 8;
};
uint32_t val;
} conf_w1;
union {
struct {
uint32_t conf8: 8;
uint32_t conf9: 8;
uint32_t conf10: 8;
uint32_t conf11: 8;
};
uint32_t val;
} conf_w2;
union {
struct {
uint32_t conf12: 8;
uint32_t conf13: 8;
uint32_t conf14: 8;
uint32_t conf15: 8;
};
uint32_t val;
} conf_w3;
union {
struct {
uint32_t conf16: 8; /*SLC timeout value*/
uint32_t conf17: 8; /*SLC timeout enable*/
uint32_t conf18: 8;
uint32_t conf19: 8; /*Interrupt to target CPU*/
};
uint32_t val;
} conf_w4;
union {
struct {
uint32_t conf20: 8;
uint32_t conf21: 8;
uint32_t conf22: 8;
uint32_t conf23: 8;
};
uint32_t val;
} conf_w5;
union {
struct {
uint32_t win_cmd: 16;
uint32_t reserved16: 16;
};
uint32_t val;
} win_cmd;
union {
struct {
uint32_t conf24: 8;
uint32_t conf25: 8;
uint32_t conf26: 8;
uint32_t conf27: 8;
};
uint32_t val;
} conf_w6;
union {
struct {
uint32_t conf28: 8;
uint32_t conf29: 8;
uint32_t conf30: 8;
uint32_t conf31: 8;
};
uint32_t val;
} conf_w7;
union {
struct {
uint32_t reg_slc0_len0: 20;
uint32_t reg_slc0_len0_check:12;
};
uint32_t val;
} pkt_len0;
union {
struct {
uint32_t reg_slc0_len1: 20;
uint32_t reg_slc0_len1_check:12;
};
uint32_t val;
} pkt_len1;
union {
struct {
uint32_t reg_slc0_len2: 20;
uint32_t reg_slc0_len2_check:12;
};
uint32_t val;
} pkt_len2;
union {
struct {
uint32_t conf32: 8;
uint32_t conf33: 8;
uint32_t conf34: 8;
uint32_t conf35: 8;
};
uint32_t val;
} conf_w8;
union {
struct {
uint32_t conf36: 8;
uint32_t conf37: 8;
uint32_t conf38: 8;
uint32_t conf39: 8;
};
uint32_t val;
} conf_w9;
union {
struct {
uint32_t conf40: 8;
uint32_t conf41: 8;
uint32_t conf42: 8;
uint32_t conf43: 8;
};
uint32_t val;
} conf_w10;
union {
struct {
uint32_t conf44: 8;
uint32_t conf45: 8;
uint32_t conf46: 8;
uint32_t conf47: 8;
};
uint32_t val;
} conf_w11;
union {
struct {
uint32_t conf48: 8;
uint32_t conf49: 8;
uint32_t conf50: 8;
uint32_t conf51: 8;
};
uint32_t val;
} conf_w12;
union {
struct {
uint32_t conf52: 8;
uint32_t conf53: 8;
uint32_t conf54: 8;
uint32_t conf55: 8;
};
uint32_t val;
} conf_w13;
union {
struct {
uint32_t conf56: 8;
uint32_t conf57: 8;
uint32_t conf58: 8;
uint32_t conf59: 8;
};
uint32_t val;
} conf_w14;
union {
struct {
uint32_t conf60: 8;
uint32_t conf61: 8;
uint32_t conf62: 8;
uint32_t conf63: 8;
};
uint32_t val;
} conf_w15;
uint32_t check_sum0; /**/
uint32_t check_sum1; /**/
uint32_t reserved_c4;
union {
struct {
uint32_t token0_wd: 12;
uint32_t reserved12: 4;
uint32_t token1_wd: 12;
uint32_t reserved28: 4;
};
uint32_t val;
} slc0_token_wdata;
uint32_t reserved_cc;
union {
struct {
uint32_t slc0_token0_dec: 1;
uint32_t slc0_token1_dec: 1;
uint32_t slc0_token0_wr: 1;
uint32_t slc0_token1_wr: 1;
uint32_t reserved4: 4;
uint32_t slc0_len_wr: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} token_con;
union {
struct {
uint32_t tohost_bit0: 1;
uint32_t tohost_bit1: 1;
uint32_t tohost_bit2: 1;
uint32_t tohost_bit3: 1;
uint32_t tohost_bit4: 1;
uint32_t tohost_bit5: 1;
uint32_t tohost_bit6: 1;
uint32_t tohost_bit7: 1;
uint32_t token0_1to0: 1;
uint32_t token1_1to0: 1;
uint32_t token0_0to1: 1;
uint32_t token1_0to1: 1;
uint32_t rx_sof: 1;
uint32_t rx_eof: 1;
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_udf: 1;
uint32_t tx_ovf: 1;
uint32_t rx_pf_valid: 1;
uint32_t ext_bit0: 1;
uint32_t ext_bit1: 1;
uint32_t ext_bit2: 1;
uint32_t ext_bit3: 1;
uint32_t rx_new_packet: 1;
uint32_t rd_retry: 1;
uint32_t gpio_sdio: 1;
uint32_t reserved26: 6;
};
uint32_t val;
} slc0_int_clr;
uint32_t reserved_d8;
union {
struct {
uint32_t tohost_bit0: 1;
uint32_t tohost_bit1: 1;
uint32_t tohost_bit2: 1;
uint32_t tohost_bit3: 1;
uint32_t tohost_bit4: 1;
uint32_t tohost_bit5: 1;
uint32_t tohost_bit6: 1;
uint32_t tohost_bit7: 1;
uint32_t token0_1to0: 1;
uint32_t token1_1to0: 1;
uint32_t token0_0to1: 1;
uint32_t token1_0to1: 1;
uint32_t rx_sof: 1;
uint32_t rx_eof: 1;
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_udf: 1;
uint32_t tx_ovf: 1;
uint32_t rx_pf_valid: 1;
uint32_t ext_bit0: 1;
uint32_t ext_bit1: 1;
uint32_t ext_bit2: 1;
uint32_t ext_bit3: 1;
uint32_t rx_new_packet: 1;
uint32_t rd_retry: 1;
uint32_t gpio_sdio: 1;
uint32_t reserved26: 6;
};
uint32_t val;
} slc0_func1_int_ena;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
union {
struct {
uint32_t tohost_bit0: 1;
uint32_t tohost_bit1: 1;
uint32_t tohost_bit2: 1;
uint32_t tohost_bit3: 1;
uint32_t tohost_bit4: 1;
uint32_t tohost_bit5: 1;
uint32_t tohost_bit6: 1;
uint32_t tohost_bit7: 1;
uint32_t token0_1to0: 1;
uint32_t token1_1to0: 1;
uint32_t token0_0to1: 1;
uint32_t token1_0to1: 1;
uint32_t rx_sof: 1;
uint32_t rx_eof: 1;
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_udf: 1;
uint32_t tx_ovf: 1;
uint32_t rx_pf_valid: 1;
uint32_t ext_bit0: 1;
uint32_t ext_bit1: 1;
uint32_t ext_bit2: 1;
uint32_t ext_bit3: 1;
uint32_t rx_new_packet: 1;
uint32_t rd_retry: 1;
uint32_t gpio_sdio: 1;
uint32_t reserved26: 6;
};
uint32_t val;
} slc0_int_ena;
uint32_t reserved_f0;
union {
struct {
uint32_t infor: 20;
uint32_t reserved20: 12;
};
uint32_t val;
} slc0_rx_infor;
uint32_t reserved_f8;
uint32_t slc0_len_wd; /**/
uint32_t apbwin_wdata; /**/
union {
struct {
uint32_t addr: 28;
uint32_t wr: 1;
uint32_t start: 1;
uint32_t bus: 1;
uint32_t reserved31: 1;
};
uint32_t val;
} apbwin_conf;
uint32_t apbwin_rdata; /**/
union {
struct {
uint32_t bit7_clraddr: 9;
uint32_t bit6_clraddr: 9;
uint32_t reserved18: 14;
};
uint32_t val;
} slc0_rdclr;
uint32_t reserved_110;
union {
struct {
uint32_t tohost_bit01: 1;
uint32_t tohost_bit11: 1;
uint32_t tohost_bit21: 1;
uint32_t tohost_bit31: 1;
uint32_t tohost_bit41: 1;
uint32_t tohost_bit51: 1;
uint32_t tohost_bit61: 1;
uint32_t tohost_bit71: 1;
uint32_t token0_1to01: 1;
uint32_t token1_1to01: 1;
uint32_t token0_0to11: 1;
uint32_t token1_0to11: 1;
uint32_t rx_sof1: 1;
uint32_t rx_eof1: 1;
uint32_t rx_start1: 1;
uint32_t tx_start1: 1;
uint32_t rx_udf1: 1;
uint32_t tx_ovf1: 1;
uint32_t rx_pf_valid1: 1;
uint32_t ext_bit01: 1;
uint32_t ext_bit11: 1;
uint32_t ext_bit21: 1;
uint32_t ext_bit31: 1;
uint32_t rx_new_packet1: 1;
uint32_t rd_retry1: 1;
uint32_t gpio_sdio1: 1;
uint32_t reserved26: 6;
};
uint32_t val;
} slc0_int_ena1;
uint32_t reserved_118;
uint32_t reserved_11c;
uint32_t reserved_120;
uint32_t reserved_124;
uint32_t reserved_128;
uint32_t reserved_12c;
uint32_t reserved_130;
uint32_t reserved_134;
uint32_t reserved_138;
uint32_t reserved_13c;
uint32_t reserved_140;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t date; /**/
uint32_t id; /**/
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
union {
struct {
uint32_t frc_sdio11: 5;
uint32_t frc_sdio20: 5;
uint32_t frc_neg_samp: 5;
uint32_t frc_pos_samp: 5;
uint32_t frc_quick_in: 5;
uint32_t sdio20_int_delay: 1;
uint32_t sdio_pad_pullup: 1;
uint32_t hspeed_con_en: 1;
uint32_t reserved28: 4;
};
uint32_t val;
} conf;
union {
struct {
uint32_t sdio20_mode: 5;
uint32_t sdio_neg_samp: 5;
uint32_t sdio_quick_in: 5;
uint32_t reserved15: 17;
};
uint32_t val;
} inf_st;
} host_dev_t;
extern host_dev_t HOST;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_HOST_STRUCT_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __HWCRYPTO_REG_H__
#define __HWCRYPTO_REG_H__
#include "soc.h"
/* registers for RSA acceleration via Multiple Precision Integer ops */
#define RSA_MEM_M_BLOCK_BASE ((DR_REG_RSA_BASE)+0x000)
/* RB & Z use the same memory block, depending on phase of operation */
#define RSA_MEM_RB_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200)
#define RSA_MEM_Z_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200)
#define RSA_MEM_Y_BLOCK_BASE ((DR_REG_RSA_BASE)+0x400)
#define RSA_MEM_X_BLOCK_BASE ((DR_REG_RSA_BASE)+0x600)
/* Configuration registers */
#define RSA_M_DASH_REG (DR_REG_RSA_BASE + 0x800)
#define RSA_LENGTH_REG (DR_REG_RSA_BASE + 0x804)
#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820)
#define RSA_SEARCH_OPEN_REG (DR_REG_RSA_BASE + 0x824)
#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828)
/* Initialization registers */
#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808)
/* Calculation start registers */
#define RSA_MODEXP_START_REG (DR_REG_RSA_BASE + 0x80c)
#define RSA_MOD_MULT_START_REG (DR_REG_RSA_BASE + 0x810)
#define RSA_MULT_START_REG (DR_REG_RSA_BASE + 0x814)
/* Interrupt registers */
#define RSA_QUERY_INTERRUPT_REG (DR_REG_RSA_BASE + 0x818)
#define RSA_CLEAR_INTERRUPT_REG (DR_REG_RSA_BASE + 0x81C)
/* SHA acceleration registers */
#define SHA_MODE_REG ((DR_REG_SHA_BASE) + 0x00)
#define SHA_MODE_SHA1 0
#define SHA_MODE_SHA224 1
#define SHA_MODE_SHA256 2
#define SHA_MODE_SHA384 3
#define SHA_MODE_SHA512 4
#define SHA_MODE_SHA512_224 5
#define SHA_MODE_SHA512_256 6
#define SHA_MODE_SHA512_T 7
#define SHA_T_STRING_REG ((DR_REG_SHA_BASE) + 0x04)
#define SHA_T_LENGTH_REG ((DR_REG_SHA_BASE) + 0x08)
#define SHA_START_REG ((DR_REG_SHA_BASE) + 0x0c)
#define SHA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x10)
#define SHA_BUSY_REG ((DR_REG_SHA_BASE) + 0x14)
#define SHA_H_BASE ((DR_REG_SHA_BASE) + 0x40)
#define SHA_M_BASE ((DR_REG_SHA_BASE) + 0x80)
/* AES acceleration registers */
#define AES_MODE_REG ((DR_REG_AES_BASE) + 0x40)
#define AES_ENDIAN_REG ((DR_REG_AES_BASE) + 0x44)
#define AES_TRIGGER_REG ((DR_REG_AES_BASE) + 0x48)
#define AES_STATE_REG ((DR_REG_AES_BASE) + 0x4c)
#define AES_KEY_BASE ((DR_REG_AES_BASE) + 0x00)
#define AES_TEXT_IN_BASE ((DR_REG_AES_BASE) + 0x20)
#define AES_TEXT_OUT_BASE ((DR_REG_AES_BASE) + 0x30)
/* HMAC Module */
#define HMAC_SET_START_REG ((DR_REG_HMAC_BASE) + 0x40)
#define HMAC_SET_PARA_PURPOSE_REG ((DR_REG_HMAC_BASE) + 0x44)
#define HMAC_SET_PARA_KEY_REG ((DR_REG_HMAC_BASE) + 0x48)
#define HMAC_SET_PARA_FINISH_REG ((DR_REG_HMAC_BASE) + 0x4c)
#define HMAC_SET_MESSAGE_ONE_REG ((DR_REG_HMAC_BASE) + 0x50)
#define HMAC_SET_MESSAGE_ING_REG ((DR_REG_HMAC_BASE) + 0x54)
#define HMAC_SET_MESSAGE_END_REG ((DR_REG_HMAC_BASE) + 0x58)
#define HMAC_SET_RESULT_FINISH_REG ((DR_REG_HMAC_BASE) + 0x5c)
#define HMAC_SET_INVALIDATE_JTAG_REG ((DR_REG_HMAC_BASE) + 0x60)
#define HMAC_SET_INVALIDATE_DS_REG ((DR_REG_HMAC_BASE) + 0x64)
#define HMAC_QUERY_ERROR_REG ((DR_REG_HMAC_BASE) + 0x68)
#define HMAC_QUERY_BUSY_REG ((DR_REG_HMAC_BASE) + 0x6c)
#define HMAC_WDATA_BASE ((DR_REG_HMAC_BASE) + 0x80)
#define HMAC_RDATA_BASE ((DR_REG_HMAC_BASE) + 0xC0)
#define HMAC_SET_MESSAGE_PAD_REG ((DR_REG_HMAC_BASE) + 0xF0)
/* AES-XTS registers */
#define AES_XTS_PLAIN_BASE ((DR_REG_AES_BASE) + 0x80)
#define AES_XTS_SIZE_REG ((DR_REG_AES_BASE) + 0xC0)
#define AES_XTS_DESTINATION_REG ((DR_REG_AES_BASE) + 0xC4)
#define AES_XTS_PHYSICAL_ADDR_REG ((DR_REG_AES_BASE) + 0xC8)
#define AES_XTS_TRIGGER_REG ((DR_REG_AES_BASE) + 0xCC)
#define AES_XTS_RELEASE_REG ((DR_REG_AES_BASE) + 0xD0)
#define AES_XTS_DESTROY_REG ((DR_REG_AES_BASE) + 0xD4)
#define AES_XTS_STATE_REG ((DR_REG_AES_BASE) + 0xD8)
#endif

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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_I2C_STRUCT_H_
#define _SOC_I2C_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t period:14; /*This register is used to configure the low level width of SCL clock.*/
uint32_t reserved14: 18;
};
uint32_t val;
} scl_low_period;
union {
struct {
uint32_t sda_force_out: 1; /*1：normally output sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/
uint32_t scl_force_out: 1; /*1：normally output scl clock 0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/
uint32_t sample_scl_level: 1; /*Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level.*/
uint32_t ack_level: 1;
uint32_t ms_mode: 1; /*Set this bit to configure the module as i2c master clear this bit to configure the module as i2c slave.*/
uint32_t trans_start: 1; /*Set this bit to start sending data in tx_fifo.*/
uint32_t tx_lsb_first: 1; /*This bit is used to control the sending mode for data need to be send. 1：receive data from most significant bit 0：receive data from least significant bit*/
uint32_t rx_lsb_first: 1; /*This bit is used to control the storage mode for received data. 1：receive data from most significant bit 0：receive data from least significant bit*/
uint32_t clk_en: 1; /*This is the clock gating control bit for reading or writing registers.*/
uint32_t arbitration_en: 1;
uint32_t fsm_rst: 1;
uint32_t ref_always_on: 1;
uint32_t reserved12: 20;
};
uint32_t val;
} ctr;
union {
struct {
uint32_t ack_rec: 1; /*This register stores the value of ACK bit.*/
uint32_t slave_rw: 1; /*when in slave mode 1：master read slave 0: master write slave.*/
uint32_t time_out: 1; /*when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level.*/
uint32_t arb_lost: 1; /*when I2C lost control of SDA line this register changes to high level.*/
uint32_t bus_busy: 1; /*1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/
uint32_t slave_addressed: 1; /*when configured as i2c slave and the address send by master is equal to slave's address then this bit will be high level.*/
uint32_t byte_trans: 1; /*This register changes to high level when one byte is transferred.*/
uint32_t reserved7: 1;
uint32_t rx_fifo_cnt: 6; /*This register represent the amount of data need to send.*/
uint32_t reserved14: 4;
uint32_t tx_fifo_cnt: 6; /*This register stores the amount of received data in ram.*/
uint32_t scl_main_state_last: 3; /*This register stores the value of state machine for i2c module. 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/
uint32_t reserved27: 1;
uint32_t scl_state_last: 3; /*This register stores the value of state machine to produce SCL. 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/
uint32_t reserved31: 1;
};
uint32_t val;
} status_reg;
union {
struct {
uint32_t tout: 24;
uint32_t time_out_en: 1;
uint32_t reserved25: 7;
};
uint32_t val;
} timeout;
union {
struct {
uint32_t addr: 15; /*when configured as i2c slave this register is used to configure slave's address.*/
uint32_t reserved15: 16;
uint32_t en_10bit: 1; /*This register is used to enable slave 10bit address mode.*/
};
uint32_t val;
} slave_addr;
union {
struct {
uint32_t rx_fifo_start_addr: 5; /*This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.*/
uint32_t rx_fifo_end_addr: 5; /*This is the offset address of the first receiving data as described in nonfifo_rx_thres_register.*/
uint32_t tx_fifo_start_addr: 5; /*This is the offset address of the first sending data as described in nonfifo_tx_thres register.*/
uint32_t tx_fifo_end_addr: 5; /*This is the offset address of the last sending data as described in nonfifo_tx_thres register.*/
uint32_t rx_update: 1;
uint32_t tx_update: 1;
uint32_t tx_fifo_init_raddr: 5;
uint32_t rx_fifo_init_waddr: 5;
};
uint32_t val;
} fifo_st;
union {
struct {
uint32_t rx_fifo_full_thrhd: 5;
uint32_t tx_fifo_empty_thrhd:5; /*Config tx_fifo empty threhd value when using apb fifo access*/
uint32_t nonfifo_en: 1; /*Set this bit to enble apb nonfifo access.*/
uint32_t fifo_addr_cfg_en: 1; /*When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram.*/
uint32_t rx_fifo_rst: 1; /*Set this bit to reset rx fifo when using apb fifo access.*/
uint32_t tx_fifo_rst: 1; /*Set this bit to reset tx fifo when using apb fifo access.*/
uint32_t nonfifo_rx_thres: 6; /*when I2C receives more than nonfifo_rx_thres data it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/
uint32_t nonfifo_tx_thres: 6; /*when I2C sends more than nonfifo_tx_thres data it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/
uint32_t reserved26: 6;
};
uint32_t val;
} fifo_conf;
union {
struct {
uint8_t data; /*The register represent the byte data read from rx_fifo when use apb fifo access*/
uint8_t reserved[3];
};
uint32_t val;
} fifo_data;
union {
struct {
uint32_t rx_fifo_full: 1; /*The raw interrupt status bit for rx_fifo full when use apb fifo access.*/
uint32_t tx_fifo_empty: 1; /*The raw interrupt status bit for tx_fifo empty when use apb fifo access.*/
uint32_t rx_fifo_ovf: 1; /*The raw interrupt status bit for receiving data overflow when use apb fifo access.*/
uint32_t end_detect: 1; /*The raw interrupt status bit for end_detect_int interrupt. when I2C deals with the END command it will produce end_detect_int interrupt.*/
uint32_t slave_tran_comp: 1; /*The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detects the STOP bit it will produce slave_tran_comp_int interrupt.*/
uint32_t arbitration_lost: 1; /*The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/
uint32_t master_tran_comp: 1; /*The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/
uint32_t trans_complete: 1; /*The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/
uint32_t time_out: 1; /*The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/
uint32_t trans_start: 1; /*The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt.*/
uint32_t ack_err: 1; /*The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/
uint32_t rx_rec_full: 1; /*The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/
uint32_t tx_send_empty: 1; /*The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/
uint32_t scl_st_to: 1;
uint32_t scl_main_st_to: 1;
uint32_t det_start: 1;
uint32_t reserved16: 16;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t rx_fifo_full: 1; /*Set this bit to clear the rx_fifo_full_int interrupt.*/
uint32_t tx_fifo_empty: 1; /*Set this bit to clear the tx_fifo_empty_int interrupt.*/
uint32_t rx_fifo_ovf: 1; /*Set this bit to clear the rx_fifo_ovf_int interrupt.*/
uint32_t end_detect: 1; /*Set this bit to clear the end_detect_int interrupt.*/
uint32_t slave_tran_comp: 1; /*Set this bit to clear the slave_tran_comp_int interrupt.*/
uint32_t arbitration_lost: 1; /*Set this bit to clear the arbitration_lost_int interrupt.*/
uint32_t master_tran_comp: 1; /*Set this bit to clear the master_tran_comp interrupt.*/
uint32_t trans_complete: 1; /*Set this bit to clear the trans_complete_int interrupt.*/
uint32_t time_out: 1; /*Set this bit to clear the time_out_int interrupt.*/
uint32_t trans_start: 1; /*Set this bit to clear the trans_start_int interrupt.*/
uint32_t ack_err: 1; /*Set this bit to clear the ack_err_int interrupt.*/
uint32_t rx_rec_full: 1; /*Set this bit to clear the rx_rec_full_int interrupt.*/
uint32_t tx_send_empty: 1; /*Set this bit to clear the tx_send_empty_int interrupt.*/
uint32_t scl_st_to: 1;
uint32_t scl_main_st_to: 1;
uint32_t det_start: 1;
uint32_t reserved16: 16;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t rx_fifo_full: 1; /*The enable bit for rx_fifo_full_int interrupt.*/
uint32_t tx_fifo_empty: 1; /*The enable bit for tx_fifo_empty_int interrupt.*/
uint32_t rx_fifo_ovf: 1; /*The enable bit for rx_fifo_ovf_int interrupt.*/
uint32_t end_detect: 1; /*The enable bit for end_detect_int interrupt.*/
uint32_t slave_tran_comp: 1; /*The enable bit for slave_tran_comp_int interrupt.*/
uint32_t arbitration_lost: 1; /*The enable bit for arbitration_lost_int interrupt.*/
uint32_t master_tran_comp: 1; /*The enable bit for master_tran_comp_int interrupt.*/
uint32_t trans_complete: 1; /*The enable bit for trans_complete_int interrupt.*/
uint32_t time_out: 1; /*The enable bit for time_out_int interrupt.*/
uint32_t trans_start: 1; /*The enable bit for trans_start_int interrupt.*/
uint32_t ack_err: 1; /*The enable bit for ack_err_int interrupt.*/
uint32_t rx_rec_full: 1; /*The enable bit for rx_rec_full_int interrupt.*/
uint32_t tx_send_empty: 1; /*The enable bit for tx_send_empty_int interrupt.*/
uint32_t scl_st_to: 1;
uint32_t scl_main_st_to: 1;
uint32_t det_start: 1;
uint32_t reserved16: 16;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t rx_fifo_full: 1; /*The masked interrupt status for rx_fifo_full_int interrupt.*/
uint32_t tx_fifo_empty: 1; /*The masked interrupt status for tx_fifo_empty_int interrupt.*/
uint32_t rx_fifo_ovf: 1; /*The masked interrupt status for rx_fifo_ovf_int interrupt.*/
uint32_t end_detect: 1; /*The masked interrupt status for end_detect_int interrupt.*/
uint32_t slave_tran_comp: 1; /*The masked interrupt status for slave_tran_comp_int interrupt.*/
uint32_t arbitration_lost: 1; /*The masked interrupt status for arbitration_lost_int interrupt.*/
uint32_t master_tran_comp: 1; /*The masked interrupt status for master_tran_comp_int interrupt.*/
uint32_t trans_complete: 1; /*The masked interrupt status for trans_complete_int interrupt.*/
uint32_t time_out: 1; /*The masked interrupt status for time_out_int interrupt.*/
uint32_t trans_start: 1; /*The masked interrupt status for trans_start_int interrupt.*/
uint32_t ack_err: 1; /*The masked interrupt status for ack_err_int interrupt.*/
uint32_t rx_rec_full: 1; /*The masked interrupt status for rx_rec_full_int interrupt.*/
uint32_t tx_send_empty: 1; /*The masked interrupt status for tx_send_empty_int interrupt.*/
uint32_t scl_st_to: 1;
uint32_t scl_main_st_to: 1;
uint32_t det_start: 1;
uint32_t reserved16: 16;
};
uint32_t val;
} int_status;
union {
struct {
uint32_t time: 10; /*This register is used to configure the clock num I2C used to hold the data after the negedge of SCL.*/
uint32_t reserved10: 22;
};
uint32_t val;
} sda_hold;
union {
struct {
uint32_t time: 10; /*This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL*/
uint32_t reserved10: 22;
};
uint32_t val;
} sda_sample;
union {
struct {
uint32_t period: 14; /*This register is used to configure the clock num during SCL is low level.*/
uint32_t reserved14: 18;
};
uint32_t val;
} scl_high_period;
uint32_t reserved_3c;
union {
struct {
uint32_t time: 10; /*This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark.*/
uint32_t reserved10: 22;
};
uint32_t val;
} scl_start_hold;
union {
struct {
uint32_t time: 10; /*This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark.*/
uint32_t reserved10: 22;
};
uint32_t val;
} scl_rstart_setup;
union {
struct {
uint32_t time: 14; /*This register is used to configure the clock num after the STOP bit's posedge.*/
uint32_t reserved14: 18;
};
uint32_t val;
} scl_stop_hold;
union {
struct {
uint32_t time: 10; /*This register is used to configure the clock num between the posedge of SCL and the posedge of SDA.*/
uint32_t reserved10: 22;
};
uint32_t val;
} scl_stop_setup;
union {
struct {
uint32_t thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/
uint32_t en: 1; /*This is the filter enable bit for SCL.*/
uint32_t reserved4: 28;
};
uint32_t val;
} scl_filter_cfg;
union {
struct {
uint32_t thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/
uint32_t en: 1; /*This is the filter enable bit for SDA.*/
uint32_t reserved4: 28;
};
uint32_t val;
} sda_filter_cfg;
union {
struct {
uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/
uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/
uint32_t reserved14: 17;
uint32_t done: 1; /*When command0 is done in I2C Master mode this bit changes to high level.*/
};
uint32_t val;
} command[16];
union {
struct {
uint32_t scl_st_to: 24;
uint32_t reserved24: 8;
};
uint32_t val;
} scl_st_time_out;
union {
struct {
uint32_t scl_main_st_to:24;
uint32_t reserved24: 8;
};
uint32_t val;
} scl_main_st_time_out;
union {
struct {
uint32_t scl_rst_slv_en: 1;
uint32_t scl_rst_slv_num: 5;
uint32_t scl_pd_en: 1;
uint32_t sda_pd_en: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} scl_sp_conf;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t date; /**/
uint32_t reserved_fc;
uint32_t ram_data[32]; /*This the start address for ram when use apb nonfifo access.*/
} i2c_dev_t;
extern i2c_dev_t I2C0;
extern i2c_dev_t I2C1;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_I2C_STRUCT_H_ */

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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_I2S_STRUCT_H_
#define _SOC_I2S_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
uint32_t reserved_0;
uint32_t reserved_4;
union {
struct {
uint32_t tx_reset: 1; /*Set this bit to reset transmitter*/
uint32_t rx_reset: 1; /*Set this bit to reset receiver*/
uint32_t tx_fifo_reset: 1; /*Set this bit to reset txFIFO*/
uint32_t rx_fifo_reset: 1; /*Set this bit to reset rxFIFO*/
uint32_t tx_start: 1; /*Set this bit to start transmitting data*/
uint32_t rx_start: 1; /*Set this bit to start receiving data*/
uint32_t tx_slave_mod: 1; /*Set this bit to enable slave transmitter mode*/
uint32_t rx_slave_mod: 1; /*Set this bit to enable slave receiver mode*/
uint32_t tx_right_first: 1; /*Set this bit to transmit right channel data first*/
uint32_t rx_right_first: 1; /*Set this bit to receive right channel data first*/
uint32_t tx_msb_shift: 1; /*Set this bit to enable transmitter in Phillips standard mode*/
uint32_t rx_msb_shift: 1; /*Set this bit to enable receiver in Phillips standard mode*/
uint32_t tx_short_sync: 1; /*Set this bit to enable transmitter in PCM standard mode*/
uint32_t rx_short_sync: 1; /*Set this bit to enable receiver in PCM standard mode*/
uint32_t tx_mono: 1; /*Set this bit to enable transmitter in mono mode*/
uint32_t rx_mono: 1; /*Set this bit to enable receiver in mono mode*/
uint32_t tx_msb_right: 1; /*Set this bit to place right channel data at the MSB in the transmit FIFO.*/
uint32_t rx_msb_right: 1; /*Set this bit to place right channel data at the MSB in the receive FIFO.*/
uint32_t tx_lsb_first_dma: 1; /*1:the data in DMA/APB transform from low bits*/
uint32_t rx_lsb_first_dma: 1; /*1:the data in DMA/APB transform from low bits*/
uint32_t sig_loopback: 1; /*Enable signal loopback mode with transmitter module and receiver module sharing the same WS and BCK signals.*/
uint32_t tx_fifo_reset_st: 1; /*1:i2s_tx_fifo reset is not ok 0:i2s_tx_fifo_reset is ok*/
uint32_t rx_fifo_reset_st: 1; /*1:i2s_rx_fifo_reset is not ok 0:i2s_rx_fifo reset is ok*/
uint32_t tx_reset_st: 1; /*1: i2s_tx_reset is not ok 0: i2s_tx_reset is ok*/
uint32_t tx_dma_equal: 1; /*1:data in left channel is equal to data in right channel*/
uint32_t rx_dma_equal: 1; /*1:data in left channel is equal to data in right channel*/
uint32_t pre_req_en: 1; /*set this bit to enable i2s to prepare data earlier*/
uint32_t tx_big_endian: 1;
uint32_t rx_big_endian: 1;
uint32_t rx_reset_st: 1;
uint32_t reserved30: 2;
};
uint32_t val;
} conf;
union {
struct {
uint32_t rx_take_data: 1; /*The raw interrupt status bit for the i2s_rx_take_data_int interrupt*/
uint32_t tx_put_data: 1; /*The raw interrupt status bit for the i2s_tx_put_data_int interrupt*/
uint32_t rx_wfull: 1; /*The raw interrupt status bit for the i2s_rx_wfull_int interrupt*/
uint32_t rx_rempty: 1; /*The raw interrupt status bit for the i2s_rx_rempty_int interrupt*/
uint32_t tx_wfull: 1; /*The raw interrupt status bit for the i2s_tx_wfull_int interrupt*/
uint32_t tx_rempty: 1; /*The raw interrupt status bit for the i2s_tx_rempty_int interrupt*/
uint32_t rx_hung: 1; /*The raw interrupt status bit for the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*The raw interrupt status bit for the i2s_tx_hung_int interrupt*/
uint32_t in_done: 1; /*The raw interrupt status bit for the i2s_in_done_int interrupt*/
uint32_t in_suc_eof: 1; /*The raw interrupt status bit for the i2s_in_suc_eof_int interrupt*/
uint32_t in_err_eof: 1; /*don't use*/
uint32_t out_done: 1; /*The raw interrupt status bit for the i2s_out_done_int interrupt*/
uint32_t out_eof: 1; /*The raw interrupt status bit for the i2s_out_eof_int interrupt*/
uint32_t in_dscr_err: 1; /*The raw interrupt status bit for the i2s_in_dscr_err_int interrupt*/
uint32_t out_dscr_err: 1; /*The raw interrupt status bit for the i2s_out_dscr_err_int interrupt*/
uint32_t in_dscr_empty: 1; /*The raw interrupt status bit for the i2s_in_dscr_empty_int interrupt*/
uint32_t out_total_eof: 1; /*The raw interrupt status bit for the i2s_out_total_eof_int interrupt*/
uint32_t reserved17: 15;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t rx_take_data: 1; /*The masked interrupt status bit for the i2s_rx_take_data_int interrupt*/
uint32_t tx_put_data: 1; /*The masked interrupt status bit for the i2s_tx_put_data_int interrupt*/
uint32_t rx_wfull: 1; /*The masked interrupt status bit for the i2s_rx_wfull_int interrupt*/
uint32_t rx_rempty: 1; /*The masked interrupt status bit for the i2s_rx_rempty_int interrupt*/
uint32_t tx_wfull: 1; /*The masked interrupt status bit for the i2s_tx_wfull_int interrupt*/
uint32_t tx_rempty: 1; /*The masked interrupt status bit for the i2s_tx_rempty_int interrupt*/
uint32_t rx_hung: 1; /*The masked interrupt status bit for the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*The masked interrupt status bit for the i2s_tx_hung_int interrupt*/
uint32_t in_done: 1; /*The masked interrupt status bit for the i2s_in_done_int interrupt*/
uint32_t in_suc_eof: 1; /*The masked interrupt status bit for the i2s_in_suc_eof_int interrupt*/
uint32_t in_err_eof: 1; /*don't use*/
uint32_t out_done: 1; /*The masked interrupt status bit for the i2s_out_done_int interrupt*/
uint32_t out_eof: 1; /*The masked interrupt status bit for the i2s_out_eof_int interrupt*/
uint32_t in_dscr_err: 1; /*The masked interrupt status bit for the i2s_in_dscr_err_int interrupt*/
uint32_t out_dscr_err: 1; /*The masked interrupt status bit for the i2s_out_dscr_err_int interrupt*/
uint32_t in_dscr_empty: 1; /*The masked interrupt status bit for the i2s_in_dscr_empty_int interrupt*/
uint32_t out_total_eof: 1; /*The masked interrupt status bit for the i2s_out_total_eof_int interrupt*/
uint32_t reserved17: 15;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t rx_take_data: 1; /*The interrupt enable bit for the i2s_rx_take_data_int interrupt*/
uint32_t tx_put_data: 1; /*The interrupt enable bit for the i2s_tx_put_data_int interrupt*/
uint32_t rx_wfull: 1; /*The interrupt enable bit for the i2s_rx_wfull_int interrupt*/
uint32_t rx_rempty: 1; /*The interrupt enable bit for the i2s_rx_rempty_int interrupt*/
uint32_t tx_wfull: 1; /*The interrupt enable bit for the i2s_tx_wfull_int interrupt*/
uint32_t tx_rempty: 1; /*The interrupt enable bit for the i2s_tx_rempty_int interrupt*/
uint32_t rx_hung: 1; /*The interrupt enable bit for the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*The interrupt enable bit for the i2s_tx_hung_int interrupt*/
uint32_t in_done: 1; /*The interrupt enable bit for the i2s_in_done_int interrupt*/
uint32_t in_suc_eof: 1; /*The interrupt enable bit for the i2s_in_suc_eof_int interrupt*/
uint32_t in_err_eof: 1; /*don't use*/
uint32_t out_done: 1; /*The interrupt enable bit for the i2s_out_done_int interrupt*/
uint32_t out_eof: 1; /*The interrupt enable bit for the i2s_out_eof_int interrupt*/
uint32_t in_dscr_err: 1; /*The interrupt enable bit for the i2s_in_dscr_err_int interrupt*/
uint32_t out_dscr_err: 1; /*The interrupt enable bit for the i2s_out_dscr_err_int interrupt*/
uint32_t in_dscr_empty: 1; /*The interrupt enable bit for the i2s_in_dscr_empty_int interrupt*/
uint32_t out_total_eof: 1; /*The interrupt enable bit for the i2s_out_total_eof_int interrupt*/
uint32_t reserved17: 15;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t take_data: 1; /*Set this bit to clear the i2s_rx_take_data_int interrupt*/
uint32_t put_data: 1; /*Set this bit to clear the i2s_tx_put_data_int interrupt*/
uint32_t rx_wfull: 1; /*Set this bit to clear the i2s_rx_wfull_int interrupt*/
uint32_t rx_rempty: 1; /*Set this bit to clear the i2s_rx_rempty_int interrupt*/
uint32_t tx_wfull: 1; /*Set this bit to clear the i2s_tx_wfull_int interrupt*/
uint32_t tx_rempty: 1; /*Set this bit to clear the i2s_tx_rempty_int interrupt*/
uint32_t rx_hung: 1; /*Set this bit to clear the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*Set this bit to clear the i2s_tx_hung_int interrupt*/
uint32_t in_done: 1; /*Set this bit to clear the i2s_in_done_int interrupt*/
uint32_t in_suc_eof: 1; /*Set this bit to clear the i2s_in_suc_eof_int interrupt*/
uint32_t in_err_eof: 1; /*don't use*/
uint32_t out_done: 1; /*Set this bit to clear the i2s_out_done_int interrupt*/
uint32_t out_eof: 1; /*Set this bit to clear the i2s_out_eof_int interrupt*/
uint32_t in_dscr_err: 1; /*Set this bit to clear the i2s_in_dscr_err_int interrupt*/
uint32_t out_dscr_err: 1; /*Set this bit to clear the i2s_out_dscr_err_int interrupt*/
uint32_t in_dscr_empty: 1; /*Set this bit to clear the i2s_in_dscr_empty_int interrupt*/
uint32_t out_total_eof: 1; /*Set this bit to clear the i2s_out_total_eof_int interrupt*/
uint32_t reserved17: 15;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t tx_bck_in_delay: 2; /*Number of delay cycles for BCK into the transmitter*/
uint32_t tx_ws_in_delay: 2; /*Number of delay cycles for WS into the transmitter*/
uint32_t rx_bck_in_delay: 2; /*Number of delay cycles for BCK into the receiver*/
uint32_t rx_ws_in_delay: 2; /*Number of delay cycles for WS into the receiver*/
uint32_t rx_sd_in_delay: 2; /*Number of delay cycles for SD into the receiver*/
uint32_t tx_bck_out_delay: 2; /*Number of delay cycles for BCK out of the transmitter*/
uint32_t tx_ws_out_delay: 2; /*Number of delay cycles for WS out of the transmitter*/
uint32_t tx_sd_out_delay: 2; /*Number of delay cycles for SD out of the transmitter*/
uint32_t rx_ws_out_delay: 2; /*Number of delay cycles for WS out of the receiver*/
uint32_t rx_bck_out_delay: 2; /*Number of delay cycles for BCK out of the receiver*/
uint32_t tx_dsync_sw: 1; /*Set this bit to synchronize signals with the double sync method into the transmitter*/
uint32_t rx_dsync_sw: 1; /*Set this bit to synchronize signals with the double sync method into the receiver*/
uint32_t data_enable_delay: 2; /*Number of delay cycles for data valid flag.*/
uint32_t tx_bck_in_inv: 1; /*Set this bit to invert BCK signal input to the slave transmitter*/
uint32_t reserved25: 7;
};
uint32_t val;
} timing;
union {
struct {
uint32_t rx_data_num: 6; /*Threshold of data length in receiver FIFO*/
uint32_t tx_data_num: 6; /*Threshold of data length in transmitter FIFO*/
uint32_t dscr_en: 1; /*Set this bit to enable I2S DMA mode*/
uint32_t tx_fifo_mod: 3; /*Transmitter FIFO mode configuration bits*/
uint32_t rx_fifo_mod: 3; /*Receiver FIFO mode configuration bits*/
uint32_t tx_fifo_mod_force_en: 1; /*The bit should always be set to 1*/
uint32_t rx_fifo_mod_force_en: 1; /*The bit should always be set to 1*/
uint32_t rx_fifo_sync: 1; /*force write back rx data to memory*/
uint32_t rx_24msb_en: 1; /*Only useful in rx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo*/
uint32_t tx_24msb_en: 1; /*Only useful in tx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo*/
uint32_t reserved24: 8;
};
uint32_t val;
} fifo_conf;
uint32_t rx_eof_num; /*the length of data to be received. It will trigger i2s_in_suc_eof_int.*/
uint32_t conf_single_data; /*the right channel or left channel put out constant value stored in this register according to tx_chan_mod and reg_tx_msb_right*/
union {
struct {
uint32_t tx_chan_mod: 3; /*I2S transmitter channel mode configuration bits.*/
uint32_t rx_chan_mod: 2; /*I2S receiver channel mode configuration bits.*/
uint32_t reserved5: 27;
};
uint32_t val;
} conf_chan;
union {
struct {
uint32_t addr: 20; /*The address of first outlink descriptor*/
uint32_t reserved20: 8;
uint32_t stop: 1; /*Set this bit to stop outlink descriptor*/
uint32_t start: 1; /*Set this bit to start outlink descriptor*/
uint32_t restart: 1; /*Set this bit to restart outlink descriptor*/
uint32_t park: 1;
};
uint32_t val;
} out_link;
union {
struct {
uint32_t addr: 20; /*The address of first inlink descriptor*/
uint32_t reserved20: 8;
uint32_t stop: 1; /*Set this bit to stop inlink descriptor*/
uint32_t start: 1; /*Set this bit to start inlink descriptor*/
uint32_t restart: 1; /*Set this bit to restart inlink descriptor*/
uint32_t park: 1;
};
uint32_t val;
} in_link;
uint32_t out_eof_des_addr; /*The address of outlink descriptor that produces EOF*/
uint32_t in_eof_des_addr; /*The address of inlink descriptor that produces EOF*/
uint32_t out_eof_bfr_des_addr; /*The address of buffer relative to the outlink descriptor that produces EOF*/
union {
struct {
uint32_t mode: 3;
uint32_t reserved3: 1;
uint32_t addr: 2;
uint32_t reserved6: 26;
};
uint32_t val;
} ahb_test;
uint32_t in_link_dscr; /*The address of current inlink descriptor*/
uint32_t in_link_dscr_bf0; /*The address of next inlink descriptor*/
uint32_t in_link_dscr_bf1; /*The address of next inlink data buffer*/
uint32_t out_link_dscr; /*The address of current outlink descriptor*/
uint32_t out_link_dscr_bf0; /*The address of next outlink descriptor*/
uint32_t out_link_dscr_bf1; /*The address of next outlink data buffer*/
union {
struct {
uint32_t in_rst: 1; /*Set this bit to reset in dma FSM*/
uint32_t out_rst: 1; /*Set this bit to reset out dma FSM*/
uint32_t ahbm_fifo_rst: 1; /*Set this bit to reset ahb interface cmdFIFO of DMA*/
uint32_t ahbm_rst: 1; /*Set this bit to reset ahb interface of DMA*/
uint32_t out_loop_test: 1; /*Set this bit to loop test inlink*/
uint32_t in_loop_test: 1; /*Set this bit to loop test outlink*/
uint32_t out_auto_wrback: 1; /*Set this bit to enable outlink-written-back automatically when out buffer is transmitted done.*/
uint32_t out_no_restart_clr: 1; /*don't use*/
uint32_t out_eof_mode: 1; /*DMA out EOF flag generation mode . 1: when dma has popped all data from the FIFO 0:when ahb has pushed all data to the FIFO*/
uint32_t outdscr_burst_en: 1; /*DMA outlink descriptor transfer mode configuration bit. 1: to prepare outlink descriptor with burst mode 0: to prepare outlink descriptor with byte mode*/
uint32_t indscr_burst_en: 1; /*DMA inlink descriptor transfer mode configuration bit. 1: to prepare inlink descriptor with burst mode 0: to prepare inlink descriptor with byte mode*/
uint32_t out_data_burst_en: 1; /*Transmitter data transfer mode configuration bit. 1: to prepare out data with burst mode 0: to prepare out data with byte mode*/
uint32_t check_owner: 1; /*Set this bit to enable check owner bit by hardware*/
uint32_t mem_trans_en: 1; /*don't use*/
uint32_t reserved14: 18;
};
uint32_t val;
} lc_conf;
union {
struct {
uint32_t wdata: 9;
uint32_t reserved9: 7;
uint32_t push: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} out_fifo_push;
union {
struct {
uint32_t rdata: 12;
uint32_t reserved12: 4;
uint32_t pop: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} in_fifo_pop;
union {
struct {
uint32_t dscr_addr: 18;
uint32_t out_dscr_state: 2;
uint32_t out_state: 3;
uint32_t cnt: 7;
uint32_t out_full: 1;
uint32_t out_empty: 1; /*DMA transmitter status register*/
};
uint32_t val;
} lc_state0;
union {
struct {
uint32_t dscr_addr: 18;
uint32_t in_dscr_state: 2;
uint32_t in_state: 3;
uint32_t cnt_debug: 7;
uint32_t in_full: 1;
uint32_t in_empty: 1; /*DMA receiver status register*/
};
uint32_t val;
} lc_state1;
union {
struct {
uint32_t fifo_timeout: 8; /*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value*/
uint32_t fifo_timeout_shift: 3; /*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
uint32_t fifo_timeout_ena: 1; /*The enable bit for FIFO timeout*/
uint32_t reserved12: 20;
};
uint32_t val;
} lc_hung_conf;
uint32_t reserved_78;
uint32_t reserved_7c;
union {
struct {
uint32_t y_max: 16; /*don't use*/
uint32_t y_min: 16; /*don't use*/
};
uint32_t val;
} cvsd_conf0;
union {
struct {
uint32_t sigma_max: 16; /*don't use*/
uint32_t sigma_min: 16; /*don't use*/
};
uint32_t val;
} cvsd_conf1;
union {
struct {
uint32_t cvsd_k: 3; /*don't use*/
uint32_t cvsd_j: 3; /*don't use*/
uint32_t cvsd_beta: 10; /*don't use*/
uint32_t cvsd_h: 3; /*don't use*/
uint32_t reserved19:13; /*don't use*/
};
uint32_t val;
} cvsd_conf2;
union {
struct {
uint32_t good_pack_max: 6; /*don't use*/
uint32_t n_err_seg: 3; /*don't use*/
uint32_t shift_rate: 3; /*don't use*/
uint32_t max_slide_sample: 8; /*don't use*/
uint32_t pack_len_8k: 5; /*don't use*/
uint32_t n_min_err: 3; /*don't use*/
uint32_t reserved28: 4; /*don't use*/
};
uint32_t val;
} plc_conf0;
union {
struct {
uint32_t bad_cef_atten_para: 8; /*don't use*/
uint32_t bad_cef_atten_para_shift: 4; /*don't use*/
uint32_t bad_ola_win2_para_shift: 4; /*don't use*/
uint32_t bad_ola_win2_para: 8; /*don't use*/
uint32_t slide_win_len: 8; /*don't use*/
};
uint32_t val;
} plc_conf1;
union {
struct {
uint32_t cvsd_seg_mod: 2; /*don't use*/
uint32_t min_period: 5; /*don't use*/
uint32_t reserved7: 25; /*don't use*/
};
uint32_t val;
} plc_conf2;
union {
struct {
uint32_t en: 1; /*don't use*/
uint32_t chan_mod: 1; /*don't use*/
uint32_t cvsd_dec_pack_err: 1; /*don't use*/
uint32_t cvsd_pack_len_8k: 5; /*don't use*/
uint32_t cvsd_inf_en: 1; /*don't use*/
uint32_t cvsd_dec_start: 1; /*don't use*/
uint32_t cvsd_dec_reset: 1; /*don't use*/
uint32_t plc_en: 1; /*don't use*/
uint32_t plc2dma_en: 1; /*don't use*/
uint32_t reserved13: 19; /*don't use*/
};
uint32_t val;
} esco_conf0;
union {
struct {
uint32_t with_en: 1; /*don't use*/
uint32_t no_en: 1; /*don't use*/
uint32_t cvsd_enc_start: 1; /*don't use*/
uint32_t cvsd_enc_reset: 1; /*don't use*/
uint32_t reserved4: 28; /*don't use*/
};
uint32_t val;
} sco_conf0;
union {
struct {
uint32_t tx_pcm_conf: 3; /*Compress/Decompress module configuration bits. 0: decompress transmitted data 1:compress transmitted data*/
uint32_t tx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for transmitted data.*/
uint32_t rx_pcm_conf: 3; /*Compress/Decompress module configuration bits. 0: decompress received data 1:compress received data*/
uint32_t rx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for received data.*/
uint32_t tx_stop_en: 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/
uint32_t tx_zeros_rm_en: 1; /*don't use*/
uint32_t reserved10: 22;
};
uint32_t val;
} conf1;
union {
struct {
uint32_t fifo_force_pd: 1; /*Force FIFO power-down*/
uint32_t fifo_force_pu: 1; /*Force FIFO power-up*/
uint32_t plc_mem_force_pd: 1;
uint32_t plc_mem_force_pu: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} pd_conf;
union {
struct {
uint32_t camera_en: 1; /*Set this bit to enable camera mode*/
uint32_t lcd_tx_wrx2_en: 1; /*LCD WR double for one datum.*/
uint32_t lcd_tx_sdx2_en: 1; /*Set this bit to duplicate data pairs (Frame Form 2) in LCD mode.*/
uint32_t data_enable_test_en: 1; /*for debug camera mode enable*/
uint32_t data_enable: 1; /*for debug camera mode enable*/
uint32_t lcd_en: 1; /*Set this bit to enable LCD mode*/
uint32_t ext_adc_start_en: 1; /*Set this bit to enable the function that ADC mode is triggered by external signal.*/
uint32_t inter_valid_en: 1; /*Set this bit to enable camera internal valid*/
uint32_t cam_sync_fifo_reset: 1; /*Set this bit to reset cam_sync_fifo*/
uint32_t cam_clk_loopback: 1; /*Set this bit to loopback cam_clk from i2s_rx*/
uint32_t cam_sync_fifo_reset_st: 1;
uint32_t reserved11: 21;
};
uint32_t val;
} conf2;
union {
struct {
uint32_t clkm_div_num: 8; /*Integral I2S clock divider value*/
uint32_t clkm_div_b: 6; /*Fractional clock divider numerator value*/
uint32_t clkm_div_a: 6; /*Fractional clock divider denominator value*/
uint32_t clk_en: 1; /*Set this bit to enable clk gate*/
uint32_t clk_sel: 2; /*Set this bit to enable clk_apll*/
uint32_t reserved23: 9;
};
uint32_t val;
} clkm_conf;
union {
struct {
uint32_t tx_bck_div_num: 6; /*Bit clock configuration bits in transmitter mode.*/
uint32_t rx_bck_div_num: 6; /*Bit clock configuration bits in receiver mode.*/
uint32_t tx_bits_mod: 6; /*Set the bits to configure bit length of I2S transmitter channel.*/
uint32_t rx_bits_mod: 6; /*Set the bits to configure bit length of I2S receiver channel.*/
uint32_t reserved24: 8;
};
uint32_t val;
} sample_rate_conf;
union {
struct {
uint32_t tx_pdm_en: 1; /*Set this bit to enable transmitter PDM mode*/
uint32_t rx_pdm_en: 1; /*Set this bit to enable receiver PDM mode*/
uint32_t pcm2pdm_conv_en: 1; /*Set this bit to enable PCM-to-PDM converter*/
uint32_t pdm2pcm_conv_en: 1; /*Set this bit to enable PDM-to-PCM converter*/
uint32_t tx_sinc_osr2: 4; /*upsample rate = 64 * reg_tx_pdm_sinc_osr2*/
uint32_t tx_prescale: 8; /*set to 0*/
uint32_t tx_hp_in_shift: 2; /*Adjust size of input signal to filter module. 0: divided by 2 1:multiplied by 1 2:multiplied by 2 3:multiplied by 4*/
uint32_t tx_lp_in_shift: 2; /*Adjust size of input signal to filter module. 0: divided by 2 1:multiplied by 1 2:multiplied by 2 3:multiplied by 4*/
uint32_t tx_sinc_in_shift: 2; /*Adjust size of input signal to filter module. 0: divided by 2 1:multiplied by 1 2:multiplied by 2 3:multiplied by 4*/
uint32_t tx_sigmadelta_in_shift: 2; /*Adjust size of input signal to filter module. 0: divided by 2 1:multiplied by 1 2:multiplied by 2 3:multiplied by 4*/
uint32_t rx_sinc_dsr_16_en: 1; /*PDM down-sampling rate for filter group1 in receiver mode. 0: downsample rate = 64 1:downsample rate = 128*/
uint32_t txhp_bypass: 1; /*Set this bit to enable tx pdm hp filter bypass*/
uint32_t tx_chan_mod: 2; /*pdm tx channel mode*/
uint32_t tx_way_mode: 2; /*0/1 pdm rx use one-way*/
uint32_t rx_way_mode: 2; /*0/1 pdm rx use one-way*/
};
uint32_t val;
} pdm_conf;
union {
struct {
uint32_t tx_pdm_fs: 10; /*PCM-to-PDM converter PCM frequency parameter*/
uint32_t tx_pdm_fp: 10; /*PCM-to-PDM converter PDM frequency parameter*/
uint32_t reserved20:12;
};
uint32_t val;
} pdm_freq_conf;
union {
struct {
uint32_t tx_idle: 1; /*1: i2s_tx is idle state*/
uint32_t reserved1: 31;
};
uint32_t val;
} state;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t date; /**/
} i2s_dev_t;
extern i2s_dev_t I2S0;
extern i2s_dev_t I2S1;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_I2S_STRUCT_H_ */

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components/soc/esp32s2beta/include/soc/interrupt_reg.h Normal file
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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_INTERRUPT_REG_H_
#define _SOC_INTERRUPT_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define DPORT_PRO_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x000)
/* DPORT_PRO_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_MAC_INTR_MAP 0x0000001F
#define DPORT_PRO_MAC_INTR_MAP_M ((DPORT_PRO_MAC_INTR_MAP_V)<<(DPORT_PRO_MAC_INTR_MAP_S))
#define DPORT_PRO_MAC_INTR_MAP_V 0x1F
#define DPORT_PRO_MAC_INTR_MAP_S 0
#define DPORT_PRO_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x004)
/* DPORT_PRO_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_MAC_NMI_MAP 0x0000001F
#define DPORT_PRO_MAC_NMI_MAP_M ((DPORT_PRO_MAC_NMI_MAP_V)<<(DPORT_PRO_MAC_NMI_MAP_S))
#define DPORT_PRO_MAC_NMI_MAP_V 0x1F
#define DPORT_PRO_MAC_NMI_MAP_S 0
#define DPORT_PRO_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x008)
/* DPORT_PRO_PWR_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_PWR_INTR_MAP 0x0000001F
#define DPORT_PRO_PWR_INTR_MAP_M ((DPORT_PRO_PWR_INTR_MAP_V)<<(DPORT_PRO_PWR_INTR_MAP_S))
#define DPORT_PRO_PWR_INTR_MAP_V 0x1F
#define DPORT_PRO_PWR_INTR_MAP_S 0
#define DPORT_PRO_BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x00C)
/* DPORT_PRO_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_BB_INT_MAP 0x0000001F
#define DPORT_PRO_BB_INT_MAP_M ((DPORT_PRO_BB_INT_MAP_V)<<(DPORT_PRO_BB_INT_MAP_S))
#define DPORT_PRO_BB_INT_MAP_V 0x1F
#define DPORT_PRO_BB_INT_MAP_S 0
#define DPORT_PRO_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x010)
/* DPORT_PRO_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_BT_MAC_INT_MAP 0x0000001F
#define DPORT_PRO_BT_MAC_INT_MAP_M ((DPORT_PRO_BT_MAC_INT_MAP_V)<<(DPORT_PRO_BT_MAC_INT_MAP_S))
#define DPORT_PRO_BT_MAC_INT_MAP_V 0x1F
#define DPORT_PRO_BT_MAC_INT_MAP_S 0
#define DPORT_PRO_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x014)
/* DPORT_PRO_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_BT_BB_INT_MAP 0x0000001F
#define DPORT_PRO_BT_BB_INT_MAP_M ((DPORT_PRO_BT_BB_INT_MAP_V)<<(DPORT_PRO_BT_BB_INT_MAP_S))
#define DPORT_PRO_BT_BB_INT_MAP_V 0x1F
#define DPORT_PRO_BT_BB_INT_MAP_S 0
#define DPORT_PRO_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x018)
/* DPORT_PRO_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_BT_BB_NMI_MAP 0x0000001F
#define DPORT_PRO_BT_BB_NMI_MAP_M ((DPORT_PRO_BT_BB_NMI_MAP_V)<<(DPORT_PRO_BT_BB_NMI_MAP_S))
#define DPORT_PRO_BT_BB_NMI_MAP_V 0x1F
#define DPORT_PRO_BT_BB_NMI_MAP_S 0
#define DPORT_PRO_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_BASE + 0x01C)
/* DPORT_PRO_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_RWBT_IRQ_MAP 0x0000001F
#define DPORT_PRO_RWBT_IRQ_MAP_M ((DPORT_PRO_RWBT_IRQ_MAP_V)<<(DPORT_PRO_RWBT_IRQ_MAP_S))
#define DPORT_PRO_RWBT_IRQ_MAP_V 0x1F
#define DPORT_PRO_RWBT_IRQ_MAP_S 0
#define DPORT_PRO_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_BASE + 0x020)
/* DPORT_PRO_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_RWBLE_IRQ_MAP 0x0000001F
#define DPORT_PRO_RWBLE_IRQ_MAP_M ((DPORT_PRO_RWBLE_IRQ_MAP_V)<<(DPORT_PRO_RWBLE_IRQ_MAP_S))
#define DPORT_PRO_RWBLE_IRQ_MAP_V 0x1F
#define DPORT_PRO_RWBLE_IRQ_MAP_S 0
#define DPORT_PRO_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x024)
/* DPORT_PRO_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_RWBT_NMI_MAP 0x0000001F
#define DPORT_PRO_RWBT_NMI_MAP_M ((DPORT_PRO_RWBT_NMI_MAP_V)<<(DPORT_PRO_RWBT_NMI_MAP_S))
#define DPORT_PRO_RWBT_NMI_MAP_V 0x1F
#define DPORT_PRO_RWBT_NMI_MAP_S 0
#define DPORT_PRO_RWBLE_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x028)
/* DPORT_PRO_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_RWBLE_NMI_MAP 0x0000001F
#define DPORT_PRO_RWBLE_NMI_MAP_M ((DPORT_PRO_RWBLE_NMI_MAP_V)<<(DPORT_PRO_RWBLE_NMI_MAP_S))
#define DPORT_PRO_RWBLE_NMI_MAP_V 0x1F
#define DPORT_PRO_RWBLE_NMI_MAP_S 0
#define DPORT_PRO_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x02C)
/* DPORT_PRO_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SLC0_INTR_MAP 0x0000001F
#define DPORT_PRO_SLC0_INTR_MAP_M ((DPORT_PRO_SLC0_INTR_MAP_V)<<(DPORT_PRO_SLC0_INTR_MAP_S))
#define DPORT_PRO_SLC0_INTR_MAP_V 0x1F
#define DPORT_PRO_SLC0_INTR_MAP_S 0
#define DPORT_PRO_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x030)
/* DPORT_PRO_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SLC1_INTR_MAP 0x0000001F
#define DPORT_PRO_SLC1_INTR_MAP_M ((DPORT_PRO_SLC1_INTR_MAP_V)<<(DPORT_PRO_SLC1_INTR_MAP_S))
#define DPORT_PRO_SLC1_INTR_MAP_V 0x1F
#define DPORT_PRO_SLC1_INTR_MAP_S 0
#define DPORT_PRO_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x034)
/* DPORT_PRO_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_UHCI0_INTR_MAP 0x0000001F
#define DPORT_PRO_UHCI0_INTR_MAP_M ((DPORT_PRO_UHCI0_INTR_MAP_V)<<(DPORT_PRO_UHCI0_INTR_MAP_S))
#define DPORT_PRO_UHCI0_INTR_MAP_V 0x1F
#define DPORT_PRO_UHCI0_INTR_MAP_S 0
#define DPORT_PRO_UHCI1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x038)
/* DPORT_PRO_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_UHCI1_INTR_MAP 0x0000001F
#define DPORT_PRO_UHCI1_INTR_MAP_M ((DPORT_PRO_UHCI1_INTR_MAP_V)<<(DPORT_PRO_UHCI1_INTR_MAP_S))
#define DPORT_PRO_UHCI1_INTR_MAP_V 0x1F
#define DPORT_PRO_UHCI1_INTR_MAP_S 0
#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x03C)
/* DPORT_PRO_TG_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG_T0_LEVEL_INT_MAP 0x0000001F
#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_M ((DPORT_PRO_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T0_LEVEL_INT_MAP_S))
#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_V 0x1F
#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_S 0
#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x040)
/* DPORT_PRO_TG_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG_T1_LEVEL_INT_MAP 0x0000001F
#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_M ((DPORT_PRO_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T1_LEVEL_INT_MAP_S))
#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_V 0x1F
#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_S 0
#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x044)
/* DPORT_PRO_TG_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP 0x0000001F
#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_M ((DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S))
#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V 0x1F
#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S 0
#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x048)
/* DPORT_PRO_TG_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP 0x0000001F
#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_M ((DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S))
#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V 0x1F
#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S 0
#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x04C)
/* DPORT_PRO_TG1_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP 0x0000001F
#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S))
#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V 0x1F
#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S 0
#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x050)
/* DPORT_PRO_TG1_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP 0x0000001F
#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S))
#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V 0x1F
#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S 0
#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x054)
/* DPORT_PRO_TG1_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP 0x0000001F
#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S))
#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V 0x1F
#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S 0
#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x058)
/* DPORT_PRO_TG1_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP 0x0000001F
#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S))
#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V 0x1F
#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S 0
#define DPORT_PRO_GPIO_DPORT_PRO_MAP_REG (DR_REG_INTERRUPT_BASE + 0x05C)
/* DPORT_PRO_GPIO_DPORT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_GPIO_DPORT_PRO_MAP 0x0000001F
#define DPORT_PRO_GPIO_DPORT_PRO_MAP_M ((DPORT_PRO_GPIO_DPORT_PRO_MAP_V)<<(DPORT_PRO_GPIO_DPORT_PRO_MAP_S))
#define DPORT_PRO_GPIO_DPORT_PRO_MAP_V 0x1F
#define DPORT_PRO_GPIO_DPORT_PRO_MAP_S 0
#define DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x060)
/* DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP 0x0000001F
#define DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP_M ((DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP_V)<<(DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP_S))
#define DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP_V 0x1F
#define DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP_S 0
#define DPORT_PRO_GPIO_DPORT_APP_MAP_REG (DR_REG_INTERRUPT_BASE + 0x064)
/* DPORT_PRO_GPIO_DPORT_APP_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_GPIO_DPORT_APP_MAP 0x0000001F
#define DPORT_PRO_GPIO_DPORT_APP_MAP_M ((DPORT_PRO_GPIO_DPORT_APP_MAP_V)<<(DPORT_PRO_GPIO_DPORT_APP_MAP_S))
#define DPORT_PRO_GPIO_DPORT_APP_MAP_V 0x1F
#define DPORT_PRO_GPIO_DPORT_APP_MAP_S 0
#define DPORT_PRO_GPIO_DPORT_APP_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x068)
/* DPORT_PRO_GPIO_DPORT_APP_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_GPIO_DPORT_APP_NMI_MAP 0x0000001F
#define DPORT_PRO_GPIO_DPORT_APP_NMI_MAP_M ((DPORT_PRO_GPIO_DPORT_APP_NMI_MAP_V)<<(DPORT_PRO_GPIO_DPORT_APP_NMI_MAP_S))
#define DPORT_PRO_GPIO_DPORT_APP_NMI_MAP_V 0x1F
#define DPORT_PRO_GPIO_DPORT_APP_NMI_MAP_S 0
#define DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x06C)
/* DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP 0x0000001F
#define DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP_M ((DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP_V)<<(DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP_S))
#define DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP_V 0x1F
#define DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP_S 0
#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_BASE + 0x070)
/* DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP 0x0000001F
#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S))
#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V 0x1F
#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S 0
#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_BASE + 0x074)
/* DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP 0x0000001F
#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S))
#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V 0x1F
#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S 0
#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_BASE + 0x078)
/* DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP 0x0000001F
#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S))
#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V 0x1F
#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S 0
#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_BASE + 0x07C)
/* DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP 0x0000001F
#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S))
#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V 0x1F
#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S 0
#define DPORT_PRO_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_BASE + 0x080)
/* DPORT_PRO_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SPI_INTR_1_MAP 0x0000001F
#define DPORT_PRO_SPI_INTR_1_MAP_M ((DPORT_PRO_SPI_INTR_1_MAP_V)<<(DPORT_PRO_SPI_INTR_1_MAP_S))
#define DPORT_PRO_SPI_INTR_1_MAP_V 0x1F
#define DPORT_PRO_SPI_INTR_1_MAP_S 0
#define DPORT_PRO_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_BASE + 0x084)
/* DPORT_PRO_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SPI_INTR_2_MAP 0x0000001F
#define DPORT_PRO_SPI_INTR_2_MAP_M ((DPORT_PRO_SPI_INTR_2_MAP_V)<<(DPORT_PRO_SPI_INTR_2_MAP_S))
#define DPORT_PRO_SPI_INTR_2_MAP_V 0x1F
#define DPORT_PRO_SPI_INTR_2_MAP_S 0
#define DPORT_PRO_SPI_INTR_3_MAP_REG (DR_REG_INTERRUPT_BASE + 0x088)
/* DPORT_PRO_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SPI_INTR_3_MAP 0x0000001F
#define DPORT_PRO_SPI_INTR_3_MAP_M ((DPORT_PRO_SPI_INTR_3_MAP_V)<<(DPORT_PRO_SPI_INTR_3_MAP_S))
#define DPORT_PRO_SPI_INTR_3_MAP_V 0x1F
#define DPORT_PRO_SPI_INTR_3_MAP_S 0
#define DPORT_PRO_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x08C)
/* DPORT_PRO_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_I2S0_INT_MAP 0x0000001F
#define DPORT_PRO_I2S0_INT_MAP_M ((DPORT_PRO_I2S0_INT_MAP_V)<<(DPORT_PRO_I2S0_INT_MAP_S))
#define DPORT_PRO_I2S0_INT_MAP_V 0x1F
#define DPORT_PRO_I2S0_INT_MAP_S 0
#define DPORT_PRO_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x090)
/* DPORT_PRO_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_I2S1_INT_MAP 0x0000001F
#define DPORT_PRO_I2S1_INT_MAP_M ((DPORT_PRO_I2S1_INT_MAP_V)<<(DPORT_PRO_I2S1_INT_MAP_S))
#define DPORT_PRO_I2S1_INT_MAP_V 0x1F
#define DPORT_PRO_I2S1_INT_MAP_S 0
#define DPORT_PRO_UART_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x094)
/* DPORT_PRO_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_UART_INTR_MAP 0x0000001F
#define DPORT_PRO_UART_INTR_MAP_M ((DPORT_PRO_UART_INTR_MAP_V)<<(DPORT_PRO_UART_INTR_MAP_S))
#define DPORT_PRO_UART_INTR_MAP_V 0x1F
#define DPORT_PRO_UART_INTR_MAP_S 0
#define DPORT_PRO_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x098)
/* DPORT_PRO_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_UART1_INTR_MAP 0x0000001F
#define DPORT_PRO_UART1_INTR_MAP_M ((DPORT_PRO_UART1_INTR_MAP_V)<<(DPORT_PRO_UART1_INTR_MAP_S))
#define DPORT_PRO_UART1_INTR_MAP_V 0x1F
#define DPORT_PRO_UART1_INTR_MAP_S 0
#define DPORT_PRO_UART2_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x09C)
/* DPORT_PRO_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_UART2_INTR_MAP 0x0000001F
#define DPORT_PRO_UART2_INTR_MAP_M ((DPORT_PRO_UART2_INTR_MAP_V)<<(DPORT_PRO_UART2_INTR_MAP_S))
#define DPORT_PRO_UART2_INTR_MAP_V 0x1F
#define DPORT_PRO_UART2_INTR_MAP_S 0
#define DPORT_PRO_SDIO_HOST_DPORT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0A0)
/* DPORT_PRO_SDIO_HOST_DPORT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SDIO_HOST_DPORT_MAP 0x0000001F
#define DPORT_PRO_SDIO_HOST_DPORT_MAP_M ((DPORT_PRO_SDIO_HOST_DPORT_MAP_V)<<(DPORT_PRO_SDIO_HOST_DPORT_MAP_S))
#define DPORT_PRO_SDIO_HOST_DPORT_MAP_V 0x1F
#define DPORT_PRO_SDIO_HOST_DPORT_MAP_S 0
#define DPORT_PRO_PWM0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0A4)
/* DPORT_PRO_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_PWM0_INTR_MAP 0x0000001F
#define DPORT_PRO_PWM0_INTR_MAP_M ((DPORT_PRO_PWM0_INTR_MAP_V)<<(DPORT_PRO_PWM0_INTR_MAP_S))
#define DPORT_PRO_PWM0_INTR_MAP_V 0x1F
#define DPORT_PRO_PWM0_INTR_MAP_S 0
#define DPORT_PRO_PWM1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0A8)
/* DPORT_PRO_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_PWM1_INTR_MAP 0x0000001F
#define DPORT_PRO_PWM1_INTR_MAP_M ((DPORT_PRO_PWM1_INTR_MAP_V)<<(DPORT_PRO_PWM1_INTR_MAP_S))
#define DPORT_PRO_PWM1_INTR_MAP_V 0x1F
#define DPORT_PRO_PWM1_INTR_MAP_S 0
#define DPORT_PRO_PWM2_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0AC)
/* DPORT_PRO_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_PWM2_INTR_MAP 0x0000001F
#define DPORT_PRO_PWM2_INTR_MAP_M ((DPORT_PRO_PWM2_INTR_MAP_V)<<(DPORT_PRO_PWM2_INTR_MAP_S))
#define DPORT_PRO_PWM2_INTR_MAP_V 0x1F
#define DPORT_PRO_PWM2_INTR_MAP_S 0
#define DPORT_PRO_PWM3_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0B0)
/* DPORT_PRO_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_PWM3_INTR_MAP 0x0000001F
#define DPORT_PRO_PWM3_INTR_MAP_M ((DPORT_PRO_PWM3_INTR_MAP_V)<<(DPORT_PRO_PWM3_INTR_MAP_S))
#define DPORT_PRO_PWM3_INTR_MAP_V 0x1F
#define DPORT_PRO_PWM3_INTR_MAP_S 0
#define DPORT_PRO_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0B4)
/* DPORT_PRO_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_LEDC_INT_MAP 0x0000001F
#define DPORT_PRO_LEDC_INT_MAP_M ((DPORT_PRO_LEDC_INT_MAP_V)<<(DPORT_PRO_LEDC_INT_MAP_S))
#define DPORT_PRO_LEDC_INT_MAP_V 0x1F
#define DPORT_PRO_LEDC_INT_MAP_S 0
#define DPORT_PRO_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0B8)
/* DPORT_PRO_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_EFUSE_INT_MAP 0x0000001F
#define DPORT_PRO_EFUSE_INT_MAP_M ((DPORT_PRO_EFUSE_INT_MAP_V)<<(DPORT_PRO_EFUSE_INT_MAP_S))
#define DPORT_PRO_EFUSE_INT_MAP_V 0x1F
#define DPORT_PRO_EFUSE_INT_MAP_S 0
#define DPORT_PRO_CAN_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0BC)
/* DPORT_PRO_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_CAN_INT_MAP 0x0000001F
#define DPORT_PRO_CAN_INT_MAP_M ((DPORT_PRO_CAN_INT_MAP_V)<<(DPORT_PRO_CAN_INT_MAP_S))
#define DPORT_PRO_CAN_INT_MAP_V 0x1F
#define DPORT_PRO_CAN_INT_MAP_S 0
#define DPORT_PRO_USB_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0C0)
/* DPORT_PRO_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_USB_INTR_MAP 0x0000001F
#define DPORT_PRO_USB_INTR_MAP_M ((DPORT_PRO_USB_INTR_MAP_V)<<(DPORT_PRO_USB_INTR_MAP_S))
#define DPORT_PRO_USB_INTR_MAP_V 0x1F
#define DPORT_PRO_USB_INTR_MAP_S 0
#define DPORT_PRO_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0C4)
/* DPORT_PRO_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_RTC_CORE_INTR_MAP 0x0000001F
#define DPORT_PRO_RTC_CORE_INTR_MAP_M ((DPORT_PRO_RTC_CORE_INTR_MAP_V)<<(DPORT_PRO_RTC_CORE_INTR_MAP_S))
#define DPORT_PRO_RTC_CORE_INTR_MAP_V 0x1F
#define DPORT_PRO_RTC_CORE_INTR_MAP_S 0
#define DPORT_PRO_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0C8)
/* DPORT_PRO_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_RMT_INTR_MAP 0x0000001F
#define DPORT_PRO_RMT_INTR_MAP_M ((DPORT_PRO_RMT_INTR_MAP_V)<<(DPORT_PRO_RMT_INTR_MAP_S))
#define DPORT_PRO_RMT_INTR_MAP_V 0x1F
#define DPORT_PRO_RMT_INTR_MAP_S 0
#define DPORT_PRO_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0CC)
/* DPORT_PRO_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_PCNT_INTR_MAP 0x0000001F
#define DPORT_PRO_PCNT_INTR_MAP_M ((DPORT_PRO_PCNT_INTR_MAP_V)<<(DPORT_PRO_PCNT_INTR_MAP_S))
#define DPORT_PRO_PCNT_INTR_MAP_V 0x1F
#define DPORT_PRO_PCNT_INTR_MAP_S 0
#define DPORT_PRO_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0D0)
/* DPORT_PRO_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_I2C_EXT0_INTR_MAP 0x0000001F
#define DPORT_PRO_I2C_EXT0_INTR_MAP_M ((DPORT_PRO_I2C_EXT0_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT0_INTR_MAP_S))
#define DPORT_PRO_I2C_EXT0_INTR_MAP_V 0x1F
#define DPORT_PRO_I2C_EXT0_INTR_MAP_S 0
#define DPORT_PRO_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0D4)
/* DPORT_PRO_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_I2C_EXT1_INTR_MAP 0x0000001F
#define DPORT_PRO_I2C_EXT1_INTR_MAP_M ((DPORT_PRO_I2C_EXT1_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT1_INTR_MAP_S))
#define DPORT_PRO_I2C_EXT1_INTR_MAP_V 0x1F
#define DPORT_PRO_I2C_EXT1_INTR_MAP_S 0
#define DPORT_PRO_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0D8)
/* DPORT_PRO_RSA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_RSA_INTR_MAP 0x0000001F
#define DPORT_PRO_RSA_INTR_MAP_M ((DPORT_PRO_RSA_INTR_MAP_V)<<(DPORT_PRO_RSA_INTR_MAP_S))
#define DPORT_PRO_RSA_INTR_MAP_V 0x1F
#define DPORT_PRO_RSA_INTR_MAP_S 0
#define DPORT_PRO_SPI1_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0DC)
/* DPORT_PRO_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SPI1_DMA_INT_MAP 0x0000001F
#define DPORT_PRO_SPI1_DMA_INT_MAP_M ((DPORT_PRO_SPI1_DMA_INT_MAP_V)<<(DPORT_PRO_SPI1_DMA_INT_MAP_S))
#define DPORT_PRO_SPI1_DMA_INT_MAP_V 0x1F
#define DPORT_PRO_SPI1_DMA_INT_MAP_S 0
#define DPORT_PRO_SPI2_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0E0)
/* DPORT_PRO_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SPI2_DMA_INT_MAP 0x0000001F
#define DPORT_PRO_SPI2_DMA_INT_MAP_M ((DPORT_PRO_SPI2_DMA_INT_MAP_V)<<(DPORT_PRO_SPI2_DMA_INT_MAP_S))
#define DPORT_PRO_SPI2_DMA_INT_MAP_V 0x1F
#define DPORT_PRO_SPI2_DMA_INT_MAP_S 0
#define DPORT_PRO_SPI3_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0E4)
/* DPORT_PRO_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SPI3_DMA_INT_MAP 0x0000001F
#define DPORT_PRO_SPI3_DMA_INT_MAP_M ((DPORT_PRO_SPI3_DMA_INT_MAP_V)<<(DPORT_PRO_SPI3_DMA_INT_MAP_S))
#define DPORT_PRO_SPI3_DMA_INT_MAP_V 0x1F
#define DPORT_PRO_SPI3_DMA_INT_MAP_S 0
#define DPORT_PRO_WDG_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0E8)
/* DPORT_PRO_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_WDG_INT_MAP 0x0000001F
#define DPORT_PRO_WDG_INT_MAP_M ((DPORT_PRO_WDG_INT_MAP_V)<<(DPORT_PRO_WDG_INT_MAP_S))
#define DPORT_PRO_WDG_INT_MAP_V 0x1F
#define DPORT_PRO_WDG_INT_MAP_S 0
#define DPORT_PRO_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0EC)
/* DPORT_PRO_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TIMER_INT1_MAP 0x0000001F
#define DPORT_PRO_TIMER_INT1_MAP_M ((DPORT_PRO_TIMER_INT1_MAP_V)<<(DPORT_PRO_TIMER_INT1_MAP_S))
#define DPORT_PRO_TIMER_INT1_MAP_V 0x1F
#define DPORT_PRO_TIMER_INT1_MAP_S 0
#define DPORT_PRO_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0F0)
/* DPORT_PRO_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TIMER_INT2_MAP 0x0000001F
#define DPORT_PRO_TIMER_INT2_MAP_M ((DPORT_PRO_TIMER_INT2_MAP_V)<<(DPORT_PRO_TIMER_INT2_MAP_S))
#define DPORT_PRO_TIMER_INT2_MAP_V 0x1F
#define DPORT_PRO_TIMER_INT2_MAP_S 0
#define DPORT_PRO_TG_T0_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0F4)
/* DPORT_PRO_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG_T0_EDGE_INT_MAP 0x0000001F
#define DPORT_PRO_TG_T0_EDGE_INT_MAP_M ((DPORT_PRO_TG_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T0_EDGE_INT_MAP_S))
#define DPORT_PRO_TG_T0_EDGE_INT_MAP_V 0x1F
#define DPORT_PRO_TG_T0_EDGE_INT_MAP_S 0
#define DPORT_PRO_TG_T1_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0F8)
/* DPORT_PRO_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG_T1_EDGE_INT_MAP 0x0000001F
#define DPORT_PRO_TG_T1_EDGE_INT_MAP_M ((DPORT_PRO_TG_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T1_EDGE_INT_MAP_S))
#define DPORT_PRO_TG_T1_EDGE_INT_MAP_V 0x1F
#define DPORT_PRO_TG_T1_EDGE_INT_MAP_S 0
#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0FC)
/* DPORT_PRO_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG_WDT_EDGE_INT_MAP 0x0000001F
#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_M ((DPORT_PRO_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_WDT_EDGE_INT_MAP_S))
#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_V 0x1F
#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_S 0
#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x100)
/* DPORT_PRO_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG_LACT_EDGE_INT_MAP 0x0000001F
#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_M ((DPORT_PRO_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_LACT_EDGE_INT_MAP_S))
#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_V 0x1F
#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_S 0
#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x104)
/* DPORT_PRO_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG1_T0_EDGE_INT_MAP 0x0000001F
#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_M ((DPORT_PRO_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T0_EDGE_INT_MAP_S))
#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_V 0x1F
#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_S 0
#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x108)
/* DPORT_PRO_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG1_T1_EDGE_INT_MAP 0x0000001F
#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_M ((DPORT_PRO_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T1_EDGE_INT_MAP_S))
#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_V 0x1F
#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_S 0
#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x10C)
/* DPORT_PRO_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP 0x0000001F
#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_M ((DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S))
#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V 0x1F
#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S 0
#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x110)
/* DPORT_PRO_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP 0x0000001F
#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_M ((DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S))
#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V 0x1F
#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S 0
#define DPORT_PRO_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x114)
/* DPORT_PRO_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_CACHE_IA_INT_MAP 0x0000001F
#define DPORT_PRO_CACHE_IA_INT_MAP_M ((DPORT_PRO_CACHE_IA_INT_MAP_V)<<(DPORT_PRO_CACHE_IA_INT_MAP_S))
#define DPORT_PRO_CACHE_IA_INT_MAP_V 0x1F
#define DPORT_PRO_CACHE_IA_INT_MAP_S 0
#define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x118)
/* DPORT_PRO_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP 0x0000001F
#define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_M ((DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_V)<<(DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_S))
#define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_V 0x1F
#define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_S 0
#define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x11C)
/* DPORT_PRO_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP 0x0000001F
#define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_M ((DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_V)<<(DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_S))
#define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_V 0x1F
#define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_S 0
#define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x120)
/* DPORT_PRO_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP 0x0000001F
#define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_M ((DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_V)<<(DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_S))
#define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_V 0x1F
#define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_S 0
#define DPORT_PRO_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x124)
/* DPORT_PRO_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_ASSIST_DEBUG_INTR_MAP 0x0000001F
#define DPORT_PRO_ASSIST_DEBUG_INTR_MAP_M ((DPORT_PRO_ASSIST_DEBUG_INTR_MAP_V)<<(DPORT_PRO_ASSIST_DEBUG_INTR_MAP_S))
#define DPORT_PRO_ASSIST_DEBUG_INTR_MAP_V 0x1F
#define DPORT_PRO_ASSIST_DEBUG_INTR_MAP_S 0
#define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x128)
/* DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP 0x0000001F
#define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_M ((DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_S))
#define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_V 0x1F
#define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_S 0
#define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x12C)
/* DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP 0x0000001F
#define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_M ((DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_S))
#define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_V 0x1F
#define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_S 0
#define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x130)
/* DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP 0x0000001F
#define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_M ((DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_S))
#define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_V 0x1F
#define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_S 0
#define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x134)
/* DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP 0x0000001F
#define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_M ((DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_S))
#define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_V 0x1F
#define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_S 0
#define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x138)
/* DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP 0x0000001F
#define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_M ((DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_S))
#define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_V 0x1F
#define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_S 0
#define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x13C)
/* DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP 0x0000001F
#define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_M ((DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_S))
#define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_V 0x1F
#define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_S 0
#define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x140)
/* DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP 0x0000001F
#define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_M ((DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_S))
#define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_V 0x1F
#define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_S 0
#define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x144)
/* DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP 0x0000001F
#define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_M ((DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_S))
#define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_V 0x1F
#define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_S 0
#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x148)
/* DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP 0x0000001F
#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_M ((DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_V)<<(DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_S))
#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_V 0x1F
#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_S 0
#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x14C)
/* DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP 0x0000001F
#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_M ((DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_V)<<(DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_S))
#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_V 0x1F
#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_S 0
#define DPORT_PRO_DMA_COPY_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x150)
/* DPORT_PRO_DMA_COPY_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_DMA_COPY_INTR_MAP 0x0000001F
#define DPORT_PRO_DMA_COPY_INTR_MAP_M ((DPORT_PRO_DMA_COPY_INTR_MAP_V)<<(DPORT_PRO_DMA_COPY_INTR_MAP_S))
#define DPORT_PRO_DMA_COPY_INTR_MAP_V 0x1F
#define DPORT_PRO_DMA_COPY_INTR_MAP_S 0
#define DPORT_PRO_SPI4_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x154)
/* DPORT_PRO_SPI4_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SPI4_DMA_INT_MAP 0x0000001F
#define DPORT_PRO_SPI4_DMA_INT_MAP_M ((DPORT_PRO_SPI4_DMA_INT_MAP_V)<<(DPORT_PRO_SPI4_DMA_INT_MAP_S))
#define DPORT_PRO_SPI4_DMA_INT_MAP_V 0x1F
#define DPORT_PRO_SPI4_DMA_INT_MAP_S 0
#define DPORT_PRO_SPI_INTR_4_MAP_REG (DR_REG_INTERRUPT_BASE + 0x158)
/* DPORT_PRO_SPI_INTR_4_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SPI_INTR_4_MAP 0x0000001F
#define DPORT_PRO_SPI_INTR_4_MAP_M ((DPORT_PRO_SPI_INTR_4_MAP_V)<<(DPORT_PRO_SPI_INTR_4_MAP_S))
#define DPORT_PRO_SPI_INTR_4_MAP_V 0x1F
#define DPORT_PRO_SPI_INTR_4_MAP_S 0
#define DPORT_PRO_INTR_STATUS_0_REG (DR_REG_INTERRUPT_BASE + 0x15C)
/* DPORT_PRO_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_PRO_INTR_STATUS_0 0xFFFFFFFF
#define DPORT_PRO_INTR_STATUS_0_M ((DPORT_PRO_INTR_STATUS_0_V)<<(DPORT_PRO_INTR_STATUS_0_S))
#define DPORT_PRO_INTR_STATUS_0_V 0xFFFFFFFF
#define DPORT_PRO_INTR_STATUS_0_S 0
#define DPORT_PRO_INTR_STATUS_1_REG (DR_REG_INTERRUPT_BASE + 0x160)
/* DPORT_PRO_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_PRO_INTR_STATUS_1 0xFFFFFFFF
#define DPORT_PRO_INTR_STATUS_1_M ((DPORT_PRO_INTR_STATUS_1_V)<<(DPORT_PRO_INTR_STATUS_1_S))
#define DPORT_PRO_INTR_STATUS_1_V 0xFFFFFFFF
#define DPORT_PRO_INTR_STATUS_1_S 0
#define DPORT_PRO_INTR_STATUS_2_REG (DR_REG_INTERRUPT_BASE + 0x164)
/* DPORT_PRO_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_PRO_INTR_STATUS_2 0xFFFFFFFF
#define DPORT_PRO_INTR_STATUS_2_M ((DPORT_PRO_INTR_STATUS_2_V)<<(DPORT_PRO_INTR_STATUS_2_S))
#define DPORT_PRO_INTR_STATUS_2_V 0xFFFFFFFF
#define DPORT_PRO_INTR_STATUS_2_S 0
#define INTERRUPT_CLOCK_GATE_REG (DR_REG_INTERRUPT_BASE + 0x168)
/* DPORT_PRO_NMI_MASK_HW : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_NMI_MASK_HW (BIT(1))
#define DPORT_PRO_NMI_MASK_HW_M (BIT(1))
#define DPORT_PRO_NMI_MASK_HW_V 0x1
#define DPORT_PRO_NMI_MASK_HW_S 1
/* INTERRUPT_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define INTERRUPT_CLK_EN (BIT(0))
#define INTERRUPT_CLK_EN_M (BIT(0))
#define INTERRUPT_CLK_EN_V 0x1
#define INTERRUPT_CLK_EN_S 0
#define INTERRUPT_DATE_REG (DR_REG_INTERRUPT_BASE + 0xFFC)
/* INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h1809110 ; */
/*description: */
#define INTERRUPT_DATE 0x0FFFFFFF
#define INTERRUPT_DATE_M ((INTERRUPT_DATE_V)<<(INTERRUPT_DATE_S))
#define INTERRUPT_DATE_V 0xFFFFFFF
#define INTERRUPT_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_INTERRUPT_REG_H_ */

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components/soc/esp32s2beta/include/soc/io_mux_reg.h Normal file
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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_IO_MUX_REG_H_
#define _SOC_IO_MUX_REG_H_
#include "soc.h"
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
/* Output enable in sleep mode */
#define SLP_OE (BIT(0))
#define SLP_OE_M (BIT(0))
#define SLP_OE_V 1
#define SLP_OE_S 0
/* Pin used for wakeup from sleep */
#define SLP_SEL (BIT(1))
#define SLP_SEL_M (BIT(1))
#define SLP_SEL_V 1
#define SLP_SEL_S 1
/* Pulldown enable in sleep mode */
#define SLP_PD (BIT(2))
#define SLP_PD_M (BIT(2))
#define SLP_PD_V 1
#define SLP_PD_S 2
/* Pullup enable in sleep mode */
#define SLP_PU (BIT(3))
#define SLP_PU_M (BIT(3))
#define SLP_PU_V 1
#define SLP_PU_S 3
/* Input enable in sleep mode */
#define SLP_IE (BIT(4))
#define SLP_IE_M (BIT(4))
#define SLP_IE_V 1
#define SLP_IE_S 4
/* Drive strength in sleep mode */
#define SLP_DRV 0x3
#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
#define SLP_DRV_V 0x3
#define SLP_DRV_S 5
/* Pulldown enable */
#define FUN_PD (BIT(7))
#define FUN_PD_M (BIT(7))
#define FUN_PD_V 1
#define FUN_PD_S 7
/* Pullup enable */
#define FUN_PU (BIT(8))
#define FUN_PU_M (BIT(8))
#define FUN_PU_V 1
#define FUN_PU_S 8
/* Input enable */
#define FUN_IE (BIT(9))
#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
#define FUN_IE_V 1
#define FUN_IE_S 9
/* Drive strength */
#define FUN_DRV 0x3
#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
#define FUN_DRV_V 0x3
#define FUN_DRV_S 10
/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
#define MCU_SEL 0x7
#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
#define MCU_SEL_V 0x7
#define MCU_SEL_S 12
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_GPIO1_U
#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U
#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U
#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_GPIO4_U
#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_GPIO5_U
#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_GPIO6_U
#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_GPIO7_U
#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U
#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U
#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U
#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_GPIO11_U
#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U
#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_GPIO13_U
#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_GPIO14_U
#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_XTAL_32K_P_U
#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_XTAL_32K_N_U
#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_DAC_1_U
#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_DAC_2_U
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_GPIO20_U
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_GPIO21_U
#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_SPICS1_U
#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_SPIHD_U
#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_SPIWP_U
#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_SPICS0_U
#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_SPICLK_U
#define IO_MUX_GPIO31_REG PERIPHS_IO_MUX_SPIQ_U
#define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_SPID_U
#define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_GPIO33_U
#define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_GPIO34_U
#define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_GPIO35_U
#define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_GPIO36_U
#define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_GPIO37_U
#define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_GPIO38_U
#define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_MTCK_U
#define IO_MUX_GPIO40_REG PERIPHS_IO_MUX_MTDO_U
#define IO_MUX_GPIO41_REG PERIPHS_IO_MUX_MTDI_U
#define IO_MUX_GPIO42_REG PERIPHS_IO_MUX_MTMS_U
#define IO_MUX_GPIO43_REG PERIPHS_IO_MUX_U0TXD_U
#define IO_MUX_GPIO44_REG PERIPHS_IO_MUX_U0RXD_U
#define IO_MUX_GPIO45_REG PERIPHS_IO_MUX_GPIO45_U
#define IO_MUX_GPIO46_REG PERIPHS_IO_MUX_GPIO46_U
#define FUNC_GPIO_GPIO 1
#define PIN_FUNC_GPIO 1
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_PULLUP(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDOWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define U1RXD_GPIO_NUM 18
#define U1TXD_GPIO_NUM 17
#define U0RXD_GPIO_NUM 44
#define U0TXD_GPIO_NUM 43
#define SPI_CLK_GPIO_NUM 30
#define SPI_Q_GPIO_NUM 31
#define SPI_D_GPIO_NUM 32
#define SPI_CS0_GPIO_NUM 29
#define SPI_HD_GPIO_NUM 27
#define SPI_WP_GPIO_NUM 28
#define SD_CLK_GPIO_NUM 12
#define SD_CMD_GPIO_NUM 11
#define SD_DATA0_GPIO_NUM 13
#define SD_DATA1_GPIO_NUM 14
#define SD_DATA2_GPIO_NUM 9
#define SD_DATA3_GPIO_NUM 10
#define MAX_RTC_GPIO_NUM 21
#define MAX_PAD_GPIO_NUM 46
#define MAX_GPIO_NUM 53
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
#define CLK_OUT3 0xf
#define CLK_OUT3_V CLK_OUT3
#define CLK_OUT3_S 8
#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S)
#define CLK_OUT2 0xf
#define CLK_OUT2_V CLK_OUT2
#define CLK_OUT2_S 4
#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S)
#define CLK_OUT1 0xf
#define CLK_OUT1_V CLK_OUT1
#define CLK_OUT1_S 0
#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S)
#define PERIPHS_IO_MUX_GPIO0_U (REG_IO_MUX_BASE +0x04)
#define FUNC_GPIO0_GPIO0 1
#define FUNC_GPIO0_GPIO0_0 0
#define PERIPHS_IO_MUX_GPIO1_U (REG_IO_MUX_BASE +0x08)
#define FUNC_GPIO1_GPIO1 1
#define FUNC_GPIO1_GPIO1_0 0
#define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE +0x0c)
#define FUNC_GPIO2_GPIO2 1
#define FUNC_GPIO2_GPIO2_0 0
#define PERIPHS_IO_MUX_GPIO3_U (REG_IO_MUX_BASE +0x10)
#define FUNC_GPIO3_GPIO3 1
#define FUNC_GPIO3_GPIO3_0 0
#define PERIPHS_IO_MUX_GPIO4_U (REG_IO_MUX_BASE +0x14)
#define FUNC_GPIO4_GPIO4 1
#define FUNC_GPIO4_GPIO4_0 0
#define PERIPHS_IO_MUX_GPIO5_U (REG_IO_MUX_BASE +0x18)
#define FUNC_GPIO5_GPIO5 1
#define FUNC_GPIO5_GPIO5_0 0
#define PERIPHS_IO_MUX_GPIO6_U (REG_IO_MUX_BASE +0x1c)
#define FUNC_GPIO6_GPIO6 1
#define FUNC_GPIO6_GPIO6_0 0
#define PERIPHS_IO_MUX_GPIO7_U (REG_IO_MUX_BASE +0x20)
#define FUNC_GPIO7_GPIO7 1
#define FUNC_GPIO7_GPIO7_0 0
#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE +0x24)
#define FUNC_GPIO8_SUBSPICS1 3
#define FUNC_GPIO8_GPIO8 1
#define FUNC_GPIO8_GPIO8_0 0
#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE +0x28)
#define FUNC_GPIO9_SUBSPIHD 3
#define FUNC_GPIO9_FSPIHD 2
#define FUNC_GPIO9_GPIO9 1
#define FUNC_GPIO9_SD_DATA2 0
#define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE +0x2c)
#define FUNC_GPIO10_SUBSPICS0 3
#define FUNC_GPIO10_FSPICS0 2
#define FUNC_GPIO10_GPIO10 1
#define FUNC_GPIO10_SD_DATA3 0
#define PERIPHS_IO_MUX_GPIO11_U (REG_IO_MUX_BASE +0x30)
#define FUNC_GPIO11_SUBSPID 3
#define FUNC_GPIO11_FSPID 2
#define FUNC_GPIO11_GPIO11 1
#define FUNC_GPIO11_SD_CMD 0
#define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE +0x34)
#define FUNC_GPIO12_SUBSPICLK 3
#define FUNC_GPIO12_FSPICLK 2
#define FUNC_GPIO12_GPIO12 1
#define FUNC_GPIO12_SD_CLK 0
#define PERIPHS_IO_MUX_GPIO13_U (REG_IO_MUX_BASE +0x38)
#define FUNC_GPIO13_SUBSPIQ 3
#define FUNC_GPIO13_FSPIQ 2
#define FUNC_GPIO13_GPIO13 1
#define FUNC_GPIO13_SD_DATA0 0
#define PERIPHS_IO_MUX_GPIO14_U (REG_IO_MUX_BASE +0x3c)
#define FUNC_GPIO14_SUBSPIWP 3
#define FUNC_GPIO14_FSPIWP 2
#define FUNC_GPIO14_GPIO14 1
#define FUNC_GPIO14_SD_DATA1 0
#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE +0x40)
#define FUNC_XTAL_32K_P_U0RTS 2
#define FUNC_XTAL_32K_P_GPIO15 1
#define FUNC_XTAL_32K_P_GPIO15_0 0
#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE +0x44)
#define FUNC_XTAL_32K_N_U0CTS 2
#define FUNC_XTAL_32K_N_GPIO16 1
#define FUNC_XTAL_32K_N_GPIO16_0 0
#define PERIPHS_IO_MUX_DAC_1_U (REG_IO_MUX_BASE +0x48)
#define FUNC_DAC_1_U1TXD 2
#define FUNC_DAC_1_GPIO17 1
#define FUNC_DAC_1_GPIO17_0 0
#define PERIPHS_IO_MUX_DAC_2_U (REG_IO_MUX_BASE +0x4c)
#define FUNC_DAC_2_CLK_OUT3 3
#define FUNC_DAC_2_U1RXD 2
#define FUNC_DAC_2_GPIO18 1
#define FUNC_DAC_2_GPIO18_0 0
#define PERIPHS_IO_MUX_GPIO19_U (REG_IO_MUX_BASE +0x50)
#define FUNC_GPIO19_CLK_OUT2 3
#define FUNC_GPIO19_U1RTS 2
#define FUNC_GPIO19_GPIO19 1
#define FUNC_GPIO19_GPIO19_0 0
#define PERIPHS_IO_MUX_GPIO20_U (REG_IO_MUX_BASE +0x54)
#define FUNC_GPIO20_CLK_OUT1 3
#define FUNC_GPIO20_U1CTS 2
#define FUNC_GPIO20_GPIO20 1
#define FUNC_GPIO20_GPIO20_0 0
#define PERIPHS_IO_MUX_GPIO21_U (REG_IO_MUX_BASE +0x58)
#define FUNC_GPIO21_GPIO21 1
#define FUNC_GPIO21_GPIO21_0 0
#define PERIPHS_IO_MUX_SPICS1_U (REG_IO_MUX_BASE +0x6c)
#define FUNC_SPICS1_GPIO26 1
#define FUNC_SPICS1_SPICS1 0
#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE +0x70)
#define FUNC_SPIHD_GPIO27 1
#define FUNC_SPIHD_SPIHD 0
#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE +0x74)
#define FUNC_SPIWP_GPIO28 1
#define FUNC_SPIWP_SPIWP 0
#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE +0x78)
#define FUNC_SPICS0_GPIO29 1
#define FUNC_SPICS0_SPICS0 0
#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE +0x7c)
#define FUNC_SPICLK_GPIO30 1
#define FUNC_SPICLK_SPICLK 0
#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE +0x80)
#define FUNC_SPIQ_GPIO31 1
#define FUNC_SPIQ_SPIQ 0
#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE +0x84)
#define FUNC_SPID_GPIO32 1
#define FUNC_SPID_SPID 0
#define PERIPHS_IO_MUX_GPIO33_U (REG_IO_MUX_BASE +0x88)
#define FUNC_GPIO33_SUBSPIHD 3
#define FUNC_GPIO33_SD_DATA2 2
#define FUNC_GPIO33_GPIO33 1
#define FUNC_GPIO33_FSPIHD 0
#define PERIPHS_IO_MUX_GPIO34_U (REG_IO_MUX_BASE +0x8c)
#define FUNC_GPIO34_SUBSPICS0 3
#define FUNC_GPIO34_SD_DATA3 2
#define FUNC_GPIO34_GPIO34 1
#define FUNC_GPIO34_FSPICS0 0
#define PERIPHS_IO_MUX_GPIO35_U (REG_IO_MUX_BASE +0x90)
#define FUNC_GPIO35_SUBSPID 3
#define FUNC_GPIO35_SD_CMD 2
#define FUNC_GPIO35_GPIO35 1
#define FUNC_GPIO35_FSPID 0
#define PERIPHS_IO_MUX_GPIO36_U (REG_IO_MUX_BASE +0x94)
#define FUNC_GPIO36_SUBSPICLK 3
#define FUNC_GPIO36_SD_CLK 2
#define FUNC_GPIO36_GPIO36 1
#define FUNC_GPIO36_FSPICLK 0
#define PERIPHS_IO_MUX_GPIO37_U (REG_IO_MUX_BASE +0x98)
#define FUNC_GPIO37_SUBSPIQ 3
#define FUNC_GPIO37_SD_DATA0 2
#define FUNC_GPIO37_GPIO37 1
#define FUNC_GPIO37_FSPIQ 0
#define PERIPHS_IO_MUX_GPIO38_U (REG_IO_MUX_BASE +0x9c)
#define FUNC_GPIO38_SUBSPIWP 3
#define FUNC_GPIO38_SD_DATA1 2
#define FUNC_GPIO38_GPIO38 1
#define FUNC_GPIO38_FSPIWP 0
#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE +0xa0)
#define FUNC_MTCK_SUBSPICS1 3
#define FUNC_MTCK_CLK_OUT3 2
#define FUNC_MTCK_GPIO39 1
#define FUNC_MTCK_MTCK 0
#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE +0xa4)
#define FUNC_MTDO_CLK_OUT2 2
#define FUNC_MTDO_GPIO40 1
#define FUNC_MTDO_MTDO 0
#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE +0xa8)
#define FUNC_MTDI_CLK_OUT1 2
#define FUNC_MTDI_GPIO41 1
#define FUNC_MTDI_MTDI 0
#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE +0xac)
#define FUNC_MTMS_GPIO42 1
#define FUNC_MTMS_MTMS 0
#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE +0xb0)
#define FUNC_U0TXD_CLK_OUT1 2
#define FUNC_U0TXD_GPIO43 1
#define FUNC_U0TXD_U0TXD 0
#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE +0xb4)
#define FUNC_U0RXD_CLK_OUT2 2
#define FUNC_U0RXD_GPIO44 1
#define FUNC_U0RXD_U0RXD 0
#define PERIPHS_IO_MUX_GPIO45_U (REG_IO_MUX_BASE +0xb8)
#define FUNC_GPIO45_GPIO45 1
#define FUNC_GPIO45_GPIO45_0 0
#define PERIPHS_IO_MUX_GPIO46_U (REG_IO_MUX_BASE +0xbc)
#define FUNC_GPIO46_GPIO46 1
#define FUNC_GPIO46_GPIO46_0 0
#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
#define IO_MUX_DATE 0xFFFFFFFF
#define IO_MUX_DATE_S 0
#define IO_MUX_DATE_VERSION 0x1809060
#endif

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components/soc/esp32s2beta/include/soc/ledc_reg.h Normal file
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components/soc/esp32s2beta/include/soc/ledc_struct.h Normal file
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_LEDC_STRUCT_H_
#define _SOC_LEDC_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
struct {
struct {
union {
struct {
uint32_t htimer_sel: 2;
uint32_t hsig_out_en: 1;
uint32_t hidle_lv: 1;
uint32_t hovf_num: 10;
uint32_t hovf_cnt_en: 1;
uint32_t reserved15: 16;
uint32_t clk_en: 1;
};
struct {
uint32_t ltimer_sel: 2;
uint32_t lsig_out_en: 1;
uint32_t lidle_lv: 1;
uint32_t low_speed_update: 1;
uint32_t lovf_num: 10;
uint32_t lovf_cnt_en: 1;
uint32_t reserved16: 16;
};
struct {
uint32_t timer_sel: 2; /*There are four high speed timers the two bits are used to select one of them for high speed channel. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/
uint32_t sig_out_en: 1; /*This is the output enable control bit for high speed channel*/
uint32_t idle_lv: 1; /*This bit is used to control the output value when high speed channel is off.*/
uint32_t reserved28: 28;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t hpoint: 20; /*The output value changes to high when htimerx(x=[0 3]) selected by high speed channel has reached reg_hpoint_hsch0[19:0]*/
uint32_t reserved20: 12;
};
uint32_t val;
} hpoint;
union {
struct {
uint32_t duty: 25; /*The register is used to control output duty. When hstimerx(x=[0 3]) chosen by high speed channel has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
uint32_t reserved25: 7;
};
uint32_t val;
} duty;
union {
struct {
uint32_t duty_scale:10; /*This register controls the increase or decrease step scale for high speed channel.*/
uint32_t duty_cycle:10; /*This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel.*/
uint32_t duty_num: 10; /*This register is used to control the number of increased or decreased times for high speed channel.*/
uint32_t duty_inc: 1; /*This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel.*/
uint32_t duty_start: 1; /*When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/
};
uint32_t val;
} conf1;
union {
struct {
uint32_t duty_read: 25; /*This register represents the current duty of the output signal for high speed channel.*/
uint32_t reserved25: 7;
};
uint32_t val;
} duty_rd;
} channel[8];
} channel_group[2]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/
struct {
struct {
union {
struct {
uint32_t duty_resolution: 5;
uint32_t clock_divider: 18;
uint32_t pause: 1;
uint32_t rst: 1;
uint32_t tick_sel: 1;
uint32_t low_speed_update: 1;
uint32_t reserved27: 5;
};
uint32_t val;
} conf;
union {
struct {
uint32_t timer_cnt: 20; /*software can read this register to get the current counter value in high speed timer*/
uint32_t reserved20: 12;
};
uint32_t val;
} value;
} timer[4];
} timer_group[2]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/
union {
struct {
uint32_t hstimer0_ovf: 1; /*The interrupt raw bit for high speed channel0 counter overflow.*/
uint32_t hstimer1_ovf: 1; /*The interrupt raw bit for high speed channel1 counter overflow.*/
uint32_t hstimer2_ovf: 1; /*The interrupt raw bit for high speed channel2 counter overflow.*/
uint32_t hstimer3_ovf: 1; /*The interrupt raw bit for high speed channel3 counter overflow.*/
uint32_t lstimer0_ovf: 1; /*The interrupt raw bit for low speed channel0 counter overflow.*/
uint32_t lstimer1_ovf: 1; /*The interrupt raw bit for low speed channel1 counter overflow.*/
uint32_t lstimer2_ovf: 1; /*The interrupt raw bit for low speed channel2 counter overflow.*/
uint32_t lstimer3_ovf: 1; /*The interrupt raw bit for low speed channel3 counter overflow.*/
uint32_t duty_chng_end_hsch0: 1; /*The interrupt raw bit for high speed channel 0 duty change done.*/
uint32_t duty_chng_end_hsch1: 1; /*The interrupt raw bit for high speed channel 1 duty change done.*/
uint32_t duty_chng_end_hsch2: 1; /*The interrupt raw bit for high speed channel 2 duty change done.*/
uint32_t duty_chng_end_hsch3: 1; /*The interrupt raw bit for high speed channel 3 duty change done.*/
uint32_t duty_chng_end_hsch4: 1; /*The interrupt raw bit for high speed channel 4 duty change done.*/
uint32_t duty_chng_end_hsch5: 1; /*The interrupt raw bit for high speed channel 5 duty change done.*/
uint32_t duty_chng_end_hsch6: 1; /*The interrupt raw bit for high speed channel 6 duty change done.*/
uint32_t duty_chng_end_hsch7: 1; /*The interrupt raw bit for high speed channel 7 duty change done.*/
uint32_t duty_chng_end_lsch0: 1; /*The interrupt raw bit for low speed channel 0 duty change done.*/
uint32_t duty_chng_end_lsch1: 1; /*The interrupt raw bit for low speed channel 1 duty change done.*/
uint32_t duty_chng_end_lsch2: 1; /*The interrupt raw bit for low speed channel 2 duty change done.*/
uint32_t duty_chng_end_lsch3: 1; /*The interrupt raw bit for low speed channel 3 duty change done.*/
uint32_t duty_chng_end_lsch4: 1; /*The interrupt raw bit for low speed channel 4 duty change done.*/
uint32_t duty_chng_end_lsch5: 1; /*The interrupt raw bit for low speed channel 5 duty change done.*/
uint32_t duty_chng_end_lsch6: 1; /*The interrupt raw bit for low speed channel 6 duty change done.*/
uint32_t duty_chng_end_lsch7: 1; /*The interrupt raw bit for low speed channel 7 duty change done.*/
uint32_t reserved24: 8;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t hstimer0_ovf: 1; /*The interrupt status bit for high speed channel0 counter overflow event.*/
uint32_t hstimer1_ovf: 1; /*The interrupt status bit for high speed channel1 counter overflow event.*/
uint32_t hstimer2_ovf: 1; /*The interrupt status bit for high speed channel2 counter overflow event.*/
uint32_t hstimer3_ovf: 1; /*The interrupt status bit for high speed channel3 counter overflow event.*/
uint32_t lstimer0_ovf: 1; /*The interrupt status bit for low speed channel0 counter overflow event.*/
uint32_t lstimer1_ovf: 1; /*The interrupt status bit for low speed channel1 counter overflow event.*/
uint32_t lstimer2_ovf: 1; /*The interrupt status bit for low speed channel2 counter overflow event.*/
uint32_t lstimer3_ovf: 1; /*The interrupt status bit for low speed channel3 counter overflow event.*/
uint32_t duty_chng_end_hsch0: 1; /*The interrupt enable bit for high speed channel 0 duty change done event.*/
uint32_t duty_chng_end_hsch1: 1; /*The interrupt status bit for high speed channel 1 duty change done event.*/
uint32_t duty_chng_end_hsch2: 1; /*The interrupt status bit for high speed channel 2 duty change done event.*/
uint32_t duty_chng_end_hsch3: 1; /*The interrupt status bit for high speed channel 3 duty change done event.*/
uint32_t duty_chng_end_hsch4: 1; /*The interrupt status bit for high speed channel 4 duty change done event.*/
uint32_t duty_chng_end_hsch5: 1; /*The interrupt status bit for high speed channel 5 duty change done event.*/
uint32_t duty_chng_end_hsch6: 1; /*The interrupt status bit for high speed channel 6 duty change done event.*/
uint32_t duty_chng_end_hsch7: 1; /*The interrupt status bit for high speed channel 7 duty change done event.*/
uint32_t duty_chng_end_lsch0: 1; /*The interrupt status bit for low speed channel 0 duty change done event.*/
uint32_t duty_chng_end_lsch1: 1; /*The interrupt status bit for low speed channel 1 duty change done event.*/
uint32_t duty_chng_end_lsch2: 1; /*The interrupt status bit for low speed channel 2 duty change done event.*/
uint32_t duty_chng_end_lsch3: 1; /*The interrupt status bit for low speed channel 3 duty change done event.*/
uint32_t duty_chng_end_lsch4: 1; /*The interrupt status bit for low speed channel 4 duty change done event.*/
uint32_t duty_chng_end_lsch5: 1; /*The interrupt status bit for low speed channel 5 duty change done event.*/
uint32_t duty_chng_end_lsch6: 1; /*The interrupt status bit for low speed channel 6 duty change done event.*/
uint32_t duty_chng_end_lsch7: 1; /*The interrupt status bit for low speed channel 7 duty change done event*/
uint32_t reserved24: 8;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t hstimer0_ovf: 1; /*The interrupt enable bit for high speed channel0 counter overflow interrupt.*/
uint32_t hstimer1_ovf: 1; /*The interrupt enable bit for high speed channel1 counter overflow interrupt.*/
uint32_t hstimer2_ovf: 1; /*The interrupt enable bit for high speed channel2 counter overflow interrupt.*/
uint32_t hstimer3_ovf: 1; /*The interrupt enable bit for high speed channel3 counter overflow interrupt.*/
uint32_t lstimer0_ovf: 1; /*The interrupt enable bit for low speed channel0 counter overflow interrupt.*/
uint32_t lstimer1_ovf: 1; /*The interrupt enable bit for low speed channel1 counter overflow interrupt.*/
uint32_t lstimer2_ovf: 1; /*The interrupt enable bit for low speed channel2 counter overflow interrupt.*/
uint32_t lstimer3_ovf: 1; /*The interrupt enable bit for low speed channel3 counter overflow interrupt.*/
uint32_t duty_chng_end_hsch0: 1; /*The interrupt enable bit for high speed channel 0 duty change done interrupt.*/
uint32_t duty_chng_end_hsch1: 1; /*The interrupt enable bit for high speed channel 1 duty change done interrupt.*/
uint32_t duty_chng_end_hsch2: 1; /*The interrupt enable bit for high speed channel 2 duty change done interrupt.*/
uint32_t duty_chng_end_hsch3: 1; /*The interrupt enable bit for high speed channel 3 duty change done interrupt.*/
uint32_t duty_chng_end_hsch4: 1; /*The interrupt enable bit for high speed channel 4 duty change done interrupt.*/
uint32_t duty_chng_end_hsch5: 1; /*The interrupt enable bit for high speed channel 5 duty change done interrupt.*/
uint32_t duty_chng_end_hsch6: 1; /*The interrupt enable bit for high speed channel 6 duty change done interrupt.*/
uint32_t duty_chng_end_hsch7: 1; /*The interrupt enable bit for high speed channel 7 duty change done interrupt.*/
uint32_t duty_chng_end_lsch0: 1; /*The interrupt enable bit for low speed channel 0 duty change done interrupt.*/
uint32_t duty_chng_end_lsch1: 1; /*The interrupt enable bit for low speed channel 1 duty change done interrupt.*/
uint32_t duty_chng_end_lsch2: 1; /*The interrupt enable bit for low speed channel 2 duty change done interrupt.*/
uint32_t duty_chng_end_lsch3: 1; /*The interrupt enable bit for low speed channel 3 duty change done interrupt.*/
uint32_t duty_chng_end_lsch4: 1; /*The interrupt enable bit for low speed channel 4 duty change done interrupt.*/
uint32_t duty_chng_end_lsch5: 1; /*The interrupt enable bit for low speed channel 5 duty change done interrupt.*/
uint32_t duty_chng_end_lsch6: 1; /*The interrupt enable bit for low speed channel 6 duty change done interrupt.*/
uint32_t duty_chng_end_lsch7: 1; /*The interrupt enable bit for low speed channel 7 duty change done interrupt.*/
uint32_t reserved24: 8;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t hstimer0_ovf: 1; /*Set this bit to clear high speed channel0 counter overflow interrupt.*/
uint32_t hstimer1_ovf: 1; /*Set this bit to clear high speed channel1 counter overflow interrupt.*/
uint32_t hstimer2_ovf: 1; /*Set this bit to clear high speed channel2 counter overflow interrupt.*/
uint32_t hstimer3_ovf: 1; /*Set this bit to clear high speed channel3 counter overflow interrupt.*/
uint32_t lstimer0_ovf: 1; /*Set this bit to clear low speed channel0 counter overflow interrupt.*/
uint32_t lstimer1_ovf: 1; /*Set this bit to clear low speed channel1 counter overflow interrupt.*/
uint32_t lstimer2_ovf: 1; /*Set this bit to clear low speed channel2 counter overflow interrupt.*/
uint32_t lstimer3_ovf: 1; /*Set this bit to clear low speed channel3 counter overflow interrupt.*/
uint32_t duty_chng_end_hsch0: 1; /*Set this bit to clear high speed channel 0 duty change done interrupt.*/
uint32_t duty_chng_end_hsch1: 1; /*Set this bit to clear high speed channel 1 duty change done interrupt.*/
uint32_t duty_chng_end_hsch2: 1; /*Set this bit to clear high speed channel 2 duty change done interrupt.*/
uint32_t duty_chng_end_hsch3: 1; /*Set this bit to clear high speed channel 3 duty change done interrupt.*/
uint32_t duty_chng_end_hsch4: 1; /*Set this bit to clear high speed channel 4 duty change done interrupt.*/
uint32_t duty_chng_end_hsch5: 1; /*Set this bit to clear high speed channel 5 duty change done interrupt.*/
uint32_t duty_chng_end_hsch6: 1; /*Set this bit to clear high speed channel 6 duty change done interrupt.*/
uint32_t duty_chng_end_hsch7: 1; /*Set this bit to clear high speed channel 7 duty change done interrupt.*/
uint32_t duty_chng_end_lsch0: 1; /*Set this bit to clear low speed channel 0 duty change done interrupt.*/
uint32_t duty_chng_end_lsch1: 1; /*Set this bit to clear low speed channel 1 duty change done interrupt.*/
uint32_t duty_chng_end_lsch2: 1; /*Set this bit to clear low speed channel 2 duty change done interrupt.*/
uint32_t duty_chng_end_lsch3: 1; /*Set this bit to clear low speed channel 3 duty change done interrupt.*/
uint32_t duty_chng_end_lsch4: 1; /*Set this bit to clear low speed channel 4 duty change done interrupt.*/
uint32_t duty_chng_end_lsch5: 1; /*Set this bit to clear low speed channel 5 duty change done interrupt.*/
uint32_t duty_chng_end_lsch6: 1; /*Set this bit to clear low speed channel 6 duty change done interrupt.*/
uint32_t duty_chng_end_lsch7: 1; /*Set this bit to clear low speed channel 7 duty change done interrupt.*/
uint32_t reserved24: 8;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t apb_clk_sel: 2;
uint32_t reserved2: 30;
};
struct {
uint32_t slow_clk_sel: 1; /*This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz, (only used by LEDC low speed channels/timers)*/
uint32_t reserved: 31;
};
uint32_t val;
} conf;
union {
struct {
uint32_t ovf_cnt_hsch0: 1;
uint32_t ovf_cnt_hsch1: 1;
uint32_t ovf_cnt_hsch2: 1;
uint32_t ovf_cnt_hsch3: 1;
uint32_t ovf_cnt_hsch4: 1;
uint32_t ovf_cnt_hsch5: 1;
uint32_t ovf_cnt_hsch6: 1;
uint32_t ovf_cnt_hsch7: 1;
uint32_t ovf_cnt_lsch0: 1;
uint32_t ovf_cnt_lsch1: 1;
uint32_t ovf_cnt_lsch2: 1;
uint32_t ovf_cnt_lsch3: 1;
uint32_t ovf_cnt_lsch4: 1;
uint32_t ovf_cnt_lsch5: 1;
uint32_t ovf_cnt_lsch6: 1;
uint32_t ovf_cnt_lsch7: 1;
uint32_t reserved16: 16;
};
uint32_t val;
} int1_raw;
union {
struct {
uint32_t ovf_cnt_hsch0: 1;
uint32_t ovf_cnt_hsch1: 1;
uint32_t ovf_cnt_hsch2: 1;
uint32_t ovf_cnt_hsch3: 1;
uint32_t ovf_cnt_hsch4: 1;
uint32_t ovf_cnt_hsch5: 1;
uint32_t ovf_cnt_hsch6: 1;
uint32_t ovf_cnt_hsch7: 1;
uint32_t ovf_cnt_lsch0: 1;
uint32_t ovf_cnt_lsch1: 1;
uint32_t ovf_cnt_lsch2: 1;
uint32_t ovf_cnt_lsch3: 1;
uint32_t ovf_cnt_lsch4: 1;
uint32_t ovf_cnt_lsch5: 1;
uint32_t ovf_cnt_lsch6: 1;
uint32_t ovf_cnt_lsch7: 1;
uint32_t reserved16: 16;
};
uint32_t val;
} int1_st;
union {
struct {
uint32_t ovf_cnt_hsch0: 1;
uint32_t ovf_cnt_hsch1: 1;
uint32_t ovf_cnt_hsch2: 1;
uint32_t ovf_cnt_hsch3: 1;
uint32_t ovf_cnt_hsch4: 1;
uint32_t ovf_cnt_hsch5: 1;
uint32_t ovf_cnt_hsch6: 1;
uint32_t ovf_cnt_hsch7: 1;
uint32_t ovf_cnt_lsch0: 1;
uint32_t ovf_cnt_lsch1: 1;
uint32_t ovf_cnt_lsch2: 1;
uint32_t ovf_cnt_lsch3: 1;
uint32_t ovf_cnt_lsch4: 1;
uint32_t ovf_cnt_lsch5: 1;
uint32_t ovf_cnt_lsch6: 1;
uint32_t ovf_cnt_lsch7: 1;
uint32_t reserved16: 16;
};
uint32_t val;
} int1_ena;
union {
struct {
uint32_t ovf_cnt_hsch0: 1;
uint32_t ovf_cnt_hsch1: 1;
uint32_t ovf_cnt_hsch2: 1;
uint32_t ovf_cnt_hsch3: 1;
uint32_t ovf_cnt_hsch4: 1;
uint32_t ovf_cnt_hsch5: 1;
uint32_t ovf_cnt_hsch6: 1;
uint32_t ovf_cnt_hsch7: 1;
uint32_t ovf_cnt_lsch0: 1;
uint32_t ovf_cnt_lsch1: 1;
uint32_t ovf_cnt_lsch2: 1;
uint32_t ovf_cnt_lsch3: 1;
uint32_t ovf_cnt_lsch4: 1;
uint32_t ovf_cnt_lsch5: 1;
uint32_t ovf_cnt_lsch6: 1;
uint32_t ovf_cnt_lsch7: 1;
uint32_t reserved16: 16;
};
uint32_t val;
} int1_clr;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
uint32_t date; /*This register represents the version .*/
} ledc_dev_t;
extern ledc_dev_t LEDC;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_LEDC_STRUCT_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_MCPWM_STRUCT_H__
#define _SOC_MCPWM_STRUCT_H__
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t prescale: 8; /*Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/
uint32_t reserved8: 24;
};
uint32_t val;
}clk_cfg;
struct {
union {
struct {
uint32_t prescale: 8; /*period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)*/
uint32_t period: 16; /*period shadow reg of PWM timer0*/
uint32_t upmethod: 2; /*Update method for active reg of PWM timer0 period 0: immediate 1: TEZ 2: sync 3: TEZ | sync. TEZ here and below means timer equal zero event*/
uint32_t reserved26: 6;
};
uint32_t val;
}period;
union {
struct {
uint32_t start: 3; /*PWM timer0 start and stop control. 0: stop @ TEZ 1: stop @ TEP 2: free run 3: start and stop @ next TEZ 4: start and stop @ next TEP. TEP here and below means timer equal period event*/
uint32_t mode: 2; /*PWM timer0 working mode 0: freeze 1: increase mod 2: decrease mod 3: up-down mod*/
uint32_t reserved5: 27;
};
uint32_t val;
}mode;
union {
struct {
uint32_t in_en: 1; /*when set timer reload with phase on sync input event is enabled*/
uint32_t sync_sw: 1; /*write the negate value will trigger a software sync*/
uint32_t out_sel: 2; /*PWM timer0 synco selection 0: synci 1: TEZ 2: TEP else 0*/
uint32_t timer_phase: 17; /*phase for timer reload on sync event*/
uint32_t reserved21: 11;
};
uint32_t val;
}sync;
union {
struct {
uint32_t value: 16; /*current PWM timer0 counter value*/
uint32_t direction: 1; /*current PWM timer0 counter direction 0: increment 1: decrement*/
uint32_t reserved17: 15;
};
uint32_t val;
}status;
}timer[3];
union {
struct {
uint32_t t0_in_sel: 3; /*select sync input for PWM timer0 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/
uint32_t t1_in_sel: 3; /*select sync input for PWM timer1 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/
uint32_t t2_in_sel: 3; /*select sync input for PWM timer2 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/
uint32_t ext_in0_inv: 1; /*invert SYNC0 from GPIO matrix*/
uint32_t ext_in1_inv: 1; /*invert SYNC1 from GPIO matrix*/
uint32_t ext_in2_inv: 1; /*invert SYNC2 from GPIO matrix*/
uint32_t reserved12: 20;
};
uint32_t val;
}timer_synci_cfg;
union {
struct {
uint32_t operator0_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator0 0: timer0 1: timer1 2: timer2*/
uint32_t operator1_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator1 0: timer0 1: timer1 2: timer2*/
uint32_t operator2_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator2 0: timer0 1: timer1 2: timer2*/
uint32_t reserved6: 26;
};
uint32_t val;
}timer_sel;
struct {
union {
struct {
uint32_t a_upmethod: 4; /*Update method for PWM compare0 A's active reg. 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: freeze*/
uint32_t b_upmethod: 4; /*Update method for PWM compare0 B's active reg. 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: freeze*/
uint32_t a_shdw_full: 1; /*Set and reset by hardware. If set PWM compare0 A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared A's active reg has been updated with shadow reg latest value*/
uint32_t b_shdw_full: 1; /*Set and reset by hardware. If set PWM compare0 B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared B's active reg has been updated with shadow reg latest value*/
uint32_t reserved10: 22;
};
uint32_t val;
}cmpr_cfg;
union {
struct {
uint32_t cmpr_val: 16; /*PWM compare0 A's shadow reg*/
uint32_t reserved16:16;
};
uint32_t val;
}cmpr_value[2];
union {
struct {
uint32_t upmethod: 4; /*Update method for PWM generate0's active reg of configuration. 0: immediate bit0: TEZ bit1: TEP bit2: sync. bit3: freeze*/
uint32_t t0_sel: 3; /*Source selection for PWM generate0 event_t0 take effect immediately 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/
uint32_t t1_sel: 3; /*Source selection for PWM generate0 event_t1 take effect immediately 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/
uint32_t reserved10: 22;
};
uint32_t val;
}gen_cfg0;
union {
struct {
uint32_t cntu_force_upmethod: 6; /*Update method for continuous software force of PWM generate0. 0: immediate bit0: TEZ bit1: TEP bit2: TEA bit3: TEB bit4: sync bit5: freeze. (TEA/B here and below means timer equals A/B event)*/
uint32_t a_cntuforce_mode: 2; /*Continuous software force mode for PWM0A. 0: disabled 1: low 2: high 3: disabled*/
uint32_t b_cntuforce_mode: 2; /*Continuous software force mode for PWM0B. 0: disabled 1: low 2: high 3: disabled*/
uint32_t a_nciforce: 1; /*non-continuous immediate software force trigger for PWM0A a toggle will trigger a force event*/
uint32_t a_nciforce_mode: 2; /*non-continuous immediate software force mode for PWM0A 0: disabled 1: low 2: high 3: disabled*/
uint32_t b_nciforce: 1; /*non-continuous immediate software force trigger for PWM0B a toggle will trigger a force event*/
uint32_t b_nciforce_mode: 2; /*non-continuous immediate software force mode for PWM0B 0: disabled 1: low 2: high 3: disabled*/
uint32_t reserved16: 16;
};
uint32_t val;
}gen_force;
union {
struct {
uint32_t utez: 2; /*Action on PWM0A triggered by event TEZ when timer increasing*/
uint32_t utep: 2; /*Action on PWM0A triggered by event TEP when timer increasing*/
uint32_t utea: 2; /*Action on PWM0A triggered by event TEA when timer increasing*/
uint32_t uteb: 2; /*Action on PWM0A triggered by event TEB when timer increasing*/
uint32_t ut0: 2; /*Action on PWM0A triggered by event_t0 when timer increasing*/
uint32_t ut1: 2; /*Action on PWM0A triggered by event_t1 when timer increasing*/
uint32_t dtez: 2; /*Action on PWM0A triggered by event TEZ when timer decreasing*/
uint32_t dtep: 2; /*Action on PWM0A triggered by event TEP when timer decreasing*/
uint32_t dtea: 2; /*Action on PWM0A triggered by event TEA when timer decreasing*/
uint32_t dteb: 2; /*Action on PWM0A triggered by event TEB when timer decreasing*/
uint32_t dt0: 2; /*Action on PWM0A triggered by event_t0 when timer decreasing*/
uint32_t dt1: 2; /*Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change 1: low 2: high 3: toggle*/
uint32_t reserved24: 8;
};
uint32_t val;
}generator[2];
union {
struct {
uint32_t fed_upmethod: 4; /*Update method for FED (falling edge delay) active reg. 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/
uint32_t red_upmethod: 4; /*Update method for RED (rising edge delay) active reg. 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/
uint32_t deb_mode: 1; /*S8 in documentation dual-edge B mode 0: fed/red take effect on different path separately 1: fed/red take effect on B path A out is in bypass or dulpB mode*/
uint32_t a_outswap: 1; /*S6 in documentation*/
uint32_t b_outswap: 1; /*S7 in documentation*/
uint32_t red_insel: 1; /*S4 in documentation*/
uint32_t fed_insel: 1; /*S5 in documentation*/
uint32_t red_outinvert: 1; /*S2 in documentation*/
uint32_t fed_outinvert: 1; /*S3 in documentation*/
uint32_t a_outbypass: 1; /*S1 in documentation*/
uint32_t b_outbypass: 1; /*S0 in documentation*/
uint32_t clk_sel: 1; /*Dead band0 clock selection. 0: PWM_clk 1: PT_clk*/
uint32_t reserved18: 14;
};
uint32_t val;
}db_cfg;
union {
struct {
uint32_t fed: 16; /*Shadow reg for FED*/
uint32_t reserved16:16;
};
uint32_t val;
}db_fed_cfg;
union {
struct {
uint32_t red: 16; /*Shadow reg for RED*/
uint32_t reserved16:16;
};
uint32_t val;
}db_red_cfg;
union {
struct {
uint32_t en: 1; /*When set carrier0 function is enabled. When reset carrier0 is bypassed*/
uint32_t prescale: 4; /*carrier0 clk (CP_clk) prescale value. Period of CP_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)*/
uint32_t duty: 3; /*carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8*/
uint32_t oshtwth: 4; /*width of the fist pulse in number of periods of the carrier*/
uint32_t out_invert: 1; /*when set invert the output of PWM0A and PWM0B for this submodule*/
uint32_t in_invert: 1; /*when set invert the input of PWM0A and PWM0B for this submodule*/
uint32_t reserved14: 18;
};
uint32_t val;
}carrier_cfg;
union {
struct {
uint32_t sw_cbc: 1; /*Cycle-by-cycle tripping software force event will trigger cycle-by-cycle trip event. 0: disable 1: enable*/
uint32_t f2_cbc: 1; /*event_f2 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/
uint32_t f1_cbc: 1; /*event_f1 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/
uint32_t f0_cbc: 1; /*event_f0 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/
uint32_t sw_ost: 1; /*one-shot tripping software force event will trigger one-shot trip event. 0: disable 1: enable*/
uint32_t f2_ost: 1; /*event_f2 will trigger one-shot trip event. 0: disable 1: enable*/
uint32_t f1_ost: 1; /*event_f1 will trigger one-shot trip event. 0: disable 1: enable*/
uint32_t f0_ost: 1; /*event_f0 will trigger one-shot trip event. 0: disable 1: enable*/
uint32_t a_cbc_d: 2; /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t a_cbc_u: 2; /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t a_ost_d: 2; /*Action on PWM0A when one-shot trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t a_ost_u: 2; /*Action on PWM0A when one-shot trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t b_cbc_d: 2; /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t b_cbc_u: 2; /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t b_ost_d: 2; /*Action on PWM0B when one-shot trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t b_ost_u: 2; /*Action on PWM0B when one-shot trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t reserved24: 8;
};
uint32_t val;
}tz_cfg0;
union {
struct {
uint32_t clr_ost: 1; /*a toggle will clear on going one-shot tripping*/
uint32_t cbcpulse: 2; /*cycle-by-cycle tripping refresh moment selection. Bit0: TEZ bit1:TEP*/
uint32_t force_cbc: 1; /*a toggle trigger a cycle-by-cycle tripping software force event*/
uint32_t force_ost: 1; /*a toggle (software negate its value) trigger a one-shot tripping software force event*/
uint32_t reserved5: 27;
};
uint32_t val;
}tz_cfg1;
union {
struct {
uint32_t cbc_on: 1; /*Set and reset by hardware. If set an cycle-by-cycle trip event is on going*/
uint32_t ost_on: 1; /*Set and reset by hardware. If set an one-shot trip event is on going*/
uint32_t reserved2: 30;
};
uint32_t val;
}tz_status;
}channel[3];
union {
struct {
uint32_t f0_en: 1; /*When set event_f0 generation is enabled*/
uint32_t f1_en: 1; /*When set event_f1 generation is enabled*/
uint32_t f2_en: 1; /*When set event_f2 generation is enabled*/
uint32_t f0_pole: 1; /*Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/
uint32_t f1_pole: 1; /*Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/
uint32_t f2_pole: 1; /*Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/
uint32_t event_f0: 1; /*Set and reset by hardware. If set event_f0 is on going*/
uint32_t event_f1: 1; /*Set and reset by hardware. If set event_f1 is on going*/
uint32_t event_f2: 1; /*Set and reset by hardware. If set event_f2 is on going*/
uint32_t reserved9: 23;
};
uint32_t val;
}fault_detect;
union {
struct {
uint32_t timer_en: 1; /*When set capture timer incrementing under APB_clk is enabled.*/
uint32_t synci_en: 1; /*When set capture timer sync is enabled.*/
uint32_t synci_sel: 3; /*capture module sync input selection. 0: none 1: timer0 synco 2: timer1 synco 3: timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix*/
uint32_t sync_sw: 1; /*Write 1 will force a capture timer sync capture timer is loaded with value in phase register.*/
uint32_t reserved6: 26;
};
uint32_t val;
}cap_timer_cfg;
uint32_t cap_timer_phase; /*Phase value for capture timer sync operation.*/
union {
struct {
uint32_t en: 1; /*When set capture on channel 0 is enabled*/
uint32_t mode: 2; /*Edge of capture on channel 0 after prescale. bit0: negedge cap en bit1: posedge cap en*/
uint32_t prescale: 8; /*Value of prescale on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1*/
uint32_t in_invert: 1; /*when set CAP0 form GPIO matrix is inverted before prescale*/
uint32_t sw: 1; /*Write 1 will trigger a software forced capture on channel 0*/
uint32_t reserved13: 19;
};
uint32_t val;
}cap_cfg_ch[3];
uint32_t cap_val_ch[3]; /*Value of last capture on channel 0*/
union {
struct {
uint32_t cap0_edge: 1; /*Edge of last capture trigger on channel 0 0: posedge 1: negedge*/
uint32_t cap1_edge: 1; /*Edge of last capture trigger on channel 1 0: posedge 1: negedge*/
uint32_t cap2_edge: 1; /*Edge of last capture trigger on channel 2 0: posedge 1: negedge*/
uint32_t reserved3: 29;
};
uint32_t val;
}cap_status;
union {
struct {
uint32_t global_up_en: 1; /*The global enable of update of all active registers in MCPWM module*/
uint32_t global_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module*/
uint32_t op0_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 0 are enabled*/
uint32_t op0_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0*/
uint32_t op1_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 1 are enabled*/
uint32_t op1_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1*/
uint32_t op2_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 2 are enabled*/
uint32_t op2_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2*/
uint32_t reserved8: 24;
};
uint32_t val;
}update_cfg;
union {
struct {
uint32_t timer0_stop_int_ena: 1; /*Interrupt when timer 0 stops*/
uint32_t timer1_stop_int_ena: 1; /*Interrupt when timer 1 stops*/
uint32_t timer2_stop_int_ena: 1; /*Interrupt when timer 2 stops*/
uint32_t timer0_tez_int_ena: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/
uint32_t timer1_tez_int_ena: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/
uint32_t timer2_tez_int_ena: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/
uint32_t timer0_tep_int_ena: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/
uint32_t timer1_tep_int_ena: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/
uint32_t timer2_tep_int_ena: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/
uint32_t fault0_int_ena: 1; /*Interrupt when event_f0 starts*/
uint32_t fault1_int_ena: 1; /*Interrupt when event_f1 starts*/
uint32_t fault2_int_ena: 1; /*Interrupt when event_f2 starts*/
uint32_t fault0_clr_int_ena: 1; /*Interrupt when event_f0 ends*/
uint32_t fault1_clr_int_ena: 1; /*Interrupt when event_f1 ends*/
uint32_t fault2_clr_int_ena: 1; /*Interrupt when event_f2 ends*/
uint32_t cmpr0_tea_int_ena: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/
uint32_t cmpr1_tea_int_ena: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/
uint32_t cmpr2_tea_int_ena: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/
uint32_t cmpr0_teb_int_ena: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/
uint32_t cmpr1_teb_int_ena: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/
uint32_t cmpr2_teb_int_ena: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/
uint32_t tz0_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
uint32_t tz0_ost_int_ena: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_ost_int_ena: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_ost_int_ena: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/
uint32_t cap0_int_ena: 1; /*A capture on channel 0 will trigger this interrupt*/
uint32_t cap1_int_ena: 1; /*A capture on channel 1 will trigger this interrupt*/
uint32_t cap2_int_ena: 1; /*A capture on channel 2 will trigger this interrupt*/
uint32_t reserved30: 2;
};
uint32_t val;
}int_ena;
union {
struct {
uint32_t timer0_stop_int_raw: 1; /*Interrupt when timer 0 stops*/
uint32_t timer1_stop_int_raw: 1; /*Interrupt when timer 1 stops*/
uint32_t timer2_stop_int_raw: 1; /*Interrupt when timer 2 stops*/
uint32_t timer0_tez_int_raw: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/
uint32_t timer1_tez_int_raw: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/
uint32_t timer2_tez_int_raw: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/
uint32_t timer0_tep_int_raw: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/
uint32_t timer1_tep_int_raw: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/
uint32_t timer2_tep_int_raw: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/
uint32_t fault0_int_raw: 1; /*Interrupt when event_f0 starts*/
uint32_t fault1_int_raw: 1; /*Interrupt when event_f1 starts*/
uint32_t fault2_int_raw: 1; /*Interrupt when event_f2 starts*/
uint32_t fault0_clr_int_raw: 1; /*Interrupt when event_f0 ends*/
uint32_t fault1_clr_int_raw: 1; /*Interrupt when event_f1 ends*/
uint32_t fault2_clr_int_raw: 1; /*Interrupt when event_f2 ends*/
uint32_t cmpr0_tea_int_raw: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/
uint32_t cmpr1_tea_int_raw: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/
uint32_t cmpr2_tea_int_raw: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/
uint32_t cmpr0_teb_int_raw: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/
uint32_t cmpr1_teb_int_raw: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/
uint32_t cmpr2_teb_int_raw: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/
uint32_t tz0_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
uint32_t tz0_ost_int_raw: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_ost_int_raw: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_ost_int_raw: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/
uint32_t cap0_int_raw: 1; /*A capture on channel 0 will trigger this interrupt*/
uint32_t cap1_int_raw: 1; /*A capture on channel 1 will trigger this interrupt*/
uint32_t cap2_int_raw: 1; /*A capture on channel 2 will trigger this interrupt*/
uint32_t reserved30: 2;
};
uint32_t val;
}int_raw;
union {
struct {
uint32_t timer0_stop_int_st: 1; /*Interrupt when timer 0 stops*/
uint32_t timer1_stop_int_st: 1; /*Interrupt when timer 1 stops*/
uint32_t timer2_stop_int_st: 1; /*Interrupt when timer 2 stops*/
uint32_t timer0_tez_int_st: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/
uint32_t timer1_tez_int_st: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/
uint32_t timer2_tez_int_st: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/
uint32_t timer0_tep_int_st: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/
uint32_t timer1_tep_int_st: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/
uint32_t timer2_tep_int_st: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/
uint32_t fault0_int_st: 1; /*Interrupt when event_f0 starts*/
uint32_t fault1_int_st: 1; /*Interrupt when event_f1 starts*/
uint32_t fault2_int_st: 1; /*Interrupt when event_f2 starts*/
uint32_t fault0_clr_int_st: 1; /*Interrupt when event_f0 ends*/
uint32_t fault1_clr_int_st: 1; /*Interrupt when event_f1 ends*/
uint32_t fault2_clr_int_st: 1; /*Interrupt when event_f2 ends*/
uint32_t cmpr0_tea_int_st: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/
uint32_t cmpr1_tea_int_st: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/
uint32_t cmpr2_tea_int_st: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/
uint32_t cmpr0_teb_int_st: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/
uint32_t cmpr1_teb_int_st: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/
uint32_t cmpr2_teb_int_st: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/
uint32_t tz0_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
uint32_t tz0_ost_int_st: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_ost_int_st: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_ost_int_st: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/
uint32_t cap0_int_st: 1; /*A capture on channel 0 will trigger this interrupt*/
uint32_t cap1_int_st: 1; /*A capture on channel 1 will trigger this interrupt*/
uint32_t cap2_int_st: 1; /*A capture on channel 2 will trigger this interrupt*/
uint32_t reserved30: 2;
};
uint32_t val;
}int_st;
union {
struct {
uint32_t timer0_stop_int_clr: 1; /*Interrupt when timer 0 stops*/
uint32_t timer1_stop_int_clr: 1; /*Interrupt when timer 1 stops*/
uint32_t timer2_stop_int_clr: 1; /*Interrupt when timer 2 stops*/
uint32_t timer0_tez_int_clr: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/
uint32_t timer1_tez_int_clr: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/
uint32_t timer2_tez_int_clr: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/
uint32_t timer0_tep_int_clr: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/
uint32_t timer1_tep_int_clr: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/
uint32_t timer2_tep_int_clr: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/
uint32_t fault0_int_clr: 1; /*Interrupt when event_f0 starts*/
uint32_t fault1_int_clr: 1; /*Interrupt when event_f1 starts*/
uint32_t fault2_int_clr: 1; /*Interrupt when event_f2 starts*/
uint32_t fault0_clr_int_clr: 1; /*Interrupt when event_f0 ends*/
uint32_t fault1_clr_int_clr: 1; /*Interrupt when event_f1 ends*/
uint32_t fault2_clr_int_clr: 1; /*Interrupt when event_f2 ends*/
uint32_t cmpr0_tea_int_clr: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/
uint32_t cmpr1_tea_int_clr: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/
uint32_t cmpr2_tea_int_clr: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/
uint32_t cmpr0_teb_int_clr: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/
uint32_t cmpr1_teb_int_clr: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/
uint32_t cmpr2_teb_int_clr: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/
uint32_t tz0_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
uint32_t tz0_ost_int_clr: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_ost_int_clr: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_ost_int_clr: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/
uint32_t cap0_int_clr: 1; /*A capture on channel 0 will trigger this interrupt*/
uint32_t cap1_int_clr: 1; /*A capture on channel 1 will trigger this interrupt*/
uint32_t cap2_int_clr: 1; /*A capture on channel 2 will trigger this interrupt*/
uint32_t reserved30: 2;
};
uint32_t val;
}int_clr;
union {
struct {
uint32_t clk_en: 1; /*Force clock on for this reg file*/
uint32_t reserved1: 31;
};
uint32_t val;
}reg_clk;
union {
struct {
uint32_t date: 28; /*Version of this reg file*/
uint32_t reserved28: 4;
};
uint32_t val;
}version;
} mcpwm_dev_t;
extern mcpwm_dev_t MCPWM0;
extern mcpwm_dev_t MCPWM1;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_MCPWM_STRUCT_H__ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include "soc/soc.h"
/* Some of the WiFi RX control registers.
* PU/PD fields defined here are used in sleep related functions.
*/
#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4)
#define NRX_CHAN_EST_FORCE_PU (BIT(7))
#define NRX_CHAN_EST_FORCE_PU_M (BIT(7))
#define NRX_CHAN_EST_FORCE_PU_V 1
#define NRX_CHAN_EST_FORCE_PU_S 7
#define NRX_CHAN_EST_FORCE_PD (BIT(6))
#define NRX_CHAN_EST_FORCE_PD_M (BIT(6))
#define NRX_CHAN_EST_FORCE_PD_V 1
#define NRX_CHAN_EST_FORCE_PD_S 6
#define NRX_RX_ROT_FORCE_PU (BIT(5))
#define NRX_RX_ROT_FORCE_PU_M (BIT(5))
#define NRX_RX_ROT_FORCE_PU_V 1
#define NRX_RX_ROT_FORCE_PU_S 5
#define NRX_RX_ROT_FORCE_PD (BIT(4))
#define NRX_RX_ROT_FORCE_PD_M (BIT(4))
#define NRX_RX_ROT_FORCE_PD_V 1
#define NRX_RX_ROT_FORCE_PD_S 4
#define NRX_VIT_FORCE_PU (BIT(3))
#define NRX_VIT_FORCE_PU_M (BIT(3))
#define NRX_VIT_FORCE_PU_V 1
#define NRX_VIT_FORCE_PU_S 3
#define NRX_VIT_FORCE_PD (BIT(2))
#define NRX_VIT_FORCE_PD_M (BIT(2))
#define NRX_VIT_FORCE_PD_V 1
#define NRX_VIT_FORCE_PD_S 2
#define NRX_DEMAP_FORCE_PU (BIT(1))
#define NRX_DEMAP_FORCE_PU_M (BIT(1))
#define NRX_DEMAP_FORCE_PU_V 1
#define NRX_DEMAP_FORCE_PU_S 1
#define NRX_DEMAP_FORCE_PD (BIT(0))
#define NRX_DEMAP_FORCE_PD_M (BIT(0))
#define NRX_DEMAP_FORCE_PD_V 1
#define NRX_DEMAP_FORCE_PD_S 0

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components/soc/esp32s2beta/include/soc/pcnt_struct.h Normal file
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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_PCNT_STRUCT_H_
#define _SOC_PCNT_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
struct{
union {
struct {
uint32_t filter_thres: 10; /*This register is used to filter pulse whose width is smaller than this value for unit0.*/
uint32_t filter_en: 1; /*This is the enable bit for filtering input signals for unit0.*/
uint32_t thr_zero_en: 1; /*This is the enable bit for comparing unit0's count with 0 value.*/
uint32_t thr_h_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_h_lim value.*/
uint32_t thr_l_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_l_lim value.*/
uint32_t thr_thres0_en: 1; /*This is the enable bit for comparing unit0's count with thres0 value.*/
uint32_t thr_thres1_en: 1; /*This is the enable bit for comparing unit0's count with thres1 value .*/
uint32_t ch0_neg_mode: 2; /*This register is used to control the mode of channel0's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
uint32_t ch0_pos_mode: 2; /*This register is used to control the mode of channel0's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
uint32_t ch0_hctrl_mode: 2; /*This register is used to control the mode of channel0's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/
uint32_t ch0_lctrl_mode: 2; /*This register is used to control the mode of channel0's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/
uint32_t ch1_neg_mode: 2; /*This register is used to control the mode of channel1's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
uint32_t ch1_pos_mode: 2; /*This register is used to control the mode of channel1's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
uint32_t ch1_hctrl_mode: 2; /*This register is used to control the mode of channel1's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/
uint32_t ch1_lctrl_mode: 2; /*This register is used to control the mode of channel1's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/
};
uint32_t val;
} conf0;
union {
struct {
uint32_t cnt_thres0:16; /*This register is used to configure thres0 value for unit0.*/
uint32_t cnt_thres1:16; /*This register is used to configure thres1 value for unit0.*/
};
uint32_t val;
} conf1;
union {
struct {
uint32_t cnt_h_lim:16; /*This register is used to configure thr_h_lim value for unit0.*/
uint32_t cnt_l_lim:16; /*This register is used to configure thr_l_lim value for unit0.*/
};
uint32_t val;
} conf2;
} conf_unit[8];
union {
struct {
uint32_t cnt_val : 16; /*This register stores the current pulse count value for unit0.*/
uint32_t reserved16: 16;
};
uint32_t val;
} cnt_unit[8];
union {
struct {
uint32_t cnt_thr_event_u0: 1; /*This is the interrupt raw bit for channel0 event.*/
uint32_t cnt_thr_event_u1: 1; /*This is the interrupt raw bit for channel1 event.*/
uint32_t cnt_thr_event_u2: 1; /*This is the interrupt raw bit for channel2 event.*/
uint32_t cnt_thr_event_u3: 1; /*This is the interrupt raw bit for channel3 event.*/
uint32_t cnt_thr_event_u4: 1; /*This is the interrupt raw bit for channel4 event.*/
uint32_t cnt_thr_event_u5: 1; /*This is the interrupt raw bit for channel5 event.*/
uint32_t cnt_thr_event_u6: 1; /*This is the interrupt raw bit for channel6 event.*/
uint32_t cnt_thr_event_u7: 1; /*This is the interrupt raw bit for channel7 event.*/
uint32_t reserved8: 24;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t cnt_thr_event_u0: 1; /*This is the interrupt status bit for channel0 event.*/
uint32_t cnt_thr_event_u1: 1; /*This is the interrupt status bit for channel1 event.*/
uint32_t cnt_thr_event_u2: 1; /*This is the interrupt status bit for channel2 event.*/
uint32_t cnt_thr_event_u3: 1; /*This is the interrupt status bit for channel3 event.*/
uint32_t cnt_thr_event_u4: 1; /*This is the interrupt status bit for channel4 event.*/
uint32_t cnt_thr_event_u5: 1; /*This is the interrupt status bit for channel5 event.*/
uint32_t cnt_thr_event_u6: 1; /*This is the interrupt status bit for channel6 event.*/
uint32_t cnt_thr_event_u7: 1; /*This is the interrupt status bit for channel7 event.*/
uint32_t reserved8: 24;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t cnt_thr_event_u0: 1; /*This is the interrupt enable bit for channel0 event.*/
uint32_t cnt_thr_event_u1: 1; /*This is the interrupt enable bit for channel1 event.*/
uint32_t cnt_thr_event_u2: 1; /*This is the interrupt enable bit for channel2 event.*/
uint32_t cnt_thr_event_u3: 1; /*This is the interrupt enable bit for channel3 event.*/
uint32_t cnt_thr_event_u4: 1; /*This is the interrupt enable bit for channel4 event.*/
uint32_t cnt_thr_event_u5: 1; /*This is the interrupt enable bit for channel5 event.*/
uint32_t cnt_thr_event_u6: 1; /*This is the interrupt enable bit for channel6 event.*/
uint32_t cnt_thr_event_u7: 1; /*This is the interrupt enable bit for channel7 event.*/
uint32_t reserved8: 24;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t cnt_thr_event_u0: 1; /*Set this bit to clear channel0 event interrupt.*/
uint32_t cnt_thr_event_u1: 1; /*Set this bit to clear channel1 event interrupt.*/
uint32_t cnt_thr_event_u2: 1; /*Set this bit to clear channel2 event interrupt.*/
uint32_t cnt_thr_event_u3: 1; /*Set this bit to clear channel3 event interrupt.*/
uint32_t cnt_thr_event_u4: 1; /*Set this bit to clear channel4 event interrupt.*/
uint32_t cnt_thr_event_u5: 1; /*Set this bit to clear channel5 event interrupt.*/
uint32_t cnt_thr_event_u6: 1; /*Set this bit to clear channel6 event interrupt.*/
uint32_t cnt_thr_event_u7: 1; /*Set this bit to clear channel7 event interrupt.*/
uint32_t reserved8: 24;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t cnt_mode:2; /*0: positive value to zero; 1: negative value to zero; 2: counter value negative ; 3: counter value positive*/
uint32_t thres1_lat:1; /* counter value equals to thresh1*/
uint32_t thres0_lat:1; /* counter value equals to thresh0*/
uint32_t l_lim_lat:1; /* counter value reaches h_lim*/
uint32_t h_lim_lat:1; /* counter value reaches l_lim*/
uint32_t zero_lat:1; /* counter value equals zero*/
uint32_t reserved7:25;
};
uint32_t val;
} status_unit[8];
union {
struct {
uint32_t cnt_rst_u0: 1; /*Set this bit to clear unit0's counter.*/
uint32_t cnt_pause_u0: 1; /*Set this bit to pause unit0's counter.*/
uint32_t cnt_rst_u1: 1; /*Set this bit to clear unit1's counter.*/
uint32_t cnt_pause_u1: 1; /*Set this bit to pause unit1's counter.*/
uint32_t cnt_rst_u2: 1; /*Set this bit to clear unit2's counter.*/
uint32_t cnt_pause_u2: 1; /*Set this bit to pause unit2's counter.*/
uint32_t cnt_rst_u3: 1; /*Set this bit to clear unit3's counter.*/
uint32_t cnt_pause_u3: 1; /*Set this bit to pause unit3's counter.*/
uint32_t cnt_rst_u4: 1; /*Set this bit to clear unit4's counter.*/
uint32_t cnt_pause_u4: 1; /*Set this bit to pause unit4's counter.*/
uint32_t cnt_rst_u5: 1; /*Set this bit to clear unit5's counter.*/
uint32_t cnt_pause_u5: 1; /*Set this bit to pause unit5's counter.*/
uint32_t cnt_rst_u6: 1; /*Set this bit to clear unit6's counter.*/
uint32_t cnt_pause_u6: 1; /*Set this bit to pause unit6's counter.*/
uint32_t cnt_rst_u7: 1; /*Set this bit to clear unit7's counter.*/
uint32_t cnt_pause_u7: 1; /*Set this bit to pause unit7's counter.*/
uint32_t clk_en: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} ctrl;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t date; /**/
} pcnt_dev_t;
extern pcnt_dev_t PCNT;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_PCNT_STRUCT_H_ */

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// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_PERIPH_DEFS_H_
#define _SOC_PERIPH_DEFS_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PERIPH_LEDC_MODULE = 0,
PERIPH_UART0_MODULE,
PERIPH_UART1_MODULE,
#ifdef CONFIG_CHIP_IS_ESP32
PERIPH_UART2_MODULE,
#else
PERIPH_USB_MODULE,
#endif
PERIPH_I2C0_MODULE,
PERIPH_I2C1_MODULE,
PERIPH_I2S0_MODULE,
PERIPH_I2S1_MODULE,
PERIPH_TIMG0_MODULE,
PERIPH_TIMG1_MODULE,
PERIPH_PWM0_MODULE,
PERIPH_PWM1_MODULE,
PERIPH_PWM2_MODULE,
PERIPH_PWM3_MODULE,
PERIPH_UHCI0_MODULE,
PERIPH_UHCI1_MODULE,
PERIPH_RMT_MODULE,
PERIPH_PCNT_MODULE,
PERIPH_SPI_MODULE, //SPI1
PERIPH_FSPI_MODULE, //SPI2
PERIPH_HSPI_MODULE, //SPI3
PERIPH_VSPI_MODULE, //SPI4
PERIPH_SPI2_DMA_MODULE,
PERIPH_SPI3_DMA_MODULE,
PERIPH_SPI_SHARED_DMA_MODULE, //this DMA is shared by SPI1 and SPI4
PERIPH_SDMMC_MODULE,
PERIPH_SDIO_SLAVE_MODULE,
PERIPH_CAN_MODULE,
PERIPH_EMAC_MODULE,
PERIPH_RNG_MODULE,
PERIPH_WIFI_MODULE,
PERIPH_BT_MODULE,
PERIPH_WIFI_BT_COMMON_MODULE,
PERIPH_BT_BASEBAND_MODULE,
PERIPH_BT_LC_MODULE,
} periph_module_t;
typedef enum {
ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/
ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
ETS_WIFI_PWR_INTR_SOURCE, /**< */
ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/
ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/
ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/
ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
ETS_RWBT_INTR_SOURCE, /**< interrupt of RWBT, level*/
ETS_RWBLE_INTR_SOURCE, /**< interrupt of RWBLE, level*/
ETS_RWBT_NMI_SOURCE, /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
ETS_RWBLE_NMI_SOURCE, /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
ETS_SLC0_INTR_SOURCE, /**< interrupt of SLC0, level*/
ETS_SLC1_INTR_SOURCE, /**< interrupt of SLC1, level*/
ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/
ETS_UHCI1_INTR_SOURCE, /**< interrupt of UHCI1, level*/
ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/
ETS_TG0_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/
ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCHDOG, level*/
ETS_TG0_LACT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, level*/
ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/
ETS_TG1_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/
ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
ETS_TG1_LACT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, LACT, level*/
ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/
ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/
ETS_GPIO_INTR_SOURCE2, /**< interrupt of GPIO, level*/
ETS_GPIO_NMI_SOURCE2, /**< interrupt of GPIO, NMI*/
ETS_DEDICATED_GPIO_INTR_SOURCE, /**< interrupt of dedicated GPIO, level*/
ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
ETS_SPI1_INTR_SOURCE = 32, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/
ETS_SPI3_INTR_SOURCE, /**< interrupt of SPI3, level*/
ETS_I2S0_INTR_SOURCE, /**< interrupt of I2S0, level*/
ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/
ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/
ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/
ETS_UART2_INTR_SOURCE, /**< interrupt of UART2, level*/
ETS_SDIO_HOST_INTR_SOURCE, /**< interrupt of SD/SDIO/MMC HOST, level*/
ETS_PWM0_INTR_SOURCE, /**< interrupt of PWM0, level, Reserved*/
ETS_PWM1_INTR_SOURCE, /**< interrupt of PWM1, level, Reserved*/
ETS_PWM2_INTR_SOURCE, /**< interrupt of PWM2, level*/
ETS_PWM3_INTR_SOURCE, /**< interruot of PWM3, level*/
ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/
ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/
ETS_CAN_INTR_SOURCE , /**< interrupt of can, level*/
ETS_USB_INTR_SOURCE = 48, /**< interrupt of USB, level*/
ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/
ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/
ETS_PCNT_INTR_SOURCE, /**< interrupt of pluse count, level*/
ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/
ETS_I2C_EXT1_INTR_SOURCE, /**< interrupt of I2C controller0, level*/
ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/
ETS_SPI1_DMA_INTR_SOURCE, /**< interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this*/
ETS_SPI2_DMA_INTR_SOURCE, /**< interrupt of SPI2 DMA, level*/
ETS_SPI3_DMA_INTR_SOURCE, /**< interrupt of SPI3 DMA, level*/
ETS_WDT_INTR_SOURCE, /**< will be cancelled*/
ETS_TIMER1_INTR_SOURCE, /**< will be cancelled*/
ETS_TIMER2_INTR_SOURCE, /**< will be cancelled*/
ETS_TG0_T0_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/
ETS_TG0_T1_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/
ETS_TG0_WDT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/
ETS_TG0_LACT_EDGE_INTR_SOURCE = 64, /**< interrupt of TIMER_GROUP0, LACT, EDGE*/
ETS_TG1_T0_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/
ETS_TG1_T1_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/
ETS_TG1_WDT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/
ETS_TG1_LACT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, EDGE*/
ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/
ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/
ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/
ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/
ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/
ETS_PMS_PRO_IRAM0_ILG_INTR_SOURCE, /**< interrupt of illegal IRAM1 access, LEVEL*/
ETS_PMS_PRO_DRAM0_ILG_INTR_SOURCE, /**< interrupt of illegal DRAM0 access, LEVEL*/
ETS_PMS_PRO_DPORT_ILG_INTR_SOURCE, /**< interrupt of illegal DPORT access, LEVEL*/
ETS_PMS_PRO_AHB_ILG_INTR_SOURCE, /**< interrupt of illegal AHB access, LEVEL*/
ETS_PMS_PRO_CACHE_ILG_INTR_SOURCE, /**< interrupt of illegal CACHE access, LEVEL*/
ETS_PMS_DMA_APB_I_ILG_INTR_SOURCE, /**< interrupt of illegal APB access, LEVEL*/
ETS_PMS_DMA_RX_I_ILG_INTR_SOURCE = 80, /**< interrupt of illegal DMA RX access, LEVEL*/
ETS_PMS_DMA_TX_I_ILG_INTR_SOURCE, /**< interrupt of illegal DMA TX access, LEVEL*/
ETS_SPI0_REJECT_CACHE_INTR_SOURCE, /**< interrupt of SPI0 Cache access rejected, LEVEL*/
ETS_SPI1_REJECT_CPU_INTR_SOURCE, /**< interrupt of SPI1 access rejected, LEVEL*/
ETS_DMA_COPY_INTR_SOURCE, /**< interrupt of DMA copy, LEVEL*/
ETS_SPI4_DMA_INTR_SOURCE, /**< interrupt of SPI4 DMA, LEVEL*/
ETS_SPI4_INTR_SOURCE, /**< interrupt of SPI4, LEVEL*/
ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */
} periph_interrput_t;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_PERIPH_DEFS_H_ */

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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_RMT_STRUCT_H_
#define _SOC_RMT_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access.*/
struct{
union {
struct {
uint32_t div_cnt: 8; /*This register is used to configure the frequency divider's factor in channel0-7.*/
uint32_t idle_thres: 16; /*In receive mode when no edge is detected on the input signal for longer than reg_idle_thres_ch0 then the receive process is done.*/
uint32_t mem_size: 4; /*This register is used to configure the the amount of memory blocks allocated to channel0-7.*/
uint32_t carrier_en: 1; /*This is the carrier modulation enable control bit for channel0-7.*/
uint32_t carrier_out_lv: 1; /*This bit is used to configure the way carrier wave is modulated for channel0-7.1'b1:transmit on low output level 1'b0:transmit on high output level.*/
uint32_t mem_pd: 1; /*This bit is used to reduce power consumed by memory. 1:memory is in low power state.*/
uint32_t clk_en: 1; /*This bit is used to control clock.when software configure RMT internal registers it controls the register clock.*/
};
uint32_t val;
} conf0;
union {
struct {
uint32_t tx_start: 1; /*Set this bit to start sending data for channel0-7.*/
uint32_t rx_en: 1; /*Set this bit to enable receiving data for channel0-7.*/
uint32_t mem_wr_rst: 1; /*Set this bit to reset write ram address for channel0-7 by receiver access.*/
uint32_t mem_rd_rst: 1; /*Set this bit to reset read ram address for channel0-7 by transmitter access.*/
uint32_t apb_mem_rst: 1; /*Set this bit to reset W/R ram address for channel0-7 by apb fifo access*/
uint32_t mem_owner: 1; /*This is the mark of channel0-7's ram usage right.1'b1：receiver uses the ram 0：transmitter uses the ram*/
uint32_t tx_conti_mode: 1; /*Set this bit to continue sending from the first data to the last data in channel0-7 again and again.*/
uint32_t rx_filter_en: 1; /*This is the receive filter enable bit for channel0-7.*/
uint32_t rx_filter_thres: 8; /*in receive mode channel0-7 ignore input pulse when the pulse width is smaller then this value.*/
uint32_t reserved16: 1;
uint32_t ref_always_on: 1; /*This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/
uint32_t idle_out_lv: 1; /*This bit configures the output signal's level for channel0-7 in IDLE state.*/
uint32_t idle_out_en: 1; /*This is the output enable control bit for channel0-7 in IDLE state.*/
uint32_t tx_stop: 1;
uint32_t reserved21: 11;
};
uint32_t val;
} conf1;
} conf_ch[8];
union {
struct {
uint32_t mem_waddr_ex: 10;
uint32_t mem_raddr_ex: 10;
uint32_t state: 3;
uint32_t mem_owner_err: 1;
uint32_t mem_full: 1;
uint32_t mem_empty: 1;
uint32_t apb_mem_wr_err: 1;
uint32_t apb_mem_rd_err: 1;
uint32_t reserved28: 4;
};
uint32_t val;
} status_ch[8];
union {
struct {
uint32_t waddr: 10;
uint32_t raddr: 10;
uint32_t reserved20: 12;
};
uint32_t val;
} apb_mem_addr_ch[8];
union {
struct {
uint32_t ch0_tx_end: 1; /*The interrupt raw bit for channel 0 turns to high level when the transmit process is done.*/
uint32_t ch0_rx_end: 1; /*The interrupt raw bit for channel 0 turns to high level when the receive process is done.*/
uint32_t ch0_err: 1; /*The interrupt raw bit for channel 0 turns to high level when channel 0 detects some errors.*/
uint32_t ch1_tx_end: 1; /*The interrupt raw bit for channel 1 turns to high level when the transmit process is done.*/
uint32_t ch1_rx_end: 1; /*The interrupt raw bit for channel 1 turns to high level when the receive process is done.*/
uint32_t ch1_err: 1; /*The interrupt raw bit for channel 1 turns to high level when channel 1 detects some errors.*/
uint32_t ch2_tx_end: 1; /*The interrupt raw bit for channel 2 turns to high level when the transmit process is done.*/
uint32_t ch2_rx_end: 1; /*The interrupt raw bit for channel 2 turns to high level when the receive process is done.*/
uint32_t ch2_err: 1; /*The interrupt raw bit for channel 2 turns to high level when channel 2 detects some errors.*/
uint32_t ch3_tx_end: 1; /*The interrupt raw bit for channel 3 turns to high level when the transmit process is done.*/
uint32_t ch3_rx_end: 1; /*The interrupt raw bit for channel 3 turns to high level when the receive process is done.*/
uint32_t ch3_err: 1; /*The interrupt raw bit for channel 3 turns to high level when channel 3 detects some errors.*/
uint32_t ch4_tx_end: 1; /*The interrupt raw bit for channel 4 turns to high level when the transmit process is done.*/
uint32_t ch4_rx_end: 1; /*The interrupt raw bit for channel 4 turns to high level when the receive process is done.*/
uint32_t ch4_err: 1; /*The interrupt raw bit for channel 4 turns to high level when channel 4 detects some errors.*/
uint32_t ch5_tx_end: 1; /*The interrupt raw bit for channel 5 turns to high level when the transmit process is done.*/
uint32_t ch5_rx_end: 1; /*The interrupt raw bit for channel 5 turns to high level when the receive process is done.*/
uint32_t ch5_err: 1; /*The interrupt raw bit for channel 5 turns to high level when channel 5 detects some errors.*/
uint32_t ch6_tx_end: 1; /*The interrupt raw bit for channel 6 turns to high level when the transmit process is done.*/
uint32_t ch6_rx_end: 1; /*The interrupt raw bit for channel 6 turns to high level when the receive process is done.*/
uint32_t ch6_err: 1; /*The interrupt raw bit for channel 6 turns to high level when channel 6 detects some errors.*/
uint32_t ch7_tx_end: 1; /*The interrupt raw bit for channel 7 turns to high level when the transmit process is done.*/
uint32_t ch7_rx_end: 1; /*The interrupt raw bit for channel 7 turns to high level when the receive process is done.*/
uint32_t ch7_err: 1; /*The interrupt raw bit for channel 7 turns to high level when channel 7 detects some errors.*/
uint32_t ch0_tx_thr_event: 1; /*The interrupt raw bit for channel 0 turns to high level when transmitter in channel0 have send data more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old data with new data.*/
uint32_t ch1_tx_thr_event: 1; /*The interrupt raw bit for channel 1 turns to high level when transmitter in channel1 have send data more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old data with new data.*/
uint32_t ch2_tx_thr_event: 1; /*The interrupt raw bit for channel 2 turns to high level when transmitter in channel2 have send data more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old data with new data.*/
uint32_t ch3_tx_thr_event: 1; /*The interrupt raw bit for channel 3 turns to high level when transmitter in channel3 have send data more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old data with new data.*/
uint32_t ch4_tx_thr_event: 1; /*The interrupt raw bit for channel 4 turns to high level when transmitter in channel4 have send data more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old data with new data.*/
uint32_t ch5_tx_thr_event: 1; /*The interrupt raw bit for channel 5 turns to high level when transmitter in channel5 have send data more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old data with new data.*/
uint32_t ch6_tx_thr_event: 1; /*The interrupt raw bit for channel 6 turns to high level when transmitter in channel6 have send data more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old data with new data.*/
uint32_t ch7_tx_thr_event: 1; /*The interrupt raw bit for channel 7 turns to high level when transmitter in channel7 have send data more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old data with new data.*/
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t ch0_tx_end: 1; /*The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0.*/
uint32_t ch0_rx_end: 1; /*The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw when rmt_ch0_rx_end_int_ena is set to 0.*/
uint32_t ch0_err: 1; /*The interrupt state bit for channel 0's rmt_ch0_err_int_raw when rmt_ch0_err_int_ena is set to 0.*/
uint32_t ch1_tx_end: 1; /*The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw when mt_ch1_tx_end_int_ena is set to 1.*/
uint32_t ch1_rx_end: 1; /*The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw when rmt_ch1_rx_end_int_ena is set to 1.*/
uint32_t ch1_err: 1; /*The interrupt state bit for channel 1's rmt_ch1_err_int_raw when rmt_ch1_err_int_ena is set to 1.*/
uint32_t ch2_tx_end: 1; /*The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw when mt_ch2_tx_end_int_ena is set to 1.*/
uint32_t ch2_rx_end: 1; /*The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw when rmt_ch2_rx_end_int_ena is set to 1.*/
uint32_t ch2_err: 1; /*The interrupt state bit for channel 2's rmt_ch2_err_int_raw when rmt_ch2_err_int_ena is set to 1.*/
uint32_t ch3_tx_end: 1; /*The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw when mt_ch3_tx_end_int_ena is set to 1.*/
uint32_t ch3_rx_end: 1; /*The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw when rmt_ch3_rx_end_int_ena is set to 1.*/
uint32_t ch3_err: 1; /*The interrupt state bit for channel 3's rmt_ch3_err_int_raw when rmt_ch3_err_int_ena is set to 1.*/
uint32_t ch4_tx_end: 1; /*The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw when mt_ch4_tx_end_int_ena is set to 1.*/
uint32_t ch4_rx_end: 1; /*The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw when rmt_ch4_rx_end_int_ena is set to 1.*/
uint32_t ch4_err: 1; /*The interrupt state bit for channel 4's rmt_ch4_err_int_raw when rmt_ch4_err_int_ena is set to 1.*/
uint32_t ch5_tx_end: 1; /*The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw when mt_ch5_tx_end_int_ena is set to 1.*/
uint32_t ch5_rx_end: 1; /*The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw when rmt_ch5_rx_end_int_ena is set to 1.*/
uint32_t ch5_err: 1; /*The interrupt state bit for channel 5's rmt_ch5_err_int_raw when rmt_ch5_err_int_ena is set to 1.*/
uint32_t ch6_tx_end: 1; /*The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw when mt_ch6_tx_end_int_ena is set to 1.*/
uint32_t ch6_rx_end: 1; /*The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw when rmt_ch6_rx_end_int_ena is set to 1.*/
uint32_t ch6_err: 1; /*The interrupt state bit for channel 6's rmt_ch6_err_int_raw when rmt_ch6_err_int_ena is set to 1.*/
uint32_t ch7_tx_end: 1; /*The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw when mt_ch7_tx_end_int_ena is set to 1.*/
uint32_t ch7_rx_end: 1; /*The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw when rmt_ch7_rx_end_int_ena is set to 1.*/
uint32_t ch7_err: 1; /*The interrupt state bit for channel 7's rmt_ch7_err_int_raw when rmt_ch7_err_int_ena is set to 1.*/
uint32_t ch0_tx_thr_event: 1; /*The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw when mt_ch0_tx_thr_event_int_ena is set to 1.*/
uint32_t ch1_tx_thr_event: 1; /*The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw when mt_ch1_tx_thr_event_int_ena is set to 1.*/
uint32_t ch2_tx_thr_event: 1; /*The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw when mt_ch2_tx_thr_event_int_ena is set to 1.*/
uint32_t ch3_tx_thr_event: 1; /*The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw when mt_ch3_tx_thr_event_int_ena is set to 1.*/
uint32_t ch4_tx_thr_event: 1; /*The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw when mt_ch4_tx_thr_event_int_ena is set to 1.*/
uint32_t ch5_tx_thr_event: 1; /*The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw when mt_ch5_tx_thr_event_int_ena is set to 1.*/
uint32_t ch6_tx_thr_event: 1; /*The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw when mt_ch6_tx_thr_event_int_ena is set to 1.*/
uint32_t ch7_tx_thr_event: 1; /*The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw when mt_ch7_tx_thr_event_int_ena is set to 1.*/
};
uint32_t val;
} int_st;
union {
struct {
uint32_t ch0_tx_end: 1; /*Set this bit to enable rmt_ch0_tx_end_int_st.*/
uint32_t ch0_rx_end: 1; /*Set this bit to enable rmt_ch0_rx_end_int_st.*/
uint32_t ch0_err: 1; /*Set this bit to enable rmt_ch0_err_int_st.*/
uint32_t ch1_tx_end: 1; /*Set this bit to enable rmt_ch1_tx_end_int_st.*/
uint32_t ch1_rx_end: 1; /*Set this bit to enable rmt_ch1_rx_end_int_st.*/
uint32_t ch1_err: 1; /*Set this bit to enable rmt_ch1_err_int_st.*/
uint32_t ch2_tx_end: 1; /*Set this bit to enable rmt_ch2_tx_end_int_st.*/
uint32_t ch2_rx_end: 1; /*Set this bit to enable rmt_ch2_rx_end_int_st.*/
uint32_t ch2_err: 1; /*Set this bit to enable rmt_ch2_err_int_st.*/
uint32_t ch3_tx_end: 1; /*Set this bit to enable rmt_ch3_tx_end_int_st.*/
uint32_t ch3_rx_end: 1; /*Set this bit to enable rmt_ch3_rx_end_int_st.*/
uint32_t ch3_err: 1; /*Set this bit to enable rmt_ch3_err_int_st.*/
uint32_t ch4_tx_end: 1; /*Set this bit to enable rmt_ch4_tx_end_int_st.*/
uint32_t ch4_rx_end: 1; /*Set this bit to enable rmt_ch4_rx_end_int_st.*/
uint32_t ch4_err: 1; /*Set this bit to enable rmt_ch4_err_int_st.*/
uint32_t ch5_tx_end: 1; /*Set this bit to enable rmt_ch5_tx_end_int_st.*/
uint32_t ch5_rx_end: 1; /*Set this bit to enable rmt_ch5_rx_end_int_st.*/
uint32_t ch5_err: 1; /*Set this bit to enable rmt_ch5_err_int_st.*/
uint32_t ch6_tx_end: 1; /*Set this bit to enable rmt_ch6_tx_end_int_st.*/
uint32_t ch6_rx_end: 1; /*Set this bit to enable rmt_ch6_rx_end_int_st.*/
uint32_t ch6_err: 1; /*Set this bit to enable rmt_ch6_err_int_st.*/
uint32_t ch7_tx_end: 1; /*Set this bit to enable rmt_ch7_tx_end_int_st.*/
uint32_t ch7_rx_end: 1; /*Set this bit to enable rmt_ch7_rx_end_int_st.*/
uint32_t ch7_err: 1; /*Set this bit to enable rmt_ch7_err_int_st.*/
uint32_t ch0_tx_thr_event: 1; /*Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/
uint32_t ch1_tx_thr_event: 1; /*Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/
uint32_t ch2_tx_thr_event: 1; /*Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/
uint32_t ch3_tx_thr_event: 1; /*Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/
uint32_t ch4_tx_thr_event: 1; /*Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/
uint32_t ch5_tx_thr_event: 1; /*Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/
uint32_t ch6_tx_thr_event: 1; /*Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/
uint32_t ch7_tx_thr_event: 1; /*Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t ch0_tx_end: 1; /*Set this bit to clear the rmt_ch0_rx_end_int_raw..*/
uint32_t ch0_rx_end: 1; /*Set this bit to clear the rmt_ch0_tx_end_int_raw.*/
uint32_t ch0_err: 1; /*Set this bit to clear the rmt_ch0_err_int_raw.*/
uint32_t ch1_tx_end: 1; /*Set this bit to clear the rmt_ch1_rx_end_int_raw..*/
uint32_t ch1_rx_end: 1; /*Set this bit to clear the rmt_ch1_tx_end_int_raw.*/
uint32_t ch1_err: 1; /*Set this bit to clear the rmt_ch1_err_int_raw.*/
uint32_t ch2_tx_end: 1; /*Set this bit to clear the rmt_ch2_rx_end_int_raw..*/
uint32_t ch2_rx_end: 1; /*Set this bit to clear the rmt_ch2_tx_end_int_raw.*/
uint32_t ch2_err: 1; /*Set this bit to clear the rmt_ch2_err_int_raw.*/
uint32_t ch3_tx_end: 1; /*Set this bit to clear the rmt_ch3_rx_end_int_raw..*/
uint32_t ch3_rx_end: 1; /*Set this bit to clear the rmt_ch3_tx_end_int_raw.*/
uint32_t ch3_err: 1; /*Set this bit to clear the rmt_ch3_err_int_raw.*/
uint32_t ch4_tx_end: 1; /*Set this bit to clear the rmt_ch4_rx_end_int_raw..*/
uint32_t ch4_rx_end: 1; /*Set this bit to clear the rmt_ch4_tx_end_int_raw.*/
uint32_t ch4_err: 1; /*Set this bit to clear the rmt_ch4_err_int_raw.*/
uint32_t ch5_tx_end: 1; /*Set this bit to clear the rmt_ch5_rx_end_int_raw..*/
uint32_t ch5_rx_end: 1; /*Set this bit to clear the rmt_ch5_tx_end_int_raw.*/
uint32_t ch5_err: 1; /*Set this bit to clear the rmt_ch5_err_int_raw.*/
uint32_t ch6_tx_end: 1; /*Set this bit to clear the rmt_ch6_rx_end_int_raw..*/
uint32_t ch6_rx_end: 1; /*Set this bit to clear the rmt_ch6_tx_end_int_raw.*/
uint32_t ch6_err: 1; /*Set this bit to clear the rmt_ch6_err_int_raw.*/
uint32_t ch7_tx_end: 1; /*Set this bit to clear the rmt_ch7_rx_end_int_raw..*/
uint32_t ch7_rx_end: 1; /*Set this bit to clear the rmt_ch7_tx_end_int_raw.*/
uint32_t ch7_err: 1; /*Set this bit to clear the rmt_ch7_err_int_raw.*/
uint32_t ch0_tx_thr_event: 1; /*Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/
uint32_t ch1_tx_thr_event: 1; /*Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/
uint32_t ch2_tx_thr_event: 1; /*Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/
uint32_t ch3_tx_thr_event: 1; /*Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/
uint32_t ch4_tx_thr_event: 1; /*Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/
uint32_t ch5_tx_thr_event: 1; /*Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/
uint32_t ch6_tx_thr_event: 1; /*Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/
uint32_t ch7_tx_thr_event: 1; /*Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t low: 16; /*This register is used to configure carrier wave's low level value for channel0-7.*/
uint32_t high:16; /*This register is used to configure carrier wave's high level value for channel0-7.*/
};
uint32_t val;
} carrier_duty_ch[8];
union {
struct {
uint32_t limit: 9;
uint32_t tx_loop_num: 10;
uint32_t tx_loop_cnt_en: 1;
uint32_t reserved20: 12;
};
uint32_t val;
} tx_lim_ch[8];
union {
struct {
uint32_t fifo_mask: 1; /*Set this bit to disable apb fifo access*/
uint32_t mem_tx_wrap_en: 1; /*when data need to be send is more than channel's mem can store then set this bit to enable reuse of mem this bit is used together with reg_rmt_tx_lim_chn.*/
uint32_t reserved2: 30;
};
uint32_t val;
} apb_conf;
union {
struct {
uint32_t ch0: 1;
uint32_t ch1: 1;
uint32_t ch2: 1;
uint32_t ch3: 1;
uint32_t ch4: 1;
uint32_t ch5: 1;
uint32_t ch6: 1;
uint32_t ch7: 1;
uint32_t en: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} tx_sim;
union {
struct {
uint32_t ch0: 1;
uint32_t ch1: 1;
uint32_t ch2: 1;
uint32_t ch3: 1;
uint32_t ch4: 1;
uint32_t ch5: 1;
uint32_t ch6: 1;
uint32_t ch7: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} ref_cnt_rst;
union {
struct {
uint32_t ch0_tx_loop: 1;
uint32_t ch1_tx_loop: 1;
uint32_t ch2_tx_loop: 1;
uint32_t ch3_tx_loop: 1;
uint32_t ch4_tx_loop: 1;
uint32_t ch5_tx_loop: 1;
uint32_t ch6_tx_loop: 1;
uint32_t ch7_tx_loop: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} int1_raw;
union {
struct {
uint32_t ch0_tx_loop: 1;
uint32_t ch1_tx_loop: 1;
uint32_t ch2_tx_loop: 1;
uint32_t ch3_tx_loop: 1;
uint32_t ch4_tx_loop: 1;
uint32_t ch5_tx_loop: 1;
uint32_t ch6_tx_loop: 1;
uint32_t ch7_tx_loop: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} int1_st;
union {
struct {
uint32_t ch0_tx_loop: 1;
uint32_t ch1_tx_loop: 1;
uint32_t ch2_tx_loop: 1;
uint32_t ch3_tx_loop: 1;
uint32_t ch4_tx_loop: 1;
uint32_t ch5_tx_loop: 1;
uint32_t ch6_tx_loop: 1;
uint32_t ch7_tx_loop: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} int1_ena;
union {
struct {
uint32_t ch0_tx_loop: 1;
uint32_t ch1_tx_loop: 1;
uint32_t ch2_tx_loop: 1;
uint32_t ch3_tx_loop: 1;
uint32_t ch4_tx_loop: 1;
uint32_t ch5_tx_loop: 1;
uint32_t ch6_tx_loop: 1;
uint32_t ch7_tx_loop: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} int1_clr;
uint32_t date; /**/
} rmt_dev_t;
extern rmt_dev_t RMT;
typedef struct {
union {
struct {
uint32_t duration0 :15;
uint32_t level0 :1;
uint32_t duration1 :15;
uint32_t level1 :1;
};
uint32_t val;
};
} rmt_item32_t;
typedef struct {
union {
struct {
uint16_t duration :15;
uint16_t level :1;
};
uint16_t val;
};
} rmt_item16_t;
//Allow access to RMT memory using RMTMEM.chan[0].data32[8]
typedef volatile struct {
struct {
union {
rmt_item32_t data32[64];
rmt_item16_t data16[128];
};
} chan[8];
} rmt_mem_t;
extern rmt_mem_t RMTMEM;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_RMT_STRUCT_H_ */

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// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @file rtc.h
* @brief Low-level RTC power, clock, and sleep functions.
*
* Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral.
* RTC_CNTL peripheral handles many functions:
* - enables/disables clocks and power to various parts of the chip; this is
* done using direct register access (forcing power up or power down) or by
* allowing state machines to control power and clocks automatically
* - handles sleep and wakeup functions
* - maintains a 48-bit counter which can be used for timekeeping
*
* These functions are not thread safe, and should not be viewed as high level
* APIs. For example, while this file provides a function which can switch
* CPU frequency, this function is on its own is not sufficient to implement
* frequency switching in ESP-IDF context: some coordination with RTOS,
* peripheral drivers, and WiFi/BT stacks is also required.
*
* These functions will normally not be used in applications directly.
* ESP-IDF provides, or will provide, drivers and other facilities to use
* RTC subsystem functionality.
*
* The functions are loosely split into the following groups:
* - rtc_clk: clock switching, calibration
* - rtc_time: reading RTC counter, conversion between counter values and time
* - rtc_sleep: entry into sleep modes
* - rtc_init: initialization
*/
/**
* @brief Possible main XTAL frequency values.
*
* Enum values should be equal to frequency in MHz.
*/
typedef enum {
RTC_XTAL_FREQ_AUTO = 0, //!< Automatic XTAL frequency detection
RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
RTC_XTAL_FREQ_26M = 26, //!< 26 MHz XTAL
RTC_XTAL_FREQ_24M = 24, //!< 24 MHz XTAL
} rtc_xtal_freq_t;
/**
* @brief CPU frequency values
*/
typedef enum {
RTC_CPU_FREQ_XTAL = 0, //!< Main XTAL frequency
RTC_CPU_FREQ_80M = 1, //!< 80 MHz
RTC_CPU_FREQ_160M = 2, //!< 160 MHz
RTC_CPU_FREQ_240M = 3, //!< 240 MHz
RTC_CPU_FREQ_2M = 4, //!< 2 MHz
RTC_CPU_320M_80M = 5, //!< for test
RTC_CPU_320M_160M = 6, //!< for test
} rtc_cpu_freq_t;
/**
* @brief RTC SLOW_CLK frequency values
*/
typedef enum {
RTC_SLOW_FREQ_RTC = 0, //!< Internal 150 kHz RC oscillator
RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL
RTC_SLOW_FREQ_8MD256 = 2, //!< Internal 8 MHz RC oscillator, divided by 256
} rtc_slow_freq_t;
/**
* @brief RTC FAST_CLK frequency values
*/
typedef enum {
RTC_FAST_FREQ_XTALD4 = 0, //!< Main XTAL, divided by 4
RTC_FAST_FREQ_8M = 1, //!< Internal 8 MHz RC oscillator
} rtc_fast_freq_t;
/* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */
#define RTC_FAST_CLK_FREQ_APPROX 8500000
/**
* @brief Clock source to be calibrated using rtc_clk_cal function
*/
typedef enum {
RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK
RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256
RTC_CAL_32K_XTAL = 2 //!< External 32 kHz XTAL
} rtc_cal_sel_t;
/**
* Initialization parameters for rtc_clk_init
*/
typedef struct {
rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
rtc_cpu_freq_t cpu_freq : 3; //!< CPU frequency to set
rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set
rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set
uint32_t clk_rtc_clk_div : 8;
uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency)
uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
} rtc_clk_config_t;
/**
* Default initializer for rtc_clk_config_t
*/
#define RTC_CLK_CONFIG_DEFAULT() { \
.xtal_freq = RTC_XTAL_FREQ_AUTO, \
.cpu_freq = RTC_CPU_FREQ_80M, \
.fast_freq = RTC_FAST_FREQ_8M, \
.slow_freq = RTC_SLOW_FREQ_RTC, \
.clk_rtc_clk_div = 0, \
.clk_8m_clk_div = 0, \
.slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
.clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
}
void rtc_clk_divider_set(uint32_t div);
void rtc_clk_8m_divider_set(uint32_t div);
/**
* Initialize clocks and set CPU frequency
*
* If cfg.xtal_freq is set to RTC_XTAL_FREQ_AUTO, this function will attempt
* to auto detect XTAL frequency. Auto detection is performed by comparing
* XTAL frequency with the frequency of internal 8MHz oscillator. Note that at
* high temperatures the frequency of the internal 8MHz oscillator may drift
* enough for auto detection to be unreliable.
* Auto detection code will attempt to distinguish between 26MHz and 40MHz
* crystals. 24 MHz crystals are not supported by auto detection code.
* If XTAL frequency can not be auto detected, this 26MHz frequency will be used.
*
* @param cfg clock configuration as rtc_clk_config_t
*/
void rtc_clk_init(rtc_clk_config_t cfg);
/**
* @brief Get main XTAL frequency
*
* This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
* rtc_clk_init function, or if the value was RTC_XTAL_FREQ_AUTO, the detected
* XTAL frequency.
*
* @return XTAL frequency, one of rtc_xtal_freq_t
*/
rtc_xtal_freq_t rtc_clk_xtal_freq_get();
/**
* @brief Update XTAL frequency
*
* Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored
* after startup.
*
* @param xtal_freq New frequency value
*/
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
/**
* @brief Enable or disable 32 kHz XTAL oscillator
* @param en true to enable, false to disable
*/
void rtc_clk_32k_enable(bool en);
/**
* @brief Get the state of 32k XTAL oscillator
* @return true if 32k XTAL oscillator has been enabled
*/
bool rtc_clk_32k_enabled();
/**
* @brief Enable 32k oscillator, configuring it for fast startup time.
* Note: to achieve higher frequency stability, rtc_clk_32k_enable function
* must be called one the 32k XTAL oscillator has started up. This function
* will initially disable the 32k XTAL oscillator, so it should not be called
* when the system is using 32k XTAL as RTC_SLOW_CLK.
*
* @param cycle Number of 32kHz cycles to bootstrap external crystal.
* If 0, no square wave will be used to bootstrap crystal oscillation.
*/
void rtc_clk_32k_bootstrap(uint32_t cycle);
/**
* @brief Enable or disable 8 MHz internal oscillator
*
* Output from 8 MHz internal oscillator is passed into a configurable
* divider, which by default divides the input clock frequency by 256.
* Output of the divider may be used as RTC_SLOW_CLK source.
* Output of the divider is referred to in register descriptions and code as
* 8md256 or simply d256. Divider values other than 256 may be configured, but
* this facility is not currently needed, so is not exposed in the code.
*
* When 8MHz/256 divided output is not needed, the divider should be disabled
* to reduce power consumption.
*
* @param clk_8m_en true to enable 8MHz generator
* @param d256_en true to enable /256 divider
*/
void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en);
/**
* @brief Get the state of 8 MHz internal oscillator
* @return true if the oscillator is enabled
*/
bool rtc_clk_8m_enabled();
/**
* @brief Get the state of /256 divider which is applied to 8MHz clock
* @return true if the divided output is enabled
*/
bool rtc_clk_8md256_enabled();
/**
* @brief Enable or disable APLL
*
* Output frequency is given by the formula:
* apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2)
*
* The dividend in this expression should be in the range of 240 - 600 MHz.
*
* In rev. 0 of ESP32, sdm0 and sdm1 are unused and always set to 0.
*
* @param enable true to enable, false to disable
* @param sdm0 frequency adjustment parameter, 0..255
* @param sdm1 frequency adjustment parameter, 0..255
* @param sdm2 frequency adjustment parameter, 0..63
* @param o_div frequency divider, 0..31
*/
void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div);
/**
* @brief Select source for RTC_SLOW_CLK
* @param slow_freq clock source (one of rtc_slow_freq_t values)
*/
void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq);
/**
* @brief Get the RTC_SLOW_CLK source
* @return currently selected clock source (one of rtc_slow_freq_t values)
*/
rtc_slow_freq_t rtc_clk_slow_freq_get();
/**
* @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz
*
* - if RTC_SLOW_FREQ_RTC is selected, returns ~150000
* - if RTC_SLOW_FREQ_32K_XTAL is selected, returns 32768
* - if RTC_SLOW_FREQ_8MD256 is selected, returns ~33000
*
* rtc_clk_cal function can be used to get more precise value by comparing
* RTC_SLOW_CLK frequency to the frequency of main XTAL.
*
* @return RTC_SLOW_CLK frequency, in Hz
*/
uint32_t rtc_clk_slow_freq_get_hz();
/**
* @brief Select source for RTC_FAST_CLK
* @param fast_freq clock source (one of rtc_fast_freq_t values)
*/
void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq);
/**
* @brief Get the RTC_FAST_CLK source
* @return currently selected clock source (one of rtc_fast_freq_t values)
*/
rtc_fast_freq_t rtc_clk_fast_freq_get();
/**
* @brief Switch CPU frequency
*
* If a PLL-derived frequency is requested (80, 160, 240 MHz), this function
* will enable the PLL. Otherwise, PLL will be disabled.
* Note: this function is not optimized for switching speed. It may take several
* hundred microseconds to perform frequency switch.
*
* @param cpu_freq new CPU frequency
*/
void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq);
/**
* @brief Switch CPU frequency
*
* This is a faster version of rtc_clk_cpu_freq_set, which can handle some of
* the frequency switch paths (XTAL -> PLL, PLL -> XTAL).
* When switching from PLL to XTAL, PLL is not disabled (unlike rtc_clk_cpu_freq_set).
* When switching back from XTAL to PLL, only the same PLL can be used.
* Therefore it is not possible to switch 240 -> XTAL -> (80 or 160) using this
* function.
*
* For unsupported cases, this function falls back to rtc_clk_cpu_freq_set.
*
* Unlike rtc_clk_cpu_freq_set, this function relies on static data, so it is
* less safe to use it e.g. from a panic handler (when memory might be corrupted).
*
* @param cpu_freq new CPU frequency
*/
void rtc_clk_cpu_freq_set_fast(rtc_cpu_freq_t cpu_freq);
/**
* @brief Get the currently selected CPU frequency
*
* Although CPU can be clocked by APLL and RTC 8M sources, such support is not
* exposed through this library. As such, this function will not return
* meaningful values when these clock sources are configured (e.g. using direct
* access to clock selection registers). In debug builds, it will assert; in
* release builds, it will return RTC_CPU_FREQ_XTAL.
*
* @return CPU frequency (one of rtc_cpu_freq_t values)
*/
rtc_cpu_freq_t rtc_clk_cpu_freq_get();
/**
* @brief Get corresponding frequency value for rtc_cpu_freq_t enum value
* @param cpu_freq CPU frequency, on of rtc_cpu_freq_t values
* @return CPU frequency, in HZ
*/
uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq);
/**
* @brief Get rtc_cpu_freq_t enum value for given CPU frequency
* @param cpu_freq_mhz CPU frequency, one of 80, 160, 240, 2, and XTAL frequency
* @param[out] out_val output, rtc_cpu_freq_t value corresponding to the frequency
* @return true if the given frequency value matches one of enum values
*/
bool rtc_clk_cpu_freq_from_mhz(int cpu_freq_mhz, rtc_cpu_freq_t* out_val);
/**
* @brief Store new APB frequency value into RTC_APB_FREQ_REG
*
* This function doesn't change any hardware clocks.
*
* Functions which perform frequency switching and change APB frequency call
* this function to update the value of APB frequency stored in RTC_APB_FREQ_REG
* (one of RTC general purpose retention registers). This should not normally
* be called from application code.
*
* @param apb_freq new APB frequency, in Hz
*/
void rtc_clk_apb_freq_update(uint32_t apb_freq);
/**
* @brief Get the current stored APB frequency.
* @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz.
*/
uint32_t rtc_clk_apb_freq_get();
#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
/**
* @brief Measure RTC slow clock's period, based on main XTAL frequency
*
* This function will time out and return 0 if the time for the given number
* of cycles to be counted exceeds the expected time twice. This may happen if
* 32k XTAL is being calibrated, but the oscillator has not started up (due to
* incorrect loading capacitance, board design issue, or lack of 32 XTAL on board).
*
* @param cal_clk clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out
*/
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
/**
* @brief Measure ratio between XTAL frequency and RTC slow clock frequency
* @param cal_clk slow clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average
* @return average ratio between XTAL frequency and slow clock frequency,
* Q13.19 fixed point format, or 0 if calibration has timed out.
*/
uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
/**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles
* @param time_in_us Time interval in microseconds
* @param slow_clk_period Period of slow clock in microseconds, Q13.19
* fixed point format (as returned by rtc_slowck_cali).
* @return number of slow clock cycles
*/
uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period);
/**
* @brief Convert time interval from RTC_SLOW_CLK to microseconds
* @param time_in_us Time interval in RTC_SLOW_CLK cycles
* @param slow_clk_period Period of slow clock in microseconds, Q13.19
* fixed point format (as returned by rtc_slowck_cali).
* @return time interval in microseconds
*/
uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
/**
* @brief Get current value of RTC counter
*
* RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK
* cycles. Counter value is not writable by software. The value is not adjusted
* when switching to a different RTC_SLOW_CLK source.
*
* Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute
*
* @return current value of RTC counter
*/
uint64_t rtc_time_get();
uint64_t rtc_light_slp_time_get();
uint64_t rtc_deep_slp_time_get();
/**
* @brief Busy loop until next RTC_SLOW_CLK cycle
*
* This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
* In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
* one RTC_SLOW_CLK cycle later.
*/
void rtc_clk_wait_for_slow_cycle();
/**
* @brief Power down flags for rtc_sleep_pd function
*/
typedef struct {
uint32_t dig_fpu : 1; //!< Set to 1 to power down digital part in sleep
uint32_t rtc_fpu : 1; //!< Set to 1 to power down RTC memories in sleep
uint32_t cpu_fpu : 1; //!< Set to 1 to power down digital memories and CPU in sleep
uint32_t i2s_fpu : 1; //!< Set to 1 to power down I2S in sleep
uint32_t bb_fpu : 1; //!< Set to 1 to power down WiFi in sleep
uint32_t nrx_fpu : 1; //!< Set to 1 to power down WiFi in sleep
uint32_t fe_fpu : 1; //!< Set to 1 to power down WiFi in sleep
} rtc_sleep_pd_config_t;
/**
* Initializer for rtc_sleep_pd_config_t which sets all flags to the same value
*/
#define RTC_SLEEP_PD_CONFIG_ALL(val) {\
.dig_fpu = (val), \
.rtc_fpu = (val), \
.cpu_fpu = (val), \
.i2s_fpu = (val), \
.bb_fpu = (val), \
.nrx_fpu = (val), \
.fe_fpu = (val), \
}
void rtc_sleep_pd(rtc_sleep_pd_config_t cfg);
/**
* @brief sleep configuration for rtc_sleep_init function
*/
typedef struct {
uint32_t lslp_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (digital domain memory)
uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used)
uint32_t rtc_fastmem_pd_en : 1; //!< power down RTC fast memory
uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory
uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals
uint32_t wifi_pd_en : 1; //!< power down WiFi
uint32_t deep_slp : 1; //!< power down digital domain
uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode
uint32_t dig_dbias_wak : 3; //!< set bias for digital domain, in active mode
uint32_t dig_dbias_slp : 3; //!< set bias for digital domain, in sleep mode
uint32_t rtc_dbias_wak : 3; //!< set bias for RTC domain, in active mode
uint32_t rtc_dbias_slp : 3; //!< set bias for RTC domain, in sleep mode
uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator
uint32_t deep_slp_reject : 1;
uint32_t light_slp_reject : 1;
} rtc_sleep_config_t;
/**
* Default initializer for rtc_sleep_config_t
*
* This initializer sets all fields to "reasonable" values (e.g. suggested for
* production use) based on a combination of RTC_SLEEP_PD_x flags.
*
* @param RTC_SLEEP_PD_x flags combined using bitwise OR
*/
#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \
.lslp_mem_inf_fpu = 0, \
.rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \
.rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \
.rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \
.rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \
.wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \
.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
.wdt_flashboot_mod_en = 0, \
.dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \
.dig_dbias_slp = RTC_CNTL_DBIAS_0V90, \
.rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \
.rtc_dbias_slp = RTC_CNTL_DBIAS_0V90, \
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
.deep_slp_reject = 1, \
.light_slp_reject = 1 \
};
#define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain)
#define RTC_SLEEP_PD_RTC_PERIPH BIT(1) //!< Power down RTC peripherals
#define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory
#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) //!< Power down RTC FAST memory
#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU
#define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator
#define RTC_SLEEP_PD_WIFI BIT(6)
/**
* @brief Prepare the chip to enter sleep mode
*
* This function configures various power control state machines to handle
* entry into light sleep or deep sleep mode, switches APB and CPU clock source
* (usually to XTAL), and sets bias voltages for digital and RTC power domains.
*
* This function does not actually enter sleep mode; this is done using
* rtc_sleep_start function. Software may do some other actions between
* rtc_sleep_init and rtc_sleep_start, such as set wakeup timer and configure
* wakeup sources.
* @param cfg sleep mode configuration
*/
void rtc_sleep_init(rtc_sleep_config_t cfg);
/**
* @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source
* @param t value of RTC counter at which wakeup from sleep will happen;
* only the lower 48 bits are used
*/
void rtc_sleep_set_wakeup_time(uint64_t t);
#define RTC_EXT0_TRIG_EN BIT(0) //!< EXT0 GPIO wakeup
#define RTC_EXT1_TRIG_EN BIT(1) //!< EXT1 GPIO wakeup
#define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup (light sleep only)
#define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup
#define RTC_SDIO_TRIG_EN BIT(4) //!< SDIO wakeup (light sleep only)
#define RTC_MAC_TRIG_EN BIT(5) //!< MAC wakeup (light sleep only)
#define RTC_UART0_TRIG_EN BIT(6) //!< UART0 wakeup (light sleep only)
#define RTC_UART1_TRIG_EN BIT(7) //!< UART1 wakeup (light sleep only)
#define RTC_TOUCH_TRIG_EN BIT(8) //!< Touch wakeup
#define RTC_ULP_TRIG_EN BIT(9) //!< ULP wakeup
#define RTC_BT_TRIG_EN BIT(10) //!< BT wakeup (light sleep only)
#define RTC_COCPU_TRIG_EN BIT(11)
#define RTC_XTAL32K_DEAD_TRIG_EN BIT(12)
#define RTC_COCPU_TRAP_TRIG_EN BIT(13)
#define RTC_USB_TRIG_EN BIT(14)
/**
* @brief Enter deep or light sleep mode
*
* This function enters the sleep mode previously configured using rtc_sleep_init
* function. Before entering sleep, software should configure wake up sources
* appropriately (set up GPIO wakeup registers, timer wakeup registers,
* and so on).
*
* If deep sleep mode was configured using rtc_sleep_init, and sleep is not
* rejected by hardware (based on reject_opt flags), this function never returns.
* When the chip wakes up from deep sleep, CPU is reset and execution starts
* from ROM bootloader.
*
* If light sleep mode was configured using rtc_sleep_init, this function
* returns on wakeup, or if sleep is rejected by hardware.
*
* @param wakeup_opt bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags
* combined with OR)
* @param reject_opt bit mask of sleep reject reasons:
* - RTC_CNTL_GPIO_REJECT_EN
* - RTC_CNTL_SDIO_REJECT_EN
* These flags are used to prevent entering sleep when e.g.
* an external host is communicating via SDIO slave
* @return non-zero if sleep was rejected by hardware
*/
uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu);
/**
* RTC power and clock control initialization settings
*/
typedef struct {
uint32_t ck8m_wait : 8; //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready
uint32_t xtal_wait : 8; //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready
uint32_t pll_wait : 8; //!< Number of rtc_fast_clk cycles to wait for PLL to be ready
uint32_t clkctl_init : 1; //!< Perform clock control related initialization
uint32_t pwrctl_init : 1; //!< Perform power control related initialization
uint32_t rtc_dboost_fpd : 1; //!< Force power down RTC_DBOOST
uint32_t xtal_fpu : 1;
uint32_t bbpll_fpu : 1;
} rtc_config_t;
/**
* Default initializer of rtc_config_t.
*
* This initializer sets all fields to "reasonable" values (e.g. suggested for
* production use).
*/
#define RTC_CONFIG_DEFAULT() {\
.ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \
.xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \
.pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \
.clkctl_init = 1, \
.pwrctl_init = 1, \
.rtc_dboost_fpd = 1, \
.xtal_fpu = 0, \
.bbpll_fpu = 0 \
}
/**
* Initialize RTC clock and power control related functions
* @param cfg configuration options as rtc_config_t
*/
void rtc_init(rtc_config_t cfg);
#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
/**
* Structure describing vddsdio configuration
*/
typedef struct {
uint32_t force : 1; //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins.
uint32_t enable : 1; //!< Enable VDDSDIO regulator
uint32_t tieh : 1; //!< Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V
uint32_t drefh : 2; //!< Tuning parameter for VDDSDIO regulator
uint32_t drefm : 2; //!< Tuning parameter for VDDSDIO regulator
uint32_t drefl : 2; //!< Tuning parameter for VDDSDIO regulator
} rtc_vddsdio_config_t;
/**
* Get current VDDSDIO configuration
* If VDDSDIO configuration is overridden by RTC, get values from RTC
* Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE
* Otherwise, use default values and the level of MTDI bootstrapping pin.
* @return currently used VDDSDIO configuration
*/
rtc_vddsdio_config_t rtc_vddsdio_get_config();
/**
* Set new VDDSDIO configuration using RTC registers.
* If config.force == 1, this overrides configuration done using bootstrapping
* pins and EFUSE.
*
* @param config new VDDSDIO configuration
*/
void rtc_vddsdio_set_config(rtc_vddsdio_config_t config);
#ifdef __cplusplus
}
#endif

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_RTC_CNTL_STRUCT_H_
#define _SOC_RTC_CNTL_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
uint32_t sw_stall_procpu_c0: 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/
uint32_t sw_appcpu_rst: 1; /*APP CPU SW reset*/
uint32_t sw_procpu_rst: 1; /*PRO CPU SW reset*/
uint32_t bb_i2c_force_pd: 1; /*BB_I2C force power down*/
uint32_t bb_i2c_force_pu: 1; /*BB_I2C force power up*/
uint32_t bbpll_i2c_force_pd: 1; /*BB_PLL _I2C force power down*/
uint32_t bbpll_i2c_force_pu: 1; /*BB_PLL_I2C force power up*/
uint32_t bbpll_force_pd: 1; /*BB_PLL force power down*/
uint32_t bbpll_force_pu: 1; /*BB_PLL force power up*/
uint32_t xtl_force_pd: 1; /*crystall force power down*/
uint32_t xtl_force_pu: 1; /*crystall force power up*/
uint32_t bias_sleep_folw_8m: 1; /*BIAS_SLEEP follow CK8M*/
uint32_t bias_force_sleep: 1; /*BIAS_SLEEP force sleep*/
uint32_t bias_force_nosleep: 1; /*BIAS_SLEEP force no sleep*/
uint32_t bias_i2c_folw_8m: 1; /*BIAS_I2C follow CK8M*/
uint32_t bias_i2c_force_pd: 1; /*BIAS_I2C force power down*/
uint32_t bias_i2c_force_pu: 1; /*BIAS_I2C force power up*/
uint32_t bias_core_folw_8m: 1; /*BIAS_CORE follow CK8M*/
uint32_t bias_core_force_pd: 1; /*BIAS_CORE force power down*/
uint32_t bias_core_force_pu: 1; /*BIAS_CORE force power up*/
uint32_t xtl_force_iso: 1;
uint32_t pll_force_iso: 1;
uint32_t analog_force_iso: 1;
uint32_t xtl_force_noiso: 1;
uint32_t pll_force_noiso: 1;
uint32_t analog_force_noiso: 1;
uint32_t dg_wrap_force_rst: 1; /*digital wrap force reset in deep sleep*/
uint32_t dg_wrap_force_norst: 1; /*digital core force no reset in deep sleep*/
uint32_t sw_sys_rst: 1; /*SW system reset*/
};
uint32_t val;
} options0;
uint32_t slp_timer0; /*RTC sleep timer low 32 bits*/
union {
struct {
uint32_t slp_val_hi: 16; /*RTC sleep timer high 16 bits*/
uint32_t main_timer_alarm_en: 1; /*timer alarm enable bit*/
uint32_t reserved17: 15;
};
uint32_t val;
} slp_timer1;
union {
struct {
uint32_t reserved0: 30;
uint32_t valid: 1; /*To indicate the register is updated*/
uint32_t update: 1; /*Set 1: to update register with RTC timer*/
};
uint32_t val;
} time_update;
uint32_t time0; /*RTC timer low 32 bits*/
union {
struct {
uint32_t time_hi: 16; /*RTC timer high 16 bits*/
uint32_t reserved16: 16;
};
uint32_t val;
} time1;
union {
struct {
uint32_t reserved0: 18;
uint32_t cocpu_wakeup: 1; /*riscV cocpu wake up register*/
uint32_t cocpu_wakeup_force_en: 1; /*riscV cocpu force wake up*/
uint32_t touch_wakeup_force_en: 1; /*touch controller force wake up*/
uint32_t ulp_cp_wakeup_force_en: 1; /*ULP-coprocessor force wake up*/
uint32_t apb2rtc_bridge_sel: 1; /*1: APB to RTC using bridge 0: APB to RTC using sync*/
uint32_t touch_slp_timer_en: 1; /*touch timer enable bit*/
uint32_t ulp_cp_slp_timer_en: 1; /*ULP-coprocessor timer enable bit*/
uint32_t ulp_cp_gpio_wakeup_ena: 1; /*ULP-coprocessor wakeup by GPIO enable*/
uint32_t ulp_cp_gpio_wakeup_clr: 1; /*ULP-coprocessor wakeup by GPIO state clear*/
uint32_t reserved27: 1;
uint32_t sdio_active_ind: 1; /*SDIO active indication*/
uint32_t slp_wakeup: 1; /*leep wakeup bit*/
uint32_t slp_reject: 1; /*leep reject bit*/
uint32_t sleep_en: 1; /*sleep enable bit*/
};
uint32_t val;
} state0;
union {
struct {
uint32_t cpu_stall_en: 1; /*CPU stall enable bit*/
uint32_t cpu_stall_wait: 5; /*CPU stall wait cycles in fast_clk_rtc*/
uint32_t ck8m_wait: 8; /*CK8M wait cycles in slow_clk_rtc*/
uint32_t xtl_buf_wait: 10; /*XTAL wait cycles in slow_clk_rtc*/
uint32_t pll_buf_wait: 8; /*PLL wait cycles in slow_clk_rtc*/
};
uint32_t val;
} timer1;
union {
struct {
uint32_t reserved0: 15;
uint32_t ulpcp_touch_start_wait: 9; /*wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work*/
uint32_t min_time_ck8m_off: 8; /*minimal cycles in slow_clk_rtc for CK8M in power down state*/
};
uint32_t val;
} timer2;
union {
struct {
uint32_t wifi_wait_timer: 9;
uint32_t wifi_powerup_timer: 7;
uint32_t rom_ram_wait_timer: 9;
uint32_t rom_ram_powerup_timer: 7;
};
uint32_t val;
} timer3;
union {
struct {
uint32_t rtc_wait_timer: 9;
uint32_t rtc_powerup_timer: 7;
uint32_t dg_wrap_wait_timer: 9;
uint32_t dg_wrap_powerup_timer: 7;
};
uint32_t val;
} timer4;
union {
struct {
uint32_t ulp_cp_subtimer_prediv: 8;
uint32_t min_slp_val: 8; /*minimal sleep cycles in slow_clk_rtc*/
uint32_t rtcmem_wait_timer: 9;
uint32_t rtcmem_powerup_timer: 7;
};
uint32_t val;
} timer5;
union {
struct {
uint32_t reserved0: 16;
uint32_t dg_dcdc_wait_timer: 9;
uint32_t dg_dcdc_powerup_timer: 7;
};
uint32_t val;
} timer6;
union {
struct {
uint32_t reserved0: 19;
uint32_t pkdet_cal_force_en: 2; /*pkdet force option*/
uint32_t pwdet_cal_force_en: 2; /*pwdet force option*/
uint32_t plla_force_pd: 1; /*PLLA force power down*/
uint32_t plla_force_pu: 1; /*PLLA force power up*/
uint32_t bbpll_cal_slp_start: 1; /*start BBPLL calibration during sleep*/
uint32_t pvtmon_pu: 1; /*1: PVTMON power up otherwise power down*/
uint32_t txrf_i2c_pu: 1; /*1: TXRF_I2C power up otherwise power down*/
uint32_t rfrx_pbus_pu: 1; /*1: RFRX_PBUS power up otherwise power down*/
uint32_t reserved29: 1;
uint32_t ckgen_i2c_pu: 1; /*1: CKGEN_I2C power up otherwise power down*/
uint32_t pll_i2c_pu: 1;
};
uint32_t val;
} ana_conf;
union {
struct {
uint32_t reset_cause_procpu: 6; /*reset cause of PRO CPU*/
uint32_t reset_cause_appcpu: 6; /*reset cause of APP CPU*/
uint32_t appcpu_stat_vector_sel: 1; /*APP CPU state vector sel*/
uint32_t procpu_stat_vector_sel: 1; /*PRO CPU state vector sel*/
uint32_t reserved14: 18;
};
uint32_t val;
} reset_state;
union {
struct {
uint32_t wakeup_cause: 12; /*wakeup cause*/
uint32_t rtc_wakeup_ena: 12; /*wakeup enable bitmap*/
uint32_t gpio_wakeup_filter: 1; /*enable filter for gpio wakeup event*/
uint32_t reserved25: 7;
};
uint32_t val;
} wakeup_state;
union {
struct {
uint32_t slp_wakeup: 1; /*enable sleep wakeup interrupt*/
uint32_t slp_reject: 1; /*enable sleep reject interrupt*/
uint32_t sdio_idle: 1; /*enable SDIO idle interrupt*/
uint32_t rtc_wdt: 1; /*enable RTC WDT interrupt*/
uint32_t rtc_time_valid: 1; /*enable RTC time valid interrupt*/
uint32_t rtc_ulp_cp: 1; /*enable ULP-coprocessor interrupt*/
uint32_t rtc_touch: 1; /*enable touch interrupt*/
uint32_t rtc_brown_out: 1; /*enable brown out interrupt*/
uint32_t rtc_main_timer: 1; /*enable RTC main timer interrupt*/
uint32_t rtc_saradc1: 1; /*enable saradc1 interrupt*/
uint32_t rtc_tsens: 1; /*enable tsens interrupt*/
uint32_t rtc_cocpu: 1; /*enable riscV cocpu interrupt*/
uint32_t rtc_saradc2: 1; /*enable saradc2 interrupt*/
uint32_t reserved13: 19;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t slp_wakeup: 1; /*sleep wakeup interrupt raw*/
uint32_t slp_reject: 1; /*sleep reject interrupt raw*/
uint32_t sdio_idle: 1; /*SDIO idle interrupt raw*/
uint32_t rtc_wdt: 1; /*RTC WDT interrupt raw*/
uint32_t rtc_time_valid: 1; /*RTC time valid interrupt raw*/
uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt raw*/
uint32_t rtc_touch: 1; /*touch interrupt raw*/
uint32_t rtc_brown_out: 1; /*brown out interrupt raw*/
uint32_t rtc_main_timer: 1; /*RTC main timer interrupt raw*/
uint32_t rtc_saradc1: 1; /*saradc1 interrupt raw*/
uint32_t rtc_tsens: 1; /*tsens interrupt raw*/
uint32_t rtc_cocpu: 1; /*riscV cocpu interrupt raw*/
uint32_t rtc_saradc2: 1; /*saradc2 interrupt raw*/
uint32_t reserved13: 19;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t slp_wakeup: 1; /*sleep wakeup interrupt state*/
uint32_t slp_reject: 1; /*sleep reject interrupt state*/
uint32_t sdio_idle: 1; /*SDIO idle interrupt state*/
uint32_t rtc_wdt: 1; /*RTC WDT interrupt state*/
uint32_t rtc_time_valid: 1; /*RTC time valid interrupt state*/
uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt state*/
uint32_t rtc_touch: 1; /*touch interrupt state*/
uint32_t rtc_brown_out: 1; /*brown out interrupt state*/
uint32_t rtc_main_timer: 1; /*RTC main timer interrupt state*/
uint32_t rtc_saradc1: 1; /*saradc1 interrupt state*/
uint32_t rtc_tsens: 1; /*tsens interrupt state*/
uint32_t rtc_cocpu: 1; /*riscV cocpu interrupt state*/
uint32_t rtc_saradc2: 1; /*saradc2 interrupt state*/
uint32_t reserved13: 19;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t slp_wakeup: 1; /*Clear sleep wakeup interrupt state*/
uint32_t slp_reject: 1; /*Clear sleep reject interrupt state*/
uint32_t sdio_idle: 1; /*Clear SDIO idle interrupt state*/
uint32_t rtc_wdt: 1; /*Clear RTC WDT interrupt state*/
uint32_t rtc_time_valid: 1; /*Clear RTC time valid interrupt state*/
uint32_t rtc_ulp_cp: 1; /*Clear ULP-coprocessor interrupt state*/
uint32_t rtc_touch: 1; /*Clear touch interrupt state*/
uint32_t rtc_brown_out: 1; /*Clear brown out interrupt state*/
uint32_t rtc_main_timer: 1; /*Clear RTC main timer interrupt state*/
uint32_t rtc_saradc1: 1; /*Clear saradc1 interrupt state*/
uint32_t rtc_tsens: 1; /*Clear tsens interrupt state*/
uint32_t rtc_cocpu: 1; /*Clear riscV cocpu interrupt state*/
uint32_t rtc_saradc2: 1; /*Clear saradc2 interrupt state*/
uint32_t reserved13: 19;
};
uint32_t val;
} int_clr;
uint32_t store[4]; /**/
union {
struct {
uint32_t reserved0: 30;
uint32_t ctr_lv: 1; /*0: power down XTAL at high level 1: power down XTAL at low level*/
uint32_t ctr_en: 1;
};
uint32_t val;
} ext_xtl_conf;
union {
struct {
uint32_t reserved0: 30;
uint32_t wakeup0_lv: 1; /*0: external wakeup at low level 1: external wakeup at high level*/
uint32_t wakeup1_lv: 1;
};
uint32_t val;
} ext_wakeup_conf;
union {
struct {
uint32_t reserved0: 24;
uint32_t gpio_reject_en: 1; /*enable GPIO reject*/
uint32_t sdio_reject_en: 1; /*enable SDIO reject*/
uint32_t light_slp_reject_en: 1; /*enable reject for light sleep*/
uint32_t deep_slp_reject_en: 1; /*enable reject for deep sleep*/
uint32_t reject_cause: 4;
};
uint32_t val;
} slp_reject_conf;
union {
struct {
uint32_t reserved0: 29;
uint32_t cpusel_conf: 1; /*CPU sel option*/
uint32_t cpuperiod_sel: 2;
};
uint32_t val;
} cpu_period_conf;
union {
struct {
uint32_t reserved0: 22;
uint32_t sdio_act_dnum:10;
};
uint32_t val;
} sdio_act_conf;
union {
struct {
uint32_t reserved0: 3;
uint32_t ck8m_div_sel_vld: 1; /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel then set vld to actually switch the clk*/
uint32_t ck8m_div: 2; /*CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.*/
uint32_t enb_ck8m: 1; /*disable CK8M and CK8M_D256_OUT*/
uint32_t enb_ck8m_div: 1; /*1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256*/
uint32_t dig_xtal32k_en: 1; /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
uint32_t dig_clk8m_d256_en: 1; /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
uint32_t dig_clk8m_en: 1; /*enable CK8M for digital core (no relationship with RTC core)*/
uint32_t reserved11: 1;
uint32_t ck8m_div_sel: 3; /*divider = reg_ck8m_div_sel + 1*/
uint32_t xtal_force_nogating: 1; /*XTAL force no gating during sleep*/
uint32_t ck8m_force_nogating: 1; /*CK8M force no gating during sleep*/
uint32_t ck8m_dfreq: 8; /*CK8M_DFREQ*/
uint32_t ck8m_force_pd: 1; /*CK8M force power down*/
uint32_t ck8m_force_pu: 1; /*CK8M force power up*/
uint32_t reserved27: 2;
uint32_t fast_clk_rtc_sel: 1; /*fast_clk_rtc sel. 0: XTAL div 4 1: CK8M*/
uint32_t ana_clk_rtc_sel: 2;
};
uint32_t val;
} clk_conf;
union {
struct {
uint32_t reserved0: 14;
uint32_t dbias_xtal_32k: 2; /*DBIAS_XTAL_32K*/
uint32_t dres_xtal_32k: 2; /*DRES_XTAL_32K*/
uint32_t xpd_xtal_32k: 1; /*XPD_XTAL_32K*/
uint32_t dac_xtal_32k: 2; /*DAC_XTAL_32K*/
uint32_t rtc_xtal32k_gpio_sel: 1; /*XTAL_32K sel. 0: external XTAL_32K 1: CLK from RTC pad X32P_C*/
uint32_t rtc_ana_clk_div_vld: 1; /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div then set vld to actually switch the clk*/
uint32_t rtc_ana_clk_div: 8;
uint32_t slow_clk_next_edge: 1;
};
uint32_t val;
} slow_clk_conf;
union {
struct {
uint32_t reserved0: 21;
uint32_t sdio_pd_en: 1; /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/
uint32_t sdio_force: 1; /*1: use SW option to control SDIO_REG 0: use state machine*/
uint32_t sdio_tieh: 1; /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/
uint32_t reg1p8_ready: 1; /*read only register for REG1P8_READY*/
uint32_t drefl_sdio: 2; /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/
uint32_t drefm_sdio: 2; /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/
uint32_t drefh_sdio: 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/
uint32_t xpd_sdio: 1;
};
uint32_t val;
} sdio_conf;
union {
struct {
uint32_t reserved0: 24;
uint32_t dbg_atten: 2; /*DBG_ATTEN*/
uint32_t enb_sck_xtal: 1; /*ENB_SCK_XTAL*/
uint32_t inc_heartbeat_refresh: 1; /*INC_HEARTBEAT_REFRESH*/
uint32_t dec_heartbeat_period: 1; /*DEC_HEARTBEAT_PERIOD*/
uint32_t inc_heartbeat_period: 1; /*INC_HEARTBEAT_PERIOD*/
uint32_t dec_heartbeat_width: 1; /*DEC_HEARTBEAT_WIDTH*/
uint32_t rst_bias_i2c: 1;
};
uint32_t val;
} bias_conf;
union {
struct {
uint32_t reserved0: 8;
uint32_t dig_dbias_slp: 3; /*DIG_REG_DBIAS during sleep*/
uint32_t dig_dbias_wak: 3; /*DIG_REG_DBIAS during wakeup*/
uint32_t sck_dcap: 8; /*SCK_DCAP*/
uint32_t rtc_dbias_slp: 3; /*RTC_DBIAS during sleep*/
uint32_t rtc_dbias_wak: 3; /*RTC_DBIAS during wakeup*/
uint32_t rtc_dboost_force_pd: 1; /*RTC_DBOOST force power down*/
uint32_t rtc_dboost_force_pu: 1; /*RTC_DBOOST force power up*/
uint32_t rtculator_force_pd: 1; /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/
uint32_t rtculator_force_pu: 1;
};
uint32_t val;
} rtc;
union {
struct {
uint32_t fastmem_force_noiso: 1; /*Fast RTC memory force no ISO*/
uint32_t fastmem_force_iso: 1; /*Fast RTC memory force ISO*/
uint32_t slowmem_force_noiso: 1; /*RTC memory force no ISO*/
uint32_t slowmem_force_iso: 1; /*RTC memory force ISO*/
uint32_t rtc_force_iso: 1; /*rtc_peri force ISO*/
uint32_t rtc_force_noiso: 1; /*rtc_peri force no ISO*/
uint32_t fastmem_folw_cpu: 1; /*1: Fast RTC memory PD following CPU 0: fast RTC memory PD following RTC state machine*/
uint32_t fastmem_force_lpd: 1; /*Fast RTC memory force PD*/
uint32_t fastmem_force_lpu: 1; /*Fast RTC memory force no PD*/
uint32_t slowmem_folw_cpu: 1; /*1: RTC memory PD following CPU 0: RTC memory PD following RTC state machine*/
uint32_t slowmem_force_lpd: 1; /*RTC memory force PD*/
uint32_t slowmem_force_lpu: 1; /*RTC memory force no PD*/
uint32_t fastmem_force_pd: 1; /*Fast RTC memory force power down*/
uint32_t fastmem_force_pu: 1; /*Fast RTC memory force power up*/
uint32_t fastmem_pd_en: 1; /*enable power down fast RTC memory in sleep*/
uint32_t slowmem_force_pd: 1; /*RTC memory force power down*/
uint32_t slowmem_force_pu: 1; /*RTC memory force power up*/
uint32_t slowmem_pd_en: 1; /*enable power down RTC memory in sleep*/
uint32_t rtc_force_pd: 1; /*rtc_peri force power down*/
uint32_t rtc_force_pu: 1; /*rtc_peri force power up*/
uint32_t rtc_pd_en: 1; /*enable power down rtc_peri in sleep*/
uint32_t rtc_pad_autohold: 1; /*read only register to indicate rtc pad auto-hold status*/
uint32_t clr_rtc_pad_autohold: 1; /*wtite only register to clear rtc pad auto-hold*/
uint32_t rtc_pad_autohold_en: 1; /*rtc pad enable auto-hold*/
uint32_t rtc_pad_force_noiso: 1; /*rtc pad force no ISO*/
uint32_t rtc_pad_force_iso: 1; /*rtc pad force ISO*/
uint32_t rtc_pad_force_unhold: 1; /*rtc pad force un-hold*/
uint32_t rtc_pad_force_hold: 1; /*rtc pad force hold*/
uint32_t reserved28: 4;
};
uint32_t val;
} rtc_pwc;
union {
struct {
uint32_t reserved0: 3;
uint32_t lslp_mem_force_pd: 1; /*memories in digital core force PD in sleep*/
uint32_t lslp_mem_force_pu: 1; /*memories in digital core force no PD in sleep*/
uint32_t rom0_force_pd: 1; /*ROM force power down*/
uint32_t rom0_force_pu: 1; /*ROM force power up*/
uint32_t inter_ram0_force_pd: 1; /*internal SRAM 0 force power down*/
uint32_t inter_ram0_force_pu: 1; /*internal SRAM 0 force power up*/
uint32_t inter_ram1_force_pd: 1; /*internal SRAM 1 force power down*/
uint32_t inter_ram1_force_pu: 1; /*internal SRAM 1 force power up*/
uint32_t inter_ram2_force_pd: 1; /*internal SRAM 2 force power down*/
uint32_t inter_ram2_force_pu: 1; /*internal SRAM 2 force power up*/
uint32_t inter_ram3_force_pd: 1; /*internal SRAM 3 force power down*/
uint32_t inter_ram3_force_pu: 1; /*internal SRAM 3 force power up*/
uint32_t inter_ram4_force_pd: 1; /*internal SRAM 4 force power down*/
uint32_t inter_ram4_force_pu: 1; /*internal SRAM 4 force power up*/
uint32_t wifi_force_pd: 1; /*wifi force power down*/
uint32_t wifi_force_pu: 1; /*wifi force power up*/
uint32_t dg_wrap_force_pd: 1; /*digital core force power down*/
uint32_t dg_wrap_force_pu: 1; /*digital core force power up*/
uint32_t dg_dcdc_force_pd: 1; /*digital dcdc force power down*/
uint32_t dg_dcdc_force_pu: 1; /*digital dcdc force power up*/
uint32_t dg_dcdc_pd_en: 1; /*enable power down digital dcdc in sleep*/
uint32_t rom0_pd_en: 1; /*enable power down ROM in sleep*/
uint32_t inter_ram0_pd_en: 1; /*enable power down internal SRAM 0 in sleep*/
uint32_t inter_ram1_pd_en: 1; /*enable power down internal SRAM 1 in sleep*/
uint32_t inter_ram2_pd_en: 1; /*enable power down internal SRAM 2 in sleep*/
uint32_t inter_ram3_pd_en: 1; /*enable power down internal SRAM 3 in sleep*/
uint32_t inter_ram4_pd_en: 1; /*enable power down internal SRAM 4 in sleep*/
uint32_t wifi_pd_en: 1; /*enable power down wifi in sleep*/
uint32_t dg_wrap_pd_en: 1;
};
uint32_t val;
} dig_pwc;
union {
struct {
uint32_t reserved0: 7;
uint32_t dig_iso_force_off: 1;
uint32_t dig_iso_force_on: 1;
uint32_t dg_pad_autohold: 1; /*read only register to indicate digital pad auto-hold status*/
uint32_t clr_dg_pad_autohold: 1; /*wtite only register to clear digital pad auto-hold*/
uint32_t dg_pad_autohold_en: 1; /*digital pad enable auto-hold*/
uint32_t dg_pad_force_noiso: 1; /*digital pad force no ISO*/
uint32_t dg_pad_force_iso: 1; /*digital pad force ISO*/
uint32_t dg_pad_force_unhold: 1; /*digital pad force un-hold*/
uint32_t dg_pad_force_hold: 1; /*digital pad force hold*/
uint32_t rom0_force_iso: 1; /*ROM force ISO*/
uint32_t rom0_force_noiso: 1; /*ROM force no ISO*/
uint32_t inter_ram0_force_iso: 1; /*internal SRAM 0 force ISO*/
uint32_t inter_ram0_force_noiso: 1; /*internal SRAM 0 force no ISO*/
uint32_t inter_ram1_force_iso: 1; /*internal SRAM 1 force ISO*/
uint32_t inter_ram1_force_noiso: 1; /*internal SRAM 1 force no ISO*/
uint32_t inter_ram2_force_iso: 1; /*internal SRAM 2 force ISO*/
uint32_t inter_ram2_force_noiso: 1; /*internal SRAM 2 force no ISO*/
uint32_t inter_ram3_force_iso: 1; /*internal SRAM 3 force ISO*/
uint32_t inter_ram3_force_noiso: 1; /*internal SRAM 3 force no ISO*/
uint32_t inter_ram4_force_iso: 1; /*internal SRAM 4 force ISO*/
uint32_t inter_ram4_force_noiso: 1; /*internal SRAM 4 force no ISO*/
uint32_t wifi_force_iso: 1; /*wifi force ISO*/
uint32_t wifi_force_noiso: 1; /*wifi force no ISO*/
uint32_t dg_wrap_force_iso: 1; /*digital core force ISO*/
uint32_t dg_wrap_force_noiso: 1;
};
uint32_t val;
} dig_iso;
union {
struct {
uint32_t reserved0: 7;
uint32_t pause_in_slp: 1; /*pause WDT in sleep*/
uint32_t appcpu_reset_en: 1; /*enable WDT reset APP CPU*/
uint32_t procpu_reset_en: 1; /*enable WDT reset PRO CPU*/
uint32_t flashboot_mod_en: 1; /*enable WDT in flash boot*/
uint32_t sys_reset_length: 3; /*system reset counter length*/
uint32_t cpu_reset_length: 3; /*CPU reset counter length*/
uint32_t level_int_en: 1; /*N/A*/
uint32_t edge_int_en: 1; /*N/A*/
uint32_t stg3: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/
uint32_t stg2: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/
uint32_t stg1: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/
uint32_t stg0: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/
uint32_t en: 1;
};
uint32_t val;
} wdt_config0;
uint32_t wdt_config1; /**/
uint32_t wdt_config2; /**/
uint32_t wdt_config3; /**/
uint32_t wdt_config4; /**/
union {
struct {
uint32_t reserved0: 31;
uint32_t feed: 1;
};
uint32_t val;
} wdt_feed;
uint32_t wdt_wprotect; /**/
union {
struct {
uint32_t reserved0: 29;
uint32_t ent_rtc: 1; /*ENT_RTC*/
uint32_t dtest_rtc: 2;
};
uint32_t val;
} test_mux;
union {
struct {
uint32_t reserved0: 20;
uint32_t appcpu_c1: 6; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
uint32_t procpu_c1: 6;
};
uint32_t val;
} sw_cpu_stall;
uint32_t store4; /**/
uint32_t store5; /**/
uint32_t store6; /**/
uint32_t store7; /**/
union {
struct {
uint32_t xpd_rom0: 1; /*rom0 power down*/
uint32_t reserved1: 1;
uint32_t xpd_dig_dcdc: 1; /*External DCDC power down*/
uint32_t rtc_peri_iso: 1; /*rtc peripheral iso*/
uint32_t xpd_rtc_peri: 1; /*rtc peripheral power down*/
uint32_t wifi_iso: 1; /*wifi iso*/
uint32_t xpd_wifi: 1; /*wifi wrap power down*/
uint32_t dig_iso: 1; /*digital wrap iso*/
uint32_t xpd_dig: 1; /*digital wrap power down*/
uint32_t rtc_touch_start: 1; /*touch should start to work*/
uint32_t rtc_touch_state_switch: 1; /*touch is about to working. Switch rtc main state*/
uint32_t rtc_touch_slp: 1; /*touch is in sleep state*/
uint32_t rtc_touch_done: 1; /*touch is done*/
uint32_t rtc_cocpu_start: 1; /*ulp/cocpu should start to work*/
uint32_t rtc_cocpu_state_switch: 1; /*ulp/cocpu is about to working. Switch rtc main state*/
uint32_t rtc_cocpu_slp: 1; /*ulp/cocpu is in sleep state*/
uint32_t rtc_cocpu_done: 1; /*ulp/cocpu is done*/
uint32_t rtc_main_state_xtal_iso: 1; /*no use any more*/
uint32_t rtc_main_state_pll_on: 1; /*rtc main state machine is in states that pll should be running*/
uint32_t rtc_rdy_for_wakeup: 1; /*rtc is ready to receive wake up trigger from wake up source*/
uint32_t rtc_main_state_wait_end: 1; /*rtc main state machine has been waited for some cycles*/
uint32_t rtc_in_wakeup_state: 1; /*rtc main state machine is in the states of wakeup process*/
uint32_t rtc_in_low_power_state: 1; /*rtc main state machine is in the states of low power*/
uint32_t rtc_main_state_in_wait_8m: 1; /*rtc main state machine is in wait 8m state*/
uint32_t rtc_main_state_in_wait_pll: 1; /*rtc main state machine is in wait pll state*/
uint32_t rtc_main_state_in_wait_xtl: 1; /*rtc main state machine is in wait xtal state*/
uint32_t rtc_main_state_in_slp: 1; /*rtc main state machine is in sleep state*/
uint32_t rtc_main_state_in_idle: 1; /*rtc main state machine is in idle state*/
uint32_t rtc_main_state: 4; /*rtc main state machine status*/
};
uint32_t val;
} low_power_st;
uint32_t diag0; /**/
union {
struct {
uint32_t adc1_hold_force: 1;
uint32_t adc2_hold_force: 1;
uint32_t pdac1_hold_force: 1;
uint32_t pdac2_hold_force: 1;
uint32_t sense1_hold_force: 1;
uint32_t sense2_hold_force: 1;
uint32_t sense3_hold_force: 1;
uint32_t sense4_hold_force: 1;
uint32_t touch_pad0_hold_force: 1;
uint32_t touch_pad1_hold_force: 1;
uint32_t touch_pad2_hold_force: 1;
uint32_t touch_pad3_hold_force: 1;
uint32_t touch_pad4_hold_force: 1;
uint32_t touch_pad5_hold_force: 1;
uint32_t touch_pad6_hold_force: 1;
uint32_t touch_pad7_hold_force: 1;
uint32_t x32p_hold_force: 1;
uint32_t x32n_hold_force: 1;
uint32_t reserved18: 14;
};
uint32_t val;
} hold_force;
uint32_t dig_pad_hold; /**/
union {
struct {
uint32_t sel: 18; /*Bitmap to select RTC pads for ext wakeup1*/
uint32_t status_clr: 1; /*clear ext wakeup1 status*/
uint32_t reserved19: 13;
};
uint32_t val;
} ext_wakeup1;
union {
struct {
uint32_t status: 18; /*ext wakeup1 status*/
uint32_t reserved18: 14;
};
uint32_t val;
} ext_wakeup1_status;
union {
struct {
uint32_t reserved0: 14;
uint32_t close_flash_ena: 1; /*enable close flash when brown out happens*/
uint32_t pd_rf_ena: 1; /*enable power down RF when brown out happens*/
uint32_t rst_wait: 10; /*brown out reset wait cycles*/
uint32_t rst_ena: 1; /*enable brown out reset*/
uint32_t thres: 3; /*brown out threshold*/
uint32_t ena: 1; /*enable brown out*/
uint32_t det: 1;
};
uint32_t val;
} brown_out;
uint32_t reserved_3c;
uint32_t reserved_40;
uint32_t reserved_44;
uint32_t reserved_48;
uint32_t reserved_4c;
union {
struct {
uint32_t date: 28;
uint32_t reserved28: 4;
};
uint32_t val;
} date;
} rtc_cntl_dev_t;
extern rtc_cntl_dev_t RTCCNTL;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_RTC_CNTL_STRUCT_H_ */

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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_RTC_GPIO_CHANNEL_H
#define _SOC_RTC_GPIO_CHANNEL_H
//RTC GPIO channels
#define RTCIO_GPIO36_CHANNEL 0 //RTCIO_CHANNEL_0
#define RTCIO_CHANNEL_0_GPIO_NUM 36
#define RTCIO_GPIO37_CHANNEL 1 //RTCIO_CHANNEL_1
#define RTCIO_CHANNEL_1_GPIO_NUM 37
#define RTCIO_GPIO38_CHANNEL 2 //RTCIO_CHANNEL_2
#define RTCIO_CHANNEL_2_GPIO_NUM 38
#define RTCIO_GPIO39_CHANNEL 3 //RTCIO_CHANNEL_3
#define RTCIO_CHANNEL_3_GPIO_NUM 39
#define RTCIO_GPIO34_CHANNEL 4 //RTCIO_CHANNEL_4
#define RTCIO_CHANNEL_4_GPIO_NUM 34
#define RTCIO_GPIO35_CHANNEL 5 //RTCIO_CHANNEL_5
#define RTCIO_CHANNEL_5_GPIO_NUM 35
#define RTCIO_GPIO25_CHANNEL 6 //RTCIO_CHANNEL_6
#define RTCIO_CHANNEL_6_GPIO_NUM 25
#define RTCIO_GPIO26_CHANNEL 7 //RTCIO_CHANNEL_7
#define RTCIO_CHANNEL_7_GPIO_NUM 26
#define RTCIO_GPIO33_CHANNEL 8 //RTCIO_CHANNEL_8
#define RTCIO_CHANNEL_8_GPIO_NUM 33
#define RTCIO_GPIO32_CHANNEL 9 //RTCIO_CHANNEL_9
#define RTCIO_CHANNEL_9_GPIO_NUM 32
#define RTCIO_GPIO4_CHANNEL 10 //RTCIO_CHANNEL_10
#define RTCIO_CHANNEL_10_GPIO_NUM 4
#define RTCIO_GPIO0_CHANNEL 11 //RTCIO_CHANNEL_11
#define RTCIO_CHANNEL_11_GPIO_NUM 0
#define RTCIO_GPIO2_CHANNEL 12 //RTCIO_CHANNEL_12
#define RTCIO_CHANNEL_12_GPIO_NUM 2
#define RTCIO_GPIO15_CHANNEL 13 //RTCIO_CHANNEL_13
#define RTCIO_CHANNEL_13_GPIO_NUM 15
#define RTCIO_GPIO13_CHANNEL 14 //RTCIO_CHANNEL_14
#define RTCIO_CHANNEL_14_GPIO_NUM 13
#define RTCIO_GPIO12_CHANNEL 15 //RTCIO_CHANNEL_15
#define RTCIO_CHANNEL_15_GPIO_NUM 12
#define RTCIO_GPIO14_CHANNEL 16 //RTCIO_CHANNEL_16
#define RTCIO_CHANNEL_16_GPIO_NUM 14
#define RTCIO_GPIO27_CHANNEL 17 //RTCIO_CHANNEL_17
#define RTCIO_CHANNEL_17_GPIO_NUM 27
#endif

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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_RTC_I2C_REG_H_
#define _SOC_RTC_I2C_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
/**
* This file lists peripheral registers of an I2C controller which is part of the RTC.
* ULP coprocessor uses this controller to implement I2C_RD and I2C_WR instructions.
*
* Part of the functionality of this controller (such as slave mode, and multi-byte
* transfers) is not wired to the ULP, and is such, is not available to the
* ULP programs.
*/
#define RTC_I2C_SCL_LOW_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0000)
/* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */
/*description: time period that scl = 0*/
#define RTC_I2C_SCL_LOW_PERIOD 0x000FFFFF
#define RTC_I2C_SCL_LOW_PERIOD_M ((RTC_I2C_SCL_LOW_PERIOD_V)<<(RTC_I2C_SCL_LOW_PERIOD_S))
#define RTC_I2C_SCL_LOW_PERIOD_V 0xFFFFF
#define RTC_I2C_SCL_LOW_PERIOD_S 0
#define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x0004)
/* RTC_I2C_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: rtc i2c reg clk gating*/
#define RTC_I2C_CLK_EN (BIT(31))
#define RTC_I2C_CLK_EN_M (BIT(31))
#define RTC_I2C_CLK_EN_V 0x1
#define RTC_I2C_CLK_EN_S 31
/* RTC_I2C_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: rtc i2c sw reset*/
#define RTC_I2C_RESET (BIT(30))
#define RTC_I2C_RESET_M (BIT(30))
#define RTC_I2C_RESET_V 0x1
#define RTC_I2C_RESET_S 30
/* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: receive lsb first*/
#define RTC_I2C_RX_LSB_FIRST (BIT(5))
#define RTC_I2C_RX_LSB_FIRST_M (BIT(5))
#define RTC_I2C_RX_LSB_FIRST_V 0x1
#define RTC_I2C_RX_LSB_FIRST_S 5
/* RTC_I2C_TX_LSB_FIRST : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: transit lsb first*/
#define RTC_I2C_TX_LSB_FIRST (BIT(4))
#define RTC_I2C_TX_LSB_FIRST_M (BIT(4))
#define RTC_I2C_TX_LSB_FIRST_V 0x1
#define RTC_I2C_TX_LSB_FIRST_S 4
/* RTC_I2C_TRANS_START : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: force start*/
#define RTC_I2C_TRANS_START (BIT(3))
#define RTC_I2C_TRANS_START_M (BIT(3))
#define RTC_I2C_TRANS_START_V 0x1
#define RTC_I2C_TRANS_START_S 3
/* RTC_I2C_MS_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: 1=master 0=slave*/
#define RTC_I2C_MS_MODE (BIT(2))
#define RTC_I2C_MS_MODE_M (BIT(2))
#define RTC_I2C_MS_MODE_V 0x1
#define RTC_I2C_MS_MODE_S 2
/* RTC_I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: 1=push pull 0=open drain*/
#define RTC_I2C_SCL_FORCE_OUT (BIT(1))
#define RTC_I2C_SCL_FORCE_OUT_M (BIT(1))
#define RTC_I2C_SCL_FORCE_OUT_V 0x1
#define RTC_I2C_SCL_FORCE_OUT_S 1
/* RTC_I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: 1=push pull 0=open drain*/
#define RTC_I2C_SDA_FORCE_OUT (BIT(0))
#define RTC_I2C_SDA_FORCE_OUT_M (BIT(0))
#define RTC_I2C_SDA_FORCE_OUT_V 0x1
#define RTC_I2C_SDA_FORCE_OUT_S 0
#define RTC_I2C_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x0008)
/* RTC_I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */
/*description: scl last status*/
#define RTC_I2C_SCL_STATE_LAST 0x00000007
#define RTC_I2C_SCL_STATE_LAST_M ((RTC_I2C_SCL_STATE_LAST_V)<<(RTC_I2C_SCL_STATE_LAST_S))
#define RTC_I2C_SCL_STATE_LAST_V 0x7
#define RTC_I2C_SCL_STATE_LAST_S 28
/* RTC_I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */
/*description: i2c last main status*/
#define RTC_I2C_SCL_MAIN_STATE_LAST 0x00000007
#define RTC_I2C_SCL_MAIN_STATE_LAST_M ((RTC_I2C_SCL_MAIN_STATE_LAST_V)<<(RTC_I2C_SCL_MAIN_STATE_LAST_S))
#define RTC_I2C_SCL_MAIN_STATE_LAST_V 0x7
#define RTC_I2C_SCL_MAIN_STATE_LAST_S 24
/* RTC_I2C_SHIFT : RO ;bitpos:[23:16] ;default: 8'b0 ; */
/*description: shifter content*/
#define RTC_I2C_SHIFT 0x000000FF
#define RTC_I2C_SHIFT_M ((RTC_I2C_SHIFT_V)<<(RTC_I2C_SHIFT_S))
#define RTC_I2C_SHIFT_V 0xFF
#define RTC_I2C_SHIFT_S 16
/* RTC_I2C_OP_CNT : RO ;bitpos:[7:6] ;default: 2'b0 ; */
/*description: which operation is working*/
#define RTC_I2C_OP_CNT 0x00000003
#define RTC_I2C_OP_CNT_M ((RTC_I2C_OP_CNT_V)<<(RTC_I2C_OP_CNT_S))
#define RTC_I2C_OP_CNT_V 0x3
#define RTC_I2C_OP_CNT_S 6
/* RTC_I2C_BYTE_TRANS : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: One byte transit done*/
#define RTC_I2C_BYTE_TRANS (BIT(5))
#define RTC_I2C_BYTE_TRANS_M (BIT(5))
#define RTC_I2C_BYTE_TRANS_V 0x1
#define RTC_I2C_BYTE_TRANS_S 5
/* RTC_I2C_SLAVE_ADDRESSED : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: slave reg sub address*/
#define RTC_I2C_SLAVE_ADDRESSED (BIT(4))
#define RTC_I2C_SLAVE_ADDRESSED_M (BIT(4))
#define RTC_I2C_SLAVE_ADDRESSED_V 0x1
#define RTC_I2C_SLAVE_ADDRESSED_S 4
/* RTC_I2C_BUS_BUSY : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: bus is busy*/
#define RTC_I2C_BUS_BUSY (BIT(3))
#define RTC_I2C_BUS_BUSY_M (BIT(3))
#define RTC_I2C_BUS_BUSY_V 0x1
#define RTC_I2C_BUS_BUSY_S 3
/* RTC_I2C_ARB_LOST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: arbitration is lost*/
#define RTC_I2C_ARB_LOST (BIT(2))
#define RTC_I2C_ARB_LOST_M (BIT(2))
#define RTC_I2C_ARB_LOST_V 0x1
#define RTC_I2C_ARB_LOST_S 2
/* RTC_I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: slave read or write*/
#define RTC_I2C_SLAVE_RW (BIT(1))
#define RTC_I2C_SLAVE_RW_M (BIT(1))
#define RTC_I2C_SLAVE_RW_V 0x1
#define RTC_I2C_SLAVE_RW_S 1
/* RTC_I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: ack response*/
#define RTC_I2C_ACK_REC (BIT(0))
#define RTC_I2C_ACK_REC_M (BIT(0))
#define RTC_I2C_ACK_REC_V 0x1
#define RTC_I2C_ACK_REC_S 0
#define RTC_I2C_TIMEOUT_REG (DR_REG_RTC_I2C_BASE + 0x000c)
/* RTC_I2C_TIMEOUT : R/W ;bitpos:[19:0] ;default: 20'h10000 ; */
/*description: time out threshold*/
#define RTC_I2C_TIMEOUT 0x000FFFFF
#define RTC_I2C_TIMEOUT_M ((RTC_I2C_TIMEOUT_V)<<(RTC_I2C_TIMEOUT_S))
#define RTC_I2C_TIMEOUT_V 0xFFFFF
#define RTC_I2C_TIMEOUT_S 0
#define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x0010)
/* RTC_I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: i2c 10bit mode enable*/
#define RTC_I2C_ADDR_10BIT_EN (BIT(31))
#define RTC_I2C_ADDR_10BIT_EN_M (BIT(31))
#define RTC_I2C_ADDR_10BIT_EN_V 0x1
#define RTC_I2C_ADDR_10BIT_EN_S 31
/* RTC_I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
/*description: slave address*/
#define RTC_I2C_SLAVE_ADDR 0x00007FFF
#define RTC_I2C_SLAVE_ADDR_M ((RTC_I2C_SLAVE_ADDR_V)<<(RTC_I2C_SLAVE_ADDR_S))
#define RTC_I2C_SLAVE_ADDR_V 0x7FFF
#define RTC_I2C_SLAVE_ADDR_S 0
#define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_I2C_BASE + 0x0014)
/* RTC_I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */
/*description: time period that scl = 1*/
#define RTC_I2C_SCL_HIGH_PERIOD 0x000FFFFF
#define RTC_I2C_SCL_HIGH_PERIOD_M ((RTC_I2C_SCL_HIGH_PERIOD_V)<<(RTC_I2C_SCL_HIGH_PERIOD_S))
#define RTC_I2C_SCL_HIGH_PERIOD_V 0xFFFFF
#define RTC_I2C_SCL_HIGH_PERIOD_S 0
#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x0018)
/* RTC_I2C_SDA_DUTY_NUM : R/W ;bitpos:[19:0] ;default: 20'h10 ; */
/*description: time period for SDA to toggle after SCL goes low*/
#define RTC_I2C_SDA_DUTY_NUM 0x000FFFFF
#define RTC_I2C_SDA_DUTY_NUM_M ((RTC_I2C_SDA_DUTY_NUM_V)<<(RTC_I2C_SDA_DUTY_NUM_S))
#define RTC_I2C_SDA_DUTY_NUM_V 0xFFFFF
#define RTC_I2C_SDA_DUTY_NUM_S 0
#define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x001c)
/* RTC_I2C_SCL_START_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */
/*description: time period for SCL to toggle after I2C start is triggered*/
#define RTC_I2C_SCL_START_PERIOD 0x000FFFFF
#define RTC_I2C_SCL_START_PERIOD_M ((RTC_I2C_SCL_START_PERIOD_V)<<(RTC_I2C_SCL_START_PERIOD_S))
#define RTC_I2C_SCL_START_PERIOD_V 0xFFFFF
#define RTC_I2C_SCL_START_PERIOD_S 0
#define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0020)
/* RTC_I2C_SCL_STOP_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */
/*description: time period for SCL to stop after I2C end is triggered*/
#define RTC_I2C_SCL_STOP_PERIOD 0x000FFFFF
#define RTC_I2C_SCL_STOP_PERIOD_M ((RTC_I2C_SCL_STOP_PERIOD_V)<<(RTC_I2C_SCL_STOP_PERIOD_S))
#define RTC_I2C_SCL_STOP_PERIOD_V 0xFFFFF
#define RTC_I2C_SCL_STOP_PERIOD_S 0
#define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x0024)
/* RTC_I2C_DETECT_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
/*description: clear detect start interrupt*/
#define RTC_I2C_DETECT_START_INT_CLR (BIT(8))
#define RTC_I2C_DETECT_START_INT_CLR_M (BIT(8))
#define RTC_I2C_DETECT_START_INT_CLR_V 0x1
#define RTC_I2C_DETECT_START_INT_CLR_S 8
/* RTC_I2C_TX_DATA_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
/*description: clear transit load data complete interrupt*/
#define RTC_I2C_TX_DATA_INT_CLR (BIT(7))
#define RTC_I2C_TX_DATA_INT_CLR_M (BIT(7))
#define RTC_I2C_TX_DATA_INT_CLR_V 0x1
#define RTC_I2C_TX_DATA_INT_CLR_S 7
/* RTC_I2C_RX_DATA_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
/*description: clear receive data interrupt*/
#define RTC_I2C_RX_DATA_INT_CLR (BIT(6))
#define RTC_I2C_RX_DATA_INT_CLR_M (BIT(6))
#define RTC_I2C_RX_DATA_INT_CLR_V 0x1
#define RTC_I2C_RX_DATA_INT_CLR_S 6
/* RTC_I2C_ACK_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
/*description: clear ack error interrupt*/
#define RTC_I2C_ACK_ERR_INT_CLR (BIT(5))
#define RTC_I2C_ACK_ERR_INT_CLR_M (BIT(5))
#define RTC_I2C_ACK_ERR_INT_CLR_V 0x1
#define RTC_I2C_ACK_ERR_INT_CLR_S 5
/* RTC_I2C_TIMEOUT_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
/*description: clear time out interrupt*/
#define RTC_I2C_TIMEOUT_INT_CLR (BIT(4))
#define RTC_I2C_TIMEOUT_INT_CLR_M (BIT(4))
#define RTC_I2C_TIMEOUT_INT_CLR_V 0x1
#define RTC_I2C_TIMEOUT_INT_CLR_S 4
/* RTC_I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
/*description: clear transit complete interrupt*/
#define RTC_I2C_TRANS_COMPLETE_INT_CLR (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V 0x1
#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S 3
/* RTC_I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
/*description: clear master transit complete interrupt*/
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S 2
/* RTC_I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
/*description: clear arbitration lost interrupt*/
#define RTC_I2C_ARBITRATION_LOST_INT_CLR (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V 0x1
#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S 1
/* RTC_I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: clear slave transit complete interrupt*/
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S 0
#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x0028)
/* RTC_I2C_DETECT_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: detect start interrupt raw*/
#define RTC_I2C_DETECT_START_INT_RAW (BIT(8))
#define RTC_I2C_DETECT_START_INT_RAW_M (BIT(8))
#define RTC_I2C_DETECT_START_INT_RAW_V 0x1
#define RTC_I2C_DETECT_START_INT_RAW_S 8
/* RTC_I2C_TX_DATA_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: transit data interrupt raw*/
#define RTC_I2C_TX_DATA_INT_RAW (BIT(7))
#define RTC_I2C_TX_DATA_INT_RAW_M (BIT(7))
#define RTC_I2C_TX_DATA_INT_RAW_V 0x1
#define RTC_I2C_TX_DATA_INT_RAW_S 7
/* RTC_I2C_RX_DATA_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: receive data interrupt raw*/
#define RTC_I2C_RX_DATA_INT_RAW (BIT(6))
#define RTC_I2C_RX_DATA_INT_RAW_M (BIT(6))
#define RTC_I2C_RX_DATA_INT_RAW_V 0x1
#define RTC_I2C_RX_DATA_INT_RAW_S 6
/* RTC_I2C_ACK_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: ack error interrupt raw*/
#define RTC_I2C_ACK_ERR_INT_RAW (BIT(5))
#define RTC_I2C_ACK_ERR_INT_RAW_M (BIT(5))
#define RTC_I2C_ACK_ERR_INT_RAW_V 0x1
#define RTC_I2C_ACK_ERR_INT_RAW_S 5
/* RTC_I2C_TIMEOUT_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: time out interrupt raw*/
#define RTC_I2C_TIMEOUT_INT_RAW (BIT(4))
#define RTC_I2C_TIMEOUT_INT_RAW_M (BIT(4))
#define RTC_I2C_TIMEOUT_INT_RAW_V 0x1
#define RTC_I2C_TIMEOUT_INT_RAW_S 4
/* RTC_I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: transit complete interrupt raw*/
#define RTC_I2C_TRANS_COMPLETE_INT_RAW (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V 0x1
#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S 3
/* RTC_I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: master transit complete interrupt raw*/
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S 2
/* RTC_I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: arbitration lost interrupt raw*/
#define RTC_I2C_ARBITRATION_LOST_INT_RAW (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V 0x1
#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S 1
/* RTC_I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: slave transit complete interrupt raw*/
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S 0
#define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x002c)
/* RTC_I2C_DETECT_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: detect start interrupt state*/
#define RTC_I2C_DETECT_START_INT_ST (BIT(8))
#define RTC_I2C_DETECT_START_INT_ST_M (BIT(8))
#define RTC_I2C_DETECT_START_INT_ST_V 0x1
#define RTC_I2C_DETECT_START_INT_ST_S 8
/* RTC_I2C_TX_DATA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: transit data interrupt state*/
#define RTC_I2C_TX_DATA_INT_ST (BIT(7))
#define RTC_I2C_TX_DATA_INT_ST_M (BIT(7))
#define RTC_I2C_TX_DATA_INT_ST_V 0x1
#define RTC_I2C_TX_DATA_INT_ST_S 7
/* RTC_I2C_RX_DATA_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: receive data interrupt state*/
#define RTC_I2C_RX_DATA_INT_ST (BIT(6))
#define RTC_I2C_RX_DATA_INT_ST_M (BIT(6))
#define RTC_I2C_RX_DATA_INT_ST_V 0x1
#define RTC_I2C_RX_DATA_INT_ST_S 6
/* RTC_I2C_ACK_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: ack error interrupt state*/
#define RTC_I2C_ACK_ERR_INT_ST (BIT(5))
#define RTC_I2C_ACK_ERR_INT_ST_M (BIT(5))
#define RTC_I2C_ACK_ERR_INT_ST_V 0x1
#define RTC_I2C_ACK_ERR_INT_ST_S 5
/* RTC_I2C_TIMEOUT_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: time out interrupt state*/
#define RTC_I2C_TIMEOUT_INT_ST (BIT(4))
#define RTC_I2C_TIMEOUT_INT_ST_M (BIT(4))
#define RTC_I2C_TIMEOUT_INT_ST_V 0x1
#define RTC_I2C_TIMEOUT_INT_ST_S 4
/* RTC_I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: transit complete interrupt state*/
#define RTC_I2C_TRANS_COMPLETE_INT_ST (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_ST_M (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_ST_V 0x1
#define RTC_I2C_TRANS_COMPLETE_INT_ST_S 3
/* RTC_I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: master transit complete interrupt state*/
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_V 0x1
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_S 2
/* RTC_I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: arbitration lost interrupt state*/
#define RTC_I2C_ARBITRATION_LOST_INT_ST (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_ST_M (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_ST_V 0x1
#define RTC_I2C_ARBITRATION_LOST_INT_ST_S 1
/* RTC_I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: slave transit complete interrupt state*/
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S 0
#define RTC_I2C_INT_ENA_REG (DR_REG_RTC_I2C_BASE + 0x0030)
/* RTC_I2C_DETECT_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: enable detect start interrupt*/
#define RTC_I2C_DETECT_START_INT_ENA (BIT(8))
#define RTC_I2C_DETECT_START_INT_ENA_M (BIT(8))
#define RTC_I2C_DETECT_START_INT_ENA_V 0x1
#define RTC_I2C_DETECT_START_INT_ENA_S 8
/* RTC_I2C_TX_DATA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: enable transit data interrupt*/
#define RTC_I2C_TX_DATA_INT_ENA (BIT(7))
#define RTC_I2C_TX_DATA_INT_ENA_M (BIT(7))
#define RTC_I2C_TX_DATA_INT_ENA_V 0x1
#define RTC_I2C_TX_DATA_INT_ENA_S 7
/* RTC_I2C_RX_DATA_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: enable receive data interrupt*/
#define RTC_I2C_RX_DATA_INT_ENA (BIT(6))
#define RTC_I2C_RX_DATA_INT_ENA_M (BIT(6))
#define RTC_I2C_RX_DATA_INT_ENA_V 0x1
#define RTC_I2C_RX_DATA_INT_ENA_S 6
/* RTC_I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: enable eack error interrupt*/
#define RTC_I2C_ACK_ERR_INT_ENA (BIT(5))
#define RTC_I2C_ACK_ERR_INT_ENA_M (BIT(5))
#define RTC_I2C_ACK_ERR_INT_ENA_V 0x1
#define RTC_I2C_ACK_ERR_INT_ENA_S 5
/* RTC_I2C_TIMEOUT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: enable time out interrupt*/
#define RTC_I2C_TIMEOUT_INT_ENA (BIT(4))
#define RTC_I2C_TIMEOUT_INT_ENA_M (BIT(4))
#define RTC_I2C_TIMEOUT_INT_ENA_V 0x1
#define RTC_I2C_TIMEOUT_INT_ENA_S 4
/* RTC_I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: enable transit complete interrupt*/
#define RTC_I2C_TRANS_COMPLETE_INT_ENA (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_ENA_M (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_ENA_V 0x1
#define RTC_I2C_TRANS_COMPLETE_INT_ENA_S 3
/* RTC_I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: enable master transit complete interrupt*/
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S 2
/* RTC_I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: enable arbitration lost interrupt*/
#define RTC_I2C_ARBITRATION_LOST_INT_ENA (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_ENA_M (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_ENA_V 0x1
#define RTC_I2C_ARBITRATION_LOST_INT_ENA_S 1
/* RTC_I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: enable slave transit complete interrupt*/
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S 0
#define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x0034)
/* RTC_I2C_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: i2c done*/
#define RTC_I2C_DONE (BIT(31))
#define RTC_I2C_DONE_M (BIT(31))
#define RTC_I2C_DONE_V 0x1
#define RTC_I2C_DONE_S 31
/* RTC_I2C_SLAVE_TX_DATA : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
/*description: data sent by slave*/
#define RTC_I2C_SLAVE_TX_DATA 0x000000FF
#define RTC_I2C_SLAVE_TX_DATA_M ((RTC_I2C_SLAVE_TX_DATA_V)<<(RTC_I2C_SLAVE_TX_DATA_S))
#define RTC_I2C_SLAVE_TX_DATA_V 0xFF
#define RTC_I2C_SLAVE_TX_DATA_S 8
/* RTC_I2C_RDATA : RO ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: data received*/
#define RTC_I2C_RDATA 0x000000FF
#define RTC_I2C_RDATA_M ((RTC_I2C_RDATA_V)<<(RTC_I2C_RDATA_S))
#define RTC_I2C_RDATA_V 0xFF
#define RTC_I2C_RDATA_S 0
#define RTC_I2C_CMD0_REG (DR_REG_RTC_I2C_BASE + 0x0038)
/* RTC_I2C_COMMAND0_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command0_done*/
#define RTC_I2C_COMMAND0_DONE (BIT(31))
#define RTC_I2C_COMMAND0_DONE_M (BIT(31))
#define RTC_I2C_COMMAND0_DONE_V 0x1
#define RTC_I2C_COMMAND0_DONE_S 31
/* RTC_I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */
/*description: command0*/
#define RTC_I2C_COMMAND0 0x00003FFF
#define RTC_I2C_COMMAND0_M ((RTC_I2C_COMMAND0_V)<<(RTC_I2C_COMMAND0_S))
#define RTC_I2C_COMMAND0_V 0x3FFF
#define RTC_I2C_COMMAND0_S 0
#define RTC_I2C_CMD1_REG (DR_REG_RTC_I2C_BASE + 0x003c)
/* RTC_I2C_COMMAND1_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command1_done*/
#define RTC_I2C_COMMAND1_DONE (BIT(31))
#define RTC_I2C_COMMAND1_DONE_M (BIT(31))
#define RTC_I2C_COMMAND1_DONE_V 0x1
#define RTC_I2C_COMMAND1_DONE_S 31
/* RTC_I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
/*description: command1*/
#define RTC_I2C_COMMAND1 0x00003FFF
#define RTC_I2C_COMMAND1_M ((RTC_I2C_COMMAND1_V)<<(RTC_I2C_COMMAND1_S))
#define RTC_I2C_COMMAND1_V 0x3FFF
#define RTC_I2C_COMMAND1_S 0
#define RTC_I2C_CMD2_REG (DR_REG_RTC_I2C_BASE + 0x0040)
/* RTC_I2C_COMMAND2_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command2_done*/
#define RTC_I2C_COMMAND2_DONE (BIT(31))
#define RTC_I2C_COMMAND2_DONE_M (BIT(31))
#define RTC_I2C_COMMAND2_DONE_V 0x1
#define RTC_I2C_COMMAND2_DONE_S 31
/* RTC_I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'h0902 ; */
/*description: command2*/
#define RTC_I2C_COMMAND2 0x00003FFF
#define RTC_I2C_COMMAND2_M ((RTC_I2C_COMMAND2_V)<<(RTC_I2C_COMMAND2_S))
#define RTC_I2C_COMMAND2_V 0x3FFF
#define RTC_I2C_COMMAND2_S 0
#define RTC_I2C_CMD3_REG (DR_REG_RTC_I2C_BASE + 0x0044)
/* RTC_I2C_COMMAND3_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command3_done*/
#define RTC_I2C_COMMAND3_DONE (BIT(31))
#define RTC_I2C_COMMAND3_DONE_M (BIT(31))
#define RTC_I2C_COMMAND3_DONE_V 0x1
#define RTC_I2C_COMMAND3_DONE_S 31
/* RTC_I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */
/*description: command3*/
#define RTC_I2C_COMMAND3 0x00003FFF
#define RTC_I2C_COMMAND3_M ((RTC_I2C_COMMAND3_V)<<(RTC_I2C_COMMAND3_S))
#define RTC_I2C_COMMAND3_V 0x3FFF
#define RTC_I2C_COMMAND3_S 0
#define RTC_I2C_CMD4_REG (DR_REG_RTC_I2C_BASE + 0x0048)
/* RTC_I2C_COMMAND4_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command4_done*/
#define RTC_I2C_COMMAND4_DONE (BIT(31))
#define RTC_I2C_COMMAND4_DONE_M (BIT(31))
#define RTC_I2C_COMMAND4_DONE_V 0x1
#define RTC_I2C_COMMAND4_DONE_S 31
/* RTC_I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */
/*description: command4*/
#define RTC_I2C_COMMAND4 0x00003FFF
#define RTC_I2C_COMMAND4_M ((RTC_I2C_COMMAND4_V)<<(RTC_I2C_COMMAND4_S))
#define RTC_I2C_COMMAND4_V 0x3FFF
#define RTC_I2C_COMMAND4_S 0
#define RTC_I2C_CMD5_REG (DR_REG_RTC_I2C_BASE + 0x004c)
/* RTC_I2C_COMMAND5_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command5_done*/
#define RTC_I2C_COMMAND5_DONE (BIT(31))
#define RTC_I2C_COMMAND5_DONE_M (BIT(31))
#define RTC_I2C_COMMAND5_DONE_V 0x1
#define RTC_I2C_COMMAND5_DONE_S 31
/* RTC_I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */
/*description: command5*/
#define RTC_I2C_COMMAND5 0x00003FFF
#define RTC_I2C_COMMAND5_M ((RTC_I2C_COMMAND5_V)<<(RTC_I2C_COMMAND5_S))
#define RTC_I2C_COMMAND5_V 0x3FFF
#define RTC_I2C_COMMAND5_S 0
#define RTC_I2C_CMD6_REG (DR_REG_RTC_I2C_BASE + 0x0050)
/* RTC_I2C_COMMAND6_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command6_done*/
#define RTC_I2C_COMMAND6_DONE (BIT(31))
#define RTC_I2C_COMMAND6_DONE_M (BIT(31))
#define RTC_I2C_COMMAND6_DONE_V 0x1
#define RTC_I2C_COMMAND6_DONE_S 31
/* RTC_I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
/*description: command6*/
#define RTC_I2C_COMMAND6 0x00003FFF
#define RTC_I2C_COMMAND6_M ((RTC_I2C_COMMAND6_V)<<(RTC_I2C_COMMAND6_S))
#define RTC_I2C_COMMAND6_V 0x3FFF
#define RTC_I2C_COMMAND6_S 0
#define RTC_I2C_CMD7_REG (DR_REG_RTC_I2C_BASE + 0x0054)
/* RTC_I2C_COMMAND7_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command7_done*/
#define RTC_I2C_COMMAND7_DONE (BIT(31))
#define RTC_I2C_COMMAND7_DONE_M (BIT(31))
#define RTC_I2C_COMMAND7_DONE_V 0x1
#define RTC_I2C_COMMAND7_DONE_S 31
/* RTC_I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'h0904 ; */
/*description: command7*/
#define RTC_I2C_COMMAND7 0x00003FFF
#define RTC_I2C_COMMAND7_M ((RTC_I2C_COMMAND7_V)<<(RTC_I2C_COMMAND7_S))
#define RTC_I2C_COMMAND7_V 0x3FFF
#define RTC_I2C_COMMAND7_S 0
#define RTC_I2C_CMD8_REG (DR_REG_RTC_I2C_BASE + 0x0058)
/* RTC_I2C_COMMAND8_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command8_done*/
#define RTC_I2C_COMMAND8_DONE (BIT(31))
#define RTC_I2C_COMMAND8_DONE_M (BIT(31))
#define RTC_I2C_COMMAND8_DONE_V 0x1
#define RTC_I2C_COMMAND8_DONE_S 31
/* RTC_I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
/*description: command8*/
#define RTC_I2C_COMMAND8 0x00003FFF
#define RTC_I2C_COMMAND8_M ((RTC_I2C_COMMAND8_V)<<(RTC_I2C_COMMAND8_S))
#define RTC_I2C_COMMAND8_V 0x3FFF
#define RTC_I2C_COMMAND8_S 0
#define RTC_I2C_CMD9_REG (DR_REG_RTC_I2C_BASE + 0x005c)
/* RTC_I2C_COMMAND9_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command9_done*/
#define RTC_I2C_COMMAND9_DONE (BIT(31))
#define RTC_I2C_COMMAND9_DONE_M (BIT(31))
#define RTC_I2C_COMMAND9_DONE_V 0x1
#define RTC_I2C_COMMAND9_DONE_S 31
/* RTC_I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */
/*description: command9*/
#define RTC_I2C_COMMAND9 0x00003FFF
#define RTC_I2C_COMMAND9_M ((RTC_I2C_COMMAND9_V)<<(RTC_I2C_COMMAND9_S))
#define RTC_I2C_COMMAND9_V 0x3FFF
#define RTC_I2C_COMMAND9_S 0
#define RTC_I2C_CMD10_REG (DR_REG_RTC_I2C_BASE + 0x0060)
/* RTC_I2C_COMMAND10_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command10_done*/
#define RTC_I2C_COMMAND10_DONE (BIT(31))
#define RTC_I2C_COMMAND10_DONE_M (BIT(31))
#define RTC_I2C_COMMAND10_DONE_V 0x1
#define RTC_I2C_COMMAND10_DONE_S 31
/* RTC_I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */
/*description: command10*/
#define RTC_I2C_COMMAND10 0x00003FFF
#define RTC_I2C_COMMAND10_M ((RTC_I2C_COMMAND10_V)<<(RTC_I2C_COMMAND10_S))
#define RTC_I2C_COMMAND10_V 0x3FFF
#define RTC_I2C_COMMAND10_S 0
#define RTC_I2C_CMD11_REG (DR_REG_RTC_I2C_BASE + 0x0064)
/* RTC_I2C_COMMAND11_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command11_done*/
#define RTC_I2C_COMMAND11_DONE (BIT(31))
#define RTC_I2C_COMMAND11_DONE_M (BIT(31))
#define RTC_I2C_COMMAND11_DONE_V 0x1
#define RTC_I2C_COMMAND11_DONE_S 31
/* RTC_I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */
/*description: command11*/
#define RTC_I2C_COMMAND11 0x00003FFF
#define RTC_I2C_COMMAND11_M ((RTC_I2C_COMMAND11_V)<<(RTC_I2C_COMMAND11_S))
#define RTC_I2C_COMMAND11_V 0x3FFF
#define RTC_I2C_COMMAND11_S 0
#define RTC_I2C_CMD12_REG (DR_REG_RTC_I2C_BASE + 0x0068)
/* RTC_I2C_COMMAND12_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command12_done*/
#define RTC_I2C_COMMAND12_DONE (BIT(31))
#define RTC_I2C_COMMAND12_DONE_M (BIT(31))
#define RTC_I2C_COMMAND12_DONE_V 0x1
#define RTC_I2C_COMMAND12_DONE_S 31
/* RTC_I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */
/*description: command12*/
#define RTC_I2C_COMMAND12 0x00003FFF
#define RTC_I2C_COMMAND12_M ((RTC_I2C_COMMAND12_V)<<(RTC_I2C_COMMAND12_S))
#define RTC_I2C_COMMAND12_V 0x3FFF
#define RTC_I2C_COMMAND12_S 0
#define RTC_I2C_CMD13_REG (DR_REG_RTC_I2C_BASE + 0x006c)
/* RTC_I2C_COMMAND13_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command13_done*/
#define RTC_I2C_COMMAND13_DONE (BIT(31))
#define RTC_I2C_COMMAND13_DONE_M (BIT(31))
#define RTC_I2C_COMMAND13_DONE_V 0x1
#define RTC_I2C_COMMAND13_DONE_S 31
/* RTC_I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
/*description: command13*/
#define RTC_I2C_COMMAND13 0x00003FFF
#define RTC_I2C_COMMAND13_M ((RTC_I2C_COMMAND13_V)<<(RTC_I2C_COMMAND13_S))
#define RTC_I2C_COMMAND13_V 0x3FFF
#define RTC_I2C_COMMAND13_S 0
#define RTC_I2C_CMD14_REG (DR_REG_RTC_I2C_BASE + 0x0070)
/* RTC_I2C_COMMAND14_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command14_done*/
#define RTC_I2C_COMMAND14_DONE (BIT(31))
#define RTC_I2C_COMMAND14_DONE_M (BIT(31))
#define RTC_I2C_COMMAND14_DONE_V 0x1
#define RTC_I2C_COMMAND14_DONE_S 31
/* RTC_I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
/*description: command14*/
#define RTC_I2C_COMMAND14 0x00003FFF
#define RTC_I2C_COMMAND14_M ((RTC_I2C_COMMAND14_V)<<(RTC_I2C_COMMAND14_S))
#define RTC_I2C_COMMAND14_V 0x3FFF
#define RTC_I2C_COMMAND14_S 0
#define RTC_I2C_CMD15_REG (DR_REG_RTC_I2C_BASE + 0x0074)
/* RTC_I2C_COMMAND15_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command15_done*/
#define RTC_I2C_COMMAND15_DONE (BIT(31))
#define RTC_I2C_COMMAND15_DONE_M (BIT(31))
#define RTC_I2C_COMMAND15_DONE_V 0x1
#define RTC_I2C_COMMAND15_DONE_S 31
/* RTC_I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
/*description: command15*/
#define RTC_I2C_COMMAND15 0x00003FFF
#define RTC_I2C_COMMAND15_M ((RTC_I2C_COMMAND15_V)<<(RTC_I2C_COMMAND15_S))
#define RTC_I2C_COMMAND15_V 0x3FFF
#define RTC_I2C_COMMAND15_S 0
#define RTC_I2C_DATE_REG (DR_REG_RTC_I2C_BASE + 0x00FC)
/* RTC_I2C_DATE : R/W ;bitpos:[27:0] ;default: 28'h1711170 ; */
/*description: */
#define RTC_I2C_DATE 0x0FFFFFFF
#define RTC_I2C_DATE_M ((RTC_I2C_DATE_V)<<(RTC_I2C_DATE_S))
#define RTC_I2C_DATE_V 0xFFFFFFF
#define RTC_I2C_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_RTC_I2C_REG_H_ */

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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_RTC_I2C_STRUCT_H_
#define _SOC_RTC_I2C_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t period: 20; /*time period that scl = 0*/
uint32_t reserved20: 12;
};
uint32_t val;
} scl_low;
union {
struct {
uint32_t sda_force_out: 1; /*1=push pull 0=open drain*/
uint32_t scl_force_out: 1; /*1=push pull 0=open drain*/
uint32_t ms_mode: 1; /*1=master 0=slave*/
uint32_t trans_start: 1; /*force start*/
uint32_t tx_lsb_first: 1; /*transit lsb first*/
uint32_t rx_lsb_first: 1; /*receive lsb first*/
uint32_t reserved6: 24;
uint32_t i2c_reset: 1; /*rtc i2c sw reset*/
uint32_t i2cclk_en: 1; /*rtc i2c reg clk gating*/
};
uint32_t val;
} ctrl;
union {
struct {
uint32_t ack_rec: 1; /*ack response*/
uint32_t slave_rw: 1; /*slave read or write*/
uint32_t arb_lost: 1; /*arbitration is lost*/
uint32_t bus_busy: 1; /*bus is busy*/
uint32_t slave_addressed: 1; /*slave reg sub address*/
uint32_t byte_trans: 1; /*One byte transit done*/
uint32_t op_cnt: 2; /*which operation is working*/
uint32_t reserved8: 8;
uint32_t shift: 8; /*shifter content*/
uint32_t scl_main_state_last: 3; /*i2c last main status*/
uint32_t reserved27: 1;
uint32_t scl_state_last: 3; /*scl last status*/
uint32_t reserved31: 1;
};
uint32_t val;
} status;
union {
struct {
uint32_t time_out: 20; /*time out threshold*/
uint32_t reserved20:12;
};
uint32_t val;
} timeout;
union {
struct {
uint32_t addr: 15; /*slave address*/
uint32_t reserved15: 16;
uint32_t en_10bit: 1; /*i2c 10bit mode enable*/
};
uint32_t val;
} slave_addr;
union {
struct {
uint32_t period: 20; /*time period that scl = 1*/
uint32_t reserved20: 12;
};
uint32_t val;
} scl_high;
union {
struct {
uint32_t sda_duty_num:20; /*time period for SDA to toggle after SCL goes low*/
uint32_t reserved20: 12;
};
uint32_t val;
} sda_duty;
union {
struct {
uint32_t scl_start_period:20; /*time period for SCL to toggle after I2C start is triggered*/
uint32_t reserved20: 12;
};
uint32_t val;
} scl_start_period;
union {
struct {
uint32_t scl_stop_period:20; /*time period for SCL to stop after I2C end is triggered*/
uint32_t reserved20: 12;
};
uint32_t val;
} scl_stop_period;
union {
struct {
uint32_t slave_tran_comp: 1; /*clear slave transit complete interrupt*/
uint32_t arbitration_lost: 1; /*clear arbitration lost interrupt*/
uint32_t master_tran_comp: 1; /*clear master transit complete interrupt*/
uint32_t trans_complete: 1; /*clear transit complete interrupt*/
uint32_t time_out: 1; /*clear time out interrupt*/
uint32_t ack_err: 1; /*clear ack error interrupt*/
uint32_t rx_data: 1; /*clear receive data interrupt*/
uint32_t tx_data: 1; /*clear transit load data complete interrupt*/
uint32_t detect_start: 1; /*clear detect start interrupt*/
uint32_t reserved9: 23;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t slave_tran_comp: 1; /*slave transit complete interrupt raw*/
uint32_t arbitration_lost: 1; /*arbitration lost interrupt raw*/
uint32_t master_tran_comp: 1; /*master transit complete interrupt raw*/
uint32_t trans_complete: 1; /*transit complete interrupt raw*/
uint32_t time_out: 1; /*time out interrupt raw*/
uint32_t ack_err: 1; /*ack error interrupt raw*/
uint32_t rx_data: 1; /*receive data interrupt raw*/
uint32_t tx_data: 1; /*transit data interrupt raw*/
uint32_t detect_start: 1; /*detect start interrupt raw*/
uint32_t reserved9: 23;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t slave_tran_comp: 1; /*slave transit complete interrupt state*/
uint32_t arbitration_lost: 1; /*arbitration lost interrupt state*/
uint32_t master_tran_comp: 1; /*master transit complete interrupt state*/
uint32_t trans_complete: 1; /*transit complete interrupt state*/
uint32_t time_out: 1; /*time out interrupt state*/
uint32_t ack_err: 1; /*ack error interrupt state*/
uint32_t rx_data: 1; /*receive data interrupt state*/
uint32_t tx_data: 1; /*transit data interrupt state*/
uint32_t detect_start: 1; /*detect start interrupt state*/
uint32_t reserved9: 23;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t slave_tran_comp: 1; /*enable slave transit complete interrupt*/
uint32_t arbitration_lost: 1; /*enable arbitration lost interrupt*/
uint32_t master_tran_comp: 1; /*enable master transit complete interrupt*/
uint32_t trans_complete: 1; /*enable transit complete interrupt*/
uint32_t time_out: 1; /*enable time out interrupt*/
uint32_t ack_err: 1; /*enable eack error interrupt*/
uint32_t rx_data: 1; /*enable receive data interrupt*/
uint32_t tx_data: 1; /*enable transit data interrupt*/
uint32_t detect_start: 1; /*enable detect start interrupt*/
uint32_t reserved9: 23;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t i2c_rdata: 8; /*data received*/
uint32_t slave_tx_data: 8; /*data sent by slave*/
uint32_t reserved16: 15;
uint32_t i2c_done: 1; /*i2c done*/
};
uint32_t val;
} fifo_data;
union {
struct {
uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/
uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/
uint32_t reserved14: 17;
uint32_t done: 1; /*command0_done*/
};
uint32_t val;
} command[16];
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
union {
struct {
uint32_t i2c_date: 28;
uint32_t reserved28: 4;
};
uint32_t val;
} date;
} rtc_i2c_dev_t;
extern rtc_i2c_dev_t RTC_I2C;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_RTC_I2C_STRUCT_H_ */

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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_RTC_IO_STRUCT_H_
#define _SOC_RTC_IO_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t reserved0: 10;
uint32_t data: 22; /*RTC GPIO 0 ~ 21 output data*/
};
uint32_t val;
} out;
union {
struct {
uint32_t reserved0: 10;
uint32_t w1ts: 22; /*RTC GPIO 0 ~ 21 output data write 1 to set*/
};
uint32_t val;
} out_w1ts;
union {
struct {
uint32_t reserved0: 10;
uint32_t w1tc: 22; /*RTC GPIO 0 ~ 21 output data write 1 to clear*/
};
uint32_t val;
} out_w1tc;
union {
struct {
uint32_t reserved0: 10;
uint32_t enable: 22; /*RTC GPIO 0 ~ 21 enable*/
};
uint32_t val;
} enable;
union {
struct {
uint32_t reserved0: 10;
uint32_t w1ts: 22; /*RTC GPIO 0 ~ 21 enable write 1 to set*/
};
uint32_t val;
} enable_w1ts;
union {
struct {
uint32_t reserved0: 10;
uint32_t w1tc: 22; /*RTC GPIO 0 ~ 21 enable write 1 to clear*/
};
uint32_t val;
} enable_w1tc;
union {
struct {
uint32_t reserved0: 10;
uint32_t status: 22; /*RTC GPIO 0 ~ 21 interrupt status*/
};
uint32_t val;
} status;
union {
struct {
uint32_t reserved0: 10;
uint32_t w1ts: 22; /*RTC GPIO 0 ~ 21 interrupt status write 1 to set*/
};
uint32_t val;
} status_w1ts;
union {
struct {
uint32_t reserved0: 10;
uint32_t w1tc: 22; /*RTC GPIO 0 ~ 21 interrupt status write 1 to clear*/
};
uint32_t val;
} status_w1tc;
union {
struct {
uint32_t reserved0: 10;
uint32_t in: 22; /*RTC GPIO input data*/
};
uint32_t val;
} in_val;
union {
struct {
uint32_t reserved0: 2;
uint32_t pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/
uint32_t reserved3: 4;
uint32_t int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
uint32_t wakeup_enable: 1; /*RTC GPIO wakeup enable bit*/
uint32_t reserved11: 21;
};
uint32_t val;
} pin[21];
union {
struct {
uint32_t reserved0: 2;
uint32_t rtc_gpio_pin21_pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/
uint32_t reserved3: 4;
uint32_t rtc_gpio_pin21_int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
uint32_t rtc_gpio_pin21_wakeup_enable: 1; /*RTC GPIO wakeup enable bit*/
uint32_t reserved11: 21;
};
uint32_t val;
} pin21;
union {
struct {
uint32_t sel0: 5;
uint32_t sel1: 5;
uint32_t sel2: 5;
uint32_t sel3: 5;
uint32_t sel4: 5;
uint32_t no_gating_12m: 1;
uint32_t reserved26: 6;
};
uint32_t val;
} debug_sel;
union {
struct {
uint32_t reserved0: 13;
uint32_t fun_ie: 1; /*input enable in work mode*/
uint32_t slp_oe: 1; /*output enable in sleep mode*/
uint32_t slp_ie: 1; /*input enable in sleep mode*/
uint32_t slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
uint32_t fun_sel: 2; /*function sel*/
uint32_t mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
uint32_t xpd: 1; /*TOUCH_XPD*/
uint32_t tie_opt: 1; /*TOUCH_TIE_OPT*/
uint32_t start: 1; /*TOUCH_START*/
uint32_t dac: 3; /*TOUCH_DAC*/
uint32_t reserved26: 1;
uint32_t rue: 1; /*RUE*/
uint32_t rde: 1; /*RDE*/
uint32_t drv: 2; /*DRV*/
uint32_t reserved31: 1;
};
uint32_t val;
} touch_pad[15];
union {
struct {
uint32_t reserved0: 13;
uint32_t x32p_fun_ie: 1; /*input enable in work mode*/
uint32_t x32p_slp_oe: 1; /*output enable in sleep mode*/
uint32_t x32p_slp_ie: 1; /*input enable in sleep mode*/
uint32_t x32p_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
uint32_t x32p_fun_sel: 2; /*function sel*/
uint32_t x32p_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
uint32_t reserved20: 7;
uint32_t x32p_rue: 1; /*RUE*/
uint32_t x32p_rde: 1; /*RDE*/
uint32_t x32p_drv: 2; /*DRV*/
uint32_t reserved31: 1;
};
uint32_t val;
} xtal_32p_pad;
union {
struct {
uint32_t reserved0: 13;
uint32_t x32n_fun_ie: 1; /*input enable in work mode*/
uint32_t x32n_slp_oe: 1; /*output enable in sleep mode*/
uint32_t x32n_slp_ie: 1; /*input enable in sleep mode*/
uint32_t x32n_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
uint32_t x32n_fun_sel: 2; /*function sel*/
uint32_t x32n_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
uint32_t reserved20: 7;
uint32_t x32n_rue: 1; /*RUE*/
uint32_t x32n_rde: 1; /*RDE*/
uint32_t x32n_drv: 2; /*DRV*/
uint32_t reserved31: 1;
};
uint32_t val;
} xtal_32n_pad;
union {
struct {
uint32_t reserved0: 3;
uint32_t dac: 8; /*PDAC1_DAC*/
uint32_t xpd_dac: 1; /*PDAC1_XPD_DAC*/
uint32_t dac_xpd_force: 1; /*1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC 0: use SAR ADC FSM to control PDAC1_XPD_DAC*/
uint32_t fun_ie: 1; /*input enable in work mode*/
uint32_t slp_oe: 1; /*output enable in sleep mode*/
uint32_t slp_ie: 1; /*input enable in sleep mode*/
uint32_t slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
uint32_t fun_sel: 2; /*PDAC1 function sel*/
uint32_t mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
uint32_t reserved20: 7;
uint32_t rue: 1; /*PDAC1_RUE*/
uint32_t rde: 1; /*PDAC1_RDE*/
uint32_t drv: 2; /*PDAC1_DRV*/
uint32_t reserved31: 1;
};
uint32_t val;
} pad_dac[2];
union {
struct {
uint32_t reserved0: 13;
uint32_t rtc_pad19_fun_ie: 1; /*input enable in work mode*/
uint32_t rtc_pad19_slp_oe: 1; /*output enable in sleep mode*/
uint32_t rtc_pad19_slp_ie: 1; /*input enable in sleep mode*/
uint32_t rtc_pad19_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
uint32_t rtc_pad19_fun_sel: 2; /*function sel*/
uint32_t rtc_pad19_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
uint32_t reserved20: 7;
uint32_t rtc_pad19_rue: 1; /*RUE*/
uint32_t rtc_pad19_rde: 1; /*RDE*/
uint32_t rtc_pad19_drv: 2; /*DRV*/
uint32_t reserved31: 1;
};
uint32_t val;
} rtc_pad19;
union {
struct {
uint32_t reserved0: 13;
uint32_t rtc_pad20_fun_ie: 1; /*input enable in work mode*/
uint32_t rtc_pad20_slp_oe: 1; /*output enable in sleep mode*/
uint32_t rtc_pad20_slp_ie: 1; /*input enable in sleep mode*/
uint32_t rtc_pad20_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
uint32_t rtc_pad20_fun_sel: 2; /*function sel*/
uint32_t rtc_pad20_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
uint32_t reserved20: 7;
uint32_t rtc_pad20_rue: 1; /*RUE*/
uint32_t rtc_pad20_rde: 1; /*RDE*/
uint32_t rtc_pad20_drv: 2; /*DRV*/
uint32_t reserved31: 1;
};
uint32_t val;
} rtc_pad20;
union {
struct {
uint32_t reserved0: 13;
uint32_t rtc_pad21_fun_ie: 1; /*input enable in work mode*/
uint32_t rtc_pad21_slp_oe: 1; /*output enable in sleep mode*/
uint32_t rtc_pad21_slp_ie: 1; /*input enable in sleep mode*/
uint32_t rtc_pad21_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
uint32_t rtc_pad21_fun_sel: 2; /*function sel*/
uint32_t rtc_pad21_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
uint32_t reserved20: 7;
uint32_t rtc_pad21_rue: 1; /*RUE*/
uint32_t rtc_pad21_rde: 1; /*RDE*/
uint32_t rtc_pad21_drv: 2; /*DRV*/
uint32_t reserved31: 1;
};
uint32_t val;
} rtc_pad21;
union {
struct {
uint32_t reserved0: 27;
uint32_t sel: 5;
};
uint32_t val;
} ext_wakeup0;
union {
struct {
uint32_t reserved0: 27;
uint32_t sel: 5; /*select RTC GPIO 0 ~ 17 to control XTAL*/
};
uint32_t val;
} xtl_ext_ctr;
union {
struct {
uint32_t reserved0: 23;
uint32_t debug_bit_sel: 5;
uint32_t scl_sel: 2;
uint32_t sda_sel: 2;
};
uint32_t val;
} sar_i2c_io;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t reserved_fc;
uint32_t reserved_100;
uint32_t reserved_104;
uint32_t reserved_108;
uint32_t reserved_10c;
uint32_t reserved_110;
uint32_t reserved_114;
uint32_t reserved_118;
uint32_t reserved_11c;
uint32_t reserved_120;
uint32_t reserved_124;
uint32_t reserved_128;
uint32_t reserved_12c;
uint32_t reserved_130;
uint32_t reserved_134;
uint32_t reserved_138;
uint32_t reserved_13c;
uint32_t reserved_140;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
union {
struct {
uint32_t date: 28;
uint32_t reserved28: 4;
};
uint32_t val;
} date;
} rtc_io_dev_t;
extern rtc_io_dev_t RTCIO;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_RTC_IO_STRUCT_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SDMMC_REG_H_
#define _SOC_SDMMC_REG_H_
#include "soc.h"
#define SDMMC_CTRL_REG (DR_REG_SDMMC_BASE + 0x00)
#define SDMMC_PWREN_REG (DR_REG_SDMMC_BASE + 0x04)
#define SDMMC_CLKDIV_REG (DR_REG_SDMMC_BASE + 0x08)
#define SDMMC_CLKSRC_REG (DR_REG_SDMMC_BASE + 0x0c)
#define SDMMC_CLKENA_REG (DR_REG_SDMMC_BASE + 0x10)
#define SDMMC_TMOUT_REG (DR_REG_SDMMC_BASE + 0x14)
#define SDMMC_CTYPE_REG (DR_REG_SDMMC_BASE + 0x18)
#define SDMMC_BLKSIZ_REG (DR_REG_SDMMC_BASE + 0x1c)
#define SDMMC_BYTCNT_REG (DR_REG_SDMMC_BASE + 0x20)
#define SDMMC_INTMASK_REG (DR_REG_SDMMC_BASE + 0x24)
#define SDMMC_CMDARG_REG (DR_REG_SDMMC_BASE + 0x28)
#define SDMMC_CMD_REG (DR_REG_SDMMC_BASE + 0x2c)
#define SDMMC_RESP0_REG (DR_REG_SDMMC_BASE + 0x30)
#define SDMMC_RESP1_REG (DR_REG_SDMMC_BASE + 0x34)
#define SDMMC_RESP2_REG (DR_REG_SDMMC_BASE + 0x38)
#define SDMMC_RESP3_REG (DR_REG_SDMMC_BASE + 0x3c)
#define SDMMC_MINTSTS_REG (DR_REG_SDMMC_BASE + 0x40)
#define SDMMC_RINTSTS_REG (DR_REG_SDMMC_BASE + 0x44)
#define SDMMC_STATUS_REG (DR_REG_SDMMC_BASE + 0x48)
#define SDMMC_FIFOTH_REG (DR_REG_SDMMC_BASE + 0x4c)
#define SDMMC_CDETECT_REG (DR_REG_SDMMC_BASE + 0x50)
#define SDMMC_WRTPRT_REG (DR_REG_SDMMC_BASE + 0x54)
#define SDMMC_GPIO_REG (DR_REG_SDMMC_BASE + 0x58)
#define SDMMC_TCBCNT_REG (DR_REG_SDMMC_BASE + 0x5c)
#define SDMMC_TBBCNT_REG (DR_REG_SDMMC_BASE + 0x60)
#define SDMMC_DEBNCE_REG (DR_REG_SDMMC_BASE + 0x64)
#define SDMMC_USRID_REG (DR_REG_SDMMC_BASE + 0x68)
#define SDMMC_VERID_REG (DR_REG_SDMMC_BASE + 0x6c)
#define SDMMC_HCON_REG (DR_REG_SDMMC_BASE + 0x70)
#define SDMMC_UHS_REG_REG (DR_REG_SDMMC_BASE + 0x74)
#define SDMMC_RST_N_REG (DR_REG_SDMMC_BASE + 0x78)
#define SDMMC_BMOD_REG (DR_REG_SDMMC_BASE + 0x80)
#define SDMMC_PLDMND_REG (DR_REG_SDMMC_BASE + 0x84)
#define SDMMC_DBADDR_REG (DR_REG_SDMMC_BASE + 0x88)
#define SDMMC_DBADDRU_REG (DR_REG_SDMMC_BASE + 0x8c)
#define SDMMC_IDSTS_REG (DR_REG_SDMMC_BASE + 0x8c)
#define SDMMC_IDINTEN_REG (DR_REG_SDMMC_BASE + 0x90)
#define SDMMC_DSCADDR_REG (DR_REG_SDMMC_BASE + 0x94)
#define SDMMC_DSCADDRL_REG (DR_REG_SDMMC_BASE + 0x98)
#define SDMMC_DSCADDRU_REG (DR_REG_SDMMC_BASE + 0x9c)
#define SDMMC_BUFADDRL_REG (DR_REG_SDMMC_BASE + 0xa0)
#define SDMMC_BUFADDRU_REG (DR_REG_SDMMC_BASE + 0xa4)
#define SDMMC_CARDTHRCTL_REG (DR_REG_SDMMC_BASE + 0x100)
#define SDMMC_BACK_END_POWER_REG (DR_REG_SDMMC_BASE + 0x104)
#define SDMMC_UHS_REG_EXT_REG (DR_REG_SDMMC_BASE + 0x108)
#define SDMMC_EMMC_DDR_REG_REG (DR_REG_SDMMC_BASE + 0x10c)
#define SDMMC_ENABLE_SHIFT_REG (DR_REG_SDMMC_BASE + 0x110)
#define SDMMC_CLOCK_REG (DR_REG_SDMMC_BASE + 0x800)
#define SDMMC_INTMASK_IO_SLOT1 BIT(17)
#define SDMMC_INTMASK_IO_SLOT0 BIT(16)
#define SDMMC_INTMASK_EBE BIT(15)
#define SDMMC_INTMASK_ACD BIT(14)
#define SDMMC_INTMASK_SBE BIT(13)
#define SDMMC_INTMASK_HLE BIT(12)
#define SDMMC_INTMASK_FRUN BIT(11)
#define SDMMC_INTMASK_HTO BIT(10)
#define SDMMC_INTMASK_DTO BIT(9)
#define SDMMC_INTMASK_RTO BIT(8)
#define SDMMC_INTMASK_DCRC BIT(7)
#define SDMMC_INTMASK_RCRC BIT(6)
#define SDMMC_INTMASK_RXDR BIT(5)
#define SDMMC_INTMASK_TXDR BIT(4)
#define SDMMC_INTMASK_DATA_OVER BIT(3)
#define SDMMC_INTMASK_CMD_DONE BIT(2)
#define SDMMC_INTMASK_RESP_ERR BIT(1)
#define SDMMC_INTMASK_CD BIT(0)
#define SDMMC_IDMAC_INTMASK_AI BIT(9)
#define SDMMC_IDMAC_INTMASK_NI BIT(8)
#define SDMMC_IDMAC_INTMASK_CES BIT(5)
#define SDMMC_IDMAC_INTMASK_DU BIT(4)
#define SDMMC_IDMAC_INTMASK_FBE BIT(2)
#define SDMMC_IDMAC_INTMASK_RI BIT(1)
#define SDMMC_IDMAC_INTMASK_TI BIT(0)
#endif /* _SOC_SDMMC_REG_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SDMMC_STRUCT_H_
#define _SOC_SDMMC_STRUCT_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
uint32_t reserved1: 1;
uint32_t disable_int_on_completion: 1;
uint32_t last_descriptor: 1;
uint32_t first_descriptor: 1;
uint32_t second_address_chained: 1;
uint32_t end_of_ring: 1;
uint32_t reserved2: 24;
uint32_t card_error_summary: 1;
uint32_t owned_by_idmac: 1;
uint32_t buffer1_size: 13;
uint32_t buffer2_size: 13;
uint32_t reserved3: 6;
void* buffer1_ptr;
union {
void* buffer2_ptr;
void* next_desc_ptr;
};
} sdmmc_desc_t;
#define SDMMC_DMA_MAX_BUF_LEN 4096
_Static_assert(sizeof(sdmmc_desc_t) == 16, "invalid size of sdmmc_desc_t structure");
typedef struct {
uint32_t cmd_index: 6; ///< Command index
uint32_t response_expect: 1; ///< set if response is expected
uint32_t response_long: 1; ///< 0: short response expected, 1: long response expected
uint32_t check_response_crc: 1; ///< set if controller should check response CRC
uint32_t data_expected: 1; ///< 0: no data expected, 1: data expected
uint32_t rw: 1; ///< 0: read from card, 1: write to card (don't care if no data expected)
uint32_t stream_mode: 1; ///< 0: block transfer, 1: stream transfer (don't care if no data expected)
uint32_t send_auto_stop: 1; ///< set to send stop at the end of the transfer
uint32_t wait_complete: 1; ///< 0: send command at once, 1: wait for previous command to complete
uint32_t stop_abort_cmd: 1; ///< set if this is a stop or abort command intended to stop current transfer
uint32_t send_init: 1; ///< set to send init sequence (80 clocks of 1)
uint32_t card_num: 5; ///< card number
uint32_t update_clk_reg: 1; ///< 0: normal command, 1: don't send command, just update clock registers
uint32_t read_ceata: 1; ///< set if performing read from CE-ATA device
uint32_t ccs_expected: 1; ///< set if CCS is expected from CE-ATA device
uint32_t enable_boot: 1; ///< set for mandatory boot mode
uint32_t expect_boot_ack: 1; ///< when set along with enable_boot, controller expects boot ack pattern
uint32_t disable_boot: 1; ///< set to terminate boot operation (don't set along with enable_boot)
uint32_t boot_mode: 1; ///< 0: mandatory boot operation, 1: alternate boot operation
uint32_t volt_switch: 1; ///< set to enable voltage switching (for CMD11 only)
uint32_t use_hold_reg: 1; ///< clear to bypass HOLD register
uint32_t reserved: 1;
uint32_t start_command: 1; ///< Start command; once command is sent to the card, bit is cleared.
} sdmmc_hw_cmd_t; ///< command format used in cmd register; this structure is defined to make it easier to build command values
_Static_assert(sizeof(sdmmc_hw_cmd_t) == 4, "invalid size of sdmmc_cmd_t structure");
typedef volatile struct {
union {
struct {
uint32_t controller_reset: 1;
uint32_t fifo_reset: 1;
uint32_t dma_reset: 1;
uint32_t reserved1: 1;
uint32_t int_enable: 1;
uint32_t dma_enable: 1;
uint32_t read_wait: 1;
uint32_t send_irq_response: 1;
uint32_t abort_read_data: 1;
uint32_t send_ccsd: 1;
uint32_t send_auto_stop_ccsd: 1;
uint32_t ceata_device_interrupt_status: 1;
uint32_t reserved2: 4;
uint32_t card_voltage_a: 4;
uint32_t card_voltage_b: 4;
uint32_t enable_od_pullup: 1;
uint32_t use_internal_dma: 1;
uint32_t reserved3: 6;
};
uint32_t val;
} ctrl;
uint32_t pwren; ///< 1: enable power to card, 0: disable power to card
union {
struct {
uint32_t div0: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
uint32_t div1: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
uint32_t div2: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
uint32_t div3: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
};
uint32_t val;
} clkdiv;
union {
struct {
uint32_t card0: 2; ///< 0-3: select clock divider for card 0 among div0-div3
uint32_t card1: 2; ///< 0-3: select clock divider for card 1 among div0-div3
uint32_t reserved: 28;
};
uint32_t val;
} clksrc;
union {
struct {
uint32_t cclk_enable: 16; ///< 1: enable clock to card, 0: disable clock
uint32_t cclk_low_power: 16; ///< 1: enable clock gating when card is idle, 0: disable clock gating
};
uint32_t val;
} clkena;
union {
struct {
uint32_t response: 8; ///< response timeout, in card output clock cycles
uint32_t data: 24; ///< data read timeout, in card output clock cycles
};
uint32_t val;
} tmout;
union {
struct {
uint32_t card_width: 16; ///< one bit for each card: 0: 1-bit mode, 1: 4-bit mode
uint32_t card_width_8: 16; ///< one bit for each card: 0: not 8-bit mode (corresponding card_width bit is used), 1: 8-bit mode (card_width bit is ignored)
};
uint32_t val;
} ctype;
uint32_t blksiz: 16; ///< block size, default 0x200
uint32_t : 16;
uint32_t bytcnt; ///< number of bytes to be transferred
union {
struct {
uint32_t cd: 1; ///< Card detect interrupt enable
uint32_t re: 1; ///< Response error interrupt enable
uint32_t cmd_done: 1; ///< Command done interrupt enable
uint32_t dto: 1; ///< Data transfer over interrupt enable
uint32_t txdr: 1; ///< Transmit FIFO data request interrupt enable
uint32_t rxdr: 1; ///< Receive FIFO data request interrupt enable
uint32_t rcrc: 1; ///< Response CRC error interrupt enable
uint32_t dcrc: 1; ///< Data CRC error interrupt enable
uint32_t rto: 1; ///< Response timeout interrupt enable
uint32_t drto: 1; ///< Data read timeout interrupt enable
uint32_t hto: 1; ///< Data starvation-by-host timeout interrupt enable
uint32_t frun: 1; ///< FIFO underrun/overrun error interrupt enable
uint32_t hle: 1; ///< Hardware locked write error interrupt enable
uint32_t sbi_bci: 1; ///< Start bit error / busy clear interrupt enable
uint32_t acd: 1; ///< Auto command done interrupt enable
uint32_t ebe: 1; ///< End bit error / write no CRC interrupt enable
uint32_t sdio: 16; ///< SDIO interrupt enable
};
uint32_t val;
} intmask;
uint32_t cmdarg; ///< Command argument to be passed to card
sdmmc_hw_cmd_t cmd;
uint32_t resp[4]; ///< Response from card
union {
struct {
uint32_t cd: 1; ///< Card detect interrupt masked status
uint32_t re: 1; ///< Response error interrupt masked status
uint32_t cmd_done: 1; ///< Command done interrupt masked status
uint32_t dto: 1; ///< Data transfer over interrupt masked status
uint32_t txdr: 1; ///< Transmit FIFO data request interrupt masked status
uint32_t rxdr: 1; ///< Receive FIFO data request interrupt masked status
uint32_t rcrc: 1; ///< Response CRC error interrupt masked status
uint32_t dcrc: 1; ///< Data CRC error interrupt masked status
uint32_t rto: 1; ///< Response timeout interrupt masked status
uint32_t drto: 1; ///< Data read timeout interrupt masked status
uint32_t hto: 1; ///< Data starvation-by-host timeout interrupt masked status
uint32_t frun: 1; ///< FIFO underrun/overrun error interrupt masked status
uint32_t hle: 1; ///< Hardware locked write error interrupt masked status
uint32_t sbi_bci: 1; ///< Start bit error / busy clear interrupt masked status
uint32_t acd: 1; ///< Auto command done interrupt masked status
uint32_t ebe: 1; ///< End bit error / write no CRC interrupt masked status
uint32_t sdio: 16; ///< SDIO interrupt masked status
};
uint32_t val;
} mintsts;
union {
struct {
uint32_t cd: 1; ///< Card detect raw interrupt status
uint32_t re: 1; ///< Response error raw interrupt status
uint32_t cmd_done: 1; ///< Command done raw interrupt status
uint32_t dto: 1; ///< Data transfer over raw interrupt status
uint32_t txdr: 1; ///< Transmit FIFO data request raw interrupt status
uint32_t rxdr: 1; ///< Receive FIFO data request raw interrupt status
uint32_t rcrc: 1; ///< Response CRC error raw interrupt status
uint32_t dcrc: 1; ///< Data CRC error raw interrupt status
uint32_t rto: 1; ///< Response timeout raw interrupt status
uint32_t drto: 1; ///< Data read timeout raw interrupt status
uint32_t hto: 1; ///< Data starvation-by-host timeout raw interrupt status
uint32_t frun: 1; ///< FIFO underrun/overrun error raw interrupt status
uint32_t hle: 1; ///< Hardware locked write error raw interrupt status
uint32_t sbi_bci: 1; ///< Start bit error / busy clear raw interrupt status
uint32_t acd: 1; ///< Auto command done raw interrupt status
uint32_t ebe: 1; ///< End bit error / write no CRC raw interrupt status
uint32_t sdio: 16; ///< SDIO raw interrupt status
};
uint32_t val;
} rintsts; ///< interrupts can be cleared by writing this register
union {
struct {
uint32_t fifo_rx_watermark: 1; ///< FIFO reached receive watermark level
uint32_t fifo_tx_watermark: 1; ///< FIFO reached transmit watermark level
uint32_t fifo_empty: 1; ///< FIFO is empty
uint32_t fifo_full: 1; ///< FIFO is full
uint32_t cmd_fsm_state: 4; ///< command FSM state
uint32_t data3_status: 1; ///< this bit reads 1 if card is present
uint32_t data_busy: 1; ///< this bit reads 1 if card is busy
uint32_t data_fsm_busy: 1; ///< this bit reads 1 if transmit/receive FSM is busy
uint32_t response_index: 6; ///< index of the previous response
uint32_t fifo_count: 13; ///< number of filled locations in the FIFO
uint32_t dma_ack: 1; ///< DMA acknowledge signal
uint32_t dma_req: 1; ///< DMA request signal
};
uint32_t val;
} status;
union {
struct {
uint32_t tx_watermark: 12; ///< FIFO TX watermark level
uint32_t reserved1: 4;
uint32_t rx_watermark: 12; ///< FIFO RX watermark level
uint32_t dw_dma_mts: 3;
uint32_t reserved2: 1;
};
uint32_t val;
} fifoth;
union {
struct {
uint32_t cards: 2; ///< bit N reads 0 if card N is present
uint32_t reserved: 30;
};
uint32_t val;
} cdetect;
union {
struct {
uint32_t cards: 2; ///< bit N reads 1 if card N is write protected
uint32_t reserved: 30;
};
uint32_t val;
} wrtprt;
uint32_t gpio; ///< unused
uint32_t tcbcnt; ///< transferred (to card) byte count
uint32_t tbbcnt; ///< transferred from host to FIFO byte count
union {
struct {
uint32_t debounce_count: 24; ///< number of host cycles used by debounce filter, typical time should be 5-25ms
uint32_t reserved: 8;
};
} debnce;
uint32_t usrid; ///< user ID
uint32_t verid; ///< IP block version
uint32_t hcon; ///< compile-time IP configuration
uint32_t uhs; ///< TBD
union {
struct {
uint32_t cards: 2; ///< bit N resets card N, active low
uint32_t reserved: 30;
};
} rst_n;
uint32_t reserved_7c;
union {
struct {
uint32_t sw_reset: 1; ///< set to reset DMA controller
uint32_t fb: 1; ///< set if AHB master performs fixed burst transfers
uint32_t dsl: 5; ///< descriptor skip length: number of words to skip between two unchained descriptors
uint32_t enable: 1; ///< set to enable IDMAC
uint32_t pbl: 3; ///< programmable burst length
uint32_t reserved: 21;
};
uint32_t val;
} bmod;
uint32_t pldmnd; ///< set any bit to resume IDMAC FSM from suspended state
sdmmc_desc_t* dbaddr; ///< descriptor list base
union {
struct {
uint32_t ti: 1; ///< transmit interrupt status
uint32_t ri: 1; ///< receive interrupt status
uint32_t fbe: 1; ///< fatal bus error
uint32_t reserved1: 1;
uint32_t du: 1; ///< descriptor unavailable
uint32_t ces: 1; ///< card error summary
uint32_t reserved2: 2;
uint32_t nis: 1; ///< normal interrupt summary
uint32_t fbe_code: 3; ///< code of fatal bus error
uint32_t fsm: 4; ///< DMAC FSM state
uint32_t reserved3: 15;
};
uint32_t val;
} idsts;
union {
struct {
uint32_t ti: 1; ///< transmit interrupt enable
uint32_t ri: 1; ///< receive interrupt enable
uint32_t fbe: 1; ///< fatal bus error interrupt enable
uint32_t reserved1: 1;
uint32_t du: 1; ///< descriptor unavailable interrupt enable
uint32_t ces: 1; ///< card error interrupt enable
uint32_t reserved2: 2;
uint32_t ni: 1; ///< normal interrupt interrupt enable
uint32_t ai: 1; ///< abnormal interrupt enable
uint32_t reserved3: 22;
};
uint32_t val;
} idinten;
uint32_t dscaddr; ///< current host descriptor address
uint32_t dscaddrl; ///< unused
uint32_t dscaddru; ///< unused
uint32_t bufaddrl; ///< unused
uint32_t bufaddru; ///< unused
uint32_t reserved_a8[22];
uint32_t cardthrctl;
uint32_t back_end_power;
uint32_t uhs_reg_ext;
uint32_t emmc_ddr_reg;
uint32_t enable_shift;
uint32_t reserved_114[443];
union {
struct {
uint32_t phase_dout: 3; ///< phase of data output clock (0x0: 0, 0x1: 90, 0x4: 180, 0x6: 270)
uint32_t phase_din: 3; ///< phase of data input clock
uint32_t phase_core: 3; ///< phase of the clock to SDMMC peripheral
uint32_t div_factor_p: 4; ///< controls clock period; it will be (div_factor_p + 1) / 160MHz
uint32_t div_factor_h: 4; ///< controls length of high pulse; it will be (div_factor_h + 1) / 160MHz
uint32_t div_factor_m: 4; ///< should be equal to div_factor_p
};
uint32_t val;
} clock;
} sdmmc_dev_t;
extern sdmmc_dev_t SDMMC;
_Static_assert(sizeof(sdmmc_dev_t) == 0x804, "invalid size of sdmmc_dev_t structure");
#ifdef __cplusplus
}
#endif
#endif //_SOC_SDMMC_STRUCT_H_

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SENS_STRUCT_H_
#define _SOC_SENS_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t sar1_clk_div: 8; /*clock divider*/
uint32_t sar1_sample_cycle: 8; /*sample cycles for SAR ADC1*/
uint32_t sar1_sample_bit: 2; /*00: for 9-bit width 01: for 10-bit width 10: for 11-bit width 11: for 12-bit width*/
uint32_t sar1_clk_gated: 1;
uint32_t sar1_sample_num: 8;
uint32_t sar1_dig_force: 1; /*1: SAR ADC1 controlled by DIG ADC1 CTRL 0: SAR ADC1 controlled by RTC ADC1 CTRL*/
uint32_t sar1_data_inv: 1; /*Invert SAR ADC1 data*/
uint32_t reserved29: 3;
};
uint32_t val;
} sar_read_ctrl;
uint32_t sar_read_status1; /**/
union {
struct {
uint32_t sar_amp_wait1:16;
uint32_t sar_amp_wait2:16;
};
uint32_t val;
} sar_meas_wait1;
union {
struct {
uint32_t sar_amp_wait3: 16;
uint32_t force_xpd_amp: 2;
uint32_t force_xpd_sar: 2;
uint32_t sar2_rstb_wait: 8;
uint32_t reserved28: 4;
};
uint32_t val;
} sar_meas_wait2;
union {
struct {
uint32_t xpd_sar_amp_fsm: 4;
uint32_t amp_rst_fb_fsm: 4;
uint32_t amp_short_ref_fsm: 4;
uint32_t amp_short_ref_gnd_fsm: 4;
uint32_t xpd_sar_fsm: 4;
uint32_t sar_rstb_fsm: 4;
uint32_t sar2_xpd_wait: 8;
};
uint32_t val;
} sar_meas_ctrl;
uint32_t sar_read_status2; /**/
uint32_t ulp_cp_sleep_cyc0; /*sleep cycles for ULP-coprocessor timer*/
uint32_t ulp_cp_sleep_cyc1; /**/
uint32_t ulp_cp_sleep_cyc2; /**/
uint32_t ulp_cp_sleep_cyc3; /**/
uint32_t ulp_cp_sleep_cyc4; /**/
union {
struct {
uint32_t sar1_bit_width: 2; /*00: 9 bit 01: 10 bits 10: 11bits 11: 12bits*/
uint32_t sar2_bit_width: 2; /*00: 9 bit 01: 10 bits 10: 11bits 11: 12bits*/
uint32_t sar2_en_test: 1; /*SAR2_EN_TEST only active when reg_sar2_dig_force = 0*/
uint32_t sar2_pwdet_cct: 3; /*SAR2_PWDET_CCT PA power detector capacitance tuning.*/
uint32_t ulp_cp_force_start_top: 1; /*1: ULP-coprocessor is started by SW 0: ULP-coprocessor is started by timer*/
uint32_t ulp_cp_start_top: 1; /*Write 1 to start ULP-coprocessor only active when reg_ulp_cp_force_start_top = 1*/
uint32_t sarclk_en: 1;
uint32_t pc_init: 11; /*initialized PC for ULP-coprocessor*/
uint32_t sar2_stop: 1; /*stop SAR ADC2 conversion*/
uint32_t sar1_stop: 1; /*stop SAR ADC1 conversion*/
uint32_t sar2_pwdet_en: 1; /*N/A*/
uint32_t reserved25: 7;
};
uint32_t val;
} sar_start_force;
union {
struct {
uint32_t mem_wr_addr_init: 11;
uint32_t mem_wr_addr_size: 11;
uint32_t rtc_mem_wr_offst_clr: 1;
uint32_t ulp_cp_clk_fo: 1; /*ulp coprocessor clk force on*/
uint32_t reserved24: 8;
};
uint32_t val;
} sar_mem_wr_ctrl;
uint32_t sar_atten1; /*2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB*/
uint32_t sar_atten2; /*2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB*/
union {
struct {
uint32_t i2c_slave_addr1: 11;
uint32_t i2c_slave_addr0: 11;
uint32_t meas_status: 8;
uint32_t reserved30: 2;
};
uint32_t val;
} sar_slave_addr1;
union {
struct {
uint32_t i2c_slave_addr3:11;
uint32_t i2c_slave_addr2:11;
uint32_t reserved22: 10;
};
uint32_t val;
} sar_slave_addr2;
union {
struct {
uint32_t i2c_slave_addr5:11;
uint32_t i2c_slave_addr4:11;
uint32_t tsens_out: 8; /*temperature sensor data out*/
uint32_t tsens_rdy_out: 1; /*indicate temperature sensor out ready*/
uint32_t reserved31: 1;
};
uint32_t val;
} sar_slave_addr3;
union {
struct {
uint32_t i2c_slave_addr7:11;
uint32_t i2c_slave_addr6:11;
uint32_t i2c_rdata: 8; /*I2C read data*/
uint32_t i2c_done: 1; /*indicate I2C done*/
uint32_t reserved31: 1;
};
uint32_t val;
} sar_slave_addr4;
union {
struct {
uint32_t tsens_xpd_wait: 12;
uint32_t tsens_xpd_force: 1;
uint32_t tsens_clk_inv: 1;
uint32_t tsens_clk_gated: 1;
uint32_t tsens_in_inv: 1; /*invert temperature sensor data*/
uint32_t tsens_clk_div: 8; /*temperature sensor clock divider*/
uint32_t tsens_power_up: 1; /*temperature sensor power up*/
uint32_t tsens_power_up_force: 1; /*1: dump out & power up controlled by SW 0: by FSM*/
uint32_t tsens_dump_out: 1; /*temperature sensor dump out only active when reg_tsens_power_up_force = 1*/
uint32_t tsens_dos: 4; /*Temperature sensor calibration bits*/
uint32_t tsens_force: 1; /*1: select saradc_reg 0: select efuse*/
};
uint32_t val;
} sar_tctrl;
union {
struct {
uint32_t sar_i2c_ctrl: 28; /*I2C control data only active when reg_sar_i2c_start_force = 1*/
uint32_t sar_i2c_start: 1; /*start I2C only active when reg_sar_i2c_start_force = 1*/
uint32_t sar_i2c_start_force: 1; /*1: I2C started by SW 0: I2C started by FSM*/
uint32_t reserved30: 2;
};
uint32_t val;
} sar_i2c_ctrl;
union {
struct {
uint32_t meas1_data_sar: 16; /*SAR ADC1 data*/
uint32_t meas1_done_sar: 1; /*SAR ADC1 conversion done indication*/
uint32_t meas1_start_sar: 1; /*SAR ADC1 controller (in RTC) starts conversion only active when reg_meas1_start_force = 1*/
uint32_t meas1_start_force: 1; /*1: SAR ADC1 controller (in RTC) is started by SW 0: SAR ADC1 controller is started by ULP-coprocessor*/
uint32_t sar1_en_pad: 12; /*SAR ADC1 pad enable bitmap only active when reg_sar1_en_pad_force = 1*/
uint32_t sar1_en_pad_force: 1; /*1: SAR ADC1 pad enable bitmap is controlled by SW 0: SAR ADC1 pad enable bitmap is controlled by ULP-coprocessor*/
};
uint32_t val;
} sar_meas_start1;
union {
struct {
uint32_t touch_meas_delay:16; /*the meas length (in 8MHz)*/
uint32_t touch_xpd_wait: 8; /*the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/
uint32_t touch_out_sel: 1; /*1: when the counter is greater then the threshold the touch pad is considered as “touched” 0: when the counter is less than the threshold the touch pad is considered as “touched”*/
uint32_t touch_out_1en: 1; /*1: wakeup interrupt is generated if SET1 is “touched” 0: wakeup interrupt is generated only if SET1 & SET2 is both “touched”*/
uint32_t xpd_hall_force: 1; /*1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor*/
uint32_t hall_phase_force: 1; /*1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor*/
uint32_t reserved28: 4;
};
uint32_t val;
} sar_touch_ctrl1;
union {
struct {
uint32_t l_thresh: 16; /*the threshold for touch pad 1*/
uint32_t h_thresh: 16; /*the threshold for touch pad 0*/
};
uint32_t val;
} touch_thresh[5];
union {
struct {
uint32_t l_val: 16; /*the counter for touch pad 1*/
uint32_t h_val: 16; /*the counter for touch pad 0*/
};
uint32_t val;
} touch_meas[5];
union {
struct {
uint32_t touch_meas_en: 10; /*10-bit register to indicate which pads are “touched”*/
uint32_t touch_meas_done: 1; /*fsm set 1 to indicate touch touch meas is done*/
uint32_t touch_start_fsm_en: 1; /*1: TOUCH_START & TOUCH_XPD is controlled by touch fsm 0: TOUCH_START & TOUCH_XPD is controlled by registers*/
uint32_t touch_start_en: 1; /*1: start touch fsm valid when reg_touch_start_force is set*/
uint32_t touch_start_force: 1; /*1: to start touch fsm by SW 0: to start touch fsm by timer*/
uint32_t touch_sleep_cycles:16; /*sleep cycles for timer*/
uint32_t touch_meas_en_clr: 1; /*to clear reg_touch_meas_en*/
uint32_t reserved31: 1;
};
uint32_t val;
} sar_touch_ctrl2;
uint32_t reserved_88;
union {
struct {
uint32_t touch_pad_worken:10; /*Bitmap defining the working set during the measurement.*/
uint32_t touch_pad_outen2:10; /*Bitmap defining SET2 for generating wakeup interrupt. SET2 is “touched” only if at least one of touch pad in SET2 is “touched”.*/
uint32_t touch_pad_outen1:10; /*Bitmap defining SET1 for generating wakeup interrupt. SET1 is “touched” only if at least one of touch pad in SET1 is “touched”.*/
uint32_t reserved30: 2;
};
uint32_t val;
} sar_touch_enable;
union {
struct {
uint32_t touch_meas_raw:10; /*touch sensor raw result*/
uint32_t reserved10: 22;
};
uint32_t val;
} sar_touch_ctrl3;
union {
struct {
uint32_t sar2_clk_div: 8; /*clock divider*/
uint32_t sar2_sample_cycle: 8; /*sample cycles for SAR ADC2*/
uint32_t sar2_sample_bit: 2; /*00: for 9-bit width 01: for 10-bit width 10: for 11-bit width 11: for 12-bit width*/
uint32_t sar2_clk_gated: 1;
uint32_t sar2_sample_num: 8;
uint32_t sar2_pwdet_force: 1;
uint32_t sar2_dig_force: 1; /*1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL 0: SAR ADC2 controlled by RTC ADC2 CTRL*/
uint32_t sar2_data_inv: 1; /*Invert SAR ADC2 data*/
uint32_t reserved30: 2;
};
uint32_t val;
} sar_read_ctrl2;
union {
struct {
uint32_t meas2_data_sar: 16; /*SAR ADC2 data*/
uint32_t meas2_done_sar: 1; /*SAR ADC2 conversion done indication*/
uint32_t meas2_start_sar: 1; /*SAR ADC2 controller (in RTC) starts conversion only active when reg_meas2_start_force = 1*/
uint32_t meas2_start_force: 1; /*1: SAR ADC2 controller (in RTC) is started by SW 0: SAR ADC2 controller is started by ULP-coprocessor*/
uint32_t sar2_en_pad: 12; /*SAR ADC2 pad enable bitmap only active when reg_sar2_en_pad_force = 1*/
uint32_t sar2_en_pad_force: 1; /*1: SAR ADC2 pad enable bitmap is controlled by SW 0: SAR ADC2 pad enable bitmap is controlled by ULP-coprocessor*/
};
uint32_t val;
} sar_meas_start2;
union {
struct {
uint32_t sw_fstep: 16; /*frequency step for CW generator can be used to adjust the frequency*/
uint32_t sw_tone_en: 1; /*1: enable CW generator 0: disable CW generator*/
uint32_t debug_bit_sel: 5;
uint32_t dac_dig_force: 1; /*1: DAC1 & DAC2 use DMA 0: DAC1 & DAC2 do not use DMA*/
uint32_t dac_clk_force_low: 1; /*1: force PDAC_CLK to low*/
uint32_t dac_clk_force_high: 1; /*1: force PDAC_CLK to high*/
uint32_t dac_clk_inv: 1; /*1: invert PDAC_CLK*/
uint32_t reserved26: 6;
};
uint32_t val;
} sar_dac_ctrl1;
union {
struct {
uint32_t dac_dc1: 8; /*DC offset for DAC1 CW generator*/
uint32_t dac_dc2: 8; /*DC offset for DAC2 CW generator*/
uint32_t dac_scale1: 2; /*00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8*/
uint32_t dac_scale2: 2; /*00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8*/
uint32_t dac_inv1: 2; /*00: do not invert any bits 01: invert all bits 10: invert MSB 11: invert all bits except MSB*/
uint32_t dac_inv2: 2; /*00: do not invert any bits 01: invert all bits 10: invert MSB 11: invert all bits except MSB*/
uint32_t dac_cw_en1: 1; /*1: to select CW generator as source to PDAC1_DAC[7:0] 0: to select register reg_pdac1_dac[7:0] as source to PDAC1_DAC[7:0]*/
uint32_t dac_cw_en2: 1; /*1: to select CW generator as source to PDAC2_DAC[7:0] 0: to select register reg_pdac2_dac[7:0] as source to PDAC2_DAC[7:0]*/
uint32_t reserved26: 6;
};
uint32_t val;
} sar_dac_ctrl2;
union {
struct {
uint32_t sar1_dac_xpd_fsm: 4;
uint32_t sar1_dac_xpd_fsm_idle: 1;
uint32_t xpd_sar_amp_fsm_idle: 1;
uint32_t amp_rst_fb_fsm_idle: 1;
uint32_t amp_short_ref_fsm_idle: 1;
uint32_t amp_short_ref_gnd_fsm_idle: 1;
uint32_t xpd_sar_fsm_idle: 1;
uint32_t sar_rstb_fsm_idle: 1;
uint32_t sar2_rstb_force: 2;
uint32_t amp_rst_fb_force: 2;
uint32_t amp_short_ref_force: 2;
uint32_t amp_short_ref_gnd_force: 2;
uint32_t reserved19: 13;
};
uint32_t val;
} sar_meas_ctrl2;
union {
struct {
uint32_t clk_fo: 1; /*cocpu clk force on*/
uint32_t start_2_reset_dis: 6; /*time from start cocpu to pull down reset*/
uint32_t start_2_intr_en: 6; /*time from start cocpu to give start interrupt*/
uint32_t shut: 1; /*to shut cocpu*/
uint32_t shut_2_clk_dis: 6; /*time from shut cocpu to disable clk*/
uint32_t shut_reset_en: 1; /*to reset cocpu*/
uint32_t sel: 1; /*1: old ULP 0: new riscV*/
uint32_t done_force: 1; /*1: select riscv done 0: select ulp done*/
uint32_t done: 1; /*done signal used by riscv to control timer.*/
uint32_t int_trigger: 1; /*trigger cocpu register interrupt*/
uint32_t clk_en: 1; /*check cocpu whether clk on*/
uint32_t reset_n: 1; /*check cocpu whether in reset state*/
uint32_t eoi: 1; /*check cocpu whether in interrupt state*/
uint32_t trap: 1; /*check cocpu whether in trap state*/
uint32_t reserved29: 3;
};
uint32_t val;
} sar_cocpu_ctrl;
union {
struct {
uint32_t saradc_int_ena: 1;
uint32_t tsens_int_ena: 1;
uint32_t start_int_ena: 1;
uint32_t cocpu_int_ena: 1;
uint32_t ebreak_int_ena: 1; /*int enable entry*/
uint32_t reserved5: 5;
uint32_t saradc_int_clr: 1;
uint32_t tsens_int_clr: 1;
uint32_t start_int_clr: 1;
uint32_t cocpu_int_clr: 1;
uint32_t ebreak_int_clr: 1; /*int clear entry*/
uint32_t reserved15: 5;
uint32_t saradc_int: 1; /*int from saradc*/
uint32_t tsens_int: 1; /*int from tsens*/
uint32_t start_int: 1; /*int from start*/
uint32_t cocpu_int: 1; /*int from register*/
uint32_t ebreak_int: 1; /*int from ebreak*/
uint32_t reserved25: 7;
};
uint32_t val;
} sar_cocpu_int;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t sar_nouse; /**/
union {
struct {
uint32_t sar_date: 28;
uint32_t reserved28: 4;
};
uint32_t val;
} sardate;
} sens_dev_t;
extern sens_dev_t SENS;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_SENS_STRUCT_H_ */

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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SLC_STRUCT_H_
#define _SOC_SLC_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t slc0_tx_rst: 1;
uint32_t slc0_rx_rst: 1;
uint32_t ahbm_fifo_rst: 1;
uint32_t ahbm_rst: 1;
uint32_t slc0_tx_loop_test: 1;
uint32_t slc0_rx_loop_test: 1;
uint32_t slc0_rx_auto_wrback: 1;
uint32_t slc0_rx_no_restart_clr: 1;
uint32_t slc0_rxdscr_burst_en: 1;
uint32_t slc0_rxdata_burst_en: 1;
uint32_t slc0_rxlink_auto_ret: 1;
uint32_t slc0_txlink_auto_ret: 1;
uint32_t slc0_txdscr_burst_en: 1;
uint32_t slc0_txdata_burst_en: 1;
uint32_t slc0_token_auto_clr: 1;
uint32_t slc0_token_sel: 1;
uint32_t reserved16: 2;
uint32_t slc0_wr_retry_mask_en: 1;
uint32_t reserved19: 13;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t frhost_bit0: 1;
uint32_t frhost_bit1: 1;
uint32_t frhost_bit2: 1;
uint32_t frhost_bit3: 1;
uint32_t frhost_bit4: 1;
uint32_t frhost_bit5: 1;
uint32_t frhost_bit6: 1;
uint32_t frhost_bit7: 1;
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_udf: 1;
uint32_t tx_ovf: 1;
uint32_t token0_1to0: 1;
uint32_t token1_1to0: 1;
uint32_t tx_done: 1;
uint32_t tx_suc_eof: 1;
uint32_t rx_done: 1;
uint32_t rx_eof: 1;
uint32_t tohost: 1;
uint32_t tx_dscr_err: 1;
uint32_t rx_dscr_err: 1;
uint32_t tx_dscr_empty: 1;
uint32_t host_rd_ack: 1;
uint32_t wr_retry_done: 1;
uint32_t tx_err_eof: 1;
uint32_t cmd_dtc: 1;
uint32_t rx_quick_eof: 1;
uint32_t host_pop_eof_err: 1;
uint32_t reserved28: 4;
};
uint32_t val;
} slc0_int_raw;
union {
struct {
uint32_t frhost_bit0: 1;
uint32_t frhost_bit1: 1;
uint32_t frhost_bit2: 1;
uint32_t frhost_bit3: 1;
uint32_t frhost_bit4: 1;
uint32_t frhost_bit5: 1;
uint32_t frhost_bit6: 1;
uint32_t frhost_bit7: 1;
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_udf: 1;
uint32_t tx_ovf: 1;
uint32_t token0_1to0: 1;
uint32_t token1_1to0: 1;
uint32_t tx_done: 1;
uint32_t tx_suc_eof: 1;
uint32_t rx_done: 1;
uint32_t rx_eof: 1;
uint32_t tohost: 1;
uint32_t tx_dscr_err: 1;
uint32_t rx_dscr_err: 1;
uint32_t tx_dscr_empty: 1;
uint32_t host_rd_ack: 1;
uint32_t wr_retry_done: 1;
uint32_t tx_err_eof: 1;
uint32_t cmd_dtc: 1;
uint32_t rx_quick_eof: 1;
uint32_t host_pop_eof_err: 1;
uint32_t reserved28: 4;
};
uint32_t val;
} slc0_int_st;
union {
struct {
uint32_t frhost_bit0: 1;
uint32_t frhost_bit1: 1;
uint32_t frhost_bit2: 1;
uint32_t frhost_bit3: 1;
uint32_t frhost_bit4: 1;
uint32_t frhost_bit5: 1;
uint32_t frhost_bit6: 1;
uint32_t frhost_bit7: 1;
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_udf: 1;
uint32_t tx_ovf: 1;
uint32_t token0_1to0: 1;
uint32_t token1_1to0: 1;
uint32_t tx_done: 1;
uint32_t tx_suc_eof: 1;
uint32_t rx_done: 1;
uint32_t rx_eof: 1;
uint32_t tohost: 1;
uint32_t tx_dscr_err: 1;
uint32_t rx_dscr_err: 1;
uint32_t tx_dscr_empty: 1;
uint32_t host_rd_ack: 1;
uint32_t wr_retry_done: 1;
uint32_t tx_err_eof: 1;
uint32_t cmd_dtc: 1;
uint32_t rx_quick_eof: 1;
uint32_t host_pop_eof_err: 1;
uint32_t reserved28: 4;
};
uint32_t val;
} slc0_int_ena;
union {
struct {
uint32_t frhost_bit0: 1;
uint32_t frhost_bit1: 1;
uint32_t frhost_bit2: 1;
uint32_t frhost_bit3: 1;
uint32_t frhost_bit4: 1;
uint32_t frhost_bit5: 1;
uint32_t frhost_bit6: 1;
uint32_t frhost_bit7: 1;
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_udf: 1;
uint32_t tx_ovf: 1;
uint32_t token0_1to0: 1;
uint32_t token1_1to0: 1;
uint32_t tx_done: 1;
uint32_t tx_suc_eof: 1;
uint32_t rx_done: 1;
uint32_t rx_eof: 1;
uint32_t tohost: 1;
uint32_t tx_dscr_err: 1;
uint32_t rx_dscr_err: 1;
uint32_t tx_dscr_empty: 1;
uint32_t host_rd_ack: 1;
uint32_t wr_retry_done: 1;
uint32_t tx_err_eof: 1;
uint32_t cmd_dtc: 1;
uint32_t rx_quick_eof: 1;
uint32_t host_pop_eof_err: 1;
uint32_t reserved28: 4;
};
uint32_t val;
} slc0_int_clr;
uint32_t reserved_14;
uint32_t reserved_18;
uint32_t reserved_1c;
uint32_t reserved_20;
union {
struct {
uint32_t slc0_rx_full: 1;
uint32_t slc0_rx_empty: 1;
uint32_t slc0_rx_buf_len:12;
uint32_t reserved14: 18;
};
uint32_t val;
} rx_status;
union {
struct {
uint32_t rxfifo_wdata: 9;
uint32_t reserved9: 7;
uint32_t rxfifo_push: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} slc0_rxfifo_push;
uint32_t reserved_2c;
union {
struct {
uint32_t slc0_tx_full: 1;
uint32_t slc0_tx_empty: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} tx_status;
union {
struct {
uint32_t txfifo_rdata: 11;
uint32_t reserved11: 5;
uint32_t txfifo_pop: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} slc0_txfifo_pop;
uint32_t reserved_38;
union {
struct {
uint32_t addr: 20;
uint32_t reserved20: 8;
uint32_t stop: 1;
uint32_t start: 1;
uint32_t restart: 1;
uint32_t park: 1;
};
uint32_t val;
} slc0_rx_link;
union {
struct {
uint32_t addr: 20;
uint32_t reserved20: 8;
uint32_t stop: 1;
uint32_t start: 1;
uint32_t restart: 1;
uint32_t park: 1;
};
uint32_t val;
} slc0_tx_link;
uint32_t reserved_44;
uint32_t reserved_48;
union {
struct {
uint32_t slc0_intvec: 8;
uint32_t reserved8: 24;
};
uint32_t val;
} intvec_tohost;
union {
struct {
uint32_t wdata: 12;
uint32_t wr: 1;
uint32_t inc: 1;
uint32_t inc_more: 1;
uint32_t reserved15: 1;
uint32_t token0: 12;
uint32_t reserved28: 4;
};
uint32_t val;
} slc0_token0;
union {
struct {
uint32_t wdata: 12;
uint32_t wr: 1;
uint32_t inc: 1;
uint32_t inc_more: 1;
uint32_t reserved15: 1;
uint32_t token1: 12;
uint32_t reserved28: 4;
};
uint32_t val;
} slc0_token1;
uint32_t reserved_58;
uint32_t reserved_5c;
union {
struct {
uint32_t slc0_check_owner: 1;
uint32_t slc0_tx_check_sum_en: 1;
uint32_t slc0_rx_check_sum_en: 1;
uint32_t cmd_hold_en: 1;
uint32_t slc0_len_auto_clr: 1;
uint32_t slc0_tx_stitch_en: 1;
uint32_t slc0_rx_stitch_en: 1;
uint32_t reserved7: 12;
uint32_t host_int_level_sel: 1;
uint32_t reserved20: 2;
uint32_t clk_en: 1;
uint32_t reserved23: 9;
};
uint32_t val;
} conf1;
uint32_t slc0_state0; /**/
uint32_t slc0_state1; /**/
uint32_t reserved_6c;
uint32_t reserved_70;
union {
struct {
uint32_t txeof_ena: 6;
uint32_t reserved6: 2;
uint32_t fifo_map_ena: 4;
uint32_t slc0_tx_dummy_mode: 1;
uint32_t hda_map_128k: 1;
uint32_t reserved14: 2;
uint32_t tx_push_idle_num: 16;
};
uint32_t val;
} bridge_conf;
uint32_t slc0_to_eof_des_addr; /**/
uint32_t slc0_tx_eof_des_addr; /**/
uint32_t slc0_to_eof_bfr_des_addr; /**/
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t reserved_8c;
union {
struct {
uint32_t mode: 3;
uint32_t reserved3: 1;
uint32_t addr: 2;
uint32_t reserved6: 26;
};
uint32_t val;
} ahb_test;
union {
struct {
uint32_t cmd_st: 3;
uint32_t reserved3: 1;
uint32_t func_st: 4;
uint32_t sdio_wakeup: 1;
uint32_t reserved9: 3;
uint32_t bus_st: 3;
uint32_t reserved15: 1;
uint32_t func1_acc_state: 5;
uint32_t reserved21: 11;
};
uint32_t val;
} sdio_st;
union {
struct {
uint32_t slc0_token_no_replace: 1;
uint32_t slc0_infor_no_replace: 1;
uint32_t slc0_rx_fill_mode: 1;
uint32_t slc0_rx_eof_mode: 1;
uint32_t slc0_rx_fill_en: 1;
uint32_t slc0_rd_retry_threshold:11;
uint32_t reserved16: 16;
};
uint32_t val;
} rx_dscr_conf;
uint32_t slc0_txlink_dscr; /**/
uint32_t slc0_txlink_dscr_bf0; /**/
uint32_t slc0_txlink_dscr_bf1; /**/
uint32_t slc0_rxlink_dscr; /**/
uint32_t slc0_rxlink_dscr_bf0; /**/
uint32_t slc0_rxlink_dscr_bf1; /**/
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t slc0_tx_erreof_des_addr; /**/
uint32_t reserved_d0;
union {
struct {
uint32_t slc0_token:12;
uint32_t reserved12:20;
};
uint32_t val;
} token_lat;
union {
struct {
uint32_t wr_retry_threshold:11;
uint32_t reserved11: 21;
};
uint32_t val;
} tx_dscr_conf;
uint32_t cmd_infor0; /**/
uint32_t cmd_infor1; /**/
union {
struct {
uint32_t len_wdata: 20;
uint32_t len_wr: 1;
uint32_t len_inc: 1;
uint32_t len_inc_more: 1;
uint32_t rx_packet_load_en: 1;
uint32_t tx_packet_load_en: 1;
uint32_t rx_get_used_dscr: 1;
uint32_t tx_get_used_dscr: 1;
uint32_t rx_new_pkt_ind: 1;
uint32_t tx_new_pkt_ind: 1;
uint32_t reserved29: 3;
};
uint32_t val;
} slc0_len_conf;
union {
struct {
uint32_t len: 20;
uint32_t reserved20:12;
};
uint32_t val;
} slc0_length;
uint32_t slc0_txpkt_h_dscr; /**/
uint32_t slc0_txpkt_e_dscr; /**/
uint32_t slc0_rxpkt_h_dscr; /**/
uint32_t slc0_rxpkt_e_dscr; /**/
uint32_t slc0_txpktu_h_dscr; /**/
uint32_t slc0_txpktu_e_dscr; /**/
uint32_t slc0_rxpktu_h_dscr; /**/
uint32_t slc0_rxpktu_e_dscr; /**/
uint32_t reserved_10c;
uint32_t reserved_110;
union {
struct {
uint32_t slc0_position: 8;
uint32_t reserved8: 24;
};
uint32_t val;
} seq_position;
union {
struct {
uint32_t rx_dscr_rec_lim: 10;
uint32_t reserved10: 22;
};
uint32_t val;
} slc0_dscr_rec_conf;
union {
struct {
uint32_t dat0_crc_err_cnt: 8;
uint32_t dat1_crc_err_cnt: 8;
uint32_t dat2_crc_err_cnt: 8;
uint32_t dat3_crc_err_cnt: 8;
};
uint32_t val;
} sdio_crc_st0;
union {
struct {
uint32_t cmd_crc_err_cnt: 8;
uint32_t reserved8: 23;
uint32_t err_cnt_clr: 1;
};
uint32_t val;
} sdio_crc_st1;
uint32_t slc0_eof_start_des; /**/
uint32_t slc0_push_dscr_addr; /**/
uint32_t slc0_done_dscr_addr; /**/
uint32_t slc0_sub_start_des; /**/
union {
struct {
uint32_t rx_dscr_cnt_lat: 10;
uint32_t reserved10: 6;
uint32_t rx_get_eof_occ: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} slc0_dscr_cnt;
union {
struct {
uint32_t len_lim: 20;
uint32_t reserved20: 12;
};
uint32_t val;
} slc0_len_lim_conf;
union {
struct {
uint32_t frhost_bit01: 1;
uint32_t frhost_bit11: 1;
uint32_t frhost_bit21: 1;
uint32_t frhost_bit31: 1;
uint32_t frhost_bit41: 1;
uint32_t frhost_bit51: 1;
uint32_t frhost_bit61: 1;
uint32_t frhost_bit71: 1;
uint32_t rx_start1: 1;
uint32_t tx_start1: 1;
uint32_t rx_udf1: 1;
uint32_t tx_ovf1: 1;
uint32_t token0_1to01: 1;
uint32_t token1_1to01: 1;
uint32_t tx_done1: 1;
uint32_t tx_suc_eof1: 1;
uint32_t rx_done1: 1;
uint32_t rx_eof1: 1;
uint32_t tohost1: 1;
uint32_t tx_dscr_err1: 1;
uint32_t rx_dscr_err1: 1;
uint32_t tx_dscr_empty1: 1;
uint32_t host_rd_ack1: 1;
uint32_t wr_retry_done1: 1;
uint32_t tx_err_eof1: 1;
uint32_t cmd_dtc1: 1;
uint32_t rx_quick_eof1: 1;
uint32_t host_pop_eof_err1: 1;
uint32_t reserved28: 4;
};
uint32_t val;
} slc0_int_st1;
union {
struct {
uint32_t frhost_bit01: 1;
uint32_t frhost_bit11: 1;
uint32_t frhost_bit21: 1;
uint32_t frhost_bit31: 1;
uint32_t frhost_bit41: 1;
uint32_t frhost_bit51: 1;
uint32_t frhost_bit61: 1;
uint32_t frhost_bit71: 1;
uint32_t rx_start1: 1;
uint32_t tx_start1: 1;
uint32_t rx_udf1: 1;
uint32_t tx_ovf1: 1;
uint32_t token0_1to01: 1;
uint32_t token1_1to01: 1;
uint32_t tx_done1: 1;
uint32_t tx_suc_eof1: 1;
uint32_t rx_done1: 1;
uint32_t rx_eof1: 1;
uint32_t tohost1: 1;
uint32_t tx_dscr_err1: 1;
uint32_t rx_dscr_err1: 1;
uint32_t tx_dscr_empty1: 1;
uint32_t host_rd_ack1: 1;
uint32_t wr_retry_done1: 1;
uint32_t tx_err_eof1: 1;
uint32_t cmd_dtc1: 1;
uint32_t rx_quick_eof1: 1;
uint32_t host_pop_eof_err1: 1;
uint32_t reserved28: 4;
};
uint32_t val;
} slc0_int_ena1;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t date; /**/
uint32_t id; /**/
} slc_dev_t;
extern slc_dev_t SLC;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_SLC_STRUCT_H_ */

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// Copyright 2010-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ESP32_SOC_H_
#define _ESP32_SOC_H_
#ifndef __ASSEMBLER__
#include <stdint.h>
#include "esp_assert.h"
#endif
//Register Bits{{
#define BIT31 0x80000000
#define BIT30 0x40000000
#define BIT29 0x20000000
#define BIT28 0x10000000
#define BIT27 0x08000000
#define BIT26 0x04000000
#define BIT25 0x02000000
#define BIT24 0x01000000
#define BIT23 0x00800000
#define BIT22 0x00400000
#define BIT21 0x00200000
#define BIT20 0x00100000
#define BIT19 0x00080000
#define BIT18 0x00040000
#define BIT17 0x00020000
#define BIT16 0x00010000
#define BIT15 0x00008000
#define BIT14 0x00004000
#define BIT13 0x00002000
#define BIT12 0x00001000
#define BIT11 0x00000800
#define BIT10 0x00000400
#define BIT9 0x00000200
#define BIT8 0x00000100
#define BIT7 0x00000080
#define BIT6 0x00000040
#define BIT5 0x00000020
#define BIT4 0x00000010
#define BIT3 0x00000008
#define BIT2 0x00000004
#define BIT1 0x00000002
#define BIT0 0x00000001
//}}
#define PRO_CPU_NUM (0)
#define DR_REG_SYSTEM_BASE 0x3f4c0000
#define DR_REG_SENSITIVE_BASE 0x3f4c1000
#define DR_REG_INTERRUPT_BASE 0x3f4c2000
#define DR_REG_DMA_COPY_BASE 0x3f4c3000
#define DR_REG_EXTMEM_BASE 0x3f4c4000
#define DR_REG_MMU_TABLE 0x3f4c5000
#define DR_REG_ITAG_TABLE 0x3f4c6000
#define DR_REG_DTAG_TABLE 0x3f4c7000
#define DR_REG_AES_BASE 0x3f4c8000
#define DR_REG_SHA_BASE 0x3f4c9000
#define DR_REG_RSA_BASE 0x3f4ca000
#define DR_REG_SECURE_BOOT_BASE 0x3f4cb000
#define DR_REG_HMAC_BASE 0x3f4cc000
#define DR_REG_DIGITAL_SINGNATURE_BASE 0x3f4cd000
#define DR_REG_ASSIST_DEBUG_BASE 0x3f4ce000
#define DR_REG_DEDICATED_GPIO_BASE 0x3f4cf000
#define DR_REG_INTRUSION_BASE 0x3f4d0000
#define DR_REG_DPORT_END 0x3f4d3FFC
#define DR_REG_UART_BASE 0x3f400000
#define DR_REG_SPI1_BASE 0x3f402000
#define DR_REG_SPI0_BASE 0x3f403000
#define DR_REG_GPIO_BASE 0x3f404000
#define DR_REG_GPIO_SD_BASE 0x3f404f00
#define DR_REG_FE2_BASE 0x3f405000
#define DR_REG_FE_BASE 0x3f406000
#define DR_REG_FRC_TIMER_BASE 0x3f407000
#define DR_REG_RTCCNTL_BASE 0x3f408000
#define DR_REG_RTCIO_BASE 0x3f408400
#define DR_REG_SENS_BASE 0x3f408800
#define DR_REG_RTC_I2C_BASE 0x3f408C00
#define DR_REG_IO_MUX_BASE 0x3f409000
#define DR_REG_HINF_BASE 0x3f40B000
#define DR_REG_I2S_BASE 0x3f40F000
#define DR_REG_UART1_BASE 0x3f410000
#define DR_REG_I2C_EXT_BASE 0x3f413000
#define DR_REG_UHCI0_BASE 0x3f414000
#define DR_REG_SLCHOST_BASE 0x3f415000
#define DR_REG_RMT_BASE 0x3f416000
#define DR_REG_PCNT_BASE 0x3f417000
#define DR_REG_SLC_BASE 0x3f418000
#define DR_REG_LEDC_BASE 0x3f419000
#define DR_REG_EFUSE_BASE 0x3f41A000
#define DR_REG_NRX_BASE 0x3f41CC00
#define DR_REG_BB_BASE 0x3f41D000
#define DR_REG_TIMERGROUP0_BASE 0x3f41F000
#define DR_REG_TIMERGROUP1_BASE 0x3f420000
#define DR_REG_RTC_SLOWMEM_BASE 0x3f421000
#define DR_REG_SPI2_BASE 0x3f424000
#define DR_REG_SPI3_BASE 0x3f425000
#define DR_REG_SYSCON_BASE 0x3f426000
#define DR_REG_APB_CTRL_BASE 0x3f426000 /* Old name for SYSCON, to be removed */
#define DR_REG_I2C1_EXT_BASE 0x3f427000
#define DR_REG_SPI4_BASE 0x3f437000
#define DR_REG_USB_WRAP_BASE 0x3f439000
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE)
#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 )
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 )
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
//Registers Operation {{
#define ETS_UNCACHED_ADDR(addr) (addr)
#define ETS_CACHED_ADDR(addr) (addr)
#ifndef __ASSEMBLER__
#define BIT(nr) (1UL << (nr))
#else
#define BIT(nr) (1 << (nr))
#endif
#ifndef __ASSEMBLER__
#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END)
#if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_FREERTOS_UNICORE ) && defined( ESP_PLATFORM )
#define ASSERT_IF_DPORT_REG(_r, OP) TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP));
#else
#define ASSERT_IF_DPORT_REG(_r, OP)
#endif
//write value to register
#define REG_WRITE(_r, _v) ({ \
ASSERT_IF_DPORT_REG((_r), REG_WRITE); \
(*(volatile uint32_t *)(_r)) = (_v); \
})
//read value from register
#define REG_READ(_r) ({ \
ASSERT_IF_DPORT_REG((_r), REG_READ); \
(*(volatile uint32_t *)(_r)); \
})
//get bit or get bits from register
#define REG_GET_BIT(_r, _b) ({ \
ASSERT_IF_DPORT_REG((_r), REG_GET_BIT); \
(*(volatile uint32_t*)(_r) & (_b)); \
})
//set bit or set bits to register
#define REG_SET_BIT(_r, _b) ({ \
ASSERT_IF_DPORT_REG((_r), REG_SET_BIT); \
(*(volatile uint32_t*)(_r) |= (_b)); \
})
//clear bit or clear bits of register
#define REG_CLR_BIT(_r, _b) ({ \
ASSERT_IF_DPORT_REG((_r), REG_CLR_BIT); \
(*(volatile uint32_t*)(_r) &= ~(_b)); \
})
//set bits of register controlled by mask
#define REG_SET_BITS(_r, _b, _m) ({ \
ASSERT_IF_DPORT_REG((_r), REG_SET_BITS); \
(*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))); \
})
//get field from register, uses field _S & _V to determine mask
#define REG_GET_FIELD(_r, _f) ({ \
ASSERT_IF_DPORT_REG((_r), REG_GET_FIELD); \
((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \
})
//set field of a register from variable, uses field _S & _V to determine mask
#define REG_SET_FIELD(_r, _f, _v) ({ \
ASSERT_IF_DPORT_REG((_r), REG_SET_FIELD); \
(REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))); \
})
//get field value from a variable, used when _f is not left shifted by _f##_S
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
//get field value from a variable, used when _f is left shifted by _f##_S
#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
//set field value to a variable, used when _f is not left shifted by _f##_S
#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
//set field value to a variable, used when _f is left shifted by _f##_S
#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
//generate a value from a field value, used when _f is not left shifted by _f##_S
#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
//generate a value from a field value, used when _f is left shifted by _f##_S
#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
//read value from register
#define READ_PERI_REG(addr) ({ \
ASSERT_IF_DPORT_REG((addr), READ_PERI_REG); \
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \
})
//write value to register
#define WRITE_PERI_REG(addr, val) ({ \
ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG); \
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \
})
//clear bits of register controlled by mask
#define CLEAR_PERI_REG_MASK(reg, mask) ({ \
ASSERT_IF_DPORT_REG((reg), CLEAR_PERI_REG_MASK); \
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \
})
//set bits of register controlled by mask
#define SET_PERI_REG_MASK(reg, mask) ({ \
ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_MASK); \
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \
})
//get bits of register controlled by mask
#define GET_PERI_REG_MASK(reg, mask) ({ \
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK); \
(READ_PERI_REG(reg) & (mask)); \
})
//get bits of register controlled by highest bit and lowest bit
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS); \
((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \
})
//set bits of register controlled by mask and shift
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({ \
ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_BITS); \
(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )); \
})
//get field of register
#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS2); \
((READ_PERI_REG(reg)>>(shift))&(mask)); \
})
#endif /* !__ASSEMBLER__ */
//}}
//Periheral Clock {{
#define APB_CLK_FREQ_ROM ( 40*1000000 )
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define UART_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz
#define REF_CLK_FREQ ( 1000000 )
#define UART_CLK_FREQ APB_CLK_FREQ
#define WDT_CLK_FREQ APB_CLK_FREQ
#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16
#define SPI_CLK_DIV 4
#define TICKS_PER_US_ROM 40 // CPU is 80MHz
//}}
/* Overall memory map */
#define SOC_DROM_LOW 0x3F000000
#define SOC_DROM_HIGH 0x3F400000
#define SOC_IROM_LOW 0x40080000
#define SOC_IROM_HIGH 0x40c00000
#define SOC_IRAM_LOW 0x40020000
#define SOC_IRAM_HIGH 0x40070000
#define SOC_RTC_IRAM_LOW 0x40070000
#define SOC_RTC_IRAM_HIGH 0x40072000
#define SOC_RTC_DRAM_LOW 0x3ff9e000
#define SOC_RTC_DRAM_HIGH 0x3ffa0000
#define SOC_RTC_DATA_LOW 0x50000000
#define SOC_RTC_DATA_HIGH 0x50002000
#define SOC_EXTRAM_DATA_LOW 0x3F500000
#define SOC_EXTRAM_DATA_HIGH 0x3FF90000
#define SOC_SLOW_EXTRAM_DATA_LOW 0x61800000
#define SOC_SLOW_EXTRAM_DATA_HIGH 0x61c00000
//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
#define SOC_DIRAM_IRAM_LOW 0x40020000
#define SOC_DIRAM_IRAM_HIGH 0x4006FFFC
#define SOC_DIRAM_DRAM_LOW 0x3FFB0000
#define SOC_DIRAM_DRAM_HIGH 0x3FFFFFFC
// Region of memory accessible via DMA. See esp_ptr_dma_capable().
#define SOC_DMA_LOW 0x3FFB0000
#define SOC_DMA_HIGH 0x40000000
// Region of memory that is byte-accessible. See esp_ptr_byte_accessible().
#define SOC_BYTE_ACCESSIBLE_LOW 0x3FF9E000
#define SOC_BYTE_ACCESSIBLE_HIGH 0x40000000
//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
#define SOC_MEM_INTERNAL_LOW 0x3FF9E000
#define SOC_MEM_INTERNAL_HIGH 0x40072000
//interrupt cpu using table, Please see the core-isa.h
/*************************************************************************************************************
* Intr num Level Type PRO CPU usage APP CPU uasge
* 0 1 extern level WMAC Reserved
* 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA
* 2 1 extern level
* 3 1 extern level
* 4 1 extern level WBB
* 5 1 extern level BT/BLE Controller BT/BLE Controller
* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
* 7 1 software BT/BLE VHCI BT/BLE VHCI
* 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX)
* 9 1 extern level
* 10 1 extern edge
* 11 3 profiling
* 12 1 extern level
* 13 1 extern level
* 14 7 nmi Reserved Reserved
* 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3)
* 16 5 timer
* 17 1 extern level
* 18 1 extern level
* 19 2 extern level
* 20 2 extern level
* 21 2 extern level
* 22 3 extern edge
* 23 3 extern level
* 24 4 extern level TG1_WDT
* 25 4 extern level CACHEERR
* 26 5 extern level
* 27 3 extern level Reserved Reserved
* 28 4 extern edge DPORT ACCESS DPORT ACCESS
* 29 3 software Reserved Reserved
* 30 4 extern edge Reserved Reserved
* 31 5 extern level
*************************************************************************************************************
*/
//CPU0 Interrupt number reserved, not touch this.
#define ETS_WMAC_INUM 0
#define ETS_BT_HOST_INUM 1
#define ETS_WBB_INUM 4
#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
#define ETS_FRC1_INUM 22
#define ETS_T1_WDT_INUM 24
#define ETS_CACHEERR_INUM 25
#define ETS_DPORT_INUM 28
//CPU0 Interrupt number used in ROM, should be cancelled in SDK
#define ETS_SLC_INUM 1
#define ETS_UART0_INUM 5
#define ETS_UART1_INUM 5
//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here.
#define ETS_FRC_TIMER2_INUM 10 /* use edge*/
#define ETS_GPIO_INUM 4
//Other interrupt number should be managed by the user
//Invalid interrupt for number interrupt matrix
#define ETS_INVALID_INUM 6
#endif /* _ESP32_SOC_H_ */

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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
// This file contains various convenience macros to be used in ULP programs.
// Helper macros to calculate bit field width from mask, using the preprocessor.
// Used later in READ_RTC_FIELD and WRITE_RTC_FIELD.
#define IS_BIT_SET(m, i) (((m) >> (i)) & 1)
#define MASK_TO_WIDTH_HELPER1(m, i) IS_BIT_SET(m, i)
#define MASK_TO_WIDTH_HELPER2(m, i) (MASK_TO_WIDTH_HELPER1(m, i) + MASK_TO_WIDTH_HELPER1(m, i + 1))
#define MASK_TO_WIDTH_HELPER4(m, i) (MASK_TO_WIDTH_HELPER2(m, i) + MASK_TO_WIDTH_HELPER2(m, i + 2))
#define MASK_TO_WIDTH_HELPER8(m, i) (MASK_TO_WIDTH_HELPER4(m, i) + MASK_TO_WIDTH_HELPER4(m, i + 4))
#define MASK_TO_WIDTH_HELPER16(m, i) (MASK_TO_WIDTH_HELPER8(m, i) + MASK_TO_WIDTH_HELPER8(m, i + 8))
#define MASK_TO_WIDTH_HELPER32(m, i) (MASK_TO_WIDTH_HELPER16(m, i) + MASK_TO_WIDTH_HELPER16(m, i + 16))
// Peripheral register access macros, build around REG_RD and REG_WR instructions.
// Registers defined in rtc_cntl_reg.h, rtc_io_reg.h, sens_reg.h, and rtc_i2c_reg.h are usable with these macros.
// Read from rtc_reg[low_bit + bit_width - 1 : low_bit] into R0, bit_width <= 16
#define READ_RTC_REG(rtc_reg, low_bit, bit_width) \
REG_RD (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit)
// Write immediate value into rtc_reg[low_bit + bit_width - 1 : low_bit], bit_width <= 8
#define WRITE_RTC_REG(rtc_reg, low_bit, bit_width, value) \
REG_WR (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit), ((value) & 0xff)
// Read from a field in rtc_reg into R0, up to 16 bits
#define READ_RTC_FIELD(rtc_reg, field) \
READ_RTC_REG(rtc_reg, field ## _S, MASK_TO_WIDTH_HELPER16(field ## _V, 0))
// Write immediate value into a field in rtc_reg, up to 8 bits
#define WRITE_RTC_FIELD(rtc_reg, field, value) \
WRITE_RTC_REG(rtc_reg, field ## _S, MASK_TO_WIDTH_HELPER8(field ## _V, 0), ((value) & field ## _V))

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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SPI_MEM_STRUCT_H_
#define _SOC_SPI_MEM_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t reserved0: 17; /*reserved*/
uint32_t flash_pe: 1; /*In user mode it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t usr: 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_hpm: 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_res: 1; /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_dp: 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_ce: 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_be: 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_se: 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_pp: 1; /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
uint32_t flash_wrsr: 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_rdsr: 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_rdid: 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_t flash_wrdi: 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_t flash_wren: 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_t flash_read: 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
};
uint32_t val;
} cmd;
uint32_t addr; /*In user mode it is the memory address. other then the bit0-bit23 is the memory address the bit24-bit31 are the byte length of a transfer.*/
union {
struct {
uint32_t reserved0: 3; /*reserved*/
uint32_t dummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/
uint32_t reserved4: 3; /*reserved*/
uint32_t fcmd_dual: 1; /*Apply 2 signals during command phase 1:enable 0: disable*/
uint32_t fcmd_quad: 1; /*Apply 4 signals during command phase 1:enable 0: disable*/
uint32_t reserved9: 1; /*reserved*/
uint32_t fcs_crc_en: 1; /*For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.*/
uint32_t tx_crc_en: 1; /*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
uint32_t reserved12: 1; /*reserved*/
uint32_t fastrd_mode: 1; /*This bit enable the bits: spi_mem_fread_qio spi_mem_fread_dio spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/
uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/
uint32_t resandres: 1; /*The Device ID is read out to SPI_MEM_RD_STATUS register this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.*/
uint32_t reserved16: 1; /*reserved*/
uint32_t flash_suspending: 1; /*The status of flash suspend only used in SPI1.*/
uint32_t q_pol: 1; /*The bit is used to set MISO line polarity 1: high 0 low*/
uint32_t d_pol: 1; /*The bit is used to set MOSI line polarity 1: high 0 low*/
uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/
uint32_t wrsr_2b: 1; /*two bytes data will be written to status register when it is set. 1: enable 0: disable.*/
uint32_t fread_dio: 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/
uint32_t fread_qio: 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/
uint32_t reserved25: 7; /*reserved*/
};
uint32_t val;
} ctrl;
union {
struct {
uint32_t clk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
uint32_t cs_hold_delay_res:12; /*Delay cycles of resume Flash when resume Flash is enable by spi clock.*/
uint32_t cs_hold_delay: 6; /*SPI cs signal is delayed by spi clock cycles.*/
uint32_t reserved20: 12; /*reserved*/
};
uint32_t val;
} ctrl1;
union {
struct {
uint32_t cs_setup_time:13; /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
uint32_t cs_hold_time: 13; /*delay cycles of cs pin by spi clock this bits are combined with spi_mem_cs_hold bit.*/
uint32_t cs_delay_mode: 2; /*spi_mem_cs signal is delayed by spi_mem_clk . 0: zero 1: if spi_mem_ck_out_edge or spi_mem_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_mem_ck_out_edge or spi_mem_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/
uint32_t cs_delay_num: 2; /*spi_mem_cs signal is delayed by system clock cycles*/
uint32_t cs_delay_edge: 1; /*The bit is used to select the spi clock edge to modify CS line timing.*/
uint32_t sync_reset: 1; /*The FSM will be reset.*/
};
uint32_t val;
} ctrl2;
union {
struct {
uint32_t clkcnt_l: 8; /*In the master mode it must be equal to spi_mem_clkcnt_N. In the slave mode it must be 0.*/
uint32_t clkcnt_h: 8; /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). In the slave mode it must be 0.*/
uint32_t clkcnt_n: 8; /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
uint32_t reserved24: 7; /*In the master mode it is pre-divider of spi_mem_clk.*/
uint32_t clk_equ_sysclk: 1; /*reserved*/
};
uint32_t val;
} clock;
union {
struct {
uint32_t reserved0: 6; /*reserved*/
uint32_t cs_hold: 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable.*/
uint32_t cs_setup: 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/
uint32_t ck_i_edge: 1; /*In the slave mode the bit is same as spi_mem_ck_out_edge in master mode. It is combined with spi_mem_miso_delay_mode bits.*/
uint32_t ck_out_edge: 1; /*the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.*/
uint32_t reserved10: 2; /*reserved*/
uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals*/
uint32_t fwrite_quad: 1; /*In the write operations read-data phase apply 4 signals*/
uint32_t fwrite_dio: 1; /*In the write operations address phase and read-data phase apply 2 signals.*/
uint32_t fwrite_qio: 1; /*In the write operations address phase and read-data phase apply 4 signals.*/
uint32_t reserved16: 8; /*reserved*/
uint32_t usr_miso_highpart: 1; /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/
uint32_t usr_mosi_highpart: 1; /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/
uint32_t usr_dummy_idle: 1; /*spi clock is disable in dummy phase when the bit is enable.*/
uint32_t usr_mosi: 1; /*This bit enable the write-data phase of an operation.*/
uint32_t usr_miso: 1; /*This bit enable the read-data phase of an operation.*/
uint32_t usr_dummy: 1; /*This bit enable the dummy phase of an operation.*/
uint32_t usr_addr: 1; /*This bit enable the address phase of an operation.*/
uint32_t usr_command: 1; /*This bit enable the command phase of an operation.*/
};
uint32_t val;
} user;
union {
struct {
uint32_t usr_dummy_cyclelen: 8; /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
uint32_t reserved8: 18; /*reserved*/
uint32_t usr_addr_bitlen: 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/
};
uint32_t val;
} user1;
union {
struct {
uint32_t usr_command_value: 16; /*The value of command.*/
uint32_t reserved16: 12; /*reserved*/
uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/
};
uint32_t val;
} user2;
union {
struct {
uint32_t usr_mosi_bit_len:11; /*The length in bits of write-data. The register value shall be (bit_num-1).*/
uint32_t reserved11: 21; /*reserved*/
};
uint32_t val;
} mosi_dlen;
union {
struct {
uint32_t usr_miso_bit_len:11; /*The length in bits of read-data. The register value shall be (bit_num-1).*/
uint32_t reserved11: 21; /*reserved*/
};
uint32_t val;
} miso_dlen;
union {
struct {
uint32_t status: 16; /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
uint32_t wb_mode: 8; /*Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
} rd_status;
uint32_t ext_addr; /*The register are the higher 32bits in the 64 bits address mode.*/
union {
struct {
uint32_t cs0_dis: 1; /*SPI CS0 pin enable 1: disable CS0 0: spi_mem_cs0 signal is from/to CS0 pin*/
uint32_t cs1_dis: 1; /*SPI CS1 pin enable 1: disable CS1 0: spi_mem_cs1 signal is from/to CS1 pin*/
uint32_t reserved2: 1; /*reserved*/
uint32_t trans_end: 1; /*The bit is used to indicate the transimitting is done.*/
uint32_t trans_end_en: 1; /*The bit is used to enable the intterrupt of SPI transmitting done.*/
uint32_t cs_pol: 2; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_mem_cs ^ spi_mem_master_cs_pol.*/
uint32_t fsub_pin: 1; /*For SPI0 flash is connected to SUBPINs.*/
uint32_t ssub_pin: 1; /*For SPI0 sram is connected to SUBPINs.*/
uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/
uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set.*/
uint32_t auto_per: 1; /*reserved*/
uint32_t reserved12: 20; /*reserved*/
};
uint32_t val;
} misc;
uint32_t tx_crc; /*For SPI1 the value of crc32.*/
union {
struct {
uint32_t req_en: 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/
uint32_t usr_cmd_4byte: 1; /*For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/
uint32_t flash_usr_cmd: 1; /*For SPI0 cache read flash for user define command 1: enable 0:disable.*/
uint32_t fdin_dual: 1; /*For SPI0 flash din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
uint32_t fdout_dual: 1; /*For SPI0 flash dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
uint32_t faddr_dual: 1; /*For SPI0 flash address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
uint32_t fdin_quad: 1; /*For SPI0 flash din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
uint32_t fdout_quad: 1; /*For SPI0 flash dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
uint32_t faddr_quad: 1; /*For SPI0 flash address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
} cache_fctrl;
union {
struct {
uint32_t usr_scmd_4byte: 1; /*For SPI0 In the spi sram mode cache read flash with 4 bytes command 1: enable 0:disable.*/
uint32_t usr_sram_dio: 1; /*For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/
uint32_t usr_sram_qio: 1; /*For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/
uint32_t usr_wr_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations.*/
uint32_t usr_rd_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.*/
uint32_t cache_sram_usr_rcmd: 1; /*For SPI0 In the spi sram mode cache read sram for user define command.*/
uint32_t sram_rdummy_cyclelen: 8; /*For SPI0 In the sram mode it is the length in bits of read dummy phase. The register value shall be (bit_num-1).*/
uint32_t sram_addr_bitlen: 6; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/
uint32_t cache_sram_usr_wcmd: 1; /*For SPI0 In the spi sram mode cache write sram for user define command*/
uint32_t reserved21: 1; /*reserved*/
uint32_t sram_wdummy_cyclelen: 8; /*For SPI0 In the sram mode it is the length in bits of write dummy phase. The register value shall be (bit_num-1).*/
uint32_t reserved30: 2; /*reserved*/
};
uint32_t val;
} cache_sctrl;
union {
struct {
uint32_t sclk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
uint32_t swb_mode: 8; /*Mode bits in the psram fast read mode it is combined with spi_mem_fastrd_mode bit.*/
uint32_t sdin_dual: 1; /*For SPI0 sram din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
uint32_t sdout_dual: 1; /*For SPI0 sram dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
uint32_t saddr_dual: 1; /*For SPI0 sram address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
uint32_t scmd_dual: 1; /*For SPI0 sram cmd phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
uint32_t sdin_quad: 1; /*For SPI0 sram din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
uint32_t sdout_quad: 1; /*For SPI0 sram dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
uint32_t saddr_quad: 1; /*For SPI0 sram address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
uint32_t scmd_quad: 1; /*For SPI0 sram cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
uint32_t reserved18:14; /*reserved*/
};
uint32_t val;
} sram_cmd;
union {
struct {
uint32_t usr_rd_cmd_value: 16; /*For SPI0 When cache mode is enable it is the read command value of command phase for sram.*/
uint32_t reserved16: 12; /*reserved*/
uint32_t usr_rd_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1).*/
};
uint32_t val;
} sram_drd_cmd;
union {
struct {
uint32_t usr_wr_cmd_value: 16; /*For SPI0 When cache mode is enable it is the write command value of command phase for sram.*/
uint32_t reserved16: 12; /*reserved*/
uint32_t usr_wr_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1).*/
};
uint32_t val;
} sram_dwr_cmd;
union {
struct {
uint32_t cnt_l: 8; /*For SPI0 sram interface it must be equal to spi_mem_clkcnt_N. In the slave mode it must be 0.*/
uint32_t cnt_h: 8; /*For SPI0 sram interface it must be floor((spi_mem_clkcnt_N+1)/2-1). In the slave mode it must be 0.*/
uint32_t cnt_n: 8; /*For SPI0 sram interface it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
uint32_t reserved24: 7; /*reserved*/
uint32_t equ_sysclk: 1; /*For SPI0 sram interface 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/
};
uint32_t val;
} sram_clk;
union {
struct {
uint32_t st: 3; /*The status of spi state machine. 0: idle state 1: preparation state 2: send command state 3: send data state 4: red data state 5:write data state 6: wait state 7: done state.*/
uint32_t reserved3: 29; /*reserved*/
};
uint32_t val;
} fsm;
union {
struct {
uint32_t hold_ena: 2; /*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at idle phase 2: hold at prepare phase.*/
uint32_t reserved2: 30; /*reserved*/
};
uint32_t val;
} hold;
union {
struct {
uint32_t dma_rx_ena: 1; /*spi dma rx data enable.*/
uint32_t dma_tx_ena: 1; /*spi dma tx data enable.*/
uint32_t in_rst: 1; /*The bit is used to reset in dma fsm and in data fifo pointer.*/
uint32_t out_rst: 1; /*The bit is used to reset out dma fsm and out data fifo pointer.*/
uint32_t ahbm_fifo_rst: 1; /*Reset spi dma ahb master fifo pointer.*/
uint32_t ahbm_rst: 1; /*Reset spi dma ahb master.*/
uint32_t in_loop_test: 1; /*Set bit to test in link.*/
uint32_t out_loop_test: 1; /*Set bit to test out link.*/
uint32_t out_auto_wrback: 1; /*when the bit is set DMA continue to use the next inlink node when the length of inlink is 0.*/
uint32_t out_eof_mode: 1; /*out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo.*/
uint32_t outdscr_burst_en: 1; /*read descriptor use burst mode when read data for memory.*/
uint32_t indscr_burst_en: 1; /*read descriptor use burst mode when write data to memory.*/
uint32_t out_data_burst_en: 1; /*spi dma read data from memory in burst mode.*/
uint32_t dma_mem_trans_ena: 1; /*reserved*/
uint32_t dma_rx_stop: 1; /*spi dma read data stop when in continue tx/rx mode.*/
uint32_t dma_tx_stop: 1; /*spi dma write data stop when in continue tx/rx mode.*/
uint32_t dma_continue: 1; /*spi dma continue tx/rx data.*/
uint32_t reserved17: 15; /*reserved*/
};
uint32_t val;
} dma_conf;
union {
struct {
uint32_t addr: 20; /*The address of the first outlink descriptor.*/
uint32_t reserved20: 8; /*reserved*/
uint32_t stop: 1; /*Set the bit to stop to use outlink descriptor.*/
uint32_t start: 1; /*Set the bit to start to use outlink descriptor.*/
uint32_t restart: 1; /*Set the bit to mount on new outlink descriptors.*/
uint32_t reserved31: 1; /*reserved*/
};
uint32_t val;
} dma_out_link;
union {
struct {
uint32_t addr: 20; /*The address of the first inlink descriptor.*/
uint32_t auto_ret: 1; /*when the bit is set the inlink descriptor returns to the first link node when a packet is error.*/
uint32_t reserved21: 7; /*reserved*/
uint32_t stop: 1; /*Set the bit to stop to use inlink descriptor.*/
uint32_t start: 1; /*Set the bit to start to use inlink descriptor.*/
uint32_t restart: 1; /*Set the bit to mount on new inlink descriptors.*/
uint32_t reserved31: 1; /*reserved*/
};
uint32_t val;
} dma_in_link;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The enable bit for lack of enough inlink descriptors.*/
uint32_t outlink_dscr_error: 1; /*The enable bit for outlink descriptor error.*/
uint32_t inlink_dscr_error: 1; /*The enable bit for inlink descriptor error.*/
uint32_t in_done: 1; /*The enable bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The enable bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The enable bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The enable bit for completing usage of a outlink descriptor .*/
uint32_t out_eof: 1; /*The enable bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The enable bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
} dma_int_ena;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The raw bit for lack of enough inlink descriptors.*/
uint32_t outlink_dscr_error: 1; /*The raw bit for outlink descriptor error.*/
uint32_t inlink_dscr_error: 1; /*The raw bit for inlink descriptor error.*/
uint32_t in_done: 1; /*The raw bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The raw bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The raw bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The raw bit for completing usage of a outlink descriptor.*/
uint32_t out_eof: 1; /*The raw bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The raw bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
} dma_int_raw;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The status bit for lack of enough inlink descriptors.*/
uint32_t outlink_dscr_error: 1; /*The status bit for outlink descriptor error.*/
uint32_t inlink_dscr_error: 1; /*The status bit for inlink descriptor error.*/
uint32_t in_done: 1; /*The status bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The status bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The status bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The status bit for completing usage of a outlink descriptor.*/
uint32_t out_eof: 1; /*The status bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The status bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
} dma_int_st;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The clear bit for lack of enough inlink descriptors.*/
uint32_t outlink_dscr_error: 1; /*The clear bit for outlink descriptor error.*/
uint32_t inlink_dscr_error: 1; /*The clear bit for inlink descriptor error.*/
uint32_t in_done: 1; /*The clear bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The clear bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The clear bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The clear bit for completing usage of a outlink descriptor.*/
uint32_t out_eof: 1; /*The clear bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The clear bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
} dma_int_clr;
uint32_t dma_in_err_eof_des_addr; /*The inlink descriptor address when spi dma produce receiving error.*/
uint32_t dma_in_suc_eof_des_addr; /*The last inlink descriptor address when spi dma produce from_suc_eof.*/
uint32_t dma_inlink_dscr; /*The content of current in descriptor pointer.*/
uint32_t dma_inlink_dscr_bf0; /*The content of next in descriptor pointer.*/
uint32_t dma_inlink_dscr_bf1; /*The content of current in descriptor data buffer pointer.*/
uint32_t dma_out_eof_bfr_des_addr; /*The address of buffer relative to the outlink descriptor that produce eof.*/
uint32_t dma_out_eof_des_addr; /*The last outlink descriptor address when spi dma produce to_eof.*/
uint32_t dma_outlink_dscr; /*The content of current out descriptor pointer.*/
uint32_t dma_outlink_dscr_bf0; /*The content of next out descriptor pointer.*/
uint32_t dma_outlink_dscr_bf1; /*The content of current out descriptor data buffer pointer.*/
union {
struct {
uint32_t out_dscr_addr: 18; /*SPI dma out descriptor address.*/
uint32_t out_dscr_state: 2; /*SPI dma out descriptor state.*/
uint32_t out_state: 3; /*SPI dma out data state.*/
uint32_t out_fifo_cnt: 7; /*The remains of SPI dma outfifo data.*/
uint32_t out_fifo_full: 1; /*SPI dma outfifo is full.*/
uint32_t out_fifo_empty: 1; /*SPI dma outfifo is empty.*/
};
uint32_t val;
} dma_out_status;
union {
struct {
uint32_t in_dscr_addr: 18; /*SPI dma in descriptor address.*/
uint32_t in_dscr_state: 2; /*SPI dma in descriptor state.*/
uint32_t in_state: 3; /*SPI dma in data state.*/
uint32_t in_fifo_cnt: 7; /*The remains of SPI dma infifo data.*/
uint32_t in_fifo_full: 1; /*SPI dma infifo is full.*/
uint32_t in_fifo_empty: 1; /*SPI dma infifo is empty.*/
};
uint32_t val;
} dma_in_status;
uint32_t data_buf[16]; /*data buffer*/
union {
struct {
uint32_t waiti_en: 1; /*auto-waiting flash idle operation when program flash or erase flash. 1: enable 0: disable.*/
uint32_t waiti_dummy: 1; /*The dummy phase enable when auto wait flash idle*/
uint32_t waiti_cmd: 8; /*The command to auto wait idle*/
uint32_t waiti_dummy_cyclelen: 8; /*The dummy cycle length when auto wait flash idle*/
uint32_t reserved18: 14; /*reserved*/
};
uint32_t val;
} flash_waiti_ctrl;
union {
struct {
uint32_t flash_per: 1; /*program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_pes: 1; /*program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t reserved2: 30;
};
uint32_t val;
} flash_sus_cmd;
union {
struct {
uint32_t flash_pes_en: 1; /*Auto-suspending enable*/
uint32_t flash_per_command: 8; /*Program/Erase resume command.*/
uint32_t flash_pes_command: 8; /*Program/Erase suspend command.*/
uint32_t reserved17: 15;
};
uint32_t val;
} flash_sus_ctrl;
union {
struct {
uint32_t din0_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din1_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din2_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din3_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t reserved8: 10; /*reserved*/
uint32_t din0_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t din1_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t din2_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t din3_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t reserved22: 10; /*reserved*/
};
uint32_t val;
} din_mode;
union {
struct {
uint32_t din0_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din1_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din2_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din3_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t reserved8: 24; /*reserved*/
};
uint32_t val;
} din_num;
union {
struct {
uint32_t dout0_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout1_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout2_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout3_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t reserved8: 10; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout0_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t dout1_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t dout2_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t dout3_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t reserved22: 10; /*reserved*/
};
uint32_t val;
} dout_mode;
union {
struct {
uint32_t dout0_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout1_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout2_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout3_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t reserved8: 24; /*reserved*/
};
uint32_t val;
} dout_num;
union {
struct {
uint32_t sdin0_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t sdin1_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t sdin2_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t sdin3_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t reserved8: 10;
uint32_t sdin0_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t sdin1_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t sdin2_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t sdin3_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t reserved22: 10; /*reserved*/
};
uint32_t val;
} sdin_mode;
union {
struct {
uint32_t sdin0_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t sdin1_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t sdin2_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t sdin3_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t reserved8: 24; /*reserved*/
};
uint32_t val;
} sdin_num;
union {
struct {
uint32_t sdout0_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t sdout1_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t sdout2_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t sdout3_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t reserved8: 10; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t sdout0_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t sdout1_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t sdout2_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t sdout3_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t reserved22: 10; /*reserved*/
};
uint32_t val;
} sdout_mode;
union {
struct {
uint32_t sdout0_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t sdout1_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t sdout2_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t sdout3_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t reserved8: 24; /*reserved*/
};
uint32_t val;
} sdout_num;
union {
struct {
uint32_t clk_en: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} clock_gate;
uint32_t reserved_118;
uint32_t reserved_11c;
uint32_t reserved_120;
uint32_t reserved_124;
uint32_t reserved_128;
uint32_t reserved_12c;
uint32_t reserved_130;
uint32_t reserved_134;
uint32_t reserved_138;
uint32_t reserved_13c;
uint32_t reserved_140;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
uint32_t reserved_1fc;
uint32_t reserved_200;
uint32_t reserved_204;
uint32_t reserved_208;
uint32_t reserved_20c;
uint32_t reserved_210;
uint32_t reserved_214;
uint32_t reserved_218;
uint32_t reserved_21c;
uint32_t reserved_220;
uint32_t reserved_224;
uint32_t reserved_228;
uint32_t reserved_22c;
uint32_t reserved_230;
uint32_t reserved_234;
uint32_t reserved_238;
uint32_t reserved_23c;
uint32_t reserved_240;
uint32_t reserved_244;
uint32_t reserved_248;
uint32_t reserved_24c;
uint32_t reserved_250;
uint32_t reserved_254;
uint32_t reserved_258;
uint32_t reserved_25c;
uint32_t reserved_260;
uint32_t reserved_264;
uint32_t reserved_268;
uint32_t reserved_26c;
uint32_t reserved_270;
uint32_t reserved_274;
uint32_t reserved_278;
uint32_t reserved_27c;
uint32_t reserved_280;
uint32_t reserved_284;
uint32_t reserved_288;
uint32_t reserved_28c;
uint32_t reserved_290;
uint32_t reserved_294;
uint32_t reserved_298;
uint32_t reserved_29c;
uint32_t reserved_2a0;
uint32_t reserved_2a4;
uint32_t reserved_2a8;
uint32_t reserved_2ac;
uint32_t reserved_2b0;
uint32_t reserved_2b4;
uint32_t reserved_2b8;
uint32_t reserved_2bc;
uint32_t reserved_2c0;
uint32_t reserved_2c4;
uint32_t reserved_2c8;
uint32_t reserved_2cc;
uint32_t reserved_2d0;
uint32_t reserved_2d4;
uint32_t reserved_2d8;
uint32_t reserved_2dc;
uint32_t reserved_2e0;
uint32_t reserved_2e4;
uint32_t reserved_2e8;
uint32_t reserved_2ec;
uint32_t reserved_2f0;
uint32_t reserved_2f4;
uint32_t reserved_2f8;
uint32_t reserved_2fc;
uint32_t reserved_300;
uint32_t reserved_304;
uint32_t reserved_308;
uint32_t reserved_30c;
uint32_t reserved_310;
uint32_t reserved_314;
uint32_t reserved_318;
uint32_t reserved_31c;
uint32_t reserved_320;
uint32_t reserved_324;
uint32_t reserved_328;
uint32_t reserved_32c;
uint32_t reserved_330;
uint32_t reserved_334;
uint32_t reserved_338;
uint32_t reserved_33c;
uint32_t reserved_340;
uint32_t reserved_344;
uint32_t reserved_348;
uint32_t reserved_34c;
uint32_t reserved_350;
uint32_t reserved_354;
uint32_t reserved_358;
uint32_t reserved_35c;
uint32_t reserved_360;
uint32_t reserved_364;
uint32_t reserved_368;
uint32_t reserved_36c;
uint32_t reserved_370;
uint32_t reserved_374;
uint32_t reserved_378;
uint32_t reserved_37c;
uint32_t reserved_380;
uint32_t reserved_384;
uint32_t reserved_388;
uint32_t reserved_38c;
uint32_t reserved_390;
uint32_t reserved_394;
uint32_t reserved_398;
uint32_t reserved_39c;
uint32_t reserved_3a0;
uint32_t reserved_3a4;
uint32_t reserved_3a8;
uint32_t reserved_3ac;
uint32_t reserved_3b0;
uint32_t reserved_3b4;
uint32_t reserved_3b8;
uint32_t reserved_3bc;
uint32_t reserved_3c0;
uint32_t reserved_3c4;
uint32_t reserved_3c8;
uint32_t reserved_3cc;
uint32_t reserved_3d0;
uint32_t reserved_3d4;
uint32_t reserved_3d8;
uint32_t reserved_3dc;
uint32_t reserved_3e0;
uint32_t reserved_3e4;
uint32_t reserved_3e8;
uint32_t reserved_3ec;
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
union {
struct {
uint32_t date: 28; /*SPI register version.*/
uint32_t reserved28: 4; /*reserved*/
};
uint32_t val;
} date;
} spi_mem_dev_t;
extern spi_mem_dev_t SPIMEM0;
extern spi_mem_dev_t SPIMEM1;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_SPI_MEM_STRUCT_H_ */

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components/soc/esp32s2beta/include/soc/spi_pins.h Normal file
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// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SPI_PINS_H_
#define _SOC_SPI_PINS_H_
#define SPI_PERIPH_NUM 4
#define SPI_FUNC_NUM 2
#define SPI_IOMUX_PIN_NUM_HD 27
#define SPI_IOMUX_PIN_NUM_CS 29
#define SPI_IOMUX_PIN_NUM_MOSI 32
#define SPI_IOMUX_PIN_NUM_CLK 30
#define SPI_IOMUX_PIN_NUM_MISO 31
#define SPI_IOMUX_PIN_NUM_WP 28
//TODO: add the next slot
#define FSPI_FUNC_NUM 0
#define FSPI_IOMUX_PIN_NUM_HD 9
#define FSPI_IOMUX_PIN_NUM_CS 10
#define FSPI_IOMUX_PIN_NUM_MOSI 11
#define FSPI_IOMUX_PIN_NUM_CLK 12
#define FSPI_IOMUX_PIN_NUM_MISO 13
#define FSPI_IOMUX_PIN_NUM_WP 14
//TODO: add the next slot
//HSPI and VSPI have no iomux pins
#endif

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components/soc/esp32s2beta/include/soc/spi_struct.h Normal file
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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SPI_STRUCT_H_
#define _SOC_SPI_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t reserved0: 18; /*reserved*/
uint32_t usr: 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t reserved19:13;
};
uint32_t val;
} cmd;
uint32_t addr; /*[31:8]:address to slave [7:0]:Reserved.*/
union {
struct {
uint32_t reserved0: 2; /*reserved*/
uint32_t ext_hold_en: 1; /*Set the bit to hold spi. The bit is combined with spi_usr_prep_hold spi_usr_cmd_hold spi_usr_addr_hold spi_usr_dummy_hold spi_usr_din_hold spi_usr_dout_hold and spi_usr_hold_pol.*/
uint32_t dummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/
uint32_t reserved4: 1; /*reserved*/
uint32_t faddr_dual: 1; /*Apply 2 signals during addr phase 1:enable 0: disable*/
uint32_t faddr_quad: 1; /*Apply 4 signals during addr phase 1:enable 0: disable*/
uint32_t fcmd_dual: 1; /*Apply 2 signals during command phase 1:enable 0: disable*/
uint32_t fcmd_quad: 1; /*Apply 4 signals during command phase 1:enable 0: disable*/
uint32_t reserved9: 4;
uint32_t fast_rd_mode: 1; /*Enable 2/4 lines addr command including read and write command.*/
uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/
uint32_t reserved15: 3;
uint32_t q_pol: 1; /*The bit is used to set MISO line polarity 1: high 0 low*/
uint32_t d_pol: 1; /*The bit is used to set MOSI line polarity 1: high 0 low*/
uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/
uint32_t reserved22: 3; /*reserved*/
uint32_t rd_bit_order: 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first*/
uint32_t wr_bit_order: 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/
uint32_t define_addr: 1; /*set spi_usr_addr and spi_usr_addr_value in spi defined slave mode. 1: disable 0:enable.*/
uint32_t reserved28: 4; /*reserved*/
};
uint32_t val;
} ctrl;
union {
struct {
uint32_t clk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
uint32_t clk_mode_13: 1; /*{CPOL CPHA} 1: support spi clk mode 1 and 3 first edge output data B[0]/B[7]*/
uint32_t rsck_data_out: 1; /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge*/
uint32_t w16_17_wr_ena: 1; /*1:reg_buf[16] [17] can be written 0:reg_buf[16] [17] can not be written.*/
uint32_t reserved5: 9; /*reserved*/
uint32_t cs_hold_delay: 6; /*SPI cs signal is delayed by spi clock cycles.*/
uint32_t reserved20: 12;
};
uint32_t val;
} ctrl1;
union {
struct {
uint32_t cs_setup_time:13; /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit.*/
uint32_t cs_hold_time: 13; /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.*/
uint32_t cs_delay_mode: 2; /*spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/
uint32_t cs_delay_num: 2; /*spi_cs signal is delayed by system clock cycles*/
uint32_t reserved30: 1; /*reserved*/
uint32_t cs_delay_edge: 1;
};
uint32_t val;
} ctrl2;
union {
struct {
uint32_t clkcnt_l: 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0.*/
uint32_t clkcnt_h: 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0.*/
uint32_t clkcnt_n: 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/
uint32_t clkdiv_pre: 13; /*In the master mode it is pre-divider of spi_clk.*/
uint32_t clk_equ_sysclk: 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock.*/
};
uint32_t val;
} clock;
union {
struct {
uint32_t doutdin: 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable.*/
uint32_t tx_start_bit: 3; /*It determines the start time of tx output data. It can be used for timing adjustment in MISO slave mode.*/
uint32_t reserved4: 1; /*reserved*/
uint32_t tsck_i_edge: 1; /*In the slave mode this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/
uint32_t cs_hold: 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable.*/
uint32_t cs_setup: 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/
uint32_t rsck_i_edge: 1; /*In the slave mode this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/
uint32_t ck_out_edge: 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/
uint32_t rd_byte_order: 1; /*In read-data (MISO) phase 1: big-endian 0: little_endian*/
uint32_t wr_byte_order: 1; /*In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/
uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals*/
uint32_t fwrite_quad: 1; /*In the write operations read-data phase apply 4 signals*/
uint32_t reserved14: 1; /*reserved*/
uint32_t reserved15: 1; /*reserved*/
uint32_t sio: 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable.*/
uint32_t usr_hold_pol: 1; /*It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/
uint32_t usr_dout_hold: 1; /*spi is hold at data out state the bit are combined with spi_usr_hold_pol bit.*/
uint32_t usr_din_hold: 1; /*spi is hold at data in state the bit are combined with spi_usr_hold_pol bit.*/
uint32_t usr_dummy_hold: 1; /*spi is hold at dummy state the bit are combined with spi_usr_hold_pol bit.*/
uint32_t usr_addr_hold: 1; /*spi is hold at address state the bit are combined with spi_usr_hold_pol bit.*/
uint32_t usr_cmd_hold: 1; /*spi is hold at command state the bit are combined with spi_usr_hold_pol bit.*/
uint32_t usr_prep_hold: 1; /*spi is hold at prepare state the bit are combined with spi_usr_hold_pol bit.*/
uint32_t usr_miso_highpart: 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/
uint32_t usr_mosi_highpart: 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/
uint32_t usr_dummy_idle: 1; /*spi clock is disable in dummy phase when the bit is enable.*/
uint32_t usr_mosi: 1; /*This bit enable the write-data phase of an operation.*/
uint32_t usr_miso: 1; /*This bit enable the read-data phase of an operation.*/
uint32_t usr_dummy: 1; /*This bit enable the dummy phase of an operation.*/
uint32_t usr_addr: 1; /*This bit enable the address phase of an operation.*/
uint32_t usr_command: 1; /*This bit enable the command phase of an operation.*/
};
uint32_t val;
} user;
union {
struct {
uint32_t usr_dummy_cyclelen: 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
uint32_t reserved8: 18; /*reserved*/
uint32_t usr_addr_bitlen: 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/
};
uint32_t val;
} user1;
union {
struct {
uint32_t usr_command_value: 16; /*The value of command.*/
uint32_t reserved16: 12; /*reserved*/
uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/
};
uint32_t val;
} user2;
union {
struct {
uint32_t usr_mosi_bit_len:24; /*The length in bits of write-data. The register value shall be (bit_num-1).*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
} mosi_dlen;
union {
struct {
uint32_t usr_miso_bit_len:24; /*The length in bits of read-data. The register value shall be (bit_num-1).*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
} miso_dlen;
uint32_t slv_wr_status; /*In the master mode this register are the higher 32bits in the 64 bits address condition.*/
union {
struct {
uint32_t cs0_dis: 1; /*SPI CS0 pin enable 1: disable CS0 0: spi_cs0 signal is from/to CS0 pin*/
uint32_t cs1_dis: 1; /*SPI CS1 pin enable 1: disable CS1 0: spi_cs1 signal is from/to CS1 pin*/
uint32_t cs2_dis: 1; /*SPI CS2 pin enable 1: disable CS2 0: spi_cs2 signal is from/to CS2 pin*/
uint32_t reserved3: 2; /*reserved*/
uint32_t ck_dis: 1; /*1: spi clk out disable 0: spi clk out enable*/
uint32_t master_cs_pol: 3; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol.*/
uint32_t reserved9: 14; /*reserved*/
uint32_t slave_cs_pol: 1; /*spi slave input cs polarity select. 1: inv 0: not change*/
uint32_t reserved24: 3; /*reserved*/
uint32_t q_idle_out: 1; /*The idle output value of spi_q.*/
uint32_t reserved28: 1; /*reserved*/
uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/
uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set.*/
uint32_t quad_din_pin_swap: 1; /*1: spi quad input swap enable 0: spi quad input swap disable*/
};
uint32_t val;
} misc;
union {
struct {
uint32_t reserved0: 4; /*reserved*/
uint32_t trans_done: 1; /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.*/
uint32_t rd_buf_inten: 1; /*The interrupt enable bit for the completion of read-buffer operation in the slave mode.*/
uint32_t wr_buf_inten: 1; /*The interrupt enable bit for the completion of write-buffer operation in the slave mode.*/
uint32_t rd_dma_inten: 1; /*The interrupt enable bit for the completion of read-status operation in the slave mode.*/
uint32_t wr_dma_inten: 1; /*The interrupt enable bit for the completion of write-status operation in the slave mode.*/
uint32_t trans_inten: 1; /*The interrupt enable bit for the completion of any operation in both the master mode and the slave mode.*/
uint32_t reserved10:13; /*reserved*/
uint32_t trans_cnt: 4; /*The operations counter in both the master mode and the slave mode.*/
uint32_t reserved27: 1; /*reserved*/
uint32_t reserved28: 1; /*reserved*/
uint32_t reserved29: 1; /*reserved*/
uint32_t slave_mode: 1; /*Set SPI work mode. 1: slave mode 0: master mode.*/
uint32_t sync_reset: 1; /*Software reset enable reset the spi clock line cs line and data lines.*/
};
uint32_t val;
} slave;
union {
struct {
uint32_t rd_addr_bytelen: 4; /*In the slave mode it is the address length in bytes for read-buffer operation. The register value shall be byte_num.*/
uint32_t wr_addr_bytelen: 4; /*In the slave mode it is the address length in bytes for write-buffer operation. The register value shall be byte_num.*/
uint32_t reserved8: 3; /*reserved*/
uint32_t wr_dma_done: 1; /*The interrupt raw bit for the completion of dma write operation in the slave mode.*/
uint32_t last_command: 3; /*In the slave mode it is the value of command.*/
uint32_t last_addr: 7; /*In the slave mode it is the value of address.*/
uint32_t reserved22: 10; /*reserved*/
};
uint32_t val;
} slave1;
union {
struct {
uint32_t rd_dummy_bytelen: 4; /*In the slave mode it is the length in spi_clk byte cycles of dummy phase for read operations.*/
uint32_t wr_dummy_bytelen: 4; /*In the slave mode it is the length in spi_clk byte cycles of dummy phase for write operations.*/
uint32_t rd_dma_done: 1; /*The interrupt raw bit for the completion of dma read operation in the slave mode.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
} slave2;
union {
struct {
uint32_t bit_len: 24; /*In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1).*/
uint32_t wr_buf_done: 1; /*The interrupt raw bit for the completion of write-buffer operation in the slave mode.*/
uint32_t reserved25: 7; /*reserved*/
};
uint32_t val;
} slv_wrbuf_dlen;
union {
struct {
uint32_t bit_len: 24; /*In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1).*/
uint32_t rd_buf_done: 1; /*The interrupt raw bit for the completion of read-buffer operation in the slave mode.*/
uint32_t reserved25: 7; /*reserved*/
};
uint32_t val;
} slv_rdbuf_dlen;
union {
struct {
uint32_t slv_rdata_bit:24; /*In the slave mode it is the byte number of read data.*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
} slv_rd_byte;
uint32_t reserved_4c;
union {
struct {
uint32_t st: 3; /*The status of spi state machine. 0: idle state 1: preparation state 2: send command state 3: send data state 4: red data state 5:write data state 6: wait state 7: done state.*/
uint32_t reserved3: 29; /*reserved*/
};
uint32_t val;
} fsm;
union {
struct {
uint32_t int_hold_ena: 2; /*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at idle phase 2: hold at prepare phase.*/
uint32_t hold_val: 1; /*spi hold output value which should be used with spi_hold_out_en.*/
uint32_t hold_out_en: 1; /*Enable set spi output hold value to spi_hold_reg. It can be used to hold spi state machine with spi_ext_hold_en and other usr hold signals.*/
uint32_t hold_out_time: 3; /*set the hold cycles of output spi_hold signal when spi_hold_out_en is enable.*/
uint32_t reserved7: 25; /*reserved*/
};
uint32_t val;
} hold;
union {
struct {
uint32_t reserved0: 2; /*reserved*/
uint32_t in_rst: 1; /*The bit is used to reset in dma fsm and in data fifo pointer.*/
uint32_t out_rst: 1; /*The bit is used to reset out dma fsm and out data fifo pointer.*/
uint32_t ahbm_fifo_rst: 1; /*Reset spi dma ahb master fifo pointer.*/
uint32_t ahbm_rst: 1; /*Reset spi dma ahb master.*/
uint32_t in_loop_test: 1; /*Set bit to test in link.*/
uint32_t out_loop_test: 1; /*Set bit to test out link.*/
uint32_t out_auto_wrback: 1; /*when the bit is set DMA continue to use the next inlink node when the length of inlink is 0.*/
uint32_t out_eof_mode: 1; /*out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo.*/
uint32_t outdscr_burst_en: 1; /*read descriptor use burst mode when read data for memory.*/
uint32_t indscr_burst_en: 1; /*read descriptor use burst mode when write data to memory.*/
uint32_t out_data_burst_en: 1; /*spi dma read data from memory in burst mode.*/
uint32_t mem_trans_en: 1;
uint32_t dma_rx_stop: 1; /*spi dma read data stop when in continue tx/rx mode.*/
uint32_t dma_tx_stop: 1; /*spi dma write data stop when in continue tx/rx mode.*/
uint32_t dma_continue: 1; /*spi dma continue tx/rx data.*/
uint32_t reserved17: 15; /*reserved*/
};
uint32_t val;
} dma_conf;
union {
struct {
uint32_t addr: 20; /*The address of the first outlink descriptor.*/
uint32_t reserved20: 8; /*reserved*/
uint32_t stop: 1; /*Set the bit to stop to use outlink descriptor.*/
uint32_t start: 1; /*Set the bit to start to use outlink descriptor.*/
uint32_t restart: 1; /*Set the bit to mount on new outlink descriptors.*/
uint32_t dma_tx_ena: 1; /*spi dma write data status bit.*/
};
uint32_t val;
} dma_out_link;
union {
struct {
uint32_t addr: 20; /*The address of the first inlink descriptor.*/
uint32_t auto_ret: 1; /*when the bit is set the inlink descriptor returns to the first link node when a packet is error.*/
uint32_t reserved21: 7; /*reserved*/
uint32_t stop: 1; /*Set the bit to stop to use inlink descriptor.*/
uint32_t start: 1; /*Set the bit to start to use inlink descriptor.*/
uint32_t restart: 1; /*Set the bit to mount on new inlink descriptors.*/
uint32_t dma_rx_ena: 1; /*spi dma read data status bit.*/
};
uint32_t val;
} dma_in_link;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The enable bit for lack of enough inlink descriptors.*/
uint32_t outlink_dscr_error: 1; /*The enable bit for outlink descriptor error.*/
uint32_t inlink_dscr_error: 1; /*The enable bit for inlink descriptor error.*/
uint32_t in_done: 1; /*The enable bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The enable bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The enable bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The enable bit for completing usage of a outlink descriptor .*/
uint32_t out_eof: 1; /*The enable bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The enable bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
} dma_int_ena;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The raw bit for lack of enough inlink descriptors.*/
uint32_t outlink_dscr_error: 1; /*The raw bit for outlink descriptor error.*/
uint32_t inlink_dscr_error: 1; /*The raw bit for inlink descriptor error.*/
uint32_t in_done: 1; /*The raw bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The raw bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The raw bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The raw bit for completing usage of a outlink descriptor.*/
uint32_t out_eof: 1; /*The raw bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The raw bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
} dma_int_raw;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The status bit for lack of enough inlink descriptors.*/
uint32_t outlink_dscr_error: 1; /*The status bit for outlink descriptor error.*/
uint32_t inlink_dscr_error: 1; /*The status bit for inlink descriptor error.*/
uint32_t in_done: 1; /*The status bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The status bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The status bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The status bit for completing usage of a outlink descriptor.*/
uint32_t out_eof: 1; /*The status bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The status bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
} dma_int_st;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The clear bit for lack of enough inlink descriptors.*/
uint32_t outlink_dscr_error: 1; /*The clear bit for outlink descriptor error.*/
uint32_t inlink_dscr_error: 1; /*The clear bit for inlink descriptor error.*/
uint32_t in_done: 1; /*The clear bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The clear bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The clear bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The clear bit for completing usage of a outlink descriptor.*/
uint32_t out_eof: 1; /*The clear bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The clear bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
} dma_int_clr;
uint32_t dma_in_err_eof_des_addr; /*The inlink descriptor address when spi dma produce receiving error.*/
uint32_t dma_in_suc_eof_des_addr; /*The last inlink descriptor address when spi dma produce from_suc_eof.*/
uint32_t dma_inlink_dscr; /*The content of current in descriptor pointer.*/
uint32_t dma_inlink_dscr_bf0; /*The content of next in descriptor pointer.*/
uint32_t dma_inlink_dscr_bf1; /*The content of current in descriptor data buffer pointer.*/
uint32_t dma_out_eof_bfr_des_addr; /*The address of buffer relative to the outlink descriptor that produce eof.*/
uint32_t dma_out_eof_des_addr; /*The last outlink descriptor address when spi dma produce to_eof.*/
uint32_t dma_outlink_dscr; /*The content of current out descriptor pointer.*/
uint32_t dma_outlink_dscr_bf0; /*The content of next out descriptor pointer.*/
uint32_t dma_outlink_dscr_bf1; /*The content of current out descriptor data buffer pointer.*/
union {
struct {
uint32_t out_dscr_addr: 18; /*SPI dma out descriptor address.*/
uint32_t out_dscr_state: 2; /*SPI dma out descriptor state.*/
uint32_t out_state: 3; /*SPI dma out data state.*/
uint32_t out_fifo_cnt: 7; /*The remains of SPI dma outfifo data.*/
uint32_t out_fifo_full: 1; /*SPI dma outfifo is full.*/
uint32_t out_fifo_empty: 1; /*SPI dma outfifo is empty.*/
};
uint32_t val;
} dma_out_status;
union {
struct {
uint32_t in_dscr_addr: 18; /*SPI dma in descriptor address.*/
uint32_t in_dscr_state: 2; /*SPI dma in descriptor state.*/
uint32_t in_state: 3; /*SPI dma in data state.*/
uint32_t in_fifo_cnt: 7; /*The remains of SPI dma infifo data.*/
uint32_t in_fifo_full: 1; /*SPI dma infifo is full.*/
uint32_t in_fifo_empty: 1; /*SPI dma infifo is empty.*/
};
uint32_t val;
} dma_in_status;
uint32_t data_buf[18]; /*data buffer*/
union {
struct {
uint32_t din0_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din1_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din2_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din3_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t reserved8: 10;
uint32_t din0_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t din1_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t din2_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t din3_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t reserved22: 10; /*reserved*/
};
uint32_t val;
} din_mode;
union {
struct {
uint32_t din0_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din1_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din2_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din3_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t reserved8: 24; /*reserved*/
};
uint32_t val;
} din_num;
union {
struct {
uint32_t dout0_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout1_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout2_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout3_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout4_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t reserved10: 8; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout0_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t dout1_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t dout2_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t dout3_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t dout4_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t reserved23: 9; /*reserved*/
};
uint32_t val;
} dout_mode;
union {
struct {
uint32_t dout0_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout1_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout2_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout3_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout4_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t reserved10:22; /*reserved*/
};
uint32_t val;
} dout_num;
union {
struct {
uint32_t sop_en: 1;
uint32_t sop_mode: 4;
uint32_t sop_rcmd: 8;
uint32_t sop_wcmd: 8;
uint32_t sop_dqs_edge: 1;
uint32_t reserved22: 10;
};
uint32_t val;
} spr_cfg0;
union {
struct {
uint32_t sop_itl: 12;
uint32_t sop_len: 6;
uint32_t sop_dlen: 6;
uint32_t sop_dc_mode: 1;
uint32_t reserved25: 7;
};
uint32_t val;
} spr_cfg1;
uint32_t reserved_104;
uint32_t reserved_108;
uint32_t reserved_10c;
uint32_t reserved_110;
uint32_t reserved_114;
uint32_t reserved_118;
uint32_t reserved_11c;
uint32_t reserved_120;
uint32_t reserved_124;
uint32_t reserved_128;
uint32_t reserved_12c;
uint32_t reserved_130;
uint32_t reserved_134;
uint32_t reserved_138;
uint32_t reserved_13c;
uint32_t reserved_140;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
uint32_t reserved_1fc;
uint32_t reserved_200;
uint32_t reserved_204;
uint32_t reserved_208;
uint32_t reserved_20c;
uint32_t reserved_210;
uint32_t reserved_214;
uint32_t reserved_218;
uint32_t reserved_21c;
uint32_t reserved_220;
uint32_t reserved_224;
uint32_t reserved_228;
uint32_t reserved_22c;
uint32_t reserved_230;
uint32_t reserved_234;
uint32_t reserved_238;
uint32_t reserved_23c;
uint32_t reserved_240;
uint32_t reserved_244;
uint32_t reserved_248;
uint32_t reserved_24c;
uint32_t reserved_250;
uint32_t reserved_254;
uint32_t reserved_258;
uint32_t reserved_25c;
uint32_t reserved_260;
uint32_t reserved_264;
uint32_t reserved_268;
uint32_t reserved_26c;
uint32_t reserved_270;
uint32_t reserved_274;
uint32_t reserved_278;
uint32_t reserved_27c;
uint32_t reserved_280;
uint32_t reserved_284;
uint32_t reserved_288;
uint32_t reserved_28c;
uint32_t reserved_290;
uint32_t reserved_294;
uint32_t reserved_298;
uint32_t reserved_29c;
uint32_t reserved_2a0;
uint32_t reserved_2a4;
uint32_t reserved_2a8;
uint32_t reserved_2ac;
uint32_t reserved_2b0;
uint32_t reserved_2b4;
uint32_t reserved_2b8;
uint32_t reserved_2bc;
uint32_t reserved_2c0;
uint32_t reserved_2c4;
uint32_t reserved_2c8;
uint32_t reserved_2cc;
uint32_t reserved_2d0;
uint32_t reserved_2d4;
uint32_t reserved_2d8;
uint32_t reserved_2dc;
uint32_t reserved_2e0;
uint32_t reserved_2e4;
uint32_t reserved_2e8;
uint32_t reserved_2ec;
uint32_t reserved_2f0;
uint32_t reserved_2f4;
uint32_t reserved_2f8;
uint32_t reserved_2fc;
uint32_t reserved_300;
uint32_t reserved_304;
uint32_t reserved_308;
uint32_t reserved_30c;
uint32_t reserved_310;
uint32_t reserved_314;
uint32_t reserved_318;
uint32_t reserved_31c;
uint32_t reserved_320;
uint32_t reserved_324;
uint32_t reserved_328;
uint32_t reserved_32c;
uint32_t reserved_330;
uint32_t reserved_334;
uint32_t reserved_338;
uint32_t reserved_33c;
uint32_t reserved_340;
uint32_t reserved_344;
uint32_t reserved_348;
uint32_t reserved_34c;
uint32_t reserved_350;
uint32_t reserved_354;
uint32_t reserved_358;
uint32_t reserved_35c;
uint32_t reserved_360;
uint32_t reserved_364;
uint32_t reserved_368;
uint32_t reserved_36c;
uint32_t reserved_370;
uint32_t reserved_374;
uint32_t reserved_378;
uint32_t reserved_37c;
uint32_t reserved_380;
uint32_t reserved_384;
uint32_t reserved_388;
uint32_t reserved_38c;
uint32_t reserved_390;
uint32_t reserved_394;
uint32_t reserved_398;
uint32_t reserved_39c;
uint32_t reserved_3a0;
uint32_t reserved_3a4;
uint32_t reserved_3a8;
uint32_t reserved_3ac;
uint32_t reserved_3b0;
uint32_t reserved_3b4;
uint32_t reserved_3b8;
uint32_t reserved_3bc;
uint32_t reserved_3c0;
uint32_t reserved_3c4;
uint32_t reserved_3c8;
uint32_t reserved_3cc;
uint32_t reserved_3d0;
uint32_t reserved_3d4;
uint32_t reserved_3d8;
uint32_t reserved_3dc;
uint32_t reserved_3e0;
uint32_t reserved_3e4;
uint32_t reserved_3e8;
uint32_t reserved_3ec;
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
union {
struct {
uint32_t date: 28; /*SPI register version.*/
uint32_t reserved28: 4; /*reserved*/
};
uint32_t val;
} date;
} spi_dev_t;
extern spi_dev_t GPSPI2; //FSPI
extern spi_dev_t GPSPI3; //HSPI
extern spi_dev_t GPSPI4; //VSPI
_Static_assert(sizeof(spi_dev_t)==0x400, "***invalid spi");
#ifdef __cplusplus
}
#endif
#endif /* _SOC_SPI_STRUCT_H_ */

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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SYSCON_REG_H_
#define _SOC_SYSCON_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x000)
/* SYSCON_SOC_CLK_SEL : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
/*description: */
#define SYSCON_SOC_CLK_SEL 0x00000003
#define SYSCON_SOC_CLK_SEL_M ((SYSCON_SOC_CLK_SEL_V)<<(SYSCON_SOC_CLK_SEL_S))
#define SYSCON_SOC_CLK_SEL_V 0x3
#define SYSCON_SOC_CLK_SEL_S 14
#define SYSCON_SOC_CLK_SEL_XTL 0
#define SYSCON_SOC_CLK_SEL_PLL 1
#define SYSCON_SOC_CLK_SEL_8M 2
#define SYSCON_SOC_CLK_SEL_APLL 3
/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: */
#define SYSCON_RST_TICK_CNT (BIT(12))
#define SYSCON_RST_TICK_CNT_M (BIT(12))
#define SYSCON_RST_TICK_CNT_V 0x1
#define SYSCON_RST_TICK_CNT_S 12
/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: */
#define SYSCON_CLK_EN (BIT(11))
#define SYSCON_CLK_EN_M (BIT(11))
#define SYSCON_CLK_EN_V 0x1
#define SYSCON_CLK_EN_S 11
/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: */
#define SYSCON_CLK_320M_EN (BIT(10))
#define SYSCON_CLK_320M_EN_M (BIT(10))
#define SYSCON_CLK_320M_EN_V 0x1
#define SYSCON_CLK_320M_EN_S 10
/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
/*description: */
#define SYSCON_PRE_DIV_CNT 0x000003FF
#define SYSCON_PRE_DIV_CNT_M ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S))
#define SYSCON_PRE_DIV_CNT_V 0x3FF
#define SYSCON_PRE_DIV_CNT_S 0
#define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x004)
/* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
/*description: */
#define SYSCON_TICK_ENABLE (BIT(16))
#define SYSCON_TICK_ENABLE_M (BIT(16))
#define SYSCON_TICK_ENABLE_V 0x1
#define SYSCON_TICK_ENABLE_S 16
/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
/*description: */
#define SYSCON_CK8M_TICK_NUM 0x000000FF
#define SYSCON_CK8M_TICK_NUM_M ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S))
#define SYSCON_CK8M_TICK_NUM_V 0xFF
#define SYSCON_CK8M_TICK_NUM_S 8
/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
/*description: */
#define SYSCON_XTAL_TICK_NUM 0x000000FF
#define SYSCON_XTAL_TICK_NUM_M ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S))
#define SYSCON_XTAL_TICK_NUM_V 0xFF
#define SYSCON_XTAL_TICK_NUM_S 0
#define SYSCON_SARADC_CTRL_REG (DR_REG_SYSCON_BASE + 0x008)
/* SYSCON_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
/*description: force option to xpd sar blocks*/
#define SYSCON_SARADC_XPD_SAR_FORCE 0x00000003
#define SYSCON_SARADC_XPD_SAR_FORCE_M ((SYSCON_SARADC_XPD_SAR_FORCE_V)<<(SYSCON_SARADC_XPD_SAR_FORCE_S))
#define SYSCON_SARADC_XPD_SAR_FORCE_V 0x3
#define SYSCON_SARADC_XPD_SAR_FORCE_S 27
/* SYSCON_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data
is from GPIO matrix*/
#define SYSCON_SARADC_DATA_TO_I2S (BIT(26))
#define SYSCON_SARADC_DATA_TO_I2S_M (BIT(26))
#define SYSCON_SARADC_DATA_TO_I2S_V 0x1
#define SYSCON_SARADC_DATA_TO_I2S_S 26
/* SYSCON_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data
in this case the resolution should not be larger than 11 bits.*/
#define SYSCON_SARADC_DATA_SAR_SEL (BIT(25))
#define SYSCON_SARADC_DATA_SAR_SEL_M (BIT(25))
#define SYSCON_SARADC_DATA_SAR_SEL_V 0x1
#define SYSCON_SARADC_DATA_SAR_SEL_S 25
/* SYSCON_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */
/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/
#define SYSCON_SARADC_SAR2_PATT_P_CLEAR (BIT(24))
#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24))
#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_V 0x1
#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_S 24
/* SYSCON_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/
#define SYSCON_SARADC_SAR1_PATT_P_CLEAR (BIT(23))
#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_M (BIT(23))
#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_V 0x1
#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_S 23
/* SYSCON_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */
/*description: 0 ~ 15 means length 1 ~ 16*/
#define SYSCON_SARADC_SAR2_PATT_LEN 0x0000000F
#define SYSCON_SARADC_SAR2_PATT_LEN_M ((SYSCON_SARADC_SAR2_PATT_LEN_V)<<(SYSCON_SARADC_SAR2_PATT_LEN_S))
#define SYSCON_SARADC_SAR2_PATT_LEN_V 0xF
#define SYSCON_SARADC_SAR2_PATT_LEN_S 19
/* SYSCON_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */
/*description: 0 ~ 15 means length 1 ~ 16*/
#define SYSCON_SARADC_SAR1_PATT_LEN 0x0000000F
#define SYSCON_SARADC_SAR1_PATT_LEN_M ((SYSCON_SARADC_SAR1_PATT_LEN_V)<<(SYSCON_SARADC_SAR1_PATT_LEN_S))
#define SYSCON_SARADC_SAR1_PATT_LEN_V 0xF
#define SYSCON_SARADC_SAR1_PATT_LEN_S 15
/* SYSCON_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
/*description: SAR clock divider*/
#define SYSCON_SARADC_SAR_CLK_DIV 0x000000FF
#define SYSCON_SARADC_SAR_CLK_DIV_M ((SYSCON_SARADC_SAR_CLK_DIV_V)<<(SYSCON_SARADC_SAR_CLK_DIV_S))
#define SYSCON_SARADC_SAR_CLK_DIV_V 0xFF
#define SYSCON_SARADC_SAR_CLK_DIV_S 7
/* SYSCON_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: */
#define SYSCON_SARADC_SAR_CLK_GATED (BIT(6))
#define SYSCON_SARADC_SAR_CLK_GATED_M (BIT(6))
#define SYSCON_SARADC_SAR_CLK_GATED_V 0x1
#define SYSCON_SARADC_SAR_CLK_GATED_S 6
/* SYSCON_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */
/*description: 0: SAR1 1: SAR2 only work for single SAR mode*/
#define SYSCON_SARADC_SAR_SEL (BIT(5))
#define SYSCON_SARADC_SAR_SEL_M (BIT(5))
#define SYSCON_SARADC_SAR_SEL_V 0x1
#define SYSCON_SARADC_SAR_SEL_S 5
/* SYSCON_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
/*description: 0: single mode 1: double mode 2: alternate mode*/
#define SYSCON_SARADC_WORK_MODE 0x00000003
#define SYSCON_SARADC_WORK_MODE_M ((SYSCON_SARADC_WORK_MODE_V)<<(SYSCON_SARADC_WORK_MODE_S))
#define SYSCON_SARADC_WORK_MODE_V 0x3
#define SYSCON_SARADC_WORK_MODE_S 3
/* SYSCON_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
/*description: */
#define SYSCON_SARADC_START (BIT(1))
#define SYSCON_SARADC_START_M (BIT(1))
#define SYSCON_SARADC_START_V 0x1
#define SYSCON_SARADC_START_S 1
/* SYSCON_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: */
#define SYSCON_SARADC_START_FORCE (BIT(0))
#define SYSCON_SARADC_START_FORCE_M (BIT(0))
#define SYSCON_SARADC_START_FORCE_V 0x1
#define SYSCON_SARADC_START_FORCE_S 0
#define SYSCON_SARADC_CTRL2_REG (DR_REG_SYSCON_BASE + 0x00C)
/* SYSCON_SARADC_TIMER_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
/*description: to enable saradc timer trigger*/
#define SYSCON_SARADC_TIMER_EN (BIT(20))
#define SYSCON_SARADC_TIMER_EN_M (BIT(20))
#define SYSCON_SARADC_TIMER_EN_V 0x1
#define SYSCON_SARADC_TIMER_EN_S 20
/* SYSCON_SARADC_TIMER_TARGET : R/W ;bitpos:[19:12] ;default: 8'd10 ; */
/*description: to set saradc timer target*/
#define SYSCON_SARADC_TIMER_TARGET 0x000000FF
#define SYSCON_SARADC_TIMER_TARGET_M ((SYSCON_SARADC_TIMER_TARGET_V)<<(SYSCON_SARADC_TIMER_TARGET_S))
#define SYSCON_SARADC_TIMER_TARGET_V 0xFF
#define SYSCON_SARADC_TIMER_TARGET_S 12
/* SYSCON_SARADC_TIMER_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
/*description: 1: select saradc timer 0: i2s_ws trigger*/
#define SYSCON_SARADC_TIMER_SEL (BIT(11))
#define SYSCON_SARADC_TIMER_SEL_M (BIT(11))
#define SYSCON_SARADC_TIMER_SEL_V 0x1
#define SYSCON_SARADC_TIMER_SEL_S 11
/* SYSCON_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
/*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/
#define SYSCON_SARADC_SAR2_INV (BIT(10))
#define SYSCON_SARADC_SAR2_INV_M (BIT(10))
#define SYSCON_SARADC_SAR2_INV_V 0x1
#define SYSCON_SARADC_SAR2_INV_S 10
/* SYSCON_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
/*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/
#define SYSCON_SARADC_SAR1_INV (BIT(9))
#define SYSCON_SARADC_SAR1_INV_M (BIT(9))
#define SYSCON_SARADC_SAR1_INV_V 0x1
#define SYSCON_SARADC_SAR1_INV_S 9
/* SYSCON_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
/*description: max conversion number*/
#define SYSCON_SARADC_MAX_MEAS_NUM 0x000000FF
#define SYSCON_SARADC_MAX_MEAS_NUM_M ((SYSCON_SARADC_MAX_MEAS_NUM_V)<<(SYSCON_SARADC_MAX_MEAS_NUM_S))
#define SYSCON_SARADC_MAX_MEAS_NUM_V 0xFF
#define SYSCON_SARADC_MAX_MEAS_NUM_S 1
/* SYSCON_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: */
#define SYSCON_SARADC_MEAS_NUM_LIMIT (BIT(0))
#define SYSCON_SARADC_MEAS_NUM_LIMIT_M (BIT(0))
#define SYSCON_SARADC_MEAS_NUM_LIMIT_V 0x1
#define SYSCON_SARADC_MEAS_NUM_LIMIT_S 0
#define SYSCON_SARADC_FSM_REG (DR_REG_SYSCON_BASE + 0x010)
/* SYSCON_SARADC_SAMPLE_CYCLE : R/W ;bitpos:[31:24] ;default: 8'd2 ; */
/*description: sample cycles*/
#define SYSCON_SARADC_SAMPLE_CYCLE 0x000000FF
#define SYSCON_SARADC_SAMPLE_CYCLE_M ((SYSCON_SARADC_SAMPLE_CYCLE_V)<<(SYSCON_SARADC_SAMPLE_CYCLE_S))
#define SYSCON_SARADC_SAMPLE_CYCLE_V 0xFF
#define SYSCON_SARADC_SAMPLE_CYCLE_S 24
/* SYSCON_SARADC_SAMPLE_NUM : R/W ;bitpos:[23:16] ;default: 8'd0 ; */
/*description: sample number*/
#define SYSCON_SARADC_SAMPLE_NUM 0x000000FF
#define SYSCON_SARADC_SAMPLE_NUM_M ((SYSCON_SARADC_SAMPLE_NUM_V)<<(SYSCON_SARADC_SAMPLE_NUM_S))
#define SYSCON_SARADC_SAMPLE_NUM_V 0xFF
#define SYSCON_SARADC_SAMPLE_NUM_S 16
#define SYSCON_SARADC_FSM_WAIT_REG (DR_REG_SYSCON_BASE + 0x014)
/* SYSCON_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */
/*description: */
#define SYSCON_SARADC_STANDBY_WAIT 0x000000FF
#define SYSCON_SARADC_STANDBY_WAIT_M ((SYSCON_SARADC_STANDBY_WAIT_V)<<(SYSCON_SARADC_STANDBY_WAIT_S))
#define SYSCON_SARADC_STANDBY_WAIT_V 0xFF
#define SYSCON_SARADC_STANDBY_WAIT_S 16
/* SYSCON_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */
/*description: */
#define SYSCON_SARADC_RSTB_WAIT 0x000000FF
#define SYSCON_SARADC_RSTB_WAIT_M ((SYSCON_SARADC_RSTB_WAIT_V)<<(SYSCON_SARADC_RSTB_WAIT_S))
#define SYSCON_SARADC_RSTB_WAIT_V 0xFF
#define SYSCON_SARADC_RSTB_WAIT_S 8
/* SYSCON_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
/*description: */
#define SYSCON_SARADC_XPD_WAIT 0x000000FF
#define SYSCON_SARADC_XPD_WAIT_M ((SYSCON_SARADC_XPD_WAIT_V)<<(SYSCON_SARADC_XPD_WAIT_S))
#define SYSCON_SARADC_XPD_WAIT_V 0xFF
#define SYSCON_SARADC_XPD_WAIT_S 0
#define SYSCON_SARADC_SAR1_STATUS_REG (DR_REG_SYSCON_BASE + 0x018)
/* SYSCON_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define SYSCON_SARADC_SAR1_STATUS 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_STATUS_M ((SYSCON_SARADC_SAR1_STATUS_V)<<(SYSCON_SARADC_SAR1_STATUS_S))
#define SYSCON_SARADC_SAR1_STATUS_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_STATUS_S 0
#define SYSCON_SARADC_SAR2_STATUS_REG (DR_REG_SYSCON_BASE + 0x01C)
/* SYSCON_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define SYSCON_SARADC_SAR2_STATUS 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_STATUS_M ((SYSCON_SARADC_SAR2_STATUS_V)<<(SYSCON_SARADC_SAR2_STATUS_S))
#define SYSCON_SARADC_SAR2_STATUS_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_STATUS_S 0
#define SYSCON_SARADC_SAR1_PATT_TAB1_REG (DR_REG_SYSCON_BASE + 0x020)
/* SYSCON_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/
#define SYSCON_SARADC_SAR1_PATT_TAB1 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB1_M ((SYSCON_SARADC_SAR1_PATT_TAB1_V)<<(SYSCON_SARADC_SAR1_PATT_TAB1_S))
#define SYSCON_SARADC_SAR1_PATT_TAB1_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB1_S 0
#define SYSCON_SARADC_SAR1_PATT_TAB2_REG (DR_REG_SYSCON_BASE + 0x024)
/* SYSCON_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/
#define SYSCON_SARADC_SAR1_PATT_TAB2 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB2_M ((SYSCON_SARADC_SAR1_PATT_TAB2_V)<<(SYSCON_SARADC_SAR1_PATT_TAB2_S))
#define SYSCON_SARADC_SAR1_PATT_TAB2_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB2_S 0
#define SYSCON_SARADC_SAR1_PATT_TAB3_REG (DR_REG_SYSCON_BASE + 0x028)
/* SYSCON_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/
#define SYSCON_SARADC_SAR1_PATT_TAB3 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB3_M ((SYSCON_SARADC_SAR1_PATT_TAB3_V)<<(SYSCON_SARADC_SAR1_PATT_TAB3_S))
#define SYSCON_SARADC_SAR1_PATT_TAB3_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB3_S 0
#define SYSCON_SARADC_SAR1_PATT_TAB4_REG (DR_REG_SYSCON_BASE + 0x02C)
/* SYSCON_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/
#define SYSCON_SARADC_SAR1_PATT_TAB4 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB4_M ((SYSCON_SARADC_SAR1_PATT_TAB4_V)<<(SYSCON_SARADC_SAR1_PATT_TAB4_S))
#define SYSCON_SARADC_SAR1_PATT_TAB4_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB4_S 0
#define SYSCON_SARADC_SAR2_PATT_TAB1_REG (DR_REG_SYSCON_BASE + 0x030)
/* SYSCON_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/
#define SYSCON_SARADC_SAR2_PATT_TAB1 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB1_M ((SYSCON_SARADC_SAR2_PATT_TAB1_V)<<(SYSCON_SARADC_SAR2_PATT_TAB1_S))
#define SYSCON_SARADC_SAR2_PATT_TAB1_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB1_S 0
#define SYSCON_SARADC_SAR2_PATT_TAB2_REG (DR_REG_SYSCON_BASE + 0x034)
/* SYSCON_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/
#define SYSCON_SARADC_SAR2_PATT_TAB2 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB2_M ((SYSCON_SARADC_SAR2_PATT_TAB2_V)<<(SYSCON_SARADC_SAR2_PATT_TAB2_S))
#define SYSCON_SARADC_SAR2_PATT_TAB2_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB2_S 0
#define SYSCON_SARADC_SAR2_PATT_TAB3_REG (DR_REG_SYSCON_BASE + 0x038)
/* SYSCON_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/
#define SYSCON_SARADC_SAR2_PATT_TAB3 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB3_M ((SYSCON_SARADC_SAR2_PATT_TAB3_V)<<(SYSCON_SARADC_SAR2_PATT_TAB3_S))
#define SYSCON_SARADC_SAR2_PATT_TAB3_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB3_S 0
#define SYSCON_SARADC_SAR2_PATT_TAB4_REG (DR_REG_SYSCON_BASE + 0x03C)
/* SYSCON_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/
#define SYSCON_SARADC_SAR2_PATT_TAB4 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB4_M ((SYSCON_SARADC_SAR2_PATT_TAB4_V)<<(SYSCON_SARADC_SAR2_PATT_TAB4_S))
#define SYSCON_SARADC_SAR2_PATT_TAB4_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB4_S 0
#define SYSCON_ADC_ARB_CTRL_REG (DR_REG_SYSCON_BASE + 0x040)
/* SYSCON_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: adc2 arbiter uses fixed priority*/
#define SYSCON_ADC_ARB_FIX_PRIORITY (BIT(12))
#define SYSCON_ADC_ARB_FIX_PRIORITY_M (BIT(12))
#define SYSCON_ADC_ARB_FIX_PRIORITY_V 0x1
#define SYSCON_ADC_ARB_FIX_PRIORITY_S 12
/* SYSCON_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */
/*description: Set adc2 arbiter wifi priority*/
#define SYSCON_ADC_ARB_WIFI_PRIORITY 0x00000003
#define SYSCON_ADC_ARB_WIFI_PRIORITY_M ((SYSCON_ADC_ARB_WIFI_PRIORITY_V)<<(SYSCON_ADC_ARB_WIFI_PRIORITY_S))
#define SYSCON_ADC_ARB_WIFI_PRIORITY_V 0x3
#define SYSCON_ADC_ARB_WIFI_PRIORITY_S 10
/* SYSCON_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */
/*description: Set adc2 arbiter rtc priority*/
#define SYSCON_ADC_ARB_RTC_PRIORITY 0x00000003
#define SYSCON_ADC_ARB_RTC_PRIORITY_M ((SYSCON_ADC_ARB_RTC_PRIORITY_V)<<(SYSCON_ADC_ARB_RTC_PRIORITY_S))
#define SYSCON_ADC_ARB_RTC_PRIORITY_V 0x3
#define SYSCON_ADC_ARB_RTC_PRIORITY_S 8
/* SYSCON_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
/*description: Set adc2 arbiter apb priority*/
#define SYSCON_ADC_ARB_APB_PRIORITY 0x00000003
#define SYSCON_ADC_ARB_APB_PRIORITY_M ((SYSCON_ADC_ARB_APB_PRIORITY_V)<<(SYSCON_ADC_ARB_APB_PRIORITY_S))
#define SYSCON_ADC_ARB_APB_PRIORITY_V 0x3
#define SYSCON_ADC_ARB_APB_PRIORITY_S 6
/* SYSCON_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: adc2 arbiter force grant*/
#define SYSCON_ADC_ARB_GRANT_FORCE (BIT(5))
#define SYSCON_ADC_ARB_GRANT_FORCE_M (BIT(5))
#define SYSCON_ADC_ARB_GRANT_FORCE_V 0x1
#define SYSCON_ADC_ARB_GRANT_FORCE_S 5
/* SYSCON_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enable wifi controller*/
#define SYSCON_ADC_ARB_WIFI_FORCE (BIT(4))
#define SYSCON_ADC_ARB_WIFI_FORCE_M (BIT(4))
#define SYSCON_ADC_ARB_WIFI_FORCE_V 0x1
#define SYSCON_ADC_ARB_WIFI_FORCE_S 4
/* SYSCON_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enable rtc controller*/
#define SYSCON_ADC_ARB_RTC_FORCE (BIT(3))
#define SYSCON_ADC_ARB_RTC_FORCE_M (BIT(3))
#define SYSCON_ADC_ARB_RTC_FORCE_V 0x1
#define SYSCON_ADC_ARB_RTC_FORCE_S 3
/* SYSCON_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enableapb controller*/
#define SYSCON_ADC_ARB_APB_FORCE (BIT(2))
#define SYSCON_ADC_ARB_APB_FORCE_M (BIT(2))
#define SYSCON_ADC_ARB_APB_FORCE_V 0x1
#define SYSCON_ADC_ARB_APB_FORCE_S 2
#define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x044)
/* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK_XTAL_OEN (BIT(10))
#define SYSCON_CLK_XTAL_OEN_M (BIT(10))
#define SYSCON_CLK_XTAL_OEN_V 0x1
#define SYSCON_CLK_XTAL_OEN_S 10
/* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK40X_BB_OEN (BIT(9))
#define SYSCON_CLK40X_BB_OEN_M (BIT(9))
#define SYSCON_CLK40X_BB_OEN_V 0x1
#define SYSCON_CLK40X_BB_OEN_S 9
/* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK_DAC_CPU_OEN (BIT(8))
#define SYSCON_CLK_DAC_CPU_OEN_M (BIT(8))
#define SYSCON_CLK_DAC_CPU_OEN_V 0x1
#define SYSCON_CLK_DAC_CPU_OEN_S 8
/* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK_ADC_INF_OEN (BIT(7))
#define SYSCON_CLK_ADC_INF_OEN_M (BIT(7))
#define SYSCON_CLK_ADC_INF_OEN_V 0x1
#define SYSCON_CLK_ADC_INF_OEN_S 7
/* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK_320M_OEN (BIT(6))
#define SYSCON_CLK_320M_OEN_M (BIT(6))
#define SYSCON_CLK_320M_OEN_V 0x1
#define SYSCON_CLK_320M_OEN_S 6
/* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK160_OEN (BIT(5))
#define SYSCON_CLK160_OEN_M (BIT(5))
#define SYSCON_CLK160_OEN_V 0x1
#define SYSCON_CLK160_OEN_S 5
/* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK80_OEN (BIT(4))
#define SYSCON_CLK80_OEN_M (BIT(4))
#define SYSCON_CLK80_OEN_V 0x1
#define SYSCON_CLK80_OEN_S 4
/* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK_BB_OEN (BIT(3))
#define SYSCON_CLK_BB_OEN_M (BIT(3))
#define SYSCON_CLK_BB_OEN_V 0x1
#define SYSCON_CLK_BB_OEN_S 3
/* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK44_OEN (BIT(2))
#define SYSCON_CLK44_OEN_M (BIT(2))
#define SYSCON_CLK44_OEN_V 0x1
#define SYSCON_CLK44_OEN_S 2
/* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK22_OEN (BIT(1))
#define SYSCON_CLK22_OEN_M (BIT(1))
#define SYSCON_CLK22_OEN_V 0x1
#define SYSCON_CLK22_OEN_S 1
/* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK20_OEN (BIT(0))
#define SYSCON_CLK20_OEN_M (BIT(0))
#define SYSCON_CLK20_OEN_V 0x1
#define SYSCON_CLK20_OEN_S 0
#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x048)
/* SYSCON_SPI_PRIOR : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: */
#define SYSCON_SPI_PRIOR (BIT(13))
#define SYSCON_SPI_PRIOR_M (BIT(13))
#define SYSCON_SPI_PRIOR_V 0x1
#define SYSCON_SPI_PRIOR_S 13
/* SYSCON_SPI1_HOLD : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: */
#define SYSCON_SPI1_HOLD (BIT(9))
#define SYSCON_SPI1_HOLD_M (BIT(9))
#define SYSCON_SPI1_HOLD_V 0x1
#define SYSCON_SPI1_HOLD_S 9
/* SYSCON_SPI0_HOLD : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: */
#define SYSCON_SPI0_HOLD (BIT(8))
#define SYSCON_SPI0_HOLD_M (BIT(8))
#define SYSCON_SPI0_HOLD_V 0x1
#define SYSCON_SPI0_HOLD_S 8
/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define SYSCON_PERI_IO_SWAP 0x000000FF
#define SYSCON_PERI_IO_SWAP_M ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S))
#define SYSCON_PERI_IO_SWAP_V 0xFF
#define SYSCON_PERI_IO_SWAP_S 0
#define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x04C)
/* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define SYSCON_EXT_MEM_PMS_LOCK (BIT(0))
#define SYSCON_EXT_MEM_PMS_LOCK_M (BIT(0))
#define SYSCON_EXT_MEM_PMS_LOCK_V 0x1
#define SYSCON_EXT_MEM_PMS_LOCK_S 0
#define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x050)
/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define SYSCON_FLASH_ACE0_ATTR 0x00000007
#define SYSCON_FLASH_ACE0_ATTR_M ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S))
#define SYSCON_FLASH_ACE0_ATTR_V 0x7
#define SYSCON_FLASH_ACE0_ATTR_S 0
#define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x054)
/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define SYSCON_FLASH_ACE1_ATTR 0x00000007
#define SYSCON_FLASH_ACE1_ATTR_M ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S))
#define SYSCON_FLASH_ACE1_ATTR_V 0x7
#define SYSCON_FLASH_ACE1_ATTR_S 0
#define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x058)
/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define SYSCON_FLASH_ACE2_ATTR 0x00000007
#define SYSCON_FLASH_ACE2_ATTR_M ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S))
#define SYSCON_FLASH_ACE2_ATTR_V 0x7
#define SYSCON_FLASH_ACE2_ATTR_S 0
#define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x05C)
/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define SYSCON_FLASH_ACE3_ATTR 0x00000007
#define SYSCON_FLASH_ACE3_ATTR_M ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S))
#define SYSCON_FLASH_ACE3_ATTR_V 0x7
#define SYSCON_FLASH_ACE3_ATTR_S 0
#define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x060)
/* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFF
#define SYSCON_FLASH_ACE0_ADDR_S_M ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S))
#define SYSCON_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE0_ADDR_S_S 0
#define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x064)
/* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
/*description: */
#define SYSCON_FLASH_ACE1_ADDR_S 0xFFFFFFFF
#define SYSCON_FLASH_ACE1_ADDR_S_M ((SYSCON_FLASH_ACE1_ADDR_S_V)<<(SYSCON_FLASH_ACE1_ADDR_S_S))
#define SYSCON_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE1_ADDR_S_S 0
#define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x068)
/* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
/*description: */
#define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFF
#define SYSCON_FLASH_ACE2_ADDR_S_M ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S))
#define SYSCON_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE2_ADDR_S_S 0
#define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x06C)
/* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
/*description: */
#define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFF
#define SYSCON_FLASH_ACE3_ADDR_S_M ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S))
#define SYSCON_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE3_ADDR_S_S 0
#define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x070)
/* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_FLASH_ACE0_SIZE 0x0000FFFF
#define SYSCON_FLASH_ACE0_SIZE_M ((SYSCON_FLASH_ACE0_SIZE_V)<<(SYSCON_FLASH_ACE0_SIZE_S))
#define SYSCON_FLASH_ACE0_SIZE_V 0xFFFF
#define SYSCON_FLASH_ACE0_SIZE_S 0
#define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x074)
/* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_FLASH_ACE1_SIZE 0x0000FFFF
#define SYSCON_FLASH_ACE1_SIZE_M ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S))
#define SYSCON_FLASH_ACE1_SIZE_V 0xFFFF
#define SYSCON_FLASH_ACE1_SIZE_S 0
#define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x078)
/* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_FLASH_ACE2_SIZE 0x0000FFFF
#define SYSCON_FLASH_ACE2_SIZE_M ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S))
#define SYSCON_FLASH_ACE2_SIZE_V 0xFFFF
#define SYSCON_FLASH_ACE2_SIZE_S 0
#define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x07C)
/* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_FLASH_ACE3_SIZE 0x0000FFFF
#define SYSCON_FLASH_ACE3_SIZE_M ((SYSCON_FLASH_ACE3_SIZE_V)<<(SYSCON_FLASH_ACE3_SIZE_S))
#define SYSCON_FLASH_ACE3_SIZE_V 0xFFFF
#define SYSCON_FLASH_ACE3_SIZE_S 0
#define SYSCON_SRAM_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x080)
/* SYSCON_SRAM_ACE0_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define SYSCON_SRAM_ACE0_ATTR 0x00000007
#define SYSCON_SRAM_ACE0_ATTR_M ((SYSCON_SRAM_ACE0_ATTR_V)<<(SYSCON_SRAM_ACE0_ATTR_S))
#define SYSCON_SRAM_ACE0_ATTR_V 0x7
#define SYSCON_SRAM_ACE0_ATTR_S 0
#define SYSCON_SRAM_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x084)
/* SYSCON_SRAM_ACE1_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define SYSCON_SRAM_ACE1_ATTR 0x00000007
#define SYSCON_SRAM_ACE1_ATTR_M ((SYSCON_SRAM_ACE1_ATTR_V)<<(SYSCON_SRAM_ACE1_ATTR_S))
#define SYSCON_SRAM_ACE1_ATTR_V 0x7
#define SYSCON_SRAM_ACE1_ATTR_S 0
#define SYSCON_SRAM_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x088)
/* SYSCON_SRAM_ACE2_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define SYSCON_SRAM_ACE2_ATTR 0x00000007
#define SYSCON_SRAM_ACE2_ATTR_M ((SYSCON_SRAM_ACE2_ATTR_V)<<(SYSCON_SRAM_ACE2_ATTR_S))
#define SYSCON_SRAM_ACE2_ATTR_V 0x7
#define SYSCON_SRAM_ACE2_ATTR_S 0
#define SYSCON_SRAM_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x08C)
/* SYSCON_SRAM_ACE3_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define SYSCON_SRAM_ACE3_ATTR 0x00000007
#define SYSCON_SRAM_ACE3_ATTR_M ((SYSCON_SRAM_ACE3_ATTR_V)<<(SYSCON_SRAM_ACE3_ATTR_S))
#define SYSCON_SRAM_ACE3_ATTR_V 0x7
#define SYSCON_SRAM_ACE3_ATTR_S 0
#define SYSCON_SRAM_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x090)
/* SYSCON_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_SRAM_ACE0_ADDR_S 0xFFFFFFFF
#define SYSCON_SRAM_ACE0_ADDR_S_M ((SYSCON_SRAM_ACE0_ADDR_S_V)<<(SYSCON_SRAM_ACE0_ADDR_S_S))
#define SYSCON_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF
#define SYSCON_SRAM_ACE0_ADDR_S_S 0
#define SYSCON_SRAM_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x094)
/* SYSCON_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
/*description: */
#define SYSCON_SRAM_ACE1_ADDR_S 0xFFFFFFFF
#define SYSCON_SRAM_ACE1_ADDR_S_M ((SYSCON_SRAM_ACE1_ADDR_S_V)<<(SYSCON_SRAM_ACE1_ADDR_S_S))
#define SYSCON_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF
#define SYSCON_SRAM_ACE1_ADDR_S_S 0
#define SYSCON_SRAM_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x098)
/* SYSCON_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
/*description: */
#define SYSCON_SRAM_ACE2_ADDR_S 0xFFFFFFFF
#define SYSCON_SRAM_ACE2_ADDR_S_M ((SYSCON_SRAM_ACE2_ADDR_S_V)<<(SYSCON_SRAM_ACE2_ADDR_S_S))
#define SYSCON_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF
#define SYSCON_SRAM_ACE2_ADDR_S_S 0
#define SYSCON_SRAM_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x09C)
/* SYSCON_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
/*description: */
#define SYSCON_SRAM_ACE3_ADDR_S 0xFFFFFFFF
#define SYSCON_SRAM_ACE3_ADDR_S_M ((SYSCON_SRAM_ACE3_ADDR_S_V)<<(SYSCON_SRAM_ACE3_ADDR_S_S))
#define SYSCON_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF
#define SYSCON_SRAM_ACE3_ADDR_S_S 0
#define SYSCON_SRAM_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x0A0)
/* SYSCON_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_SRAM_ACE0_SIZE 0x0000FFFF
#define SYSCON_SRAM_ACE0_SIZE_M ((SYSCON_SRAM_ACE0_SIZE_V)<<(SYSCON_SRAM_ACE0_SIZE_S))
#define SYSCON_SRAM_ACE0_SIZE_V 0xFFFF
#define SYSCON_SRAM_ACE0_SIZE_S 0
#define SYSCON_SRAM_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x0A4)
/* SYSCON_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_SRAM_ACE1_SIZE 0x0000FFFF
#define SYSCON_SRAM_ACE1_SIZE_M ((SYSCON_SRAM_ACE1_SIZE_V)<<(SYSCON_SRAM_ACE1_SIZE_S))
#define SYSCON_SRAM_ACE1_SIZE_V 0xFFFF
#define SYSCON_SRAM_ACE1_SIZE_S 0
#define SYSCON_SRAM_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x0A8)
/* SYSCON_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_SRAM_ACE2_SIZE 0x0000FFFF
#define SYSCON_SRAM_ACE2_SIZE_M ((SYSCON_SRAM_ACE2_SIZE_V)<<(SYSCON_SRAM_ACE2_SIZE_S))
#define SYSCON_SRAM_ACE2_SIZE_V 0xFFFF
#define SYSCON_SRAM_ACE2_SIZE_S 0
#define SYSCON_SRAM_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x0AC)
/* SYSCON_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_SRAM_ACE3_SIZE 0x0000FFFF
#define SYSCON_SRAM_ACE3_SIZE_M ((SYSCON_SRAM_ACE3_SIZE_V)<<(SYSCON_SRAM_ACE3_SIZE_S))
#define SYSCON_SRAM_ACE3_SIZE_V 0xFFFF
#define SYSCON_SRAM_ACE3_SIZE_S 0
#define SYSCON_SPI0_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x0B0)
/* SYSCON_SPI0_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
/*description: */
#define SYSCON_SPI0_REJECT_CDE 0x0000001F
#define SYSCON_SPI0_REJECT_CDE_M ((SYSCON_SPI0_REJECT_CDE_V)<<(SYSCON_SPI0_REJECT_CDE_S))
#define SYSCON_SPI0_REJECT_CDE_V 0x1F
#define SYSCON_SPI0_REJECT_CDE_S 2
/* SYSCON_SPI0_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define SYSCON_SPI0_REJECT_CLR (BIT(1))
#define SYSCON_SPI0_REJECT_CLR_M (BIT(1))
#define SYSCON_SPI0_REJECT_CLR_V 0x1
#define SYSCON_SPI0_REJECT_CLR_S 1
/* SYSCON_SPI0_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define SYSCON_SPI0_REJECT_INT (BIT(0))
#define SYSCON_SPI0_REJECT_INT_M (BIT(0))
#define SYSCON_SPI0_REJECT_INT_V 0x1
#define SYSCON_SPI0_REJECT_INT_S 0
#define SYSCON_SPI0_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x0B4)
/* SYSCON_SPI0_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_SPI0_REJECT_ADDR 0xFFFFFFFF
#define SYSCON_SPI0_REJECT_ADDR_M ((SYSCON_SPI0_REJECT_ADDR_V)<<(SYSCON_SPI0_REJECT_ADDR_S))
#define SYSCON_SPI0_REJECT_ADDR_V 0xFFFFFFFF
#define SYSCON_SPI0_REJECT_ADDR_S 0
#define SYSCON_SPI1_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x0B8)
/* SYSCON_SPI1_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
/*description: */
#define SYSCON_SPI1_REJECT_CDE 0x0000001F
#define SYSCON_SPI1_REJECT_CDE_M ((SYSCON_SPI1_REJECT_CDE_V)<<(SYSCON_SPI1_REJECT_CDE_S))
#define SYSCON_SPI1_REJECT_CDE_V 0x1F
#define SYSCON_SPI1_REJECT_CDE_S 2
/* SYSCON_SPI1_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define SYSCON_SPI1_REJECT_CLR (BIT(1))
#define SYSCON_SPI1_REJECT_CLR_M (BIT(1))
#define SYSCON_SPI1_REJECT_CLR_V 0x1
#define SYSCON_SPI1_REJECT_CLR_S 1
/* SYSCON_SPI1_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define SYSCON_SPI1_REJECT_INT (BIT(0))
#define SYSCON_SPI1_REJECT_INT_M (BIT(0))
#define SYSCON_SPI1_REJECT_INT_V 0x1
#define SYSCON_SPI1_REJECT_INT_S 0
#define SYSCON_SPI1_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x0BC)
/* SYSCON_SPI1_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_SPI1_REJECT_ADDR 0xFFFFFFFF
#define SYSCON_SPI1_REJECT_ADDR_M ((SYSCON_SPI1_REJECT_ADDR_V)<<(SYSCON_SPI1_REJECT_ADDR_S))
#define SYSCON_SPI1_REJECT_ADDR_V 0xFFFFFFFF
#define SYSCON_SPI1_REJECT_ADDR_S 0
#define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x0C0)
/* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0))
#define SYSCON_SDIO_WIN_ACCESS_EN_M (BIT(0))
#define SYSCON_SDIO_WIN_ACCESS_EN_V 0x1
#define SYSCON_SDIO_WIN_ACCESS_EN_S 0
#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x0C4)
/* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define SYSCON_REDCY_ANDOR (BIT(31))
#define SYSCON_REDCY_ANDOR_M (BIT(31))
#define SYSCON_REDCY_ANDOR_V 0x1
#define SYSCON_REDCY_ANDOR_S 31
/* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
/*description: */
#define SYSCON_REDCY_SIG0 0x7FFFFFFF
#define SYSCON_REDCY_SIG0_M ((SYSCON_REDCY_SIG0_V)<<(SYSCON_REDCY_SIG0_S))
#define SYSCON_REDCY_SIG0_V 0x7FFFFFFF
#define SYSCON_REDCY_SIG0_S 0
#define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x0C8)
/* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define SYSCON_REDCY_NANDOR (BIT(31))
#define SYSCON_REDCY_NANDOR_M (BIT(31))
#define SYSCON_REDCY_NANDOR_V 0x1
#define SYSCON_REDCY_NANDOR_S 31
/* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
/*description: */
#define SYSCON_REDCY_SIG1 0x7FFFFFFF
#define SYSCON_REDCY_SIG1_M ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S))
#define SYSCON_REDCY_SIG1_V 0x7FFFFFFF
#define SYSCON_REDCY_SIG1_S 0
#define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0x0CC)
/* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_WIFI_BB_CFG 0xFFFFFFFF
#define SYSCON_WIFI_BB_CFG_M ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S))
#define SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF
#define SYSCON_WIFI_BB_CFG_S 0
#define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x0D0)
/* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_WIFI_BB_CFG_2 0xFFFFFFFF
#define SYSCON_WIFI_BB_CFG_2_M ((SYSCON_WIFI_BB_CFG_2_V)<<(SYSCON_WIFI_BB_CFG_2_S))
#define SYSCON_WIFI_BB_CFG_2_V 0xFFFFFFFF
#define SYSCON_WIFI_BB_CFG_2_S 0
#define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x0D4)
/* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
/*description: */
#define SYSCON_WIFI_CLK_EN 0xFFFFFFFF
#define SYSCON_WIFI_CLK_EN_M ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S))
#define SYSCON_WIFI_CLK_EN_V 0xFFFFFFFF
#define SYSCON_WIFI_CLK_EN_S 0
#define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x0D8)
/* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_WIFI_RST 0xFFFFFFFF
#define SYSCON_WIFI_RST_M ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S))
#define SYSCON_WIFI_RST_V 0xFFFFFFFF
#define SYSCON_WIFI_RST_S 0
#define DPORT_WIFI_CLK_EN_REG SYSCON_WIFI_CLK_EN_REG
/* DPORT_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
/*description: */
#define DPORT_WIFI_CLK_EN 0xFFFFFFFF
#define DPORT_WIFI_CLK_EN_M ((DPORT_WIFI_CLK_EN_V)<<(DPORT_WIFI_CLK_EN_S))
#define DPORT_WIFI_CLK_EN_V 0xFFFFFFFF
#define DPORT_WIFI_CLK_EN_S 0
/* Mask for all Wifi clock bits - 0, 1, 2, 3, 6, 7, 8, 9, 10, 15, 19, 20, 21
Bit15 not included here because of the bit now can't be cleared */
#define DPORT_WIFI_CLK_WIFI_EN 0x003807cf
#define DPORT_WIFI_CLK_WIFI_EN_M ((DPORT_WIFI_CLK_WIFI_EN_V)<<(DPORT_WIFI_CLK_WIFI_EN_S))
#define DPORT_WIFI_CLK_WIFI_EN_V 0x7cf
#define DPORT_WIFI_CLK_WIFI_EN_S 0
/* Mask for all Bluetooth clock bits - 11, 16, 17 */
#define DPORT_WIFI_CLK_BT_EN 0x61
#define DPORT_WIFI_CLK_BT_EN_M ((DPORT_WIFI_CLK_BT_EN_V)<<(DPORT_WIFI_CLK_BT_EN_S))
#define DPORT_WIFI_CLK_BT_EN_V 0x61
#define DPORT_WIFI_CLK_BT_EN_S 11
/* Mask for clock bits used by both WIFI and Bluetooth, bit 0, 3, 6, 7, 8, 9 */
#define DPORT_WIFI_CLK_WIFI_BT_COMMON_M 0x000003c9
/* Digital team to check */
//bluetooth baseband bit11
#define DPORT_BT_BASEBAND_EN BIT(11)
//bluetooth LC bit16 and bit17
#define DPORT_BT_LC_EN (BIT(16)|BIT(17))
/* Remaining single bit clock masks */
#define DPORT_WIFI_CLK_SDIOSLAVE_EN BIT(4)
#define DPORT_WIFI_CLK_UNUSED_BIT5 BIT(5)
#define DPORT_WIFI_CLK_UNUSED_BIT12 BIT(12)
#define DPORT_WIFI_CLK_SDIO_HOST_EN BIT(13)
#define DPORT_WIFI_CLK_EMAC_EN BIT(14)
#define DPORT_WIFI_CLK_RNG_EN BIT(15)
#define DPORT_CORE_RST_EN_REG DPORT_WIFI_RST_EN_REG
#define DPORT_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG
/* DPORT_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_WIFI_RST 0xFFFFFFFF
#define DPORT_WIFI_RST_M ((DPORT_WIFI_RST_V)<<(DPORT_WIFI_RST_S))
#define DPORT_WIFI_RST_V 0xFFFFFFFF
#define DPORT_WIFI_RST_S 0
#define DPORT_RW_BTLP_RST (BIT(10))
#define DPORT_RW_BTMAC_RST (BIT(9))
#define DPORT_MACPWR_RST (BIT(8))
#define DPORT_EMAC_RST (BIT(7))
#define DPORT_SDIO_HOST_RST (BIT(6))
#define DPORT_SDIO_RST (BIT(5))
#define DPORT_BTMAC_RST (BIT(4))
#define DPORT_BT_RST (BIT(3))
#define DPORT_MAC_RST (BIT(2))
#define DPORT_FE_RST (BIT(1))
#define DPORT_BB_RST (BIT(0))
#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x0DC)
/* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
#define SYSCON_DC_MEM_FORCE_PD (BIT(5))
#define SYSCON_DC_MEM_FORCE_PD_M (BIT(5))
#define SYSCON_DC_MEM_FORCE_PD_V 0x1
#define SYSCON_DC_MEM_FORCE_PD_S 5
/* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: */
#define SYSCON_DC_MEM_FORCE_PU (BIT(4))
#define SYSCON_DC_MEM_FORCE_PU_M (BIT(4))
#define SYSCON_DC_MEM_FORCE_PU_V 0x1
#define SYSCON_DC_MEM_FORCE_PU_S 4
/* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define SYSCON_PBUS_MEM_FORCE_PD (BIT(3))
#define SYSCON_PBUS_MEM_FORCE_PD_M (BIT(3))
#define SYSCON_PBUS_MEM_FORCE_PD_V 0x1
#define SYSCON_PBUS_MEM_FORCE_PD_S 3
/* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: */
#define SYSCON_PBUS_MEM_FORCE_PU (BIT(2))
#define SYSCON_PBUS_MEM_FORCE_PU_M (BIT(2))
#define SYSCON_PBUS_MEM_FORCE_PU_V 0x1
#define SYSCON_PBUS_MEM_FORCE_PU_S 2
/* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define SYSCON_AGC_MEM_FORCE_PD (BIT(1))
#define SYSCON_AGC_MEM_FORCE_PD_M (BIT(1))
#define SYSCON_AGC_MEM_FORCE_PD_V 0x1
#define SYSCON_AGC_MEM_FORCE_PD_S 1
/* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define SYSCON_AGC_MEM_FORCE_PU (BIT(0))
#define SYSCON_AGC_MEM_FORCE_PU_M (BIT(0))
#define SYSCON_AGC_MEM_FORCE_PU_V 0x1
#define SYSCON_AGC_MEM_FORCE_PU_S 0
#define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC)
/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h18102500 ; */
/*description: */
#define SYSCON_DATE 0xFFFFFFFF
#define SYSCON_DATE_M ((SYSCON_DATE_V)<<(SYSCON_DATE_S))
#define SYSCON_DATE_V 0xFFFFFFFF
#define SYSCON_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_SYSCON_REG_H_ */

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SYSCON_STRUCT_H_
#define _SOC_SYSCON_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t pre_div: 10;
uint32_t clk_320m_en: 1;
uint32_t clk_en: 1;
uint32_t rst_tick: 1;
uint32_t quick_clk_chng: 1;
uint32_t reserved14: 18;
};
uint32_t val;
}clk_conf;
union {
struct {
uint32_t xtal_tick: 8;
uint32_t reserved8: 24;
};
uint32_t val;
}xtal_tick_conf;
union {
struct {
uint32_t pll_tick: 8;
uint32_t reserved8: 24;
};
uint32_t val;
}pll_tick_conf;
union {
struct {
uint32_t ck8m_tick: 8;
uint32_t reserved8: 24;
};
uint32_t val;
}ck8m_tick_conf;
union {
struct {
uint32_t start_force: 1;
uint32_t start: 1;
uint32_t sar2_mux: 1; /*1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL*/
uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/
uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/
uint32_t sar_clk_gated: 1;
uint32_t sar_clk_div: 8; /*SAR clock divider*/
uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/
uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/
uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/
uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/
uint32_t reserved27: 5;
};
uint32_t val;
}saradc_ctrl;
union {
struct {
uint32_t meas_num_limit: 1;
uint32_t max_meas_num: 8; /*max conversion number*/
uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/
uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/
uint32_t reserved11: 21;
};
uint32_t val;
}saradc_ctrl2;
union {
struct {
uint32_t rstb_wait: 8;
uint32_t standby_wait: 8;
uint32_t start_wait: 8;
uint32_t sample_cycle: 8; /*sample cycles*/
};
uint32_t val;
}saradc_fsm;
uint32_t saradc_sar1_patt_tab[4]; /*item 0 ~ 3 for ADC1 pattern table*/
uint32_t saradc_sar2_patt_tab[4]; /*item 0 ~ 3 for ADC2 pattern table*/
union {
struct {
uint32_t apll_tick: 8;
uint32_t reserved8: 24;
};
uint32_t val;
}apll_tick_conf;
uint32_t reserved_40;
uint32_t reserved_44;
uint32_t reserved_48;
uint32_t reserved_4c;
uint32_t reserved_50;
uint32_t reserved_54;
uint32_t reserved_58;
uint32_t reserved_5c;
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t date; /**/
} syscon_dev_t;
#ifdef __cplusplus
}
#endif
extern syscon_dev_t SYSCON;
#endif /* _SOC_SYSCON_STRUCT_H_ */

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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SYSTEM_REG_H_
#define _SOC_SYSTEM_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define DPORT_ROM_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x000)
/* DPORT_ROM_FO : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
/*description: */
#define DPORT_ROM_FO 0x00000003
#define DPORT_ROM_FO_M ((DPORT_ROM_FO_V)<<(DPORT_ROM_FO_S))
#define DPORT_ROM_FO_V 0x3
#define DPORT_ROM_FO_S 0
#define DPORT_ROM_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x004)
/* DPORT_ROM_PD : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
/*description: */
#define DPORT_ROM_PD 0x00000003
#define DPORT_ROM_PD_M ((DPORT_ROM_PD_V)<<(DPORT_ROM_PD_S))
#define DPORT_ROM_PD_V 0x3
#define DPORT_ROM_PD_S 0
#define DPORT_SRAM_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x008)
/* DPORT_SRAM_FO : R/W ;bitpos:[21:0] ;default: ~22'b0 ; */
/*description: */
#define DPORT_SRAM_FO 0x003FFFFF
#define DPORT_SRAM_FO_M ((DPORT_SRAM_FO_V)<<(DPORT_SRAM_FO_S))
#define DPORT_SRAM_FO_V 0x3FFFFF
#define DPORT_SRAM_FO_S 0
#define DPORT_SRAM_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x00C)
/* DPORT_SRAM_PD : R/W ;bitpos:[21:0] ;default: 22'b0 ; */
/*description: */
#define DPORT_SRAM_PD 0x003FFFFF
#define DPORT_SRAM_PD_M ((DPORT_SRAM_PD_V)<<(DPORT_SRAM_PD_S))
#define DPORT_SRAM_PD_V 0x3FFFFF
#define DPORT_SRAM_PD_S 0
#define DPORT_PERI_CLK_EN_REG DPORT_CPU_PERI_CLK_EN_REG
#define DPORT_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x010)
/* DPORT_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: */
#define DPORT_CLK_EN_DEDICATED_GPIO (BIT(7))
#define DPORT_CLK_EN_DEDICATED_GPIO_M (BIT(7))
#define DPORT_CLK_EN_DEDICATED_GPIO_V 0x1
#define DPORT_CLK_EN_DEDICATED_GPIO_S 7
/* DPORT_CLK_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: */
#define DPORT_CLK_EN_ASSIST_DEBUG (BIT(6))
#define DPORT_CLK_EN_ASSIST_DEBUG_M (BIT(6))
#define DPORT_CLK_EN_ASSIST_DEBUG_V 0x1
#define DPORT_CLK_EN_ASSIST_DEBUG_S 6
/* DPORT_CLK_EN_DIGITAL_SIGNATURE : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
#define DPORT_CLK_EN_DIGITAL_SIGNATURE (BIT(5))
#define DPORT_CLK_EN_DIGITAL_SIGNATURE_M (BIT(5))
#define DPORT_CLK_EN_DIGITAL_SIGNATURE_V 0x1
#define DPORT_CLK_EN_DIGITAL_SIGNATURE_S 5
/* DPORT_CLK_EN_HMAC : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: */
#define DPORT_CLK_EN_HMAC (BIT(4))
#define DPORT_CLK_EN_HMAC_M (BIT(4))
#define DPORT_CLK_EN_HMAC_V 0x1
#define DPORT_CLK_EN_HMAC_S 4
/* DPORT_CLK_EN_SECURE_BOOT : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define DPORT_CLK_EN_SECURE_BOOT (BIT(3))
#define DPORT_CLK_EN_SECURE_BOOT_M (BIT(3))
#define DPORT_CLK_EN_SECURE_BOOT_V 0x1
#define DPORT_CLK_EN_SECURE_BOOT_S 3
/* DPORT_CLK_EN_RSA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define DPORT_CLK_EN_RSA (BIT(2))
#define DPORT_CLK_EN_RSA_M (BIT(2))
#define DPORT_CLK_EN_RSA_V 0x1
#define DPORT_CLK_EN_RSA_S 2
/* DPORT_CLK_EN_SHA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define DPORT_CLK_EN_SHA (BIT(1))
#define DPORT_CLK_EN_SHA_M (BIT(1))
#define DPORT_CLK_EN_SHA_V 0x1
#define DPORT_CLK_EN_SHA_S 1
/* DPORT_CLK_EN_AES : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define DPORT_CLK_EN_AES (BIT(0))
#define DPORT_CLK_EN_AES_M (BIT(0))
#define DPORT_CLK_EN_AES_V 0x1
#define DPORT_CLK_EN_AES_S 0
#define DPORT_PERI_EN_AES DPORT_CLK_EN_AES
#define DPORT_PERI_EN_SHA DPORT_CLK_EN_SHA
#define DPORT_PERI_EN_RSA DPORT_CLK_EN_RSA
/* NB: Secure boot reset will hold SHA & AES in reset */
#define DPORT_PERI_EN_SECUREBOOT DPORT_CLK_EN_SECURE_BOOT
/* NB: Digital signature reset will hold AES & RSA in reset */
#define DPORT_PERI_EN_DIGITAL_SIGNATURE DPORT_CLK_EN_DIGITAL_SIGNATURE
#define DPORT_PERI_EN_ASSIST_DEBUG DPORT_CLK_EN_ASSIST_DEBUG
#define DPORT_PERI_RST_EN_REG DPORT_CPU_PERI_RST_EN_REG
#define DPORT_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x014)
/* DPORT_RST_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b1 ; */
/*description: */
#define DPORT_RST_EN_DEDICATED_GPIO (BIT(7))
#define DPORT_RST_EN_DEDICATED_GPIO_M (BIT(7))
#define DPORT_RST_EN_DEDICATED_GPIO_V 0x1
#define DPORT_RST_EN_DEDICATED_GPIO_S 7
/* DPORT_RST_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: */
#define DPORT_RST_EN_ASSIST_DEBUG (BIT(6))
#define DPORT_RST_EN_ASSIST_DEBUG_M (BIT(6))
#define DPORT_RST_EN_ASSIST_DEBUG_V 0x1
#define DPORT_RST_EN_ASSIST_DEBUG_S 6
/* DPORT_RST_EN_DIGITAL_SIGNATURE : R/W ;bitpos:[5] ;default: 1'b1 ; */
/*description: */
#define DPORT_RST_EN_DIGITAL_SIGNATURE (BIT(5))
#define DPORT_RST_EN_DIGITAL_SIGNATURE_M (BIT(5))
#define DPORT_RST_EN_DIGITAL_SIGNATURE_V 0x1
#define DPORT_RST_EN_DIGITAL_SIGNATURE_S 5
/* DPORT_RST_EN_HMAC : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: */
#define DPORT_RST_EN_HMAC (BIT(4))
#define DPORT_RST_EN_HMAC_M (BIT(4))
#define DPORT_RST_EN_HMAC_V 0x1
#define DPORT_RST_EN_HMAC_S 4
/* DPORT_RST_EN_SECURE_BOOT : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: */
#define DPORT_RST_EN_SECURE_BOOT (BIT(3))
#define DPORT_RST_EN_SECURE_BOOT_M (BIT(3))
#define DPORT_RST_EN_SECURE_BOOT_V 0x1
#define DPORT_RST_EN_SECURE_BOOT_S 3
/* DPORT_RST_EN_RSA : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: */
#define DPORT_RST_EN_RSA (BIT(2))
#define DPORT_RST_EN_RSA_M (BIT(2))
#define DPORT_RST_EN_RSA_V 0x1
#define DPORT_RST_EN_RSA_S 2
/* DPORT_RST_EN_SHA : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: */
#define DPORT_RST_EN_SHA (BIT(1))
#define DPORT_RST_EN_SHA_M (BIT(1))
#define DPORT_RST_EN_SHA_V 0x1
#define DPORT_RST_EN_SHA_S 1
/* DPORT_RST_EN_AES : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define DPORT_RST_EN_AES (BIT(0))
#define DPORT_RST_EN_AES_M (BIT(0))
#define DPORT_RST_EN_AES_V 0x1
#define DPORT_RST_EN_AES_S 0
#define DPORT_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x018)
/* DPORT_CPU_WAIT_MODE_FORCE_ON : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: */
#define DPORT_CPU_WAIT_MODE_FORCE_ON (BIT(3))
#define DPORT_CPU_WAIT_MODE_FORCE_ON_M (BIT(3))
#define DPORT_CPU_WAIT_MODE_FORCE_ON_V 0x1
#define DPORT_CPU_WAIT_MODE_FORCE_ON_S 3
/* DPORT_PLL_FREQ_SEL : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: */
#define DPORT_PLL_FREQ_SEL (BIT(2))
#define DPORT_PLL_FREQ_SEL_M (BIT(2))
#define DPORT_PLL_FREQ_SEL_V 0x1
#define DPORT_PLL_FREQ_SEL_S 2
/* DPORT_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
/*description: */
#define DPORT_CPUPERIOD_SEL 0x00000003
#define DPORT_CPUPERIOD_SEL_M ((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S))
#define DPORT_CPUPERIOD_SEL_V 0x3
#define DPORT_CPUPERIOD_SEL_S 0
#define DPORT_JTAG_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x01C)
/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 0xFFFFFFFF
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S))
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V 0xFFFFFFFF
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S 0
#define DPORT_JTAG_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x020)
/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 0xFFFFFFFF
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S))
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V 0xFFFFFFFF
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S 0
#define DPORT_JTAG_CTRL_2_REG (DR_REG_SYSTEM_BASE + 0x024)
/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 0xFFFFFFFF
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S))
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V 0xFFFFFFFF
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S 0
#define DPORT_JTAG_CTRL_3_REG (DR_REG_SYSTEM_BASE + 0x028)
/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 0xFFFFFFFF
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S))
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V 0xFFFFFFFF
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S 0
#define DPORT_JTAG_CTRL_4_REG (DR_REG_SYSTEM_BASE + 0x02C)
/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 0xFFFFFFFF
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S))
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V 0xFFFFFFFF
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S 0
#define DPORT_JTAG_CTRL_5_REG (DR_REG_SYSTEM_BASE + 0x030)
/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 0xFFFFFFFF
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S))
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V 0xFFFFFFFF
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S 0
#define DPORT_JTAG_CTRL_6_REG (DR_REG_SYSTEM_BASE + 0x034)
/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 0xFFFFFFFF
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S))
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V 0xFFFFFFFF
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S 0
#define DPORT_JTAG_CTRL_7_REG (DR_REG_SYSTEM_BASE + 0x038)
/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 0xFFFFFFFF
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S))
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V 0xFFFFFFFF
#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S 0
#define DPORT_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x03C)
/* DPORT_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define DPORT_LSLP_MEM_PD_MASK (BIT(0))
#define DPORT_LSLP_MEM_PD_MASK_M (BIT(0))
#define DPORT_LSLP_MEM_PD_MASK_V 0x1
#define DPORT_LSLP_MEM_PD_MASK_S 0
#define DPORT_PERIP_CLK_EN_REG DPORT_PERIP_CLK_EN0_REG
#define DPORT_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x040)
/* DPORT_SPI4_CLK_EN : R/W ;bitpos:[31] ;default: 1'h1 ; */
/*description: */
#define DPORT_SPI4_CLK_EN (BIT(31))
#define DPORT_SPI4_CLK_EN_M (BIT(31))
#define DPORT_SPI4_CLK_EN_V 0x1
#define DPORT_SPI4_CLK_EN_S 31
/* DPORT_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
/*description: */
#define DPORT_ADC2_ARB_CLK_EN (BIT(30))
#define DPORT_ADC2_ARB_CLK_EN_M (BIT(30))
#define DPORT_ADC2_ARB_CLK_EN_V 0x1
#define DPORT_ADC2_ARB_CLK_EN_S 30
/* DPORT_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
/*description: */
#define DPORT_SYSTIMER_CLK_EN (BIT(29))
#define DPORT_SYSTIMER_CLK_EN_M (BIT(29))
#define DPORT_SYSTIMER_CLK_EN_V 0x1
#define DPORT_SYSTIMER_CLK_EN_S 29
/* DPORT_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */
/*description: */
#define DPORT_APB_SARADC_CLK_EN (BIT(28))
#define DPORT_APB_SARADC_CLK_EN_M (BIT(28))
#define DPORT_APB_SARADC_CLK_EN_V 0x1
#define DPORT_APB_SARADC_CLK_EN_S 28
/* DPORT_SPI3_DMA_CLK_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */
/*description: */
#define DPORT_SPI3_DMA_CLK_EN (BIT(27))
#define DPORT_SPI3_DMA_CLK_EN_M (BIT(27))
#define DPORT_SPI3_DMA_CLK_EN_V 0x1
#define DPORT_SPI3_DMA_CLK_EN_S 27
/* DPORT_PWM3_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: */
#define DPORT_PWM3_CLK_EN (BIT(26))
#define DPORT_PWM3_CLK_EN_M (BIT(26))
#define DPORT_PWM3_CLK_EN_V 0x1
#define DPORT_PWM3_CLK_EN_S 26
/* DPORT_PWM2_CLK_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: */
#define DPORT_PWM2_CLK_EN (BIT(25))
#define DPORT_PWM2_CLK_EN_M (BIT(25))
#define DPORT_PWM2_CLK_EN_V 0x1
#define DPORT_PWM2_CLK_EN_S 25
/* DPORT_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
/*description: */
#define DPORT_UART_MEM_CLK_EN (BIT(24))
#define DPORT_UART_MEM_CLK_EN_M (BIT(24))
#define DPORT_UART_MEM_CLK_EN_V 0x1
#define DPORT_UART_MEM_CLK_EN_S 24
/* DPORT_USB_CLK_EN : R/W ;bitpos:[23] ;default: 1'b1 ; */
/*description: */
#define DPORT_USB_CLK_EN (BIT(23))
#define DPORT_USB_CLK_EN_M (BIT(23))
#define DPORT_USB_CLK_EN_V 0x1
#define DPORT_USB_CLK_EN_S 23
/* DPORT_SPI2_DMA_CLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
/*description: */
#define DPORT_SPI2_DMA_CLK_EN (BIT(22))
#define DPORT_SPI2_DMA_CLK_EN_M (BIT(22))
#define DPORT_SPI2_DMA_CLK_EN_V 0x1
#define DPORT_SPI2_DMA_CLK_EN_S 22
/* DPORT_I2S1_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
/*description: */
#define DPORT_I2S1_CLK_EN (BIT(21))
#define DPORT_I2S1_CLK_EN_M (BIT(21))
#define DPORT_I2S1_CLK_EN_V 0x1
#define DPORT_I2S1_CLK_EN_S 21
/* DPORT_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define DPORT_PWM1_CLK_EN (BIT(20))
#define DPORT_PWM1_CLK_EN_M (BIT(20))
#define DPORT_PWM1_CLK_EN_V 0x1
#define DPORT_PWM1_CLK_EN_S 20
/* DPORT_CAN_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
/*description: */
#define DPORT_CAN_CLK_EN (BIT(19))
#define DPORT_CAN_CLK_EN_M (BIT(19))
#define DPORT_CAN_CLK_EN_V 0x1
#define DPORT_CAN_CLK_EN_S 19
/* DPORT_I2C_EXT1_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
/*description: */
#define DPORT_I2C_EXT1_CLK_EN (BIT(18))
#define DPORT_I2C_EXT1_CLK_EN_M (BIT(18))
#define DPORT_I2C_EXT1_CLK_EN_V 0x1
#define DPORT_I2C_EXT1_CLK_EN_S 18
/* DPORT_PWM0_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: */
#define DPORT_PWM0_CLK_EN (BIT(17))
#define DPORT_PWM0_CLK_EN_M (BIT(17))
#define DPORT_PWM0_CLK_EN_V 0x1
#define DPORT_PWM0_CLK_EN_S 17
/* DPORT_SPI3_CLK_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */
/*description: */
#define DPORT_SPI3_CLK_EN (BIT(16))
#define DPORT_SPI3_CLK_EN_M (BIT(16))
#define DPORT_SPI3_CLK_EN_V 0x1
#define DPORT_SPI3_CLK_EN_S 16
/* DPORT_TIMERGROUP1_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */
/*description: */
#define DPORT_TIMERGROUP1_CLK_EN (BIT(15))
#define DPORT_TIMERGROUP1_CLK_EN_M (BIT(15))
#define DPORT_TIMERGROUP1_CLK_EN_V 0x1
#define DPORT_TIMERGROUP1_CLK_EN_S 15
/* DPORT_EFUSE_CLK_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */
/*description: */
#define DPORT_EFUSE_CLK_EN (BIT(14))
#define DPORT_EFUSE_CLK_EN_M (BIT(14))
#define DPORT_EFUSE_CLK_EN_V 0x1
#define DPORT_EFUSE_CLK_EN_S 14
/* DPORT_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */
/*description: */
#define DPORT_TIMERGROUP_CLK_EN (BIT(13))
#define DPORT_TIMERGROUP_CLK_EN_M (BIT(13))
#define DPORT_TIMERGROUP_CLK_EN_V 0x1
#define DPORT_TIMERGROUP_CLK_EN_S 13
/* DPORT_UHCI1_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: */
#define DPORT_UHCI1_CLK_EN (BIT(12))
#define DPORT_UHCI1_CLK_EN_M (BIT(12))
#define DPORT_UHCI1_CLK_EN_V 0x1
#define DPORT_UHCI1_CLK_EN_S 12
/* DPORT_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: */
#define DPORT_LEDC_CLK_EN (BIT(11))
#define DPORT_LEDC_CLK_EN_M (BIT(11))
#define DPORT_LEDC_CLK_EN_V 0x1
#define DPORT_LEDC_CLK_EN_S 11
/* DPORT_PCNT_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: */
#define DPORT_PCNT_CLK_EN (BIT(10))
#define DPORT_PCNT_CLK_EN_M (BIT(10))
#define DPORT_PCNT_CLK_EN_V 0x1
#define DPORT_PCNT_CLK_EN_S 10
/* DPORT_RMT_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: */
#define DPORT_RMT_CLK_EN (BIT(9))
#define DPORT_RMT_CLK_EN_M (BIT(9))
#define DPORT_RMT_CLK_EN_V 0x1
#define DPORT_RMT_CLK_EN_S 9
/* DPORT_UHCI0_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: */
#define DPORT_UHCI0_CLK_EN (BIT(8))
#define DPORT_UHCI0_CLK_EN_M (BIT(8))
#define DPORT_UHCI0_CLK_EN_V 0x1
#define DPORT_UHCI0_CLK_EN_S 8
/* DPORT_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: */
#define DPORT_I2C_EXT0_CLK_EN (BIT(7))
#define DPORT_I2C_EXT0_CLK_EN_M (BIT(7))
#define DPORT_I2C_EXT0_CLK_EN_V 0x1
#define DPORT_I2C_EXT0_CLK_EN_S 7
/* DPORT_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: */
#define DPORT_SPI2_CLK_EN (BIT(6))
#define DPORT_SPI2_CLK_EN_M (BIT(6))
#define DPORT_SPI2_CLK_EN_V 0x1
#define DPORT_SPI2_CLK_EN_S 6
/* DPORT_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
/*description: */
#define DPORT_UART1_CLK_EN (BIT(5))
#define DPORT_UART1_CLK_EN_M (BIT(5))
#define DPORT_UART1_CLK_EN_V 0x1
#define DPORT_UART1_CLK_EN_S 5
/* DPORT_I2S0_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: */
#define DPORT_I2S0_CLK_EN (BIT(4))
#define DPORT_I2S0_CLK_EN_M (BIT(4))
#define DPORT_I2S0_CLK_EN_V 0x1
#define DPORT_I2S0_CLK_EN_S 4
/* DPORT_WDG_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: */
#define DPORT_WDG_CLK_EN (BIT(3))
#define DPORT_WDG_CLK_EN_M (BIT(3))
#define DPORT_WDG_CLK_EN_V 0x1
#define DPORT_WDG_CLK_EN_S 3
/* DPORT_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: */
#define DPORT_UART_CLK_EN (BIT(2))
#define DPORT_UART_CLK_EN_M (BIT(2))
#define DPORT_UART_CLK_EN_V 0x1
#define DPORT_UART_CLK_EN_S 2
/* DPORT_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: */
#define DPORT_SPI01_CLK_EN (BIT(1))
#define DPORT_SPI01_CLK_EN_M (BIT(1))
#define DPORT_SPI01_CLK_EN_V 0x1
#define DPORT_SPI01_CLK_EN_S 1
/* DPORT_TIMERS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define DPORT_TIMERS_CLK_EN (BIT(0))
#define DPORT_TIMERS_CLK_EN_M (BIT(0))
#define DPORT_TIMERS_CLK_EN_V 0x1
#define DPORT_TIMERS_CLK_EN_S 0
#define DPORT_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x044)
/* DPORT_SPI_SHARED_DMA_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define DPORT_SPI_SHARED_DMA_CLK_EN (BIT(0))
#define DPORT_SPI_SHARED_DMA_CLK_EN_M (BIT(0))
#define DPORT_SPI_SHARED_DMA_CLK_EN_V 0x1
#define DPORT_SPI_SHARED_DMA_CLK_EN_S 0
#define DPORT_PERIP_RST_EN_REG DPORT_PERIP_RST_EN0_REG
#define DPORT_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x048)
/* DPORT_SPI4_RST : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define DPORT_SPI4_RST (BIT(31))
#define DPORT_SPI4_RST_M (BIT(31))
#define DPORT_SPI4_RST_V 0x1
#define DPORT_SPI4_RST_S 31
/* DPORT_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: */
#define DPORT_ADC2_ARB_RST (BIT(30))
#define DPORT_ADC2_ARB_RST_M (BIT(30))
#define DPORT_ADC2_ARB_RST_V 0x1
#define DPORT_ADC2_ARB_RST_S 30
/* DPORT_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
#define DPORT_SYSTIMER_RST (BIT(29))
#define DPORT_SYSTIMER_RST_M (BIT(29))
#define DPORT_SYSTIMER_RST_V 0x1
#define DPORT_SYSTIMER_RST_S 29
/* DPORT_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
#define DPORT_APB_SARADC_RST (BIT(28))
#define DPORT_APB_SARADC_RST_M (BIT(28))
#define DPORT_APB_SARADC_RST_V 0x1
#define DPORT_APB_SARADC_RST_S 28
/* DPORT_SPI3_DMA_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: */
#define DPORT_SPI3_DMA_RST (BIT(27))
#define DPORT_SPI3_DMA_RST_M (BIT(27))
#define DPORT_SPI3_DMA_RST_V 0x1
#define DPORT_SPI3_DMA_RST_S 27
/* DPORT_PWM3_RST : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: */
#define DPORT_PWM3_RST (BIT(26))
#define DPORT_PWM3_RST_M (BIT(26))
#define DPORT_PWM3_RST_V 0x1
#define DPORT_PWM3_RST_S 26
/* DPORT_PWM2_RST : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: */
#define DPORT_PWM2_RST (BIT(25))
#define DPORT_PWM2_RST_M (BIT(25))
#define DPORT_PWM2_RST_V 0x1
#define DPORT_PWM2_RST_S 25
/* DPORT_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: */
#define DPORT_UART_MEM_RST (BIT(24))
#define DPORT_UART_MEM_RST_M (BIT(24))
#define DPORT_UART_MEM_RST_V 0x1
#define DPORT_UART_MEM_RST_S 24
/* DPORT_USB_RST : R/W ;bitpos:[23] ;default: 1'b0 ; */
/*description: */
#define DPORT_USB_RST (BIT(23))
#define DPORT_USB_RST_M (BIT(23))
#define DPORT_USB_RST_V 0x1
#define DPORT_USB_RST_S 23
/* DPORT_SPI2_DMA_RST : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: */
#define DPORT_SPI2_DMA_RST (BIT(22))
#define DPORT_SPI2_DMA_RST_M (BIT(22))
#define DPORT_SPI2_DMA_RST_V 0x1
#define DPORT_SPI2_DMA_RST_S 22
/* DPORT_I2S1_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */
/*description: */
#define DPORT_I2S1_RST (BIT(21))
#define DPORT_I2S1_RST_M (BIT(21))
#define DPORT_I2S1_RST_V 0x1
#define DPORT_I2S1_RST_S 21
/* DPORT_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define DPORT_PWM1_RST (BIT(20))
#define DPORT_PWM1_RST_M (BIT(20))
#define DPORT_PWM1_RST_V 0x1
#define DPORT_PWM1_RST_S 20
/* DPORT_CAN_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */
/*description: */
#define DPORT_CAN_RST (BIT(19))
#define DPORT_CAN_RST_M (BIT(19))
#define DPORT_CAN_RST_V 0x1
#define DPORT_CAN_RST_S 19
/* DPORT_I2C_EXT1_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */
/*description: */
#define DPORT_I2C_EXT1_RST (BIT(18))
#define DPORT_I2C_EXT1_RST_M (BIT(18))
#define DPORT_I2C_EXT1_RST_V 0x1
#define DPORT_I2C_EXT1_RST_S 18
/* DPORT_PWM0_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: */
#define DPORT_PWM0_RST (BIT(17))
#define DPORT_PWM0_RST_M (BIT(17))
#define DPORT_PWM0_RST_V 0x1
#define DPORT_PWM0_RST_S 17
/* DPORT_SPI3_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: */
#define DPORT_SPI3_RST (BIT(16))
#define DPORT_SPI3_RST_M (BIT(16))
#define DPORT_SPI3_RST_V 0x1
#define DPORT_SPI3_RST_S 16
/* DPORT_TIMERGROUP1_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: */
#define DPORT_TIMERGROUP1_RST (BIT(15))
#define DPORT_TIMERGROUP1_RST_M (BIT(15))
#define DPORT_TIMERGROUP1_RST_V 0x1
#define DPORT_TIMERGROUP1_RST_S 15
/* DPORT_EFUSE_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: */
#define DPORT_EFUSE_RST (BIT(14))
#define DPORT_EFUSE_RST_M (BIT(14))
#define DPORT_EFUSE_RST_V 0x1
#define DPORT_EFUSE_RST_S 14
/* DPORT_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: */
#define DPORT_TIMERGROUP_RST (BIT(13))
#define DPORT_TIMERGROUP_RST_M (BIT(13))
#define DPORT_TIMERGROUP_RST_V 0x1
#define DPORT_TIMERGROUP_RST_S 13
/* DPORT_UHCI1_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: */
#define DPORT_UHCI1_RST (BIT(12))
#define DPORT_UHCI1_RST_M (BIT(12))
#define DPORT_UHCI1_RST_V 0x1
#define DPORT_UHCI1_RST_S 12
/* DPORT_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: */
#define DPORT_LEDC_RST (BIT(11))
#define DPORT_LEDC_RST_M (BIT(11))
#define DPORT_LEDC_RST_V 0x1
#define DPORT_LEDC_RST_S 11
/* DPORT_PCNT_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: */
#define DPORT_PCNT_RST (BIT(10))
#define DPORT_PCNT_RST_M (BIT(10))
#define DPORT_PCNT_RST_V 0x1
#define DPORT_PCNT_RST_S 10
/* DPORT_RMT_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: */
#define DPORT_RMT_RST (BIT(9))
#define DPORT_RMT_RST_M (BIT(9))
#define DPORT_RMT_RST_V 0x1
#define DPORT_RMT_RST_S 9
/* DPORT_UHCI0_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: */
#define DPORT_UHCI0_RST (BIT(8))
#define DPORT_UHCI0_RST_M (BIT(8))
#define DPORT_UHCI0_RST_V 0x1
#define DPORT_UHCI0_RST_S 8
/* DPORT_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: */
#define DPORT_I2C_EXT0_RST (BIT(7))
#define DPORT_I2C_EXT0_RST_M (BIT(7))
#define DPORT_I2C_EXT0_RST_V 0x1
#define DPORT_I2C_EXT0_RST_S 7
/* DPORT_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: */
#define DPORT_SPI2_RST (BIT(6))
#define DPORT_SPI2_RST_M (BIT(6))
#define DPORT_SPI2_RST_V 0x1
#define DPORT_SPI2_RST_S 6
/* DPORT_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
#define DPORT_UART1_RST (BIT(5))
#define DPORT_UART1_RST_M (BIT(5))
#define DPORT_UART1_RST_V 0x1
#define DPORT_UART1_RST_S 5
/* DPORT_I2S0_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: */
#define DPORT_I2S0_RST (BIT(4))
#define DPORT_I2S0_RST_M (BIT(4))
#define DPORT_I2S0_RST_V 0x1
#define DPORT_I2S0_RST_S 4
/* DPORT_WDG_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define DPORT_WDG_RST (BIT(3))
#define DPORT_WDG_RST_M (BIT(3))
#define DPORT_WDG_RST_V 0x1
#define DPORT_WDG_RST_S 3
/* DPORT_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define DPORT_UART_RST (BIT(2))
#define DPORT_UART_RST_M (BIT(2))
#define DPORT_UART_RST_V 0x1
#define DPORT_UART_RST_S 2
/* DPORT_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define DPORT_SPI01_RST (BIT(1))
#define DPORT_SPI01_RST_M (BIT(1))
#define DPORT_SPI01_RST_V 0x1
#define DPORT_SPI01_RST_S 1
/* DPORT_TIMERS_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define DPORT_TIMERS_RST (BIT(0))
#define DPORT_TIMERS_RST_M (BIT(0))
#define DPORT_TIMERS_RST_V 0x1
#define DPORT_TIMERS_RST_S 0
#define DPORT_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x04C)
/* DPORT_SPI_SHARED_DMA_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define DPORT_SPI_SHARED_DMA_RST (BIT(0))
#define DPORT_SPI_SHARED_DMA_RST_M (BIT(0))
#define DPORT_SPI_SHARED_DMA_RST_V 0x1
#define DPORT_SPI_SHARED_DMA_RST_S 0
#define DPORT_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x050)
/* DPORT_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */
/*description: */
#define DPORT_BT_LPCK_DIV_NUM 0x00000FFF
#define DPORT_BT_LPCK_DIV_NUM_M ((DPORT_BT_LPCK_DIV_NUM_V)<<(DPORT_BT_LPCK_DIV_NUM_S))
#define DPORT_BT_LPCK_DIV_NUM_V 0xFFF
#define DPORT_BT_LPCK_DIV_NUM_S 0
#define DPORT_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x054)
/* DPORT_LPCLK_RTC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
#define DPORT_LPCLK_RTC_EN (BIT(28))
#define DPORT_LPCLK_RTC_EN_M (BIT(28))
#define DPORT_LPCLK_RTC_EN_V 0x1
#define DPORT_LPCLK_RTC_EN_S 28
/* DPORT_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: */
#define DPORT_LPCLK_SEL_XTAL32K (BIT(27))
#define DPORT_LPCLK_SEL_XTAL32K_M (BIT(27))
#define DPORT_LPCLK_SEL_XTAL32K_V 0x1
#define DPORT_LPCLK_SEL_XTAL32K_S 27
/* DPORT_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: */
#define DPORT_LPCLK_SEL_XTAL (BIT(26))
#define DPORT_LPCLK_SEL_XTAL_M (BIT(26))
#define DPORT_LPCLK_SEL_XTAL_V 0x1
#define DPORT_LPCLK_SEL_XTAL_S 26
/* DPORT_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */
/*description: */
#define DPORT_LPCLK_SEL_8M (BIT(25))
#define DPORT_LPCLK_SEL_8M_M (BIT(25))
#define DPORT_LPCLK_SEL_8M_V 0x1
#define DPORT_LPCLK_SEL_8M_S 25
/* DPORT_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: */
#define DPORT_LPCLK_SEL_RTC_SLOW (BIT(24))
#define DPORT_LPCLK_SEL_RTC_SLOW_M (BIT(24))
#define DPORT_LPCLK_SEL_RTC_SLOW_V 0x1
#define DPORT_LPCLK_SEL_RTC_SLOW_S 24
/* DPORT_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */
/*description: */
#define DPORT_BT_LPCK_DIV_A 0x00000FFF
#define DPORT_BT_LPCK_DIV_A_M ((DPORT_BT_LPCK_DIV_A_V)<<(DPORT_BT_LPCK_DIV_A_S))
#define DPORT_BT_LPCK_DIV_A_V 0xFFF
#define DPORT_BT_LPCK_DIV_A_S 12
/* DPORT_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */
/*description: */
#define DPORT_BT_LPCK_DIV_B 0x00000FFF
#define DPORT_BT_LPCK_DIV_B_M ((DPORT_BT_LPCK_DIV_B_V)<<(DPORT_BT_LPCK_DIV_B_S))
#define DPORT_BT_LPCK_DIV_B_V 0xFFF
#define DPORT_BT_LPCK_DIV_B_S 0
#define DPORT_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x058)
/* DPORT_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define DPORT_CPU_INTR_FROM_CPU_0 (BIT(0))
#define DPORT_CPU_INTR_FROM_CPU_0_M (BIT(0))
#define DPORT_CPU_INTR_FROM_CPU_0_V 0x1
#define DPORT_CPU_INTR_FROM_CPU_0_S 0
#define DPORT_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x05C)
/* DPORT_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define DPORT_CPU_INTR_FROM_CPU_1 (BIT(0))
#define DPORT_CPU_INTR_FROM_CPU_1_M (BIT(0))
#define DPORT_CPU_INTR_FROM_CPU_1_V 0x1
#define DPORT_CPU_INTR_FROM_CPU_1_S 0
#define DPORT_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x060)
/* DPORT_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define DPORT_CPU_INTR_FROM_CPU_2 (BIT(0))
#define DPORT_CPU_INTR_FROM_CPU_2_M (BIT(0))
#define DPORT_CPU_INTR_FROM_CPU_2_V 0x1
#define DPORT_CPU_INTR_FROM_CPU_2_S 0
#define DPORT_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x064)
/* DPORT_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define DPORT_CPU_INTR_FROM_CPU_3 (BIT(0))
#define DPORT_CPU_INTR_FROM_CPU_3_M (BIT(0))
#define DPORT_CPU_INTR_FROM_CPU_3_V 0x1
#define DPORT_CPU_INTR_FROM_CPU_3_S 0
#define DPORT_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x068)
/* DPORT_RSA_MEM_PD : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define DPORT_RSA_MEM_PD (BIT(0))
#define DPORT_RSA_MEM_PD_M (BIT(0))
#define DPORT_RSA_MEM_PD_V 0x1
#define DPORT_RSA_MEM_PD_S 0
#define DPORT_RSA_PD DPORT_RSA_MEM_PD
#define DPORT_SPI_DMA_CHAN_SEL_REG DPORT_SPI_SHARED_DMA_SEL_REG
#define DPORT_SPI_SHARED_DMA_SEL_REG (DR_REG_SYSTEM_BASE + 0x06C)
/* DPORT_SPI_SHARED_DMA_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define DPORT_SPI_SHARED_DMA_SEL (BIT(0))
#define DPORT_SPI_SHARED_DMA_SEL_M (BIT(0))
#define DPORT_SPI_SHARED_DMA_SEL_V 0x1
#define DPORT_SPI_SHARED_DMA_SEL_S 0
#define DPORT_BUSTOEXTMEM_ENA_REG (DR_REG_SYSTEM_BASE + 0x070)
/* DPORT_BUSTOEXTMEM_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define DPORT_BUSTOEXTMEM_ENA (BIT(0))
#define DPORT_BUSTOEXTMEM_ENA_M (BIT(0))
#define DPORT_BUSTOEXTMEM_ENA_V 0x1
#define DPORT_BUSTOEXTMEM_ENA_S 0
#define DPORT_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x074)
/* DPORT_PRO_CACHE_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_CACHE_RESET (BIT(2))
#define DPORT_PRO_CACHE_RESET_M (BIT(2))
#define DPORT_PRO_CACHE_RESET_V 0x1
#define DPORT_PRO_CACHE_RESET_S 2
/* DPORT_PRO_DCACHE_CLK_ON : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: */
#define DPORT_PRO_DCACHE_CLK_ON (BIT(1))
#define DPORT_PRO_DCACHE_CLK_ON_M (BIT(1))
#define DPORT_PRO_DCACHE_CLK_ON_V 0x1
#define DPORT_PRO_DCACHE_CLK_ON_S 1
/* DPORT_PRO_ICACHE_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define DPORT_PRO_ICACHE_CLK_ON (BIT(0))
#define DPORT_PRO_ICACHE_CLK_ON_M (BIT(0))
#define DPORT_PRO_ICACHE_CLK_ON_V 0x1
#define DPORT_PRO_ICACHE_CLK_ON_S 0
#define DPORT_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x078)
/* DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3))
#define DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(3))
#define DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x1
#define DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3
/* DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2))
#define DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (BIT(2))
#define DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x1
#define DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2
/* DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1))
#define DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT_M (BIT(1))
#define DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x1
#define DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1
/* DPORT_ENABLE_SPI_MANUAL_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define DPORT_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0))
#define DPORT_ENABLE_SPI_MANUAL_ENCRYPT_M (BIT(0))
#define DPORT_ENABLE_SPI_MANUAL_ENCRYPT_V 0x1
#define DPORT_ENABLE_SPI_MANUAL_ENCRYPT_S 0
#define DPORT_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x07C)
/* DPORT_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: */
#define DPORT_RTC_MEM_CRC_FINISH (BIT(31))
#define DPORT_RTC_MEM_CRC_FINISH_M (BIT(31))
#define DPORT_RTC_MEM_CRC_FINISH_V 0x1
#define DPORT_RTC_MEM_CRC_FINISH_S 31
/* DPORT_RTC_MEM_CRC_LEN : R/W ;bitpos:[30:20] ;default: 11'h7ff ; */
/*description: */
#define DPORT_RTC_MEM_CRC_LEN 0x000007FF
#define DPORT_RTC_MEM_CRC_LEN_M ((DPORT_RTC_MEM_CRC_LEN_V)<<(DPORT_RTC_MEM_CRC_LEN_S))
#define DPORT_RTC_MEM_CRC_LEN_V 0x7FF
#define DPORT_RTC_MEM_CRC_LEN_S 20
/* DPORT_RTC_MEM_CRC_ADDR : R/W ;bitpos:[19:9] ;default: 11'h0 ; */
/*description: */
#define DPORT_RTC_MEM_CRC_ADDR 0x000007FF
#define DPORT_RTC_MEM_CRC_ADDR_M ((DPORT_RTC_MEM_CRC_ADDR_V)<<(DPORT_RTC_MEM_CRC_ADDR_S))
#define DPORT_RTC_MEM_CRC_ADDR_V 0x7FF
#define DPORT_RTC_MEM_CRC_ADDR_S 9
/* DPORT_RTC_MEM_CRC_START : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: */
#define DPORT_RTC_MEM_CRC_START (BIT(8))
#define DPORT_RTC_MEM_CRC_START_M (BIT(8))
#define DPORT_RTC_MEM_CRC_START_V 0x1
#define DPORT_RTC_MEM_CRC_START_S 8
#define DPORT_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x080)
/* DPORT_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define DPORT_RTC_MEM_CRC_RES 0xFFFFFFFF
#define DPORT_RTC_MEM_CRC_RES_M ((DPORT_RTC_MEM_CRC_RES_V)<<(DPORT_RTC_MEM_CRC_RES_S))
#define DPORT_RTC_MEM_CRC_RES_V 0xFFFFFFFF
#define DPORT_RTC_MEM_CRC_RES_S 0
#define DPORT_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x084)
/* DPORT_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define DPORT_REDUNDANT_ECO_RESULT (BIT(1))
#define DPORT_REDUNDANT_ECO_RESULT_M (BIT(1))
#define DPORT_REDUNDANT_ECO_RESULT_V 0x1
#define DPORT_REDUNDANT_ECO_RESULT_S 1
/* DPORT_REDUNDANT_ECO_DRIVE : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define DPORT_REDUNDANT_ECO_DRIVE (BIT(0))
#define DPORT_REDUNDANT_ECO_DRIVE_M (BIT(0))
#define DPORT_REDUNDANT_ECO_DRIVE_V 0x1
#define DPORT_REDUNDANT_ECO_DRIVE_S 0
#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x088)
/* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_CLK_EN (BIT(0))
#define SYSTEM_CLK_EN_M (BIT(0))
#define SYSTEM_CLK_EN_V 0x1
#define SYSTEM_CLK_EN_S 0
#define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0xFFC)
/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1810300 ; */
/*description: */
#define SYSTEM_DATE 0x0FFFFFFF
#define SYSTEM_DATE_M ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S))
#define SYSTEM_DATE_V 0xFFFFFFF
#define SYSTEM_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_SYSTEM_REG_H_ */

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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_TIMG_REG_H_
#define _SOC_TIMG_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
/* Possible values for TIMG_WDT_STGx */
#define TIMG_WDT_STG_SEL_OFF 0
#define TIMG_WDT_STG_SEL_INT 1
#define TIMG_WDT_STG_SEL_RESET_CPU 2
#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000)
/* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_EN (BIT(31))
#define TIMG_T0_EN_M (BIT(31))
#define TIMG_T0_EN_V 0x1
#define TIMG_T0_EN_S 31
/* TIMG_T0_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
/*description: */
#define TIMG_T0_INCREASE (BIT(30))
#define TIMG_T0_INCREASE_M (BIT(30))
#define TIMG_T0_INCREASE_V 0x1
#define TIMG_T0_INCREASE_S 30
/* TIMG_T0_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
/*description: */
#define TIMG_T0_AUTORELOAD (BIT(29))
#define TIMG_T0_AUTORELOAD_M (BIT(29))
#define TIMG_T0_AUTORELOAD_V 0x1
#define TIMG_T0_AUTORELOAD_S 29
/* TIMG_T0_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
/*description: */
#define TIMG_T0_DIVIDER 0x0000FFFF
#define TIMG_T0_DIVIDER_M ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S))
#define TIMG_T0_DIVIDER_V 0xFFFF
#define TIMG_T0_DIVIDER_S 13
/* TIMG_T0_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_EDGE_INT_EN (BIT(12))
#define TIMG_T0_EDGE_INT_EN_M (BIT(12))
#define TIMG_T0_EDGE_INT_EN_V 0x1
#define TIMG_T0_EDGE_INT_EN_S 12
/* TIMG_T0_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_LEVEL_INT_EN (BIT(11))
#define TIMG_T0_LEVEL_INT_EN_M (BIT(11))
#define TIMG_T0_LEVEL_INT_EN_V 0x1
#define TIMG_T0_LEVEL_INT_EN_S 11
/* TIMG_T0_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_ALARM_EN (BIT(10))
#define TIMG_T0_ALARM_EN_M (BIT(10))
#define TIMG_T0_ALARM_EN_V 0x1
#define TIMG_T0_ALARM_EN_S 10
/* TIMG_T0_USE_XTAL : R/W ;bitpos:[9] ;default: 1'd0 ; */
/*description: */
#define TIMG_T0_USE_XTAL (BIT(9))
#define TIMG_T0_USE_XTAL_M (BIT(9))
#define TIMG_T0_USE_XTAL_V 0x1
#define TIMG_T0_USE_XTAL_S 9
#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x0004)
/* TIMG_T0_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T0_LO 0xFFFFFFFF
#define TIMG_T0_LO_M ((TIMG_T0_LO_V)<<(TIMG_T0_LO_S))
#define TIMG_T0_LO_V 0xFFFFFFFF
#define TIMG_T0_LO_S 0
#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x0008)
/* TIMG_T0_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T0_HI 0xFFFFFFFF
#define TIMG_T0_HI_M ((TIMG_T0_HI_V)<<(TIMG_T0_HI_S))
#define TIMG_T0_HI_V 0xFFFFFFFF
#define TIMG_T0_HI_S 0
#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x000c)
/* TIMG_T0_UPDATE : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_UPDATE (BIT(31))
#define TIMG_T0_UPDATE_M (BIT(31))
#define TIMG_T0_UPDATE_V 0x1
#define TIMG_T0_UPDATE_S 31
#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0010)
/* TIMG_T0_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T0_ALARM_LO 0xFFFFFFFF
#define TIMG_T0_ALARM_LO_M ((TIMG_T0_ALARM_LO_V)<<(TIMG_T0_ALARM_LO_S))
#define TIMG_T0_ALARM_LO_V 0xFFFFFFFF
#define TIMG_T0_ALARM_LO_S 0
#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0014)
/* TIMG_T0_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T0_ALARM_HI 0xFFFFFFFF
#define TIMG_T0_ALARM_HI_M ((TIMG_T0_ALARM_HI_V)<<(TIMG_T0_ALARM_HI_S))
#define TIMG_T0_ALARM_HI_V 0xFFFFFFFF
#define TIMG_T0_ALARM_HI_S 0
#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x0018)
/* TIMG_T0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T0_LOAD_LO 0xFFFFFFFF
#define TIMG_T0_LOAD_LO_M ((TIMG_T0_LOAD_LO_V)<<(TIMG_T0_LOAD_LO_S))
#define TIMG_T0_LOAD_LO_V 0xFFFFFFFF
#define TIMG_T0_LOAD_LO_S 0
#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x001c)
/* TIMG_T0_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T0_LOAD_HI 0xFFFFFFFF
#define TIMG_T0_LOAD_HI_M ((TIMG_T0_LOAD_HI_V)<<(TIMG_T0_LOAD_HI_S))
#define TIMG_T0_LOAD_HI_V 0xFFFFFFFF
#define TIMG_T0_LOAD_HI_S 0
#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0020)
/* TIMG_T0_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T0_LOAD 0xFFFFFFFF
#define TIMG_T0_LOAD_M ((TIMG_T0_LOAD_V)<<(TIMG_T0_LOAD_S))
#define TIMG_T0_LOAD_V 0xFFFFFFFF
#define TIMG_T0_LOAD_S 0
#define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0024)
/* TIMG_T1_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_T1_EN (BIT(31))
#define TIMG_T1_EN_M (BIT(31))
#define TIMG_T1_EN_V 0x1
#define TIMG_T1_EN_S 31
/* TIMG_T1_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
/*description: */
#define TIMG_T1_INCREASE (BIT(30))
#define TIMG_T1_INCREASE_M (BIT(30))
#define TIMG_T1_INCREASE_V 0x1
#define TIMG_T1_INCREASE_S 30
/* TIMG_T1_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
/*description: */
#define TIMG_T1_AUTORELOAD (BIT(29))
#define TIMG_T1_AUTORELOAD_M (BIT(29))
#define TIMG_T1_AUTORELOAD_V 0x1
#define TIMG_T1_AUTORELOAD_S 29
/* TIMG_T1_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
/*description: */
#define TIMG_T1_DIVIDER 0x0000FFFF
#define TIMG_T1_DIVIDER_M ((TIMG_T1_DIVIDER_V)<<(TIMG_T1_DIVIDER_S))
#define TIMG_T1_DIVIDER_V 0xFFFF
#define TIMG_T1_DIVIDER_S 13
/* TIMG_T1_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
/*description: */
#define TIMG_T1_EDGE_INT_EN (BIT(12))
#define TIMG_T1_EDGE_INT_EN_M (BIT(12))
#define TIMG_T1_EDGE_INT_EN_V 0x1
#define TIMG_T1_EDGE_INT_EN_S 12
/* TIMG_T1_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */
/*description: */
#define TIMG_T1_LEVEL_INT_EN (BIT(11))
#define TIMG_T1_LEVEL_INT_EN_M (BIT(11))
#define TIMG_T1_LEVEL_INT_EN_V 0x1
#define TIMG_T1_LEVEL_INT_EN_S 11
/* TIMG_T1_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */
/*description: */
#define TIMG_T1_ALARM_EN (BIT(10))
#define TIMG_T1_ALARM_EN_M (BIT(10))
#define TIMG_T1_ALARM_EN_V 0x1
#define TIMG_T1_ALARM_EN_S 10
/* TIMG_T1_USE_XTAL : R/W ;bitpos:[9] ;default: 1'd0 ; */
/*description: */
#define TIMG_T1_USE_XTAL (BIT(9))
#define TIMG_T1_USE_XTAL_M (BIT(9))
#define TIMG_T1_USE_XTAL_V 0x1
#define TIMG_T1_USE_XTAL_S 9
#define TIMG_T1LO_REG(i) (REG_TIMG_BASE(i) + 0x0028)
/* TIMG_T1_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T1_LO 0xFFFFFFFF
#define TIMG_T1_LO_M ((TIMG_T1_LO_V)<<(TIMG_T1_LO_S))
#define TIMG_T1_LO_V 0xFFFFFFFF
#define TIMG_T1_LO_S 0
#define TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x002c)
/* TIMG_T1_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T1_HI 0xFFFFFFFF
#define TIMG_T1_HI_M ((TIMG_T1_HI_V)<<(TIMG_T1_HI_S))
#define TIMG_T1_HI_V 0xFFFFFFFF
#define TIMG_T1_HI_S 0
#define TIMG_T1UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x0030)
/* TIMG_T1_UPDATE : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_T1_UPDATE (BIT(31))
#define TIMG_T1_UPDATE_M (BIT(31))
#define TIMG_T1_UPDATE_V 0x1
#define TIMG_T1_UPDATE_S 31
#define TIMG_T1ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0034)
/* TIMG_T1_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T1_ALARM_LO 0xFFFFFFFF
#define TIMG_T1_ALARM_LO_M ((TIMG_T1_ALARM_LO_V)<<(TIMG_T1_ALARM_LO_S))
#define TIMG_T1_ALARM_LO_V 0xFFFFFFFF
#define TIMG_T1_ALARM_LO_S 0
#define TIMG_T1ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0038)
/* TIMG_T1_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T1_ALARM_HI 0xFFFFFFFF
#define TIMG_T1_ALARM_HI_M ((TIMG_T1_ALARM_HI_V)<<(TIMG_T1_ALARM_HI_S))
#define TIMG_T1_ALARM_HI_V 0xFFFFFFFF
#define TIMG_T1_ALARM_HI_S 0
#define TIMG_T1LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x003c)
/* TIMG_T1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T1_LOAD_LO 0xFFFFFFFF
#define TIMG_T1_LOAD_LO_M ((TIMG_T1_LOAD_LO_V)<<(TIMG_T1_LOAD_LO_S))
#define TIMG_T1_LOAD_LO_V 0xFFFFFFFF
#define TIMG_T1_LOAD_LO_S 0
#define TIMG_T1LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x0040)
/* TIMG_T1_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T1_LOAD_HI 0xFFFFFFFF
#define TIMG_T1_LOAD_HI_M ((TIMG_T1_LOAD_HI_V)<<(TIMG_T1_LOAD_HI_S))
#define TIMG_T1_LOAD_HI_V 0xFFFFFFFF
#define TIMG_T1_LOAD_HI_S 0
#define TIMG_T1LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0044)
/* TIMG_T1_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T1_LOAD 0xFFFFFFFF
#define TIMG_T1_LOAD_M ((TIMG_T1_LOAD_V)<<(TIMG_T1_LOAD_S))
#define TIMG_T1_LOAD_V 0xFFFFFFFF
#define TIMG_T1_LOAD_S 0
#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x0048)
/* TIMG_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_EN (BIT(31))
#define TIMG_WDT_EN_M (BIT(31))
#define TIMG_WDT_EN_V 0x1
#define TIMG_WDT_EN_S 31
/* TIMG_WDT_STG0 : R/W ;bitpos:[30:29] ;default: 1'd0 ; */
/*description: */
#define TIMG_WDT_STG0 0x00000003
#define TIMG_WDT_STG0_M ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S))
#define TIMG_WDT_STG0_V 0x3
#define TIMG_WDT_STG0_S 29
/* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 1'd0 ; */
/*description: */
#define TIMG_WDT_STG1 0x00000003
#define TIMG_WDT_STG1_M ((TIMG_WDT_STG1_V)<<(TIMG_WDT_STG1_S))
#define TIMG_WDT_STG1_V 0x3
#define TIMG_WDT_STG1_S 27
/* TIMG_WDT_STG2 : R/W ;bitpos:[26:25] ;default: 1'd0 ; */
/*description: */
#define TIMG_WDT_STG2 0x00000003
#define TIMG_WDT_STG2_M ((TIMG_WDT_STG2_V)<<(TIMG_WDT_STG2_S))
#define TIMG_WDT_STG2_V 0x3
#define TIMG_WDT_STG2_S 25
/* TIMG_WDT_STG3 : R/W ;bitpos:[24:23] ;default: 1'd0 ; */
/*description: */
#define TIMG_WDT_STG3 0x00000003
#define TIMG_WDT_STG3_M ((TIMG_WDT_STG3_V)<<(TIMG_WDT_STG3_S))
#define TIMG_WDT_STG3_V 0x3
#define TIMG_WDT_STG3_S 23
/* TIMG_WDT_EDGE_INT_EN : R/W ;bitpos:[22] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_EDGE_INT_EN (BIT(22))
#define TIMG_WDT_EDGE_INT_EN_M (BIT(22))
#define TIMG_WDT_EDGE_INT_EN_V 0x1
#define TIMG_WDT_EDGE_INT_EN_S 22
/* TIMG_WDT_LEVEL_INT_EN : R/W ;bitpos:[21] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_LEVEL_INT_EN (BIT(21))
#define TIMG_WDT_LEVEL_INT_EN_M (BIT(21))
#define TIMG_WDT_LEVEL_INT_EN_V 0x1
#define TIMG_WDT_LEVEL_INT_EN_S 21
/* TIMG_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[20:18] ;default: 3'h1 ; */
/*description: */
#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007
#define TIMG_WDT_CPU_RESET_LENGTH_M ((TIMG_WDT_CPU_RESET_LENGTH_V)<<(TIMG_WDT_CPU_RESET_LENGTH_S))
#define TIMG_WDT_CPU_RESET_LENGTH_V 0x7
#define TIMG_WDT_CPU_RESET_LENGTH_S 18
/* TIMG_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[17:15] ;default: 3'h1 ; */
/*description: */
#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007
#define TIMG_WDT_SYS_RESET_LENGTH_M ((TIMG_WDT_SYS_RESET_LENGTH_V)<<(TIMG_WDT_SYS_RESET_LENGTH_S))
#define TIMG_WDT_SYS_RESET_LENGTH_V 0x7
#define TIMG_WDT_SYS_RESET_LENGTH_S 15
/* TIMG_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */
/*description: */
#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14))
#define TIMG_WDT_FLASHBOOT_MOD_EN_M (BIT(14))
#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x1
#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14
/* TIMG_WDT_PROCPU_RESET_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */
/*description: */
#define TIMG_WDT_PROCPU_RESET_EN (BIT(13))
#define TIMG_WDT_PROCPU_RESET_EN_M (BIT(13))
#define TIMG_WDT_PROCPU_RESET_EN_V 0x1
#define TIMG_WDT_PROCPU_RESET_EN_S 13
/* TIMG_WDT_APPCPU_RESET_EN : R/W ;bitpos:[12] ;default: 1'd0 ; */
/*description: */
#define TIMG_WDT_APPCPU_RESET_EN (BIT(12))
#define TIMG_WDT_APPCPU_RESET_EN_M (BIT(12))
#define TIMG_WDT_APPCPU_RESET_EN_V 0x1
#define TIMG_WDT_APPCPU_RESET_EN_S 12
#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x004c)
/* TIMG_WDT_CLK_PRESCALE : R/W ;bitpos:[31:16] ;default: 16'h1 ; */
/*description: */
#define TIMG_WDT_CLK_PRESCALE 0x0000FFFF
#define TIMG_WDT_CLK_PRESCALE_M ((TIMG_WDT_CLK_PRESCALE_V)<<(TIMG_WDT_CLK_PRESCALE_S))
#define TIMG_WDT_CLK_PRESCALE_V 0xFFFF
#define TIMG_WDT_CLK_PRESCALE_S 16
#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x0050)
/* TIMG_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd26000000 ; */
/*description: */
#define TIMG_WDT_STG0_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG0_HOLD_M ((TIMG_WDT_STG0_HOLD_V)<<(TIMG_WDT_STG0_HOLD_S))
#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFF
#define TIMG_WDT_STG0_HOLD_S 0
#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x0054)
/* TIMG_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'h7ffffff ; */
/*description: */
#define TIMG_WDT_STG1_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG1_HOLD_M ((TIMG_WDT_STG1_HOLD_V)<<(TIMG_WDT_STG1_HOLD_S))
#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFF
#define TIMG_WDT_STG1_HOLD_S 0
#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x0058)
/* TIMG_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */
/*description: */
#define TIMG_WDT_STG2_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG2_HOLD_M ((TIMG_WDT_STG2_HOLD_V)<<(TIMG_WDT_STG2_HOLD_S))
#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFF
#define TIMG_WDT_STG2_HOLD_S 0
#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x005c)
/* TIMG_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */
/*description: */
#define TIMG_WDT_STG3_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG3_HOLD_M ((TIMG_WDT_STG3_HOLD_V)<<(TIMG_WDT_STG3_HOLD_S))
#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFF
#define TIMG_WDT_STG3_HOLD_S 0
#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x0060)
/* TIMG_WDT_FEED : WO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_WDT_FEED 0xFFFFFFFF
#define TIMG_WDT_FEED_M ((TIMG_WDT_FEED_V)<<(TIMG_WDT_FEED_S))
#define TIMG_WDT_FEED_V 0xFFFFFFFF
#define TIMG_WDT_FEED_S 0
#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x0064)
/* TIMG_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
/*description: */
#define TIMG_WDT_WKEY 0xFFFFFFFF
#define TIMG_WDT_WKEY_M ((TIMG_WDT_WKEY_V)<<(TIMG_WDT_WKEY_S))
#define TIMG_WDT_WKEY_V 0xFFFFFFFF
#define TIMG_WDT_WKEY_S 0
#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068)
/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_RTC_CALI_START (BIT(31))
#define TIMG_RTC_CALI_START_M (BIT(31))
#define TIMG_RTC_CALI_START_V 0x1
#define TIMG_RTC_CALI_START_S 31
/* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */
/*description: */
#define TIMG_RTC_CALI_MAX 0x00007FFF
#define TIMG_RTC_CALI_MAX_M ((TIMG_RTC_CALI_MAX_V)<<(TIMG_RTC_CALI_MAX_S))
#define TIMG_RTC_CALI_MAX_V 0x7FFF
#define TIMG_RTC_CALI_MAX_S 16
/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */
/*description: */
#define TIMG_RTC_CALI_RDY (BIT(15))
#define TIMG_RTC_CALI_RDY_M (BIT(15))
#define TIMG_RTC_CALI_RDY_V 0x1
#define TIMG_RTC_CALI_RDY_S 15
/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */
/*description: */
#define TIMG_RTC_CALI_CLK_SEL 0x00000003
#define TIMG_RTC_CALI_CLK_SEL_M ((TIMG_RTC_CALI_CLK_SEL_V)<<(TIMG_RTC_CALI_CLK_SEL_S))
#define TIMG_RTC_CALI_CLK_SEL_V 0x3
#define TIMG_RTC_CALI_CLK_SEL_S 13
/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */
/*description: */
#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_M (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_V 0x1
#define TIMG_RTC_CALI_START_CYCLING_S 12
#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c)
/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */
/*description: */
#define TIMG_RTC_CALI_VALUE 0x01FFFFFF
#define TIMG_RTC_CALI_VALUE_M ((TIMG_RTC_CALI_VALUE_V)<<(TIMG_RTC_CALI_VALUE_S))
#define TIMG_RTC_CALI_VALUE_V 0x1FFFFFF
#define TIMG_RTC_CALI_VALUE_S 7
/* TIMG_RTC_CALI_CYCLING_DATA_VLD : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0))
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (BIT(0))
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x1
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0
#define TIMG_LACTCONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0070)
/* TIMG_LACT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_EN (BIT(31))
#define TIMG_LACT_EN_M (BIT(31))
#define TIMG_LACT_EN_V 0x1
#define TIMG_LACT_EN_S 31
/* TIMG_LACT_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
/*description: */
#define TIMG_LACT_INCREASE (BIT(30))
#define TIMG_LACT_INCREASE_M (BIT(30))
#define TIMG_LACT_INCREASE_V 0x1
#define TIMG_LACT_INCREASE_S 30
/* TIMG_LACT_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
/*description: */
#define TIMG_LACT_AUTORELOAD (BIT(29))
#define TIMG_LACT_AUTORELOAD_M (BIT(29))
#define TIMG_LACT_AUTORELOAD_V 0x1
#define TIMG_LACT_AUTORELOAD_S 29
/* TIMG_LACT_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
/*description: */
#define TIMG_LACT_DIVIDER 0x0000FFFF
#define TIMG_LACT_DIVIDER_M ((TIMG_LACT_DIVIDER_V)<<(TIMG_LACT_DIVIDER_S))
#define TIMG_LACT_DIVIDER_V 0xFFFF
#define TIMG_LACT_DIVIDER_S 13
/* TIMG_LACT_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_EDGE_INT_EN (BIT(12))
#define TIMG_LACT_EDGE_INT_EN_M (BIT(12))
#define TIMG_LACT_EDGE_INT_EN_V 0x1
#define TIMG_LACT_EDGE_INT_EN_S 12
/* TIMG_LACT_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_LEVEL_INT_EN (BIT(11))
#define TIMG_LACT_LEVEL_INT_EN_M (BIT(11))
#define TIMG_LACT_LEVEL_INT_EN_V 0x1
#define TIMG_LACT_LEVEL_INT_EN_S 11
/* TIMG_LACT_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_ALARM_EN (BIT(10))
#define TIMG_LACT_ALARM_EN_M (BIT(10))
#define TIMG_LACT_ALARM_EN_V 0x1
#define TIMG_LACT_ALARM_EN_S 10
/* TIMG_LACT_LAC_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */
/*description: */
#define TIMG_LACT_LAC_EN (BIT(9))
#define TIMG_LACT_LAC_EN_M (BIT(9))
#define TIMG_LACT_LAC_EN_V 0x1
#define TIMG_LACT_LAC_EN_S 9
/* TIMG_LACT_CPST_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */
/*description: */
#define TIMG_LACT_CPST_EN (BIT(8))
#define TIMG_LACT_CPST_EN_M (BIT(8))
#define TIMG_LACT_CPST_EN_V 0x1
#define TIMG_LACT_CPST_EN_S 8
/* TIMG_LACT_RTC_ONLY : R/W ;bitpos:[7] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_RTC_ONLY (BIT(7))
#define TIMG_LACT_RTC_ONLY_M (BIT(7))
#define TIMG_LACT_RTC_ONLY_V 0x1
#define TIMG_LACT_RTC_ONLY_S 7
/* TIMG_LACT_USE_REFTICK : R/W ;bitpos:[6] ;default: 1'd0 ; */
/*description: */
#define TIMG_LACT_USE_REFTICK (BIT(6))
#define TIMG_LACT_USE_REFTICK_M (BIT(6))
#define TIMG_LACT_USE_REFTICK_V 0x1
#define TIMG_LACT_USE_REFTICK_S 6
#define TIMG_LACTRTC_REG(i) (REG_TIMG_BASE(i) + 0x0074)
/* TIMG_LACT_RTC_STEP_LEN : R/W ;bitpos:[31:6] ;default: 26'h0 ; */
/*description: */
#define TIMG_LACT_RTC_STEP_LEN 0x03FFFFFF
#define TIMG_LACT_RTC_STEP_LEN_M ((TIMG_LACT_RTC_STEP_LEN_V)<<(TIMG_LACT_RTC_STEP_LEN_S))
#define TIMG_LACT_RTC_STEP_LEN_V 0x3FFFFFF
#define TIMG_LACT_RTC_STEP_LEN_S 6
#define TIMG_LACTLO_REG(i) (REG_TIMG_BASE(i) + 0x0078)
/* TIMG_LACT_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_LO 0xFFFFFFFF
#define TIMG_LACT_LO_M ((TIMG_LACT_LO_V)<<(TIMG_LACT_LO_S))
#define TIMG_LACT_LO_V 0xFFFFFFFF
#define TIMG_LACT_LO_S 0
#define TIMG_LACTHI_REG(i) (REG_TIMG_BASE(i) + 0x007c)
/* TIMG_LACT_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_HI 0xFFFFFFFF
#define TIMG_LACT_HI_M ((TIMG_LACT_HI_V)<<(TIMG_LACT_HI_S))
#define TIMG_LACT_HI_V 0xFFFFFFFF
#define TIMG_LACT_HI_S 0
#define TIMG_LACTUPDATE_REG(i) (REG_TIMG_BASE(i) + 0x0080)
/* TIMG_LACT_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_UPDATE 0xFFFFFFFF
#define TIMG_LACT_UPDATE_M ((TIMG_LACT_UPDATE_V)<<(TIMG_LACT_UPDATE_S))
#define TIMG_LACT_UPDATE_V 0xFFFFFFFF
#define TIMG_LACT_UPDATE_S 0
#define TIMG_LACTALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0084)
/* TIMG_LACT_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_ALARM_LO 0xFFFFFFFF
#define TIMG_LACT_ALARM_LO_M ((TIMG_LACT_ALARM_LO_V)<<(TIMG_LACT_ALARM_LO_S))
#define TIMG_LACT_ALARM_LO_V 0xFFFFFFFF
#define TIMG_LACT_ALARM_LO_S 0
#define TIMG_LACTALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0088)
/* TIMG_LACT_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_ALARM_HI 0xFFFFFFFF
#define TIMG_LACT_ALARM_HI_M ((TIMG_LACT_ALARM_HI_V)<<(TIMG_LACT_ALARM_HI_S))
#define TIMG_LACT_ALARM_HI_V 0xFFFFFFFF
#define TIMG_LACT_ALARM_HI_S 0
#define TIMG_LACTLOADLO_REG(i) (REG_TIMG_BASE(i) + 0x008c)
/* TIMG_LACT_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_LOAD_LO 0xFFFFFFFF
#define TIMG_LACT_LOAD_LO_M ((TIMG_LACT_LOAD_LO_V)<<(TIMG_LACT_LOAD_LO_S))
#define TIMG_LACT_LOAD_LO_V 0xFFFFFFFF
#define TIMG_LACT_LOAD_LO_S 0
#define TIMG_LACTLOADHI_REG(i) (REG_TIMG_BASE(i) + 0x0090)
/* TIMG_LACT_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_LOAD_HI 0xFFFFFFFF
#define TIMG_LACT_LOAD_HI_M ((TIMG_LACT_LOAD_HI_V)<<(TIMG_LACT_LOAD_HI_S))
#define TIMG_LACT_LOAD_HI_V 0xFFFFFFFF
#define TIMG_LACT_LOAD_HI_S 0
#define TIMG_LACTLOAD_REG(i) (REG_TIMG_BASE(i) + 0x0094)
/* TIMG_LACT_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_LACT_LOAD 0xFFFFFFFF
#define TIMG_LACT_LOAD_M ((TIMG_LACT_LOAD_V)<<(TIMG_LACT_LOAD_S))
#define TIMG_LACT_LOAD_V 0xFFFFFFFF
#define TIMG_LACT_LOAD_S 0
#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0098)
/* TIMG_LACT_INT_ENA : R/W ;bitpos:[3] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_INT_ENA (BIT(3))
#define TIMG_LACT_INT_ENA_M (BIT(3))
#define TIMG_LACT_INT_ENA_V 0x1
#define TIMG_LACT_INT_ENA_S 3
/* TIMG_WDT_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_INT_ENA (BIT(2))
#define TIMG_WDT_INT_ENA_M (BIT(2))
#define TIMG_WDT_INT_ENA_V 0x1
#define TIMG_WDT_INT_ENA_S 2
/* TIMG_T1_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */
/*description: */
#define TIMG_T1_INT_ENA (BIT(1))
#define TIMG_T1_INT_ENA_M (BIT(1))
#define TIMG_T1_INT_ENA_V 0x1
#define TIMG_T1_INT_ENA_S 1
/* TIMG_T0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_INT_ENA (BIT(0))
#define TIMG_T0_INT_ENA_M (BIT(0))
#define TIMG_T0_INT_ENA_V 0x1
#define TIMG_T0_INT_ENA_S 0
#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x009c)
/* TIMG_LACT_INT_RAW : RO ;bitpos:[3] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_INT_RAW (BIT(3))
#define TIMG_LACT_INT_RAW_M (BIT(3))
#define TIMG_LACT_INT_RAW_V 0x1
#define TIMG_LACT_INT_RAW_S 3
/* TIMG_WDT_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_INT_RAW (BIT(2))
#define TIMG_WDT_INT_RAW_M (BIT(2))
#define TIMG_WDT_INT_RAW_V 0x1
#define TIMG_WDT_INT_RAW_S 2
/* TIMG_T1_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */
/*description: */
#define TIMG_T1_INT_RAW (BIT(1))
#define TIMG_T1_INT_RAW_M (BIT(1))
#define TIMG_T1_INT_RAW_V 0x1
#define TIMG_T1_INT_RAW_S 1
/* TIMG_T0_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_INT_RAW (BIT(0))
#define TIMG_T0_INT_RAW_M (BIT(0))
#define TIMG_T0_INT_RAW_V 0x1
#define TIMG_T0_INT_RAW_S 0
#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x00a0)
/* TIMG_LACT_INT_ST : RO ;bitpos:[3] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_INT_ST (BIT(3))
#define TIMG_LACT_INT_ST_M (BIT(3))
#define TIMG_LACT_INT_ST_V 0x1
#define TIMG_LACT_INT_ST_S 3
/* TIMG_WDT_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_INT_ST (BIT(2))
#define TIMG_WDT_INT_ST_M (BIT(2))
#define TIMG_WDT_INT_ST_V 0x1
#define TIMG_WDT_INT_ST_S 2
/* TIMG_T1_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */
/*description: */
#define TIMG_T1_INT_ST (BIT(1))
#define TIMG_T1_INT_ST_M (BIT(1))
#define TIMG_T1_INT_ST_V 0x1
#define TIMG_T1_INT_ST_S 1
/* TIMG_T0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_INT_ST (BIT(0))
#define TIMG_T0_INT_ST_M (BIT(0))
#define TIMG_T0_INT_ST_V 0x1
#define TIMG_T0_INT_ST_S 0
#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x00a4)
/* TIMG_LACT_INT_CLR : WO ;bitpos:[3] ;default: 1'h0 ; */
/*description: */
#define TIMG_LACT_INT_CLR (BIT(3))
#define TIMG_LACT_INT_CLR_M (BIT(3))
#define TIMG_LACT_INT_CLR_V 0x1
#define TIMG_LACT_INT_CLR_S 3
/* TIMG_WDT_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_INT_CLR (BIT(2))
#define TIMG_WDT_INT_CLR_M (BIT(2))
#define TIMG_WDT_INT_CLR_V 0x1
#define TIMG_WDT_INT_CLR_S 2
/* TIMG_T1_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */
/*description: */
#define TIMG_T1_INT_CLR (BIT(1))
#define TIMG_T1_INT_CLR_M (BIT(1))
#define TIMG_T1_INT_CLR_V 0x1
#define TIMG_T1_INT_CLR_S 1
/* TIMG_T0_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_INT_CLR (BIT(0))
#define TIMG_T0_INT_CLR_M (BIT(0))
#define TIMG_T0_INT_CLR_V 0x1
#define TIMG_T0_INT_CLR_S 0
#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x00a8)
/* TIMG_RTC_CALI_TIMEOUT_THRES : R/W ;bitpos:[31:7] ;default: 25'h1ffffff ; */
/*description: timeout if cali value counts over threshold*/
#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFF
#define TIMG_RTC_CALI_TIMEOUT_THRES_M ((TIMG_RTC_CALI_TIMEOUT_THRES_V)<<(TIMG_RTC_CALI_TIMEOUT_THRES_S))
#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x1FFFFFF
#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7
/* TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W ;bitpos:[6:3] ;default: 4'd3 ; */
/*description: Cycles that release calibration timeout reset*/
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000F
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M ((TIMG_RTC_CALI_TIMEOUT_RST_CNT_V)<<(TIMG_RTC_CALI_TIMEOUT_RST_CNT_S))
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0xF
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3
/* TIMG_RTC_CALI_TIMEOUT : RO ;bitpos:[0] ;default: 1'h0 ; */
/*description: timeout indicator*/
#define TIMG_RTC_CALI_TIMEOUT (BIT(0))
#define TIMG_RTC_CALI_TIMEOUT_M (BIT(0))
#define TIMG_RTC_CALI_TIMEOUT_V 0x1
#define TIMG_RTC_CALI_TIMEOUT_S 0
#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0x00f8)
/* TIMG_NTIMERS_DATE : R/W ;bitpos:[27:0] ;default: 28'h1810190 ; */
/*description: */
#define TIMG_NTIMERS_DATE 0x0FFFFFFF
#define TIMG_NTIMERS_DATE_M ((TIMG_NTIMERS_DATE_V)<<(TIMG_NTIMERS_DATE_S))
#define TIMG_NTIMERS_DATE_V 0xFFFFFFF
#define TIMG_NTIMERS_DATE_S 0
#define TIMG_CLK_REG(i) (REG_TIMG_BASE(i) + 0x00fc)
/* TIMG_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_CLK_EN (BIT(31))
#define TIMG_CLK_EN_M (BIT(31))
#define TIMG_CLK_EN_V 0x1
#define TIMG_CLK_EN_S 31
#ifdef __cplusplus
}
#endif
#endif /*_SOC_TIMG_REG_H_ */

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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_TIMG_STRUCT_H_
#define _SOC_TIMG_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
struct {
union {
struct {
uint32_t reserved0: 9;
uint32_t use_xtal: 1;
uint32_t alarm_en: 1;
uint32_t level_int_en: 1;
uint32_t edge_int_en: 1;
uint32_t divider: 16;
uint32_t autoreload: 1;
uint32_t increase: 1;
uint32_t enable: 1;
};
uint32_t val;
} config;
uint32_t cnt_low; /**/
uint32_t cnt_high; /**/
union {
struct {
uint32_t reserved0: 31;
uint32_t update: 1;
};
uint32_t val;
} update;
uint32_t alarm_low; /**/
uint32_t alarm_high; /**/
uint32_t load_low; /**/
uint32_t load_high; /**/
uint32_t reload; /**/
} hw_timer[2];
union {
struct {
uint32_t reserved0: 12;
uint32_t appcpu_reset_en: 1;
uint32_t procpu_reset_en: 1;
uint32_t flashboot_mod_en: 1;
uint32_t sys_reset_length: 3;
uint32_t cpu_reset_length: 3;
uint32_t level_int_en: 1;
uint32_t edge_int_en: 1;
uint32_t stg3: 2;
uint32_t stg2: 2;
uint32_t stg1: 2;
uint32_t stg0: 2;
uint32_t en: 1;
};
uint32_t val;
} wdt_config0;
union {
struct {
uint32_t reserved0: 16;
uint32_t clk_prescale: 16;
};
uint32_t val;
} wdt_config1;
uint32_t wdt_config2; /**/
uint32_t wdt_config3; /**/
uint32_t wdt_config4; /**/
uint32_t wdt_config5; /**/
uint32_t wdt_feed; /**/
uint32_t wdt_wprotect; /**/
union {
struct {
uint32_t reserved0: 12;
uint32_t start_cycling: 1;
uint32_t clk_sel: 2;
uint32_t rdy: 1;
uint32_t max: 15;
uint32_t start: 1;
};
uint32_t val;
} rtc_cali_cfg;
union {
struct {
uint32_t reserved0: 7;
uint32_t value: 25;
};
uint32_t val;
} rtc_cali_cfg1;
union {
struct {
uint32_t reserved0: 6;
uint32_t use_reftick: 1;
uint32_t rtc_only: 1;
uint32_t cpst_en: 1;
uint32_t lac_en: 1;
uint32_t alarm_en: 1;
uint32_t level_int_en: 1;
uint32_t edge_int_en: 1;
uint32_t divider: 16;
uint32_t autoreload: 1;
uint32_t increase: 1;
uint32_t en: 1;
};
uint32_t val;
} lactconfig;
union {
struct {
uint32_t reserved0: 6;
uint32_t step_len: 26;
};
uint32_t val;
} lactrtc;
uint32_t lactlo; /**/
uint32_t lacthi; /**/
uint32_t lactupdate; /**/
uint32_t lactalarmlo; /**/
uint32_t lactalarmhi; /**/
uint32_t lactloadlo; /**/
uint32_t lactloadhi; /**/
uint32_t lactload; /**/
union {
struct {
uint32_t t0: 1;
uint32_t t1: 1;
uint32_t wdt: 1;
uint32_t lact: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t t0: 1;
uint32_t t1: 1;
uint32_t wdt: 1;
uint32_t lact: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t t0: 1;
uint32_t t1: 1;
uint32_t wdt: 1;
uint32_t lact: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t t0: 1;
uint32_t t1: 1;
uint32_t wdt: 1;
uint32_t lact: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t timeout: 1; /*timeout indicator*/
uint32_t reserved1: 2;
uint32_t timeout_rst_cnt: 4; /*Cycles that release calibration timeout reset*/
uint32_t timeout_thres: 25; /*timeout if cali value counts over threshold*/
};
uint32_t val;
} rtc_cali_cfg2;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
union {
struct {
uint32_t date: 28;
uint32_t reserved28: 4;
};
uint32_t val;
} timg_date;
union {
struct {
uint32_t reserved0: 31;
uint32_t en: 1;
};
uint32_t val;
} clk;
} timg_dev_t;
extern timg_dev_t TIMERG0;
extern timg_dev_t TIMERG1;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_TIMG_STRUCT_H_ */

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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_TOUCH_CHANNEL_H
#define _SOC_TOUCH_CHANNEL_H
//Touch channels
#define TOUCH_PAD_GPIO4_CHANNEL TOUCH_PAD_NUM0
#define TOUCH_PAD_NUM0_GPIO_NUM 4
#define TOUCH_PAD_GPIO0_CHANNEL TOUCH_PAD_NUM1
#define TOUCH_PAD_NUM1_GPIO_NUM 0
#define TOUCH_PAD_GPIO2_CHANNEL TOUCH_PAD_NUM2
#define TOUCH_PAD_NUM2_GPIO_NUM 2
#define TOUCH_PAD_GPIO15_CHANNEL TOUCH_PAD_NUM3
#define TOUCH_PAD_NUM3_GPIO_NUM 15
#define TOUCH_PAD_GPIO13_CHANNEL TOUCH_PAD_NUM4
#define TOUCH_PAD_NUM4_GPIO_NUM 13
#define TOUCH_PAD_GPIO12_CHANNEL TOUCH_PAD_NUM5
#define TOUCH_PAD_NUM5_GPIO_NUM 12
#define TOUCH_PAD_GPIO14_CHANNEL TOUCH_PAD_NUM6
#define TOUCH_PAD_NUM6_GPIO_NUM 14
#define TOUCH_PAD_GPIO27_CHANNEL TOUCH_PAD_NUM7
#define TOUCH_PAD_NUM7_GPIO_NUM 27
#define TOUCH_PAD_GPIO33_CHANNEL TOUCH_PAD_NUM8
#define TOUCH_PAD_NUM8_GPIO_NUM 33
#define TOUCH_PAD_GPIO32_CHANNEL TOUCH_PAD_NUM9
#define TOUCH_PAD_NUM9_GPIO_NUM 32
#endif

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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_UART_CHANNEL_H
#define _SOC_UART_CHANNEL_H
//UART channels
#define UART_GPIO1_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 1
#define UART_GPIO3_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 3
#define UART_GPIO19_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_CTS_DIRECT_GPIO_NUM 19
#define UART_GPIO22_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RTS_DIRECT_GPIO_NUM 22
#define UART_TXD_GPIO1_DIRECT_CHANNEL UART_GPIO1_DIRECT_CHANNEL
#define UART_RXD_GPIO3_DIRECT_CHANNEL UART_GPIO3_DIRECT_CHANNEL
#define UART_CTS_GPIO19_DIRECT_CHANNEL UART_GPIO19_DIRECT_CHANNEL
#define UART_RTS_GPIO22_DIRECT_CHANNEL UART_GPIO22_DIRECT_CHANNEL
#define UART_GPIO10_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_TXD_DIRECT_GPIO_NUM 10
#define UART_GPIO9_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_RXD_DIRECT_GPIO_NUM 9
#define UART_GPIO6_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_CTS_DIRECT_GPIO_NUM 6
#define UART_GPIO11_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_RTS_DIRECT_GPIO_NUM 11
#define UART_TXD_GPIO10_DIRECT_CHANNEL UART_GPIO10_DIRECT_CHANNEL
#define UART_RXD_GPIO9_DIRECT_CHANNEL UART_GPIO9_DIRECT_CHANNEL
#define UART_CTS_GPIO6_DIRECT_CHANNEL UART_GPIO6_DIRECT_CHANNEL
#define UART_RTS_GPIO11_DIRECT_CHANNEL UART_GPIO11_DIRECT_CHANNEL
#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_TXD_DIRECT_GPIO_NUM 17
#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_RXD_DIRECT_GPIO_NUM 16
#define UART_GPIO8_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_CTS_DIRECT_GPIO_NUM 8
#define UART_GPIO7_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_RTS_DIRECT_GPIO_NUM 7
#define UART_TXD_GPIO17_DIRECT_CHANNEL UART_GPIO17_DIRECT_CHANNEL
#define UART_RXD_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL
#define UART_CTS_GPIO8_DIRECT_CHANNEL UART_GPIO8_DIRECT_CHANNEL
#define UART_RTS_GPIO7_DIRECT_CHANNEL UART_GPIO7_DIRECT_CHANNEL
#endif

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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_UART_STRUCT_H_
#define _SOC_UART_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint8_t rw_byte; /*This register stores one byte data read by rx fifo.*/
uint8_t reserved[3];
};
uint32_t val;
} ahb_fifo;
union {
struct {
uint32_t rxfifo_full: 1; /*This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/
uint32_t txfifo_empty: 1; /*This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/
uint32_t parity_err: 1; /*This interrupt raw bit turns to high level when receiver detects the parity error of data.*/
uint32_t frm_err: 1; /*This interrupt raw bit turns to high level when receiver detects data's frame error .*/
uint32_t rxfifo_ovf: 1; /*This interrupt raw bit turns to high level when receiver receives more data than the fifo can store.*/
uint32_t dsr_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal.*/
uint32_t cts_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal.*/
uint32_t brk_det: 1; /*This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit.*/
uint32_t rxfifo_tout: 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/
uint32_t sw_xon: 1; /*This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1.*/
uint32_t sw_xoff: 1; /*This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1.*/
uint32_t glitch_det: 1; /*This interrupt raw bit turns to high level when receiver detects the start bit.*/
uint32_t tx_brk_done: 1; /*This interrupt raw bit turns to high level when transmitter completes sending 0 after all the data in transmitter's fifo are send.*/
uint32_t tx_brk_idle_done: 1; /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the last data has been send.*/
uint32_t tx_done: 1; /*This interrupt raw bit turns to high level when transmitter has send all the data in fifo.*/
uint32_t rs485_parity_err: 1; /*This interrupt raw bit turns to high level when rs485 detects the parity error.*/
uint32_t rs485_frm_err: 1; /*This interrupt raw bit turns to high level when rs485 detects the data frame error.*/
uint32_t rs485_clash: 1; /*This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver.*/
uint32_t at_cmd_char_det: 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars.*/
uint32_t reserved19: 13;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t rxfifo_full: 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/
uint32_t txfifo_empty: 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.*/
uint32_t parity_err: 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/
uint32_t frm_err: 1; /*This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/
uint32_t rxfifo_ovf: 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/
uint32_t dsr_chg: 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
uint32_t cts_chg: 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/
uint32_t brk_det: 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
uint32_t rxfifo_tout: 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/
uint32_t sw_xon: 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/
uint32_t sw_xoff: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
uint32_t glitch_det: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/
uint32_t tx_brk_done: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/
uint32_t tx_brk_idle_done: 1; /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/
uint32_t tx_done: 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
uint32_t rs485_parity_err: 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/
uint32_t rs485_frm_err: 1; /*This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/
uint32_t rs485_clash: 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/
uint32_t at_cmd_char_det: 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/
uint32_t reserved19: 13;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t rxfifo_full: 1; /*This is the enable bit for rxfifo_full_int_st register.*/
uint32_t txfifo_empty: 1; /*This is the enable bit for rxfifo_full_int_st register.*/
uint32_t parity_err: 1; /*This is the enable bit for parity_err_int_st register.*/
uint32_t frm_err: 1; /*This is the enable bit for frm_err_int_st register.*/
uint32_t rxfifo_ovf: 1; /*This is the enable bit for rxfifo_ovf_int_st register.*/
uint32_t dsr_chg: 1; /*This is the enable bit for dsr_chg_int_st register.*/
uint32_t cts_chg: 1; /*This is the enable bit for cts_chg_int_st register.*/
uint32_t brk_det: 1; /*This is the enable bit for brk_det_int_st register.*/
uint32_t rxfifo_tout: 1; /*This is the enable bit for rxfifo_tout_int_st register.*/
uint32_t sw_xon: 1; /*This is the enable bit for sw_xon_int_st register.*/
uint32_t sw_xoff: 1; /*This is the enable bit for sw_xoff_int_st register.*/
uint32_t glitch_det: 1; /*This is the enable bit for glitch_det_int_st register.*/
uint32_t tx_brk_done: 1; /*This is the enable bit for tx_brk_done_int_st register.*/
uint32_t tx_brk_idle_done: 1; /*This is the enable bit for tx_brk_idle_done_int_st register.*/
uint32_t tx_done: 1; /*This is the enable bit for tx_done_int_st register.*/
uint32_t rs485_parity_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/
uint32_t rs485_frm_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/
uint32_t rs485_clash: 1; /*This is the enable bit for rs485_clash_int_st register.*/
uint32_t at_cmd_char_det: 1; /*This is the enable bit for at_cmd_char_det_int_st register.*/
uint32_t reserved19: 13;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t rxfifo_full: 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/
uint32_t txfifo_empty: 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/
uint32_t parity_err: 1; /*Set this bit to clear parity_err_int_raw interrupt.*/
uint32_t frm_err: 1; /*Set this bit to clear frm_err_int_raw interrupt.*/
uint32_t rxfifo_ovf: 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
uint32_t dsr_chg: 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/
uint32_t cts_chg: 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/
uint32_t brk_det: 1; /*Set this bit to clear the brk_det_int_raw interrupt.*/
uint32_t rxfifo_tout: 1; /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
uint32_t sw_xon: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/
uint32_t sw_xoff: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/
uint32_t glitch_det: 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/
uint32_t tx_brk_done: 1; /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/
uint32_t tx_brk_idle_done: 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
uint32_t tx_done: 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/
uint32_t rs485_parity_err: 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
uint32_t rs485_frm_err: 1; /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
uint32_t rs485_clash: 1; /*Set this bit to clear the rs485_clash_int_raw interrupt.*/
uint32_t at_cmd_char_det: 1; /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
uint32_t reserved19: 13;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t div_int: 20; /*The register value is the integer part of the frequency divider's factor.*/
uint32_t div_frag: 4; /*The register value is the decimal part of the frequency divider's factor.*/
uint32_t reserved24: 8;
};
uint32_t val;
} clk_div;
union {
struct {
uint32_t en: 1; /*This is the enable bit for detecting baudrate.*/
uint32_t reserved1: 7;
uint32_t glitch_filt: 8; /*when input pulse width is lower then this value ignore this pulse.this register is used in auto-baud detect process.*/
uint32_t reserved16: 16;
};
uint32_t val;
} auto_baud;
union {
struct {
uint32_t rxfifo_cnt: 8; /*(rx_mem_cnt rxfifo_cnt) stores the byte number of valid data in receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/
uint32_t st_urx_out: 4; /*This register stores the value of receiver's finite state machine. 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/
uint32_t reserved12: 1;
uint32_t dsrn: 1; /*This register stores the level value of the internal uart dsr signal.*/
uint32_t ctsn: 1; /*This register stores the level value of the internal uart cts signal.*/
uint32_t rxd: 1; /*This register stores the level value of the internal uart rxd signal.*/
uint32_t txfifo_cnt: 8; /*(tx_mem_cnt txfifo_cnt) stores the byte number of valid data in transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/
uint32_t st_utx_out: 4; /*This register stores the value of transmitter's finite state machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1*/
uint32_t reserved28: 1;
uint32_t dtrn: 1; /*The register represent the level value of the internal uart dsr signal.*/
uint32_t rtsn: 1; /*This register represent the level value of the internal uart cts signal.*/
uint32_t txd: 1; /*This register represent the level value of the internal uart rxd signal.*/
};
uint32_t val;
} status;
union {
struct {
uint32_t parity: 1; /*This register is used to configure the parity check mode. 0:even 1:odd*/
uint32_t parity_en: 1; /*Set this bit to enable uart parity check.*/
uint32_t bit_num: 2; /*This register is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/
uint32_t stop_bit_num: 2; /*This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/
uint32_t sw_rts: 1; /*This register is used to configure the software rts signal which is used in software flow control.*/
uint32_t sw_dtr: 1; /*This register is used to configure the software dtr signal which is used in software flow control..*/
uint32_t txd_brk: 1; /*Set this bit to enable transmitter to send 0 when the process of sending data is done.*/
uint32_t irda_dplx: 1; /*Set this bit to enable irda loop-back mode.*/
uint32_t irda_tx_en: 1; /*This is the start enable bit for irda transmitter.*/
uint32_t irda_wctl: 1; /*1：the irda transmitter's 11th bit is the same to the 10th bit. 0：set irda transmitter's 11th bit to 0.*/
uint32_t irda_tx_inv: 1; /*Set this bit to inverse the level value of irda transmitter's level.*/
uint32_t irda_rx_inv: 1; /*Set this bit to inverse the level value of irda receiver's level.*/
uint32_t loopback: 1; /*Set this bit to enable uart loop-back test mode.*/
uint32_t tx_flow_en: 1; /*Set this bit to enable transmitter's flow control function.*/
uint32_t irda_en: 1; /*Set this bit to enable irda protocol.*/
uint32_t rxfifo_rst: 1; /*Set this bit to reset uart receiver's fifo.*/
uint32_t txfifo_rst: 1; /*Set this bit to reset uart transmitter's fifo.*/
uint32_t rxd_inv: 1; /*Set this bit to inverse the level value of uart rxd signal.*/
uint32_t cts_inv: 1; /*Set this bit to inverse the level value of uart cts signal.*/
uint32_t dsr_inv: 1; /*Set this bit to inverse the level value of uart dsr signal.*/
uint32_t txd_inv: 1; /*Set this bit to inverse the level value of uart txd signal.*/
uint32_t rts_inv: 1; /*Set this bit to inverse the level value of uart rts signal.*/
uint32_t dtr_inv: 1; /*Set this bit to inverse the level value of uart dtr signal.*/
uint32_t clk_en: 1; /*1：force clock on for registers：support clock only when write registers*/
uint32_t err_wr_mask: 1; /*1：receiver stops storing data int fifo when data is wrong. 0：receiver stores the data even if the received data is wrong.*/
uint32_t tick_ref_always_on: 1; /*This register is used to select the clock.1：apb clock：ref_tick*/
uint32_t reserved28: 4;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t rxfifo_full_thrhd: 7;
uint32_t reserved7: 1;
uint32_t txfifo_empty_thrhd: 7;
uint32_t rx_tout_flow_dis: 1;
uint32_t rx_flow_thrhd: 7;
uint32_t rx_flow_en: 1;
uint32_t rx_tout_thrhd: 7;
uint32_t rx_tout_en: 1;
};
uint32_t val;
} conf1;
union {
struct {
uint32_t min_cnt: 20; /*This register stores the value of the minimum duration time for the low level pulse， it is used in baudrate-detect process.*/
uint32_t reserved20: 12;
};
uint32_t val;
} lowpulse;
union {
struct {
uint32_t min_cnt: 20; /*This register stores the value of the maximum duration time for the high level pulse， it is used in baudrate-detect process.*/
uint32_t reserved20: 12;
};
uint32_t val;
} highpulse;
union {
struct {
uint32_t edge_cnt: 10; /*This register stores the count of rxd edge change， it is used in baudrate-detect process.*/
uint32_t reserved10: 22;
};
uint32_t val;
} rxd_cnt;
union {
struct {
uint32_t sw_flow_con_en: 1; /*Set this bit to enable software flow control. it is used with register sw_xon or sw_xoff .*/
uint32_t xonoff_del: 1; /*Set this bit to remove flow control char from the received data.*/
uint32_t force_xon: 1; /*Set this bit to clear ctsn to stop the transmitter from sending data.*/
uint32_t force_xoff: 1; /*Set this bit to set ctsn to enable the transmitter to go on sending data.*/
uint32_t send_xon: 1; /*Set this bit to send xon char， it is cleared by hardware automatically.*/
uint32_t send_xoff: 1; /*Set this bit to send xoff char， it is cleared by hardware automatically.*/
uint32_t reserved6: 26;
};
uint32_t val;
} flow_conf;
union {
struct {
uint32_t active_threshold:10; /*When the input rxd edge changes more than this register value， the uart is active from light sleeping mode.*/
uint32_t reserved10: 22;
};
uint32_t val;
} sleep_conf;
union {
struct {
uint32_t xon_threshold: 8; /*when the data amount in receiver's fifo is more than this register value， it will send a xoff char with uart_sw_flow_con_en set to 1.*/
uint32_t xoff_threshold: 8; /*When the data amount in receiver's fifo is less than this register value， it will send a xon char with uart_sw_flow_con_en set to 1.*/
uint32_t xon_char: 8; /*This register stores the xon flow control char.*/
uint32_t xoff_char: 8; /*This register stores the xoff flow control char.*/
};
uint32_t val;
} swfc_conf;
union {
struct {
uint32_t rx_idle_thrhd:10; /*when receiver takes more time than this register value to receive a byte data， it will produce frame end signal for uhci to stop receiving data.*/
uint32_t tx_idle_num: 10; /*This register is used to configure the duration time between transfers.*/
uint32_t tx_brk_num: 8; /*This register is used to configure the number of 0 send after the process of sending data is done. it is active when txd_brk is set to 1.*/
uint32_t reserved28: 4;
};
uint32_t val;
} idle_conf;
union {
struct {
uint32_t en: 1; /*Set this bit to choose rs485 mode.*/
uint32_t dl0_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/
uint32_t dl1_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/
uint32_t tx_rx_en: 1; /*Set this bit to enable loop-back transmitter's output data signal to receiver's input data signal.*/
uint32_t rx_busy_tx_en: 1; /*1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/
uint32_t rx_dly_num: 1; /*This register is used to delay the receiver's internal data signal.*/
uint32_t tx_dly_num: 4; /*This register is used to delay the transmitter's internal data signal.*/
uint32_t reserved10: 22;
};
uint32_t val;
} rs485_conf;
union {
struct {
uint32_t pre_idle_num:24; /*This register is used to configure the idle duration time before the first at_cmd is received by receiver， when the the duration is less than this register value it will not take the next data received as at_cmd char.*/
uint32_t reserved24: 8;
};
uint32_t val;
} at_cmd_precnt;
union {
struct {
uint32_t post_idle_num:24; /*This register is used to configure the duration time between the last at_cmd and the next data， when the duration is less than this register value it will not take the previous data as at_cmd char.*/
uint32_t reserved24: 8;
};
uint32_t val;
} at_cmd_postcnt;
union {
struct {
uint32_t rx_gap_tout:24; /*This register is used to configure the duration time between the at_cmd chars， when the duration time is less than this register value it will not take the data as continous at_cmd chars.*/
uint32_t reserved24: 8;
};
uint32_t val;
} at_cmd_gaptout;
union {
struct {
uint32_t data: 8; /*This register is used to configure the content of at_cmd char.*/
uint32_t char_num: 8; /*This register is used to configure the number of continuous at_cmd chars received by receiver.*/
uint32_t reserved16: 16;
};
uint32_t val;
} at_cmd_char;
union {
struct {
uint32_t mem_pd: 1; /*Set this bit to power down memory，when reg_mem_pd registers in the 3 uarts are all set to 1 memory will enter low power mode.*/
uint32_t reserved1: 1;
uint32_t reserved2: 1;
uint32_t rx_size: 4; /*This register is used to configure the amount of mem allocated to receiver's fifo. the default byte num is 128.*/
uint32_t tx_size: 4; /*This register is used to configure the amount of mem allocated to transmitter's fifo.the default byte num is 128.*/
uint32_t reserved11: 4;
uint32_t rx_flow_thrhd_h3: 3; /*refer to the rx_flow_thrhd's description.*/
uint32_t rx_tout_thrhd_h3: 3; /*refer to the rx_tout_thrhd's description.*/
uint32_t xon_threshold_h2: 2; /*refer to the uart_xon_threshold's description.*/
uint32_t xoff_threshold_h2: 2; /*refer to the uart_xoff_threshold's description.*/
uint32_t rx_mem_full_thrhd: 3; /*refer to the rxfifo_full_thrhd's description.*/
uint32_t tx_mem_empty_thrhd: 3; /*refer to txfifo_empty_thrhd 's description.*/
uint32_t reserved31: 1;
};
uint32_t val;
} mem_conf;
union {
struct {
uint32_t apb_tx_waddr:11;
uint32_t tx_raddr: 11;
uint32_t reserved22: 10;
};
uint32_t val;
} mem_tx_status;
union {
struct {
uint32_t apb_rx_raddr:11;
uint32_t rx_waddr: 11;
uint32_t reserved22: 10;
};
uint32_t val;
} mem_rx_status;
union {
struct {
uint32_t rx_cnt: 3; /*refer to the rxfifo_cnt's description.*/
uint32_t tx_cnt: 3; /*refer to the txfifo_cnt's description.*/
uint32_t reserved6: 26;
};
uint32_t val;
} mem_cnt_status;
union {
struct {
uint32_t min_cnt: 20; /*This register stores the count of rxd pos-edge edge， it is used in baudrate-detect process.*/
uint32_t reserved20: 12;
};
uint32_t val;
} pospulse;
union {
struct {
uint32_t min_cnt: 20; /*This register stores the count of rxd neg-edge edge， it is used in baudrate-detect process.*/
uint32_t reserved20: 12;
};
uint32_t val;
} negpulse;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t date; /**/
uint32_t id; /**/
} uart_dev_t;
extern uart_dev_t UART0;
extern uart_dev_t UART1;
extern uart_dev_t UART2;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_UART_STRUCT_H_ */

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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_UHCI_STRUCT_H_
#define _SOC_UHCI_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t in_rst: 1;
uint32_t out_rst: 1;
uint32_t ahbm_fifo_rst: 1;
uint32_t ahbm_rst: 1;
uint32_t in_loop_test: 1;
uint32_t out_loop_test: 1;
uint32_t out_auto_wrback: 1;
uint32_t out_no_restart_clr: 1;
uint32_t out_eof_mode: 1;
uint32_t uart0_ce: 1;
uint32_t uart1_ce: 1;
uint32_t reserved11: 1;
uint32_t outdscr_burst_en: 1;
uint32_t indscr_burst_en: 1;
uint32_t out_data_burst_en: 1;
uint32_t mem_trans_en: 1;
uint32_t seper_en: 1;
uint32_t head_en: 1;
uint32_t crc_rec_en: 1;
uint32_t uart_idle_eof_en: 1;
uint32_t len_eof_en: 1;
uint32_t encode_crc_en: 1;
uint32_t clk_en: 1;
uint32_t uart_rx_brk_eof_en: 1;
uint32_t reserved24: 8;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_hung: 1;
uint32_t tx_hung: 1;
uint32_t in_done: 1;
uint32_t in_suc_eof: 1;
uint32_t in_err_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t in_dscr_err: 1;
uint32_t out_dscr_err: 1;
uint32_t in_dscr_empty: 1;
uint32_t outlink_eof_err: 1;
uint32_t out_total_eof: 1;
uint32_t send_s_q: 1;
uint32_t send_a_q: 1;
uint32_t dma_in_fifo_full_wm: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_hung: 1;
uint32_t tx_hung: 1;
uint32_t in_done: 1;
uint32_t in_suc_eof: 1;
uint32_t in_err_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t in_dscr_err: 1;
uint32_t out_dscr_err: 1;
uint32_t in_dscr_empty: 1;
uint32_t outlink_eof_err: 1;
uint32_t out_total_eof: 1;
uint32_t send_s_q: 1;
uint32_t send_a_q: 1;
uint32_t dma_in_fifo_full_wm: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_hung: 1;
uint32_t tx_hung: 1;
uint32_t in_done: 1;
uint32_t in_suc_eof: 1;
uint32_t in_err_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t in_dscr_err: 1;
uint32_t out_dscr_err: 1;
uint32_t in_dscr_empty: 1;
uint32_t outlink_eof_err: 1;
uint32_t out_total_eof: 1;
uint32_t send_s_q: 1;
uint32_t send_a_q: 1;
uint32_t dma_in_fifo_full_wm: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_hung: 1;
uint32_t tx_hung: 1;
uint32_t in_done: 1;
uint32_t in_suc_eof: 1;
uint32_t in_err_eof: 1;
uint32_t out_done: 1;
uint32_t out_eof: 1;
uint32_t in_dscr_err: 1;
uint32_t out_dscr_err: 1;
uint32_t in_dscr_empty: 1;
uint32_t outlink_eof_err: 1;
uint32_t out_total_eof: 1;
uint32_t send_s_q: 1;
uint32_t send_a_q: 1;
uint32_t dma_in_fifo_full_wm: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t full: 1;
uint32_t empty: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} dma_out_status;
union {
struct {
uint32_t fifo_wdata: 9;
uint32_t reserved9: 7;
uint32_t fifo_push: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} dma_out_push;
union {
struct {
uint32_t full: 1;
uint32_t empty: 1;
uint32_t reserved2: 2;
uint32_t rx_err_cause: 3;
uint32_t reserved7: 25;
};
uint32_t val;
} dma_in_status;
union {
struct {
uint32_t fifo_rdata: 12;
uint32_t reserved12: 4;
uint32_t fifo_pop: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} dma_in_pop;
union {
struct {
uint32_t addr: 20;
uint32_t reserved20: 8;
uint32_t stop: 1;
uint32_t start: 1;
uint32_t restart: 1;
uint32_t park: 1;
};
uint32_t val;
} dma_out_link;
union {
struct {
uint32_t addr: 20;
uint32_t auto_ret: 1;
uint32_t reserved21: 7;
uint32_t stop: 1;
uint32_t start: 1;
uint32_t restart: 1;
uint32_t park: 1;
};
uint32_t val;
} dma_in_link;
union {
struct {
uint32_t check_sum_en: 1;
uint32_t check_seq_en: 1;
uint32_t crc_disable: 1;
uint32_t save_head: 1;
uint32_t tx_check_sum_re: 1;
uint32_t tx_ack_num_re: 1;
uint32_t check_owner: 1;
uint32_t wait_sw_start: 1;
uint32_t sw_start: 1;
uint32_t dma_in_fifo_full_thrs:12;
uint32_t reserved21: 11;
};
uint32_t val;
} conf1;
union {
struct {
uint32_t dscr_addr: 18;
uint32_t in_dscr_state: 2;
uint32_t in_state: 3;
uint32_t fifo_cnt_debug: 5;
uint32_t decode_state: 3;
uint32_t reserved31: 1;
};
uint32_t val;
} state0;
union {
struct {
uint32_t outlink_dscr_addr:18;
uint32_t out_dscr_state: 2;
uint32_t out_state: 3;
uint32_t fifo_cnt: 5;
uint32_t encode_state: 3;
uint32_t reserved31: 1;
};
uint32_t val;
} state1;
uint32_t dma_out_eof_des_addr; /**/
uint32_t dma_in_suc_eof_des_addr; /**/
uint32_t dma_in_err_eof_des_addr; /**/
uint32_t dma_out_eof_bfr_des_addr; /**/
union {
struct {
uint32_t test_mode: 3;
uint32_t reserved3: 1;
uint32_t test_addr: 2;
uint32_t reserved6: 26;
};
uint32_t val;
} ahb_test;
uint32_t dma_in_dscr; /**/
uint32_t dma_in_dscr_bf0; /**/
uint32_t dma_in_dscr_bf1; /**/
uint32_t dma_out_dscr; /**/
uint32_t dma_out_dscr_bf0; /**/
uint32_t dma_out_dscr_bf1; /**/
union {
struct {
uint32_t tx_c0_esc_en: 1;
uint32_t tx_db_esc_en: 1;
uint32_t tx_11_esc_en: 1;
uint32_t tx_13_esc_en: 1;
uint32_t rx_c0_esc_en: 1;
uint32_t rx_db_esc_en: 1;
uint32_t rx_11_esc_en: 1;
uint32_t rx_13_esc_en: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} escape_conf;
union {
struct {
uint32_t txfifo_timeout: 8;
uint32_t txfifo_timeout_shift: 3;
uint32_t txfifo_timeout_ena: 1;
uint32_t rxfifo_timeout: 8;
uint32_t rxfifo_timeout_shift: 3;
uint32_t rxfifo_timeout_ena: 1;
uint32_t reserved24: 8;
};
uint32_t val;
} hung_conf;
uint32_t ack_num; /**/
uint32_t rx_head; /**/
union {
struct {
uint32_t single_send_num: 3;
uint32_t single_send_en: 1;
uint32_t always_send_num: 3;
uint32_t always_send_en: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} quick_sent;
struct {
uint32_t w_data[2]; /**/
} q_data[7];
union {
struct {
uint32_t seper_char: 8;
uint32_t seper_esc_char0: 8;
uint32_t seper_esc_char1: 8;
uint32_t reserved24: 8;
};
uint32_t val;
} esc_conf0;
union {
struct {
uint32_t seq0: 8;
uint32_t seq0_char0: 8;
uint32_t seq0_char1: 8;
uint32_t reserved24: 8;
};
uint32_t val;
} esc_conf1;
union {
struct {
uint32_t seq1: 8;
uint32_t seq1_char0: 8;
uint32_t seq1_char1: 8;
uint32_t reserved24: 8;
};
uint32_t val;
} esc_conf2;
union {
struct {
uint32_t seq2: 8;
uint32_t seq2_char0: 8;
uint32_t seq2_char1: 8;
uint32_t reserved24: 8;
};
uint32_t val;
} esc_conf3;
union {
struct {
uint32_t thrs: 13;
uint32_t reserved13:19;
};
uint32_t val;
} pkt_thres;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t date; /**/
} uhci_dev_t;
extern uhci_dev_t UHCI0;
extern uhci_dev_t UHCI1;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_UHCI_STRUCT_H_ */

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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include "soc.h"
/* Hardware random number generator register */
#define WDEV_RND_REG 0x60035100

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// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdbool.h>
#include <stdint.h>
#include <stddef.h>
#include <assert.h>
#include "rom/ets_sys.h"
#include "rom/rtc.h"
#include "rom/uart.h"
#include "rom/gpio.h"
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/rtc_io_reg.h"
#include "soc/sens_reg.h"
#include "soc/dport_reg.h"
#include "soc/efuse_reg.h"
#include "soc/syscon_reg.h"
#include "i2c_rtc_clk.h"
#include "soc_log.h"
#include "sdkconfig.h"
#include "xtensa/core-macros.h"
#define MHZ (1000000)
/* Frequency of the 8M oscillator is 8.5MHz +/- 5%, at the default DCAP setting */
#define RTC_FAST_CLK_FREQ_8M 8500000
#define RTC_SLOW_CLK_FREQ_150K 150000
#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_8M / 256)
#define RTC_SLOW_CLK_FREQ_32K 32768
static const char* TAG = "rtc_clk";
/* Various constants related to the analog internals of the chip.
* Defined here because they don't have any use outside of this file.
*/
#define BBPLL_ENDIV5_VAL_320M 0x43
#define BBPLL_BBADC_DSMP_VAL_320M 0x84
#define BBPLL_ENDIV5_VAL_480M 0xc3
#define BBPLL_BBADC_DSMP_VAL_480M 0x74
#define APLL_SDM_STOP_VAL_1 0x09
#define APLL_SDM_STOP_VAL_2_REV0 0x69
#define APLL_SDM_STOP_VAL_2_REV1 0x49
#define APLL_CAL_DELAY_1 0x0f
#define APLL_CAL_DELAY_2 0x3f
#define APLL_CAL_DELAY_3 0x1f
#define XTAL_32K_DAC_VAL 1
#define XTAL_32K_DRES_VAL 3
#define XTAL_32K_DGM_VAL 0
#define XTAL_32K_BOOTSTRAP_DAC_VAL 3
#define XTAL_32K_BOOTSTRAP_DRES_VAL 3
#define XTAL_32K_BOOTSTRAP_DBIAS_VAL 0
#define XTAL_32K_BOOTSTRAP_TIME_US 7
/* Delays for various clock sources to be enabled/switched.
* All values are in microseconds.
* TODO: some of these are excessive, and should be reduced.
*/
#define DELAY_PLL_DBIAS_RAISE 3
#define DELAY_PLL_ENABLE_WITH_150K 80
#define DELAY_PLL_ENABLE_WITH_32K 160
#define DELAY_FAST_CLK_SWITCH 3
#define DELAY_SLOW_CLK_SWITCH 300
#define DELAY_8M_ENABLE 50
/* Number of 8M/256 clock cycles to use for XTAL frequency estimation.
* 10 cycles will take approximately 300 microseconds.
*/
#define XTAL_FREQ_EST_CYCLES 10
/* Core voltage needs to be increased in two cases:
* 1. running at 240 MHz
* 2. running with 80MHz Flash frequency
*/
#ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M
#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V25
#else
#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10
#endif
#define DIG_DBIAS_240M RTC_CNTL_DBIAS_1V25
#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
/* PLL currently enabled, if any */
typedef enum {
RTC_PLL_NONE,
RTC_PLL_320M,
RTC_PLL_480M
} rtc_pll_t;
static rtc_pll_t s_cur_pll = RTC_PLL_NONE;
/* Current CPU frequency; saved in a variable for faster freq. switching */
static rtc_cpu_freq_t s_cur_freq = RTC_CPU_FREQ_XTAL;
void rtc_clk_32k_enable_internal(int dac, int dres, int dgm)
{
SET_PERI_REG_MASK(RTC_IO_XTAL_32P_PAD_REG, RTC_IO_X32P_MUX_SEL);
SET_PERI_REG_MASK(RTC_IO_XTAL_32N_PAD_REG, RTC_IO_X32N_MUX_SEL);
CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32P_PAD_REG, RTC_IO_X32P_RUE | RTC_IO_X32P_FUN_IE | RTC_IO_X32P_RDE);
CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32N_PAD_REG, RTC_IO_X32N_RUE | RTC_IO_X32N_FUN_IE | RTC_IO_X32N_RDE);
REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DAC_XTAL_32K, dac);
REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DRES_XTAL_32K, dres);
REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DGM_XTAL_32K, dgm);
/* Differential buffer option. May need to change */
// CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DBUF_XTAL_32K);
/* Clear xpd force to use xtal32k watch dog to control xtal pxd. default on */
CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XTAL32K_XPD_FORCE);
}
void rtc_clk_32k_enable(bool enable)
{
if (enable) {
rtc_clk_32k_enable_internal(XTAL_32K_DAC_VAL, XTAL_32K_DRES_VAL, XTAL_32K_DGM_VAL);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XPD_XTAL_32K);
SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XTAL32K_XPD_FORCE);
}
}
/* Helping external 32kHz crystal to start up.
* External crystal connected to outputs GPIO32 GPIO33.
* Forms N pulses with a frequency of about 32KHz on the outputs of the crystal.
*/
/* I doudt whether the old function can work correctly on ESP32...Need to review when having time */
void rtc_clk_32k_bootstrap(uint32_t cycle)
{
/* Config a clock to stimulate xtal, this clock is divided by a clock mux
* The default selection of the clock mux is to use 8M, but it may not have enough accuracy compared with 40M xtal
* This clock will be a pulse clk with a double frequency of 32.768k.
* and then it will become a 32.768k clock with 50% duty cycle in RTC.
* (40M / 32.768k) * 2 = 2441 + 13/32
*/
REG_SET_FIELD(DPORT_BT_LPCK_DIV_INT_REG, DPORT_BT_LPCK_DIV_NUM, 2441);
REG_SET_FIELD(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_BT_LPCK_DIV_A, 32);
REG_SET_FIELD(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_BT_LPCK_DIV_B, 13);
/* Enable clock mux with 40M */
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN);
CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_8M);
SET_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_XTAL);
/* connect clock to RTC */
SET_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_RTC_EN);
/* connect clock to analog */
SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_ENCKINIT_XTAL_32K);
/* Enable 32k xtal */
rtc_clk_32k_enable_internal(XTAL_32K_BOOTSTRAP_DAC_VAL, XTAL_32K_BOOTSTRAP_DRES_VAL, XTAL_32K_BOOTSTRAP_DBIAS_VAL);
/* wait 32k xtal to be stable. Need to find a better way */
ets_delay_us(cycle);
/* Close clock source */
CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_XTAL);
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN);
CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_ENCKINIT_XTAL_32K);
CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_RTC_EN);
}
bool rtc_clk_32k_enabled()
{
uint32_t xtal_conf = READ_PERI_REG(RTC_CNTL_EXT_XTL_CONF_REG);
/* If xtal xpd is controlled by software */
bool xtal_xpd_sw = (xtal_conf & RTC_CNTL_XTAL32K_XPD_FORCE) >> RTC_CNTL_XTAL32K_XPD_FORCE_S;
/* If xtal xpd software control is on */
bool xtal_xpd_st = (xtal_conf & RTC_CNTL_XPD_XTAL_32K) >> RTC_CNTL_XPD_XTAL_32K_S;
if (xtal_xpd_sw & !xtal_xpd_st) {
return false;
} else {
return true;
}
}
void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
{
if (clk_8m_en) {
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
/* no need to wait once enabled by software */
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, 1);
ets_delay_us(DELAY_8M_ENABLE);
} else {
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT);
}
/* d256 should be independent configured with 8M
* Maybe we can split this function into 8m and dmd256
*/
if (d256_en) {
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
} else {
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
}
}
bool rtc_clk_8m_enabled()
{
return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0;
}
bool rtc_clk_8md256_enabled()
{
return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
}
void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div)
{
REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD, enable ? 0 : 1);
REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU, enable ? 1 : 0);
/* BIAS I2C not exist any more, but not sure how to get the same effect yet...
* if (!enable &&
* REG_GET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_SOC_CLK_SEL) != SYSCON_SOC_CLK_SEL_PLL) {
* REG_SET_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
* } else {
* REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
* }
*/
if (enable) {
/* no need to differentiate ECO chip any more
uint8_t sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV1;
uint32_t is_rev0 = (GET_PERI_REG_BITS2(EFUSE_BLK0_RDATA3_REG, 1, 15) == 0);
if (is_rev0) {
sdm0 = 0;
sdm1 = 0;
sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV0;
}
*/
I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM2, sdm2);
I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM0, sdm0);
I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM1, sdm1);
I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_1);
I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_2_REV1);
I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV, o_div);
/* calibration */
I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_1);
I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_2);
I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_3);
/* wait for calibration end */
while (!(I2C_READREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_CAL_END))) {
/* use ets_delay_us so the RTC bus doesn't get flooded */
ets_delay_us(1);
}
}
}
void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
{
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq);
/* Why we need to connect this clock to digital?
* Or maybe this clock should be connected to digital when xtal 32k clock is enabled instead?
*/
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN,
(slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0);
ets_delay_us(DELAY_SLOW_CLK_SWITCH);
}
rtc_slow_freq_t rtc_clk_slow_freq_get()
{
return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
}
uint32_t rtc_clk_slow_freq_get_hz()
{
switch(rtc_clk_slow_freq_get()) {
case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K;
case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K;
case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256;
}
return 0;
}
void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq)
{
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, fast_freq);
ets_delay_us(DELAY_FAST_CLK_SWITCH);
}
rtc_fast_freq_t rtc_clk_fast_freq_get()
{
return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL);
}
/* In 7.2.2, cpu can run at 80M/160M/240M if PLL is 480M
* pll can run 80M/160M is PLL is 320M
*/
#define DR_REG_I2C_MST_BASE 0x3f40E000
#define I2C_MST_ANA_STATE_REG (DR_REG_I2C_MST_BASE + 0x040)
#define I2C_MST_BBPLL_CAL_END (BIT(24))
#define I2C_MST_BBPLL_CAL_END_M (BIT(24))
#define I2C_MST_BBPLL_CAL_END_V 0x1
#define I2C_MST_BBPLL_CAL_END_S 24
void rtc_clk_bbpll_set(rtc_xtal_freq_t xtal_freq, rtc_pll_t pll_freq)
{
uint8_t div_ref;
uint8_t div7_0;
uint8_t dr1;
uint8_t dr3;
uint8_t dchgp;
uint8_t dcur;
if (pll_freq == RTC_PLL_480M) {
/* Raise the voltage, if needed */
/* move to 240M logic */
//REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M);
/* Set this register to let digital know pll is 480M */
SET_PERI_REG_MASK(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL);
/* Configure 480M PLL */
switch (xtal_freq) {
case RTC_XTAL_FREQ_40M:
div_ref = 0;
div7_0 = 8;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dcur = 4;
break;
case RTC_XTAL_FREQ_26M:
div_ref = 12;
div7_0 = 156;
dr1 = 3;
dr3 = 3;
dchgp = 4;
dcur = 1;
break;
case RTC_XTAL_FREQ_24M:
div_ref = 11;
div7_0 = 156;
dr1 = 3;
dr3 = 3;
dchgp = 4;
dcur = 1;
break;
default:
div_ref = 0;
div7_0 = 8;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dcur = 4;
break;
}
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6B);
} else {
/* Raise the voltage */
//REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M);
//ets_delay_us(DELAY_PLL_DBIAS_RAISE);
CLEAR_PERI_REG_MASK(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL);
/* Configure 480M PLL */
switch (xtal_freq) {
case RTC_XTAL_FREQ_40M:
div_ref = 0;
div7_0 = 4;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dcur = 5;
break;
case RTC_XTAL_FREQ_26M:
div_ref = 12;
div7_0 = 236;
dr1 = 3;
dr3 = 3;
dchgp = 0;
dcur = 2;
break;
case RTC_XTAL_FREQ_24M:
div_ref = 11;
div7_0 = 236;
dr1 = 3;
dr3 = 3;
dchgp = 0;
dcur = 2;
break;
default:
div_ref = 0;
div7_0 = 4;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dcur = 5;
break;
}
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69);
}
uint8_t i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref);
uint8_t i2c_bbpll_div_7_0 = div7_0;
uint8_t i2c_bbpll_dcur = (2 << I2C_BBPLL_OC_DLREF_SEL_LSB ) | (1 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1);
I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
/* this delay is replaced by polling Pll calibration end flag
* uint32_t delay_pll_en = (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_RTC) ?
* DELAY_PLL_ENABLE_WITH_150K : DELAY_PLL_ENABLE_WITH_32K;
* ets_delay_us(delay_pll_en);
*/
/* this calibration didn't work on 480M
need to test exact delay according to 320M
while (!GET_PERI_REG_MASK(I2C_MST_ANA_STATE_REG, I2C_MST_BBPLL_CAL_END)) {
ets_delay_us(1);
}
*/
ets_delay_us(50000);
}
/**
* Switch to XTAL frequency. Does not disable the PLL.
*/
static void rtc_clk_cpu_freq_to_xtal()
{
rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
ets_update_cpu_frequency(xtal_freq);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT, 0);
REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_SOC_CLK_SEL, SYSCON_SOC_CLK_SEL_XTL);
/* Why we need to do this ? */
//DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 0); // clear DPORT_CPUPERIOD_SEL
rtc_clk_apb_freq_update(xtal_freq * MHZ);
s_cur_freq = RTC_CPU_FREQ_XTAL;
}
/**
* Switch to one of PLL-based frequencies. Current frequency can be XTAL or PLL.
* PLL must already be enabled.
* If switching between frequencies derived from different PLLs (320M and 480M),
* fall back to rtc_clk_cpu_freq_set.
* @param cpu_freq new CPU frequency
*/
static void rtc_clk_cpu_freq_to_pll(rtc_cpu_freq_t cpu_freq)
{
int freq = 0;
if ((s_cur_pll == RTC_PLL_NONE) || ((s_cur_pll == RTC_PLL_320M) && (cpu_freq == RTC_CPU_FREQ_240M))) {
/*
* if switch from non-pll or switch from PLL 320M to 480M
* need to switch PLLs, fall back to full implementation
*/
rtc_clk_cpu_freq_set(cpu_freq);
return;
}
if ((cpu_freq == RTC_CPU_FREQ_80M) || (cpu_freq == RTC_CPU_320M_80M)) {
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M);
DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 0);
freq = 80;
} else if ((cpu_freq == RTC_CPU_FREQ_160M) || (cpu_freq == RTC_CPU_320M_160M)) {
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M);
DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 1);
freq = 160;
} else if (cpu_freq == RTC_CPU_FREQ_240M) {
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M);
DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 2);
freq = 240;
}
// REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_SOC_CLK_SEL, SYSCON_SOC_CLK_SEL_PLL);
rtc_clk_apb_freq_update(80 * MHZ);
ets_update_cpu_frequency(freq);
s_cur_freq = cpu_freq;
}
void rtc_clk_cpu_freq_set_fast(rtc_cpu_freq_t cpu_freq)
{
if (cpu_freq == s_cur_freq) {
return;
} else if (cpu_freq == RTC_CPU_FREQ_2M || s_cur_freq == RTC_CPU_FREQ_2M) {
/* fall back to full implementation if switch to/from 2M is needed */
rtc_clk_cpu_freq_set(cpu_freq);
} else if (cpu_freq == RTC_CPU_FREQ_XTAL) {
rtc_clk_cpu_freq_to_xtal();
} else if (cpu_freq > RTC_CPU_FREQ_XTAL) {
rtc_clk_cpu_freq_to_pll(cpu_freq);
/* Not neccessary any more */
//rtc_clk_wait_for_slow_cycle();
}
}
void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq)
{
rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
/* Switch CPU to XTAL frequency first */
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_SOC_CLK_SEL, SYSCON_SOC_CLK_SEL_XTL);
REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT, 0);
ets_update_cpu_frequency(xtal_freq);
/* Frequency switch is synchronized to SLOW_CLK cycle. Wait until the switch
* is complete before disabling the PLL.
*/
/* register SOC_CLK_SEL is moved to APB domain, so this delay is not neccessary any more */
//rtc_clk_wait_for_slow_cycle();
DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0);
/* BBPLL force power down won't affect force power up setting */
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD |
RTC_CNTL_BBPLL_I2C_FORCE_PD);
s_cur_pll = RTC_PLL_NONE;
rtc_clk_apb_freq_update(xtal_freq * MHZ);
/* is APLL under force power down? */
/* may need equivalent function
uint32_t apll_fpd = REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
* if (apll_fpd) {
* SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
* }
*/
/* now switch to the desired frequency */
if (cpu_freq == RTC_CPU_FREQ_XTAL) {
/* already at XTAL, nothing to do */
} else if (cpu_freq == RTC_CPU_FREQ_2M) {
/* set up divider to produce 2MHz from XTAL */
REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT, (xtal_freq / 2) - 1);
ets_update_cpu_frequency(2);
rtc_clk_apb_freq_update(2 * MHZ);
/* lower the voltage */
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_2M);
} else {
/* use PLL as clock source */
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
RTC_CNTL_BB_I2C_FORCE_PD |
RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
if (cpu_freq > RTC_CPU_FREQ_2M) {
rtc_clk_bbpll_set(xtal_freq, RTC_PLL_320M);
s_cur_pll = RTC_PLL_320M;
} else {
rtc_clk_bbpll_set(xtal_freq, RTC_PLL_480M);
s_cur_pll = RTC_PLL_480M;
}
if ((cpu_freq == RTC_CPU_FREQ_80M) || (cpu_freq == RTC_CPU_320M_80M)) {
DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0);
ets_update_cpu_frequency(80);
} else if ((cpu_freq == RTC_CPU_FREQ_160M) || (cpu_freq == RTC_CPU_320M_160M)) {
DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 1);
ets_update_cpu_frequency(160);
} else if (cpu_freq == RTC_CPU_FREQ_240M) {
DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 2);
ets_update_cpu_frequency(240);
}
REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_SOC_CLK_SEL, SYSCON_SOC_CLK_SEL_PLL);
//rtc_clk_wait_for_slow_cycle();
rtc_clk_apb_freq_update(80 * MHZ);
}
s_cur_freq = cpu_freq;
}
rtc_cpu_freq_t rtc_clk_cpu_freq_get()
{
uint32_t soc_clk_sel = REG_GET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_SOC_CLK_SEL);
switch (soc_clk_sel) {
case SYSCON_SOC_CLK_SEL_XTL: {
uint32_t pre_div = REG_GET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT);
if (pre_div == 0) {
return RTC_CPU_FREQ_XTAL;
} else if (pre_div == rtc_clk_xtal_freq_get() / 2 - 1) {
return RTC_CPU_FREQ_2M;
} else {
assert(false && "unsupported frequency");
}
break;
}
case SYSCON_SOC_CLK_SEL_PLL: {
uint32_t cpuperiod_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL);
if (cpuperiod_sel == 0) {
return RTC_CPU_FREQ_80M;
} else if (cpuperiod_sel == 1) {
return RTC_CPU_FREQ_160M;
} else if (cpuperiod_sel == 2) {
return RTC_CPU_FREQ_240M;
} else {
assert(false && "unsupported frequency");
}
break;
}
case SYSCON_SOC_CLK_SEL_APLL:
case SYSCON_SOC_CLK_SEL_8M:
default:
assert(false && "unsupported frequency");
}
return SYSCON_SOC_CLK_SEL_XTL;
}
uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq)
{
switch (cpu_freq) {
case RTC_CPU_FREQ_XTAL:
return ((uint32_t) rtc_clk_xtal_freq_get()) * MHZ;
case RTC_CPU_FREQ_2M:
return 2 * MHZ;
case RTC_CPU_FREQ_80M:
return 80 * MHZ;
case RTC_CPU_FREQ_160M:
return 160 * MHZ;
case RTC_CPU_FREQ_240M:
return 240 * MHZ;
case RTC_CPU_320M_80M:
return 80 * MHZ;
case RTC_CPU_320M_160M:
return 160 * MHZ;
default:
assert(false && "invalid rtc_cpu_freq_t value");
return 0;
}
}
bool rtc_clk_cpu_freq_from_mhz(int mhz, rtc_cpu_freq_t* out_val)
{
if (mhz == 240) {
*out_val = RTC_CPU_FREQ_240M;
} else if (mhz == 160) {
*out_val = RTC_CPU_FREQ_160M;
} else if (mhz == 80) {
*out_val = RTC_CPU_FREQ_80M;
} else if (mhz == (int) rtc_clk_xtal_freq_get()) {
*out_val = RTC_CPU_FREQ_XTAL;
} else if (mhz == 2) {
*out_val = RTC_CPU_FREQ_2M;
} else {
return false;
}
return true;
}
/* Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are stored as two copies in
* lower and upper 16-bit halves. These are the routines to work with such a
* representation.
*/
static bool clk_val_is_valid(uint32_t val) {
return (val & 0xffff) == ((val >> 16) & 0xffff) &&
val != 0 &&
val != UINT32_MAX;
}
static uint32_t reg_val_to_clk_val(uint32_t val) {
return val & UINT16_MAX;
}
static uint32_t clk_val_to_reg_val(uint32_t val) {
return (val & UINT16_MAX) | ((val & UINT16_MAX) << 16);
}
rtc_xtal_freq_t rtc_clk_xtal_freq_get()
{
/* We may have already written XTAL value into RTC_XTAL_FREQ_REG */
uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
if (!clk_val_is_valid(xtal_freq_reg)) {
SOC_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value: 0x%08x", xtal_freq_reg);
return RTC_XTAL_FREQ_AUTO;
}
return reg_val_to_clk_val(xtal_freq_reg);
}
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
{
WRITE_PERI_REG(RTC_XTAL_FREQ_REG, clk_val_to_reg_val(xtal_freq));
}
static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate()
{
/* Enable 8M/256 clock if needed */
const bool clk_8m_enabled = rtc_clk_8m_enabled();
const bool clk_8md256_enabled = rtc_clk_8md256_enabled();
if (!clk_8md256_enabled) {
rtc_clk_8m_enable(true, true);
}
uint64_t cal_val = rtc_clk_cal_ratio(RTC_CAL_8MD256, XTAL_FREQ_EST_CYCLES);
/* cal_val contains period of 8M/256 clock in XTAL clock cycles
* (shifted by RTC_CLK_CAL_FRACT bits).
* Xtal frequency will be (cal_val * 8M / 256) / 2^19
*/
uint32_t freq_mhz = (cal_val * RTC_FAST_CLK_FREQ_APPROX / MHZ / 256 ) >> RTC_CLK_CAL_FRACT;
/* Guess the XTAL type. For now, only 40 and 26MHz are supported.
*/
switch (freq_mhz) {
case 21 ... 31:
return RTC_XTAL_FREQ_26M;
case 32 ... 33:
SOC_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 26 MHz", freq_mhz);
return RTC_XTAL_FREQ_26M;
case 34 ... 35:
SOC_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 40 MHz", freq_mhz);
return RTC_XTAL_FREQ_40M;
case 36 ... 45:
return RTC_XTAL_FREQ_40M;
default:
SOC_LOGW(TAG, "Bogus XTAL frequency: %d MHz", freq_mhz);
return RTC_XTAL_FREQ_AUTO;
}
/* Restore 8M and 8md256 clocks to original state */
rtc_clk_8m_enable(clk_8m_enabled, clk_8md256_enabled);
}
void rtc_clk_apb_freq_update(uint32_t apb_freq)
{
WRITE_PERI_REG(RTC_APB_FREQ_REG, clk_val_to_reg_val(apb_freq >> 12));
}
uint32_t rtc_clk_apb_freq_get()
{
uint32_t freq_hz = reg_val_to_clk_val(READ_PERI_REG(RTC_APB_FREQ_REG)) << 12;
// round to the nearest MHz
freq_hz += MHZ / 2;
uint32_t remainder = freq_hz % MHZ;
return freq_hz - remainder;
}
void rtc_clk_divider_set(uint32_t div)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD);
REG_SET_FIELD(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV, div);
SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD);
}
void rtc_clk_8m_divider_set(uint32_t div)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD);
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, div);
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD);
}
void rtc_clk_init(rtc_clk_config_t cfg)
{
rtc_cpu_freq_t cpu_source_before = rtc_clk_cpu_freq_get();
/* If we get a TG WDT system reset while running at 240MHz,
* DPORT_CPUPERIOD_SEL register will be reset to 0 resulting in 120MHz
* APB and CPU frequencies after reset. This will cause issues with XTAL
* frequency estimation, so we switch to XTAL frequency first.
*
* Ideally we would only do this if SYSCON_SOC_CLK_SEL == PLL and
* PLL is configured for 480M, but it takes less time to switch to 40M and
* run the following code than querying the PLL does.
*/
if (REG_GET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_SOC_CLK_SEL) == SYSCON_SOC_CLK_SEL_PLL) {
rtc_clk_cpu_freq_set(RTC_CPU_FREQ_XTAL);
}
/* Set tuning parameters for 8M and 150k clocks.
* Note: this doesn't attempt to set the clocks to precise frequencies.
* Instead, we calibrate these clocks against XTAL frequency later, when necessary.
* - SCK_DCAP value controls tuning of 150k clock.
* The higher the value of DCAP is, the lower is the frequency.
* - CK8M_DFREQ value controls tuning of 8M clock.
* CLK_8M_DFREQ constant gives the best temperature characteristics.
*/
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq);
/* Configure 150k clock division */
rtc_clk_divider_set(cfg.clk_rtc_clk_div);
/* Configure 8M clock division */
rtc_clk_8m_divider_set(cfg.clk_8m_clk_div);
/* Enable the internal bus used to configure PLLs */
SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S);
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_APLL_M | I2C_BBPLL_M);
/* Estimate XTAL frequency */
rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
if (clk_val_is_valid(READ_PERI_REG(RTC_XTAL_FREQ_REG))) {
/* XTAL frequency has already been set, use existing value */
xtal_freq = rtc_clk_xtal_freq_get();
} else {
/* Not set yet, estimate XTAL frequency based on RTC_FAST_CLK */
xtal_freq = rtc_clk_xtal_freq_estimate();
if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
SOC_LOGW(TAG, "Can't estimate XTAL frequency, assuming 26MHz");
xtal_freq = RTC_XTAL_FREQ_26M;
}
}
} else if (!clk_val_is_valid(READ_PERI_REG(RTC_XTAL_FREQ_REG))) {
/* Exact frequency was set in sdkconfig, but still warn if autodetected
* frequency is different. If autodetection failed, worst case we get a
* bit of garbage output.
*/
rtc_xtal_freq_t est_xtal_freq = rtc_clk_xtal_freq_estimate();
if (est_xtal_freq != xtal_freq) {
SOC_LOGW(TAG, "Possibly invalid CONFIG_ESP32_XTAL_FREQ setting (%dMHz). Detected %d MHz.",
xtal_freq, est_xtal_freq);
}
}
uart_tx_wait_idle(0);
rtc_clk_xtal_freq_update(xtal_freq);
rtc_clk_apb_freq_update(xtal_freq * MHZ);
/* Set CPU frequency */
rtc_clk_cpu_freq_set(cfg.cpu_freq);
/* Re-calculate the ccount to make time calculation correct. */
uint32_t freq_before = rtc_clk_cpu_freq_value(cpu_source_before) / MHZ;
uint32_t freq_after = rtc_clk_cpu_freq_value(cfg.cpu_freq) / MHZ;
XTHAL_SET_CCOUNT( XTHAL_GET_CCOUNT() * freq_after / freq_before );
/* Slow & fast clocks setup */
if (cfg.slow_freq == RTC_SLOW_FREQ_32K_XTAL) {
rtc_clk_32k_enable(true);
}
if (cfg.fast_freq == RTC_FAST_FREQ_8M) {
bool need_8md256 = cfg.slow_freq == RTC_SLOW_FREQ_8MD256;
rtc_clk_8m_enable(true, need_8md256);
}
rtc_clk_fast_freq_set(cfg.fast_freq);
rtc_clk_slow_freq_set(cfg.slow_freq);
}
/* Name used in libphy.a:phy_chip_v7.o
* TODO: update the library to use rtc_clk_xtal_freq_get
*/
rtc_xtal_freq_t rtc_get_xtal() __attribute__((alias("rtc_clk_xtal_freq_get")));

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// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdint.h>
#include "soc/soc.h"
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/dport_reg.h"
#include "soc/efuse_reg.h"
#include "soc/gpio_reg.h"
#include "soc/spi_mem_reg.h"
#include "i2c_rtc_clk.h"
/* Various delays to be programmed into power control state machines */
#define RTC_CNTL_XTL_BUF_WAIT_SLP 2
#define RTC_CNTL_PLL_BUF_WAIT_SLP 2
#define RTC_CNTL_CK8M_WAIT_SLP 4
#define OTHER_BLOCKS_POWERUP 1
#define OTHER_BLOCKS_WAIT 1
#define ROM_RAM_POWERUP_CYCLES OTHER_BLOCKS_POWERUP
#define ROM_RAM_WAIT_CYCLES OTHER_BLOCKS_WAIT
#define WIFI_POWERUP_CYCLES OTHER_BLOCKS_POWERUP
#define WIFI_WAIT_CYCLES OTHER_BLOCKS_WAIT
#define RTC_POWERUP_CYCLES OTHER_BLOCKS_POWERUP
#define RTC_WAIT_CYCLES OTHER_BLOCKS_WAIT
#define DG_WRAP_POWERUP_CYCLES OTHER_BLOCKS_POWERUP
#define DG_WRAP_WAIT_CYCLES OTHER_BLOCKS_WAIT
#define RTC_MEM_POWERUP_CYCLES OTHER_BLOCKS_POWERUP
#define RTC_MEM_WAIT_CYCLES OTHER_BLOCKS_WAIT
#ifndef CONFIG_HARDWARE_IS_FPGA
void rtc_init(rtc_config_t cfg)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, cfg.xtal_wait);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait);
/* Moved from rtc sleep to rtc init to save sleep function running time */
// set shortest possible sleep time limit
REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_MIN_SLP_VAL, RTC_CNTL_MIN_SLP_VAL_MIN);
/* This power domian removed
* set rom&ram timer
* REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_ROM_RAM_POWERUP_TIMER, ROM_RAM_POWERUP_CYCLES);
* REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_ROM_RAM_WAIT_TIMER, ROM_RAM_WAIT_CYCLES);
*/
// set wifi timer
REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, WIFI_POWERUP_CYCLES);
REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, WIFI_WAIT_CYCLES);
// set rtc peri timer
REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_POWERUP_TIMER, RTC_POWERUP_CYCLES);
REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_WAIT_TIMER, RTC_WAIT_CYCLES);
// set digital wrap timer
REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_POWERUP_TIMER, DG_WRAP_POWERUP_CYCLES);
REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_WAIT_TIMER, DG_WRAP_WAIT_CYCLES);
// set rtc memory timer
REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_POWERUP_TIMER, RTC_MEM_POWERUP_CYCLES);
REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_WAIT_TIMER, RTC_MEM_WAIT_CYCLES);
SET_PERI_REG_MASK(RTC_CNTL_BIAS_CONF_REG,
RTC_CNTL_DEC_HEARTBEAT_WIDTH | RTC_CNTL_INC_HEARTBEAT_PERIOD);
/* Reset RTC bias to default value (needed if waking up from deep sleep) */
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_1V10);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, RTC_CNTL_DBIAS_1V10);
if (cfg.clkctl_init) {
//clear CMMU clock force on
CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_MMU_POWER_CTRL_REG, DPORT_PRO_CACHE_MMU_MEM_FORCE_ON);
//clear rom clock force on
REG_SET_FIELD(DPORT_ROM_CTRL_0_REG, DPORT_ROM_FO, 0);
//clear sram clock force on
REG_SET_FIELD(DPORT_SRAM_CTRL_0_REG, DPORT_SRAM_FO, 0);
//clear tag clock force on
CLEAR_PERI_REG_MASK(DPORT_PRO_DCACHE_TAG_POWER_CTRL_REG, DPORT_PRO_DCACHE_TAG_MEM_FORCE_ON);
CLEAR_PERI_REG_MASK(DPORT_PRO_ICACHE_TAG_POWER_CTRL_REG, DPORT_PRO_ICACHE_TAG_MEM_FORCE_ON);
//clear register clock force on
CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_GATE_REG(0), SPI_MEM_CLK_EN);
CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_GATE_REG(1), SPI_MEM_CLK_EN);
}
if (cfg.pwrctl_init) {
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
//cancel xtal force pu if no need to force power up
//cannot cancel xtal force pu if pll is force power on
if (!(cfg.xtal_fpu | cfg.bbpll_fpu)) {
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU);
} else {
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU);
}
// cancel BIAS force pu
// CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FORCE_PU);
// CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP);
// bias follow 8M
// SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FOLW_8M);
// SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FOLW_8M);
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_SLEEP_FOLW_8M);
// CLEAR APLL close
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
//cancel bbpll force pu if setting no force power up
if (!cfg.bbpll_fpu) {
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_I2C_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
} else {
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_I2C_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
}
//cancel RTC REG force PU
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PWC_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU);
//combine two rtc memory options
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_NOISO);
if (cfg.rtc_dboost_fpd) {
SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
}
//cancel digital pu force
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU);
/* If this mask is enabled, all soc memories cannot enter power down mode */
/* We should control soc memory power down mode from RTC, so we will not touch this register any more */
CLEAR_PERI_REG_MASK(DPORT_MEM_PD_MASK_REG, DPORT_LSLP_MEM_PD_MASK);
/* If this pd_cfg is set to 1, all memory won't enter low power mode during light sleep */
/* If this pd_cfg is set to 0, all memory will enter low power mode during light sleep */
rtc_sleep_pd_config_t pd_cfg = RTC_SLEEP_PD_CONFIG_ALL(0);
rtc_sleep_pd(pd_cfg);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
// ROM_RAM power domain is removed
// CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_ROM_RAM_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO);
// CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_ROM_RAM_FORCE_NOISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_NOISO);
//cancel digital PADS force no iso
//wangqiang ++
rom_i2c_writeReg_Mask(0x6a,1,0,1,0,2);
rom_i2c_writeReg_Mask(0x6a,1,2,5,4,2);
#ifdef CONFIG_CHIP_IS_ESP32
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_UNHOLD);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_NOISO);
#endif
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
#ifdef CONFIG_CHIP_IS_ESP32
SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_AUTOHOLD_EN);
SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN);
#endif
}
}
#endif
rtc_vddsdio_config_t rtc_vddsdio_get_config()
{
rtc_vddsdio_config_t result;
uint32_t sdio_conf_reg = REG_READ(RTC_CNTL_SDIO_CONF_REG);
result.drefh = (sdio_conf_reg & RTC_CNTL_DREFH_SDIO_M) >> RTC_CNTL_DREFH_SDIO_S;
result.drefm = (sdio_conf_reg & RTC_CNTL_DREFM_SDIO_M) >> RTC_CNTL_DREFM_SDIO_S;
result.drefl = (sdio_conf_reg & RTC_CNTL_DREFL_SDIO_M) >> RTC_CNTL_DREFL_SDIO_S;
if (sdio_conf_reg & RTC_CNTL_SDIO_FORCE) {
// Get configuration from RTC
result.force = 1;
result.enable = (sdio_conf_reg & RTC_CNTL_XPD_SDIO_REG_M) >> RTC_CNTL_XPD_SDIO_REG_S;
result.tieh = (sdio_conf_reg & RTC_CNTL_SDIO_TIEH_M) >> RTC_CNTL_SDIO_TIEH_S;
return result;
}
#if 0
uint32_t efuse_reg = REG_READ(EFUSE_BLK0_RDATA4_REG);
if (efuse_reg & EFUSE_RD_SDIO_FORCE) {
// Get configuration from EFUSE
result.force = 0;
result.enable = (efuse_reg & EFUSE_RD_XPD_SDIO_REG_M) >> EFUSE_RD_XPD_SDIO_REG_S;
result.tieh = (efuse_reg & EFUSE_RD_SDIO_TIEH_M) >> EFUSE_RD_SDIO_TIEH_S;
//DREFH/M/L eFuse are used for EFUSE_ADC_VREF instead. Therefore tuning
//will only be available on older chips that don't have EFUSE_ADC_VREF
if(REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG ,EFUSE_RD_BLK3_PART_RESERVE) == 0){
//BLK3_PART_RESERVE indicates the presence of EFUSE_ADC_VREF
// in this case, DREFH/M/L are also set from EFUSE
result.drefh = (efuse_reg & EFUSE_RD_SDIO_DREFH_M) >> EFUSE_RD_SDIO_DREFH_S;
result.drefm = (efuse_reg & EFUSE_RD_SDIO_DREFM_M) >> EFUSE_RD_SDIO_DREFM_S;
result.drefl = (efuse_reg & EFUSE_RD_SDIO_DREFL_M) >> EFUSE_RD_SDIO_DREFL_S;
}
return result;
}
#endif
// Otherwise, VDD_SDIO is controlled by bootstrapping pin
uint32_t strap_reg = REG_READ(GPIO_STRAP_REG);
result.force = 0;
result.tieh = (strap_reg & BIT(5)) ? RTC_VDDSDIO_TIEH_1_8V : RTC_VDDSDIO_TIEH_3_3V;
result.enable = 1;
return result;
}
void rtc_vddsdio_set_config(rtc_vddsdio_config_t config)
{
uint32_t val = 0;
val |= (config.force << RTC_CNTL_SDIO_FORCE_S);
val |= (config.enable << RTC_CNTL_XPD_SDIO_REG_S);
val |= (config.drefh << RTC_CNTL_DREFH_SDIO_S);
val |= (config.drefm << RTC_CNTL_DREFM_SDIO_S);
val |= (config.drefl << RTC_CNTL_DREFL_SDIO_S);
val |= (config.tieh << RTC_CNTL_SDIO_TIEH_S);
val |= RTC_CNTL_SDIO_PD_EN;
REG_WRITE(RTC_CNTL_SDIO_CONF_REG, val);
}

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// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdint.h>
#include <assert.h>
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/apb_ctrl_reg.h"
typedef enum {
PM_LIGHT_SLEEP = BIT(2), /*!< WiFi PD, memory in light sleep */
} pm_sleep_mode_t;
typedef enum{
PM_SW_NOREJECT = 0,
PM_SW_REJECT = 1
} pm_sw_reject_t;
/* These MAC-related functions are defined in the closed source part of
* RTC library
*/
extern void pm_mac_init();
extern int pm_check_mac_idle();
extern void pm_mac_deinit();
/* This sleep-related function is called from the closed source part of RTC
* library.
*/
pm_sw_reject_t pm_set_sleep_mode(pm_sleep_mode_t sleep_mode, void(*pmac_save_params)())
{
(void) pmac_save_params; /* unused */
pm_mac_deinit();
if (pm_check_mac_idle()) {
pm_mac_init();
return PM_SW_REJECT;
}
rtc_sleep_config_t cfg = { 0 };
switch (sleep_mode) {
case PM_LIGHT_SLEEP:
cfg.wifi_pd_en = 1;
cfg.dig_dbias_wak = 4;
cfg.dig_dbias_slp = 0;
cfg.rtc_dbias_wak = 0;
cfg.rtc_dbias_slp = 0;
rtc_sleep_init(cfg);
break;
default:
assert(0 && "unsupported sleep mode");
}
return PM_SW_NOREJECT;
}

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// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdint.h>
#include "soc/soc.h"
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/dport_reg.h"
#include "soc/rtc.h"
#include "soc/i2s_reg.h"
#include "soc/timer_group_reg.h"
#include "soc/bb_reg.h"
#include "soc/nrx_reg.h"
#include "soc/fe_reg.h"
#include "soc/rtc.h"
#include "rom/ets_sys.h"
#define MHZ (1000000)
/**
* Configure whether certain peripherals are powered down in deep sleep
* @param cfg power down flags as rtc_sleep_pd_config_t structure
*/
void rtc_sleep_pd(rtc_sleep_pd_config_t cfg)
{
REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu);
REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_LPU, cfg.rtc_fpu);
//DPORT_REG_SET_FIELD(DPORT_MEM_PD_MASK_REG, DPORT_LSLP_MEM_PD_MASK, ~cfg.cpu_pd);
REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_PLC_MEM_FORCE_PU, cfg.i2s_fpu);
REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_FIFO_FORCE_PU, cfg.i2s_fpu);
REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_DC_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_AGC_MEM_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu);
REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu);
REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu);
REG_SET_FIELD(NRXPD_CTRL, NRX_VIT_FORCE_PU, cfg.nrx_fpu);
REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu);
REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu);
}
void rtc_sleep_init(rtc_sleep_config_t cfg)
{
/* Already defined in rtc init
// set 5 PWC state machine times to fit in main state machine time
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, RTC_CNTL_XTL_BUF_WAIT_SLP);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP);
*/
/* I don't think it worthes to run this function everytime as it is just a test option */
if (cfg.lslp_mem_inf_fpu)
{
rtc_sleep_pd_config_t pd_cfg = RTC_SLEEP_PD_CONFIG_ALL(1);
rtc_sleep_pd(pd_cfg);
}
/* This option seems to be unneccessary
if (cfg.rtc_mem_inf_fpu) {
SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU);
}
*/
if (cfg.rtc_mem_inf_follow_cpu) {
SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FOLW_CPU);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FOLW_CPU);
}
if (cfg.rtc_fastmem_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN);
}
if (cfg.rtc_slowmem_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN);
}
if (cfg.rtc_peri_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN);
}
if (cfg.wifi_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
}
/*
#ifdef CONFIG_CHIP_IS_ESP32
if (cfg.rom_mem_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_ROM_RAM_PD_EN);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_ROM_RAM_PD_EN);
}
#endif
*/
if (cfg.deep_slp) {
/* redundant ? People may not want to touch such registers after init
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG,
RTC_CNTL_DG_PAD_FORCE_ISO | RTC_CNTL_DG_PAD_FORCE_NOISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG,
RTC_CNTL_DG_WRAP_FORCE_PU | RTC_CNTL_DG_WRAP_FORCE_PD);
#ifdef CONFIG_CHIP_IS_ESP32
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP);
#endif
*/
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, RTC_CNTL_DBG_ATTEN_DEFAULT);
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
// Shut down parts of RTC which may have been left enabled by the wireless drivers
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,
RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU |
RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, 0);
}
/* enable VDDSDIO control by state machine */
REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE);
REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, cfg.rtc_dbias_slp);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, cfg.rtc_dbias_wak);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, cfg.dig_dbias_wak);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_SLP, cfg.dig_dbias_slp);
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject);
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject);
}
void rtc_sleep_set_wakeup_time(uint64_t t)
{
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
}
uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu)
{
REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt);
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_SLEEP_REJECT_ENA, reject_opt);
/* Start entry into sleep mode */
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
while (GET_PERI_REG_MASK(RTC_CNTL_INT_RAW_REG,
RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) == 0) {
;
}
/* In deep sleep mode, we never get here */
uint32_t reject = REG_GET_FIELD(RTC_CNTL_INT_RAW_REG, RTC_CNTL_SLP_REJECT_INT_RAW);
SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR);
/* restore config if it is a light sleep */
if (lslp_mem_inf_fpu)
{
rtc_sleep_pd_config_t pd_cfg = RTC_SLEEP_PD_CONFIG_ALL(0);
rtc_sleep_pd(pd_cfg);
}
/* move setting from init to sleep, so we don't need to have this any more
* restore DBG_ATTEN to the default value
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, RTC_CNTL_DBG_ATTEN_DEFAULT);
*/
return reject;
}

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// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdint.h>
#include "rom/ets_sys.h"
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/timer_group_reg.h"
#define MHZ (1000000)
/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of
* RTC_SLOW_CLK cycles.
*
* Slow clock calibration feature has two modes of operation: one-off and cycling.
* In cycling mode (which is enabled by default on SoC reset), counting of XTAL
* cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
* using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
* once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
* enabled using TIMG_RTC_CALI_START bit.
*/
/**
* @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio
* @param cal_clk which clock to calibrate
* @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles
*/
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
{
/* Enable requested clock (150k clock is always on) */
int dig_32k_xtal_state = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN);
if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_state) {
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1);
}
if (cal_clk == RTC_CAL_8MD256) {
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
}
/* Prepare calibration */
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk);
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
/* Figure out how long to wait for calibration to finish */
/* Set timeout reg and expect time delay*/
uint32_t expected_freq;
if (cal_clk == RTC_CAL_32K_XTAL) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, (slowclk_cycles << 12));
expected_freq = 32768;
} else if (cal_clk == RTC_CAL_8MD256) {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, (slowclk_cycles << 12));
expected_freq = RTC_FAST_CLK_FREQ_APPROX / 256;
} else {
REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, (slowclk_cycles << 10));
expected_freq = 150000;
}
uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq);
/* Start calibration */
CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
/* Wait for calibration to finish up to another us_time_estimate */
ets_delay_us(us_time_estimate);
uint32_t cal_val;
while (true) {
if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) {
cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE);
break;
}
if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) {
cal_val = 0;
break;
}
}
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, dig_32k_xtal_state);
if (cal_clk == RTC_CAL_8MD256) {
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
}
return cal_val;
}
uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
{
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles;
uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX);
return ratio;
}
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
{
rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles;
uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider;
uint32_t period = (uint32_t)(period_64 & UINT32_MAX);
return period;
}
uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period)
{
/* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days.
* TODO: fix overflow.
*/
return (time_in_us << RTC_CLK_CAL_FRACT) / period;
}
uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
{
return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT;
}
uint64_t rtc_time_get()
{
SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
while (GET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_VALID) == 0) {
ets_delay_us(1); // might take 1 RTC slowclk period, don't flood RTC bus
}
SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_TIME_VALID_INT_CLR);
uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
return t;
}
uint64_t rtc_light_slp_time_get()
{
uint64_t t_wake = READ_PERI_REG(RTC_CNTL_TIME_LOW0_REG);
t_wake |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH0_REG)) << 32;
uint64_t t_slp = READ_PERI_REG(RTC_CNTL_TIME_LOW1_REG);
t_slp |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH1_REG)) << 32;
return (t_wake - t_slp);
}
uint64_t rtc_deep_slp_time_get()
{
uint64_t t_slp = READ_PERI_REG(RTC_CNTL_TIME_LOW1_REG);
t_slp |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH1_REG)) << 32;
uint64_t t_wake = rtc_time_get();
return (t_wake - t_slp);
}
void rtc_clk_wait_for_slow_cycle() //This function may not by useful any more
{
SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE);
while (GET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE)) {
ets_delay_us(1);
}
}

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// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
/**
* @file soc_log.h
* @brief SOC library logging functions
*
* To make SOC library compatible with environments which don't use ESP-IDF,
* this header file provides wrappers for logging functions.
*/
#define SOC_LOGE(tag, fmt, ...) ets_printf("%s(err): " fmt, tag, ##__VA_ARGS__)
#define SOC_LOGW(tag, fmt, ...) ets_printf("%s(warn): " fmt, tag, ##__VA_ARGS__)
#define SOC_LOGI(tag, fmt, ...) ets_printf("%s(info): " fmt, tag, ##__VA_ARGS__)
#define SOC_LOGD(tag, fmt, ...) ets_printf("%s(dbg): " fmt, tag, ##__VA_ARGS__)
#define SOC_LOGV(tag, fmt, ...) ets_printf("%s: " fmt, tag, ##__VA_ARGS__)

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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef BOOTLOADER_BUILD
#include <stdlib.h>
#include <stdint.h>
#include "soc/soc.h"
#include "soc/soc_memory_layout.h"
#include "esp_heap_caps.h"
#include "sdkconfig.h"
/* Memory layout for ESP32 SoC */
/*
Memory type descriptors. These describe the capabilities of a type of memory in the SoC. Each type of memory
map consist of one or more regions in the address space.
Each type contains an array of prioritised capabilities; types with later entries are only taken if earlier
ones can't fulfill the memory request.
The prioritised capabilities work roughly like this:
- For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions,
finally eat into the application memory.
- For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
- Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM.
- Most other malloc caps only fit in one region anyway.
*/
const soc_memory_type_desc_t soc_memory_types[] = {
//Type 0: DRAM
{ "DRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_DMA|MALLOC_CAP_32BIT, 0 }, false, false},
// Type 1: DRAM used for startup stacks
{ "DRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_DMA|MALLOC_CAP_32BIT, 0 }, false, true},
//Type 2: DRAM which has an alias on the I-port
//(This DRAM is also the region used by ROM during startup)
{ "D/IRAM", { 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL|MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }, true, true},
//Type 3: IRAM
{ "IRAM", { MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
//Type 4: SPI SRAM data
//TODO, in fact, part of them support EDMA, to be supported.
{ "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false},
//Type 5: SPI SRAM data from AHB DBUS3, slower than normal
//TODO, add a bit to control the access of it
#if CONFIG_USE_AHB_DBUS3_ACCESS_SPIRAM
{ "SPIRAM(Slow)", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false},
#endif
};
const size_t soc_memory_type_count = sizeof(soc_memory_types)/sizeof(soc_memory_type_desc_t);
/*
Region descriptors. These describe all regions of memory available, and map them to a type in the above type.
Because of requirements in the coalescing code which merges adjacent regions, this list should always be sorted
from low to high start address.
*/
const soc_memory_region_t soc_memory_regions[] = {
#ifdef CONFIG_SPIRAM_SUPPORT
{ SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW, 4, 0}, //SPI SRAM, if available
#if CONFIG_USE_AHB_DBUS3_ACCESS_SPIRAM
{ SOC_SLOW_EXTRAM_DATA_LOW, SOC_SLOW_EXTRAM_DATA_HIGH - SOC_SLOW_EXTRAM_DATA_LOW, 5, 0}, //SPI SRAM, if available
#endif
#endif
#if CONFIG_INSTRUCTION_CACHE_8KB
#if CONFIG_DATA_CACHE_0KB
{ 0x3FFB2000, 0x2000, 0, 0x400B2000}, //Block 1, can be use as I/D cache memory
{ 0x3FFB4000, 0x2000, 0, 0x400B4000}, //Block 2, can be use as D cache memory
{ 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory
#elif CONFIG_DATA_CACHE_8KB
{ 0x3FFB4000, 0x2000, 0, 0x400B4000}, //Block 2, can be use as D cache memory
{ 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory
#else
{ 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory
#endif
#else
#if CONFIG_DATA_CACHE_0KB
{ 0x3FFB4000, 0x2000, 0, 0x400B4000}, //Block 2, can be use as D cache memory
{ 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory
#elif CONFIG_DATA_CACHE_8KB
{ 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory
#endif
#endif
{ 0x3FFB8000, 0x4000, 0, 0x40028000}, //Block 4, can be remapped to ROM, can be used as trace memory
{ 0x3FFBC000, 0x4000, 0, 0x4002C000}, //Block 5, can be remapped to ROM, can be used as trace memory
{ 0x3FFC0000, 0x4000, 0, 0x40030000}, //Block 6, can be used as trace memory
{ 0x3FFC4000, 0x4000, 0, 0x40034000}, //Block 7, can be used as trace memory
{ 0x3FFC8000, 0x4000, 0, 0x40038000}, //Block 8, can be used as trace memory
{ 0x3FFCC000, 0x4000, 0, 0x4003C000}, //Block 9, can be used as trace memory
{ 0x3FFD0000, 0x4000, 0, 0x40040000}, //Block 10, can be used as trace memory
{ 0x3FFD4000, 0x4000, 0, 0x40044000}, //Block 11, can be used as trace memory
{ 0x3FFD8000, 0x4000, 0, 0x40048000}, //Block 12, can be used as trace memory
{ 0x3FFDC000, 0x4000, 0, 0x4004C000}, //Block 13, can be used as trace memory
{ 0x3FFE0000, 0x4000, 0, 0x40050000}, //Block 14, can be used as trace memory
{ 0x3FFE4000, 0x4000, 0, 0x40054000}, //Block 15, can be used as trace memory
{ 0x3FFE8000, 0x4000, 0, 0x40058000}, //Block 16, can be used as trace memory
{ 0x3FFEC000, 0x4000, 0, 0x4005C000}, //Block 17, can be used as trace memory
{ 0x3FFF0000, 0x4000, 0, 0x40060000}, //Block 18, can be used for MAC dump, can be used as trace memory
{ 0x3FFF4000, 0x4000, 0, 0x40064000}, //Block 19, can be used for MAC dump, can be used as trace memory
{ 0x3FFF8000, 0x4000, 0, 0x40068000}, //Block 20, can be used for MAC dump, can be used as trace memory
{ 0x3FFFC000, 0x4000, 1, 0x4006C000}, //Block 21, can be used for MAC dump, can be used as trace memory, used for startup stack
};
const size_t soc_memory_region_count = sizeof(soc_memory_regions)/sizeof(soc_memory_region_t);
extern int _data_start_xtos;
/* Reserved memory regions
These are removed from the soc_memory_regions array when heaps are created.
*/
const soc_reserved_region_t soc_reserved_regions[] = {
// { 0x40070000, 0x40078000 }, //CPU0 cache region
// { 0x40078000, 0x40080000 }, //CPU1 cache region
{ 0x3fff8000, (intptr_t)&_data_start_xtos}, //ROM data region
#if CONFIG_MEMMAP_TRACEMEM
#if CONFIG_MEMMAP_TRACEMEM_TWOBANKS
{ 0x3fff8000, 0x40000000 }, //Reserve trace mem region
#else
{ 0x3fff8000, 0x3fffc000 }, //Reserve trace mem region
#endif
#endif
#ifdef CONFIG_SPIRAM_SUPPORT
{ SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH}, //SPI RAM gets added later if needed, in spiram.c; reserve it for now
#if CONFIG_USE_AHB_DBUS3_ACCESS_SPIRAM
{ SOC_SLOW_EXTRAM_DATA_LOW, SOC_SLOW_EXTRAM_DATA_HIGH}, //SPI RAM(Slow) gets added later if needed, in spiram.c; reserve it for now
#endif
#endif
};
const size_t soc_reserved_region_count = sizeof(soc_reserved_regions)/sizeof(soc_reserved_region_t);
#endif

12
components/soc/esp32s2beta/sources.cmake Normal file
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@ -0,0 +1,12 @@
set(SOC_SRCS "rtc_clk.c"
"rtc_init.c"
"rtc_pm.c"
"rtc_sleep.c"
"rtc_time.c"
"soc_memory_layout.c"
"spi_periph.c")
if(NOT CMAKE_BUILD_EARLY_EXPANSION)
set_source_files_properties("esp32s2beta/rtc_clk.c" PROPERTIES
COMPILE_FLAGS "-fno-jump-tables -fno-tree-switch-conversion")
endif()

123
components/soc/esp32s2beta/spi_periph.c Normal file
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// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "soc/spi_periph.h"
#include "stddef.h"
/*
Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const spi_signal_conn_t spi_periph_signal[4] = {
{
.spiclk_out = SPICLK_OUT_IDX,
.spiclk_in = 0,/* SPI clock is not an input signal*/
.spid_out = SPID_OUT_IDX,
.spiq_out = SPIQ_OUT_IDX,
.spiwp_out = SPIWP_OUT_IDX,
.spihd_out = SPIHD_OUT_IDX,
.spid_in = SPID_IN_IDX,
.spiq_in = SPIQ_IN_IDX,
.spiwp_in = SPIWP_IN_IDX,
.spihd_in = SPIHD_IN_IDX,
.spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX},/* SPI0/1 do not have CS2 now */
.spics_in = 0,/* SPI cs is not an input signal*/
.spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
.spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
.spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
.spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
.spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
.spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
.irq = ETS_SPI1_INTR_SOURCE,
.irq_dma = ETS_SPI1_DMA_INTR_SOURCE,
.module = PERIPH_SPI_MODULE,
.hw = (spi_dev_t *) &SPIMEM1,
.func = SPI_FUNC_NUM,
}, {
.spiclk_out = FSPICLK_OUT_MUX_IDX,
.spiclk_in = FSPICLK_IN_IDX,
.spid_out = FSPID_OUT_IDX,
.spiq_out = FSPIQ_OUT_IDX,
.spiwp_out = FSPIWP_OUT_IDX,
.spihd_out = FSPIHD_OUT_IDX,
.spid_in = FSPID_IN_IDX,
.spiq_in = FSPIQ_IN_IDX,
.spiwp_in = FSPIWP_IN_IDX,
.spihd_in = FSPIHD_IN_IDX,
.spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX},
.spics_in = FSPICS0_IN_IDX,
.spiclk_iomux_pin = FSPI_IOMUX_PIN_NUM_CLK,
.spid_iomux_pin = FSPI_IOMUX_PIN_NUM_MOSI,
.spiq_iomux_pin = FSPI_IOMUX_PIN_NUM_MISO,
.spiwp_iomux_pin = FSPI_IOMUX_PIN_NUM_WP,
.spihd_iomux_pin = FSPI_IOMUX_PIN_NUM_HD,
.spics0_iomux_pin = FSPI_IOMUX_PIN_NUM_CS,
.irq = ETS_SPI2_INTR_SOURCE,
.irq_dma = ETS_SPI2_DMA_INTR_SOURCE,
.module = PERIPH_FSPI_MODULE,
.hw = &GPSPI2,
.func = FSPI_FUNC_NUM,
}, {
.spiclk_out = SPI3_CLK_OUT_MUX_IDX,
.spiclk_in = SPI3_CLK_IN_IDX,
.spid_out = SPI3_D_OUT_IDX,
.spiq_out = SPI3_Q_OUT_IDX,
//SPI3 doesn't have wp and hd signals
.spiwp_out = -1,
.spihd_out = -1,
.spid_in = SPI3_D_IN_IDX,
.spiq_in = SPI3_Q_IN_IDX,
.spiwp_in = -1,
.spihd_in = -1,
.spics_out = {SPI3_CS0_OUT_IDX, SPI3_CS1_OUT_IDX, SPI3_CS2_OUT_IDX},
.spics_in = SPI3_CS0_IN_IDX,
//SPI3 doesn't have iomux pins
.spiclk_iomux_pin = -1,
.spid_iomux_pin = -1,
.spiq_iomux_pin = -1,
.spiwp_iomux_pin = -1,
.spihd_iomux_pin = -1,
.spics0_iomux_pin = -1,
.irq = ETS_SPI3_INTR_SOURCE,
.irq_dma = ETS_SPI3_DMA_INTR_SOURCE,
.module = PERIPH_HSPI_MODULE,
.hw = &GPSPI3,
.func = -1,
}, {
.spiclk_out = SPI4_CLK_OUT_MUX_IDX,
.spiclk_in = SPI4_CLK_IN_IDX,
.spid_out = SPI4_D_OUT_IDX,
.spiq_out = SPI4_Q_OUT_IDX,
//SPI4 doesn't have wp and hd signals
.spiwp_out = -1,
.spihd_out = -1,
.spid_in = SPI4_D_IN_IDX,
.spiq_in = SPI4_Q_IN_IDX,
.spiwp_in = -1,
.spihd_in = -1,
.spics_out = {SPI4_CS0_OUT_IDX, SPI4_CS1_OUT_IDX, SPI4_CS2_OUT_IDX},
.spics_in = SPI4_CS0_IN_IDX,
//SPI4 doesn't have iomux pins
.spiclk_iomux_pin = -1,
.spid_iomux_pin = -1,
.spiq_iomux_pin = -1,
.spiwp_iomux_pin = -1,
.spihd_iomux_pin = -1,
.spics0_iomux_pin = -1,
.irq = ETS_SPI4_INTR_SOURCE,
.irq_dma = ETS_SPI4_DMA_INTR_SOURCE,
.module = PERIPH_VSPI_MODULE,
.hw = &GPSPI4,
.func = -1,
}
};

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