DISABLED_FOR_TARGETS macros are used Partly revert "ci: disable unavailable tests for esp32s2beta" This partly reverts commit76a3a5fb48
. Partly revert "ci: disable UTs for esp32s2beta without runners" This partly reverts commiteb158e9a22
. Partly revert "fix unit test and examples for s2beta" This partly reverts commit9baa7826be
. Partly revert "efuse: Add support for esp32s2beta" This partly reverts commitdb84ba868c
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388 lines
No EOL
12 KiB
C
388 lines
No EOL
12 KiB
C
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "soc/soc_caps.h"
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#ifdef SOC_SDMMC_HOST_SUPPORTED
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "esp_log.h"
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#include "esp_heap_caps.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "driver/gpio.h"
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#include "driver/sdmmc_host.h"
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#include "driver/sdmmc_defs.h"
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#include "sdmmc_cmd.h"
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#include "unity.h"
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/* Second ESP32 board attached as follows:
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* Master Slave
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* IO18 EN
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* IO19 IO0
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* IO14 SD_CLK
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* IO15 SD_CMD
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* IO2 SD_D0
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* IO4 SD_D1
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* IO12 SD_D2
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* IO13 SD_D3
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*/
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/* TODO: add SDIO slave header files, remove these definitions */
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#define DR_REG_SLC_MASK 0xfffffc00
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#define SLCCONF1 (DR_REG_SLC_BASE + 0x60)
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#define SLC_SLC0_RX_STITCH_EN (BIT(6))
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#define SLC_SLC0_TX_STITCH_EN (BIT(5))
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#define SLC0TX_LINK (DR_REG_SLC_BASE + 0x40)
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#define SLC_SLC0_TXLINK_PARK (BIT(31))
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#define SLC_SLC0_TXLINK_RESTART (BIT(30))
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#define SLC_SLC0_TXLINK_START (BIT(29))
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#define DR_REG_SLCHOST_MASK 0xfffffc00
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#define SLCHOST_STATE_W0 (DR_REG_SLCHOST_BASE + 0x64)
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#define SLCHOST_CONF_W0 (DR_REG_SLCHOST_BASE + 0x6C)
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#define SLCHOST_CONF_W5 (DR_REG_SLCHOST_BASE + 0x80)
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#define SLCHOST_WIN_CMD (DR_REG_SLCHOST_BASE + 0x84)
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#define SLC_WIN_CMD_READ 0x80
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#define SLC_WIN_CMD_WRITE 0xC0
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#define SLC_WIN_CMD_S 8
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#define SLC_THRESHOLD_ADDR 0x1f800
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static const char* TAG = "sdio_test";
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static esp_err_t slave_slchost_reg_read(sdmmc_card_t* card, uint32_t addr, uint32_t* out_val)
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{
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if ((addr & DR_REG_SLCHOST_MASK) != DR_REG_SLCHOST_BASE) {
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ESP_LOGW(TAG, "%s: invalid addr 0x%08x\n", __func__, addr);
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return ESP_ERR_INVALID_ARG;
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}
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return sdmmc_io_read_bytes(card, 1, addr & (~DR_REG_SLCHOST_MASK), out_val, sizeof(*out_val));
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}
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static esp_err_t slave_slchost_reg_write(sdmmc_card_t* card, uint32_t addr, uint32_t val)
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{
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if ((addr & DR_REG_SLCHOST_MASK) != DR_REG_SLCHOST_BASE) {
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ESP_LOGW(TAG, "%s: invalid addr 0x%08x\n", __func__, addr);
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return ESP_ERR_INVALID_ARG;
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}
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return sdmmc_io_write_bytes(card, 1, addr & (~DR_REG_SLCHOST_MASK), &val, sizeof(val));
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}
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static esp_err_t slave_slc_reg_read(sdmmc_card_t* card, uint32_t addr, uint32_t* val)
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{
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if ((addr & DR_REG_SLC_MASK) != DR_REG_SLC_BASE) {
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ESP_LOGW(TAG, "%s: invalid addr 0x%08x\n", __func__, addr);
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return ESP_ERR_INVALID_ARG;
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}
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uint32_t word = (addr - DR_REG_SLC_BASE) / 4;
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if (word > INT8_MAX) {
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return ESP_ERR_INVALID_ARG;
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}
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uint32_t window_command = word | (SLC_WIN_CMD_READ << SLC_WIN_CMD_S);
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esp_err_t err = slave_slchost_reg_write(card, SLCHOST_WIN_CMD, window_command);
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if (err != ESP_OK) {
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return err;
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}
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return slave_slchost_reg_read(card, SLCHOST_STATE_W0, val);
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}
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static esp_err_t slave_slc_reg_write(sdmmc_card_t* card, uint32_t addr, uint32_t val)
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{
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if ((addr & DR_REG_SLC_MASK) != DR_REG_SLC_BASE) {
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ESP_LOGW(TAG, "%s: invalid addr 0x%08x\n", __func__, addr);
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return ESP_ERR_INVALID_ARG;
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}
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uint32_t word = (addr - DR_REG_SLC_BASE) / 4;
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if (word > INT8_MAX) {
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return ESP_ERR_INVALID_ARG;
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}
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esp_err_t err = slave_slchost_reg_write(card, SLCHOST_CONF_W5, val);
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if (err != ESP_OK) {
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return err;
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}
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uint32_t window_command = word | (SLC_WIN_CMD_WRITE << SLC_WIN_CMD_S);
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return slave_slchost_reg_write(card, SLCHOST_WIN_CMD, window_command);
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}
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/** Reset and put slave into download mode */
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static void reset_slave(void)
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{
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const int pin_en = 18;
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const int pin_io0 = 19;
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gpio_config_t gpio_cfg = {
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.pin_bit_mask = BIT64(pin_en) | BIT64(pin_io0),
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.mode = GPIO_MODE_OUTPUT_OD,
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};
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TEST_ESP_OK(gpio_config(&gpio_cfg));
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gpio_set_level(pin_en, 0);
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gpio_set_level(pin_io0, 0);
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vTaskDelay(10 / portTICK_PERIOD_MS);
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gpio_set_level(pin_en, 1);
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vTaskDelay(10 / portTICK_PERIOD_MS);
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gpio_set_level(pin_io0, 1);
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}
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static void sdio_slave_common_init(sdmmc_card_t* card)
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{
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uint8_t card_cap;
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esp_err_t err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_CARD_CAP, &card_cap);
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TEST_ESP_OK(err);
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printf("CAP: 0x%02x\n", card_cap);
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uint8_t hs;
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err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_HIGHSPEED, &hs);
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TEST_ESP_OK(err);
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printf("HS: 0x%02x\n", hs);
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#define FUNC1_EN_MASK (BIT(1))
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uint8_t ioe;
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err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_FN_ENABLE, &ioe);
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TEST_ESP_OK(err);
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printf("IOE: 0x%02x\n", ioe);
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uint8_t ior = 0;
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err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_FN_READY, &ior);
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TEST_ESP_OK(err);
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printf("IOR: 0x%02x\n", ior);
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// enable function 1
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ioe |= FUNC1_EN_MASK;
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err = sdmmc_io_write_byte(card, 0, SD_IO_CCCR_FN_ENABLE, ioe, NULL);
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TEST_ESP_OK(err);
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err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_FN_ENABLE, &ioe);
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TEST_ESP_OK(err);
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printf("IOE: 0x%02x\n", ioe);
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// wait for the card to become ready
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while ( (ior & FUNC1_EN_MASK) == 0 ) {
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err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_FN_READY, &ior);
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TEST_ESP_OK(err);
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printf("IOR: 0x%02x\n", ior);
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}
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// get interrupt status
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uint8_t ie;
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err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_INT_ENABLE, &ie);
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TEST_ESP_OK(err);
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printf("IE: 0x%02x\n", ie);
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// enable interrupts for function 1&2 and master enable
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ie |= BIT(0) | FUNC1_EN_MASK;
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err = sdmmc_io_write_byte(card, 0, SD_IO_CCCR_INT_ENABLE, ie, NULL);
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TEST_ESP_OK(err);
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err = sdmmc_io_read_byte(card, 0, SD_IO_CCCR_INT_ENABLE, &ie);
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TEST_ESP_OK(err);
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printf("IE: 0x%02x\n", ie);
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}
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/** Common for all SDIO devices, set block size for specific function */
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static void sdio_slave_set_blocksize(sdmmc_card_t* card, int function, uint16_t bs)
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{
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const uint8_t* bs_u8 = (const uint8_t*) &bs;
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uint16_t bs_read = 0;
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uint8_t* bs_read_u8 = (uint8_t*) &bs_read;
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uint32_t offset = SD_IO_FBR_START * function;
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TEST_ESP_OK( sdmmc_io_write_byte(card, 0, offset + SD_IO_CCCR_BLKSIZEL, bs_u8[0], NULL));
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TEST_ESP_OK( sdmmc_io_write_byte(card, 0, offset + SD_IO_CCCR_BLKSIZEH, bs_u8[1], NULL));
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TEST_ESP_OK( sdmmc_io_read_byte(card, 0, offset + SD_IO_CCCR_BLKSIZEL, &bs_read_u8[0]));
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TEST_ESP_OK( sdmmc_io_read_byte(card, 0, offset + SD_IO_CCCR_BLKSIZEH, &bs_read_u8[1]));
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TEST_ASSERT_EQUAL_HEX16(bs, bs_read);
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}
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/**
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* ESP32 ROM code does not set some SDIO slave registers to the defaults
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* we need, this function clears/sets some bits.
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*/
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static void esp32_slave_init_extra(sdmmc_card_t* card)
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{
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printf("Initialize some ESP32 SDIO slave registers\n");
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uint32_t reg_val;
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TEST_ESP_OK( slave_slc_reg_read(card, SLCCONF1, ®_val) );
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reg_val &= ~(SLC_SLC0_RX_STITCH_EN | SLC_SLC0_TX_STITCH_EN);
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TEST_ESP_OK( slave_slc_reg_write(card, SLCCONF1, reg_val) );
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TEST_ESP_OK( slave_slc_reg_read(card, SLC0TX_LINK, ®_val) );
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reg_val |= SLC_SLC0_TXLINK_START;
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TEST_ESP_OK( slave_slc_reg_write(card, SLC0TX_LINK, reg_val) );
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}
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/**
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* ESP32 bootloader implements "SIP" protocol which can be used to exchange
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* some commands, events, and data packets between the host and the slave.
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* This function sends a SIP command, testing CMD53 block writes along the way.
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*/
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static void esp32_send_sip_command(sdmmc_card_t* card)
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{
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printf("Test block write using CMD53\n");
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const size_t block_size = 512;
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uint8_t* data = heap_caps_calloc(1, block_size, MALLOC_CAP_DMA);
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struct sip_cmd_bootup {
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uint32_t boot_addr;
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uint32_t discard_link;
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};
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struct sip_cmd_write_reg {
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uint32_t addr;
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uint32_t val;
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};
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struct sip_hdr {
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uint8_t fc[2];
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uint16_t len;
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uint32_t cmdid;
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uint32_t seq;
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};
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struct sip_hdr* hdr = (struct sip_hdr*) data;
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size_t len;
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#define SEND_WRITE_REG_CMD
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#ifdef SEND_WRITE_REG_CMD
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struct sip_cmd_write_reg *write_reg = (struct sip_cmd_write_reg*) (data + sizeof(*hdr));
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len = sizeof(*hdr) + sizeof(*write_reg);
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hdr->cmdid = 3; /* SIP_CMD_WRITE_REG */
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write_reg->addr = GPIO_ENABLE_W1TS_REG;
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write_reg->val = BIT(0) | BIT(2) | BIT(4); /* Turn of RGB LEDs on WROVER-KIT */
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#else
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struct sip_cmd_bootup *bootup = (struct sip_cmd_bootup*) (data + sizeof(*hdr));
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len = sizeof(*hdr) + sizeof(*bootup);
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hdr->cmdid = 5; /* SIP_CMD_BOOTUP */
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bootup->boot_addr = 0x4005a980; /* start_tb_console function in ROM */
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bootup->discard_link = 1;
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#endif
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hdr->len = len;
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TEST_ESP_OK( sdmmc_io_write_blocks(card, 1, SLC_THRESHOLD_ADDR - len, data, block_size) );
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free(data);
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}
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static void test_cmd52_read_write_single_byte(sdmmc_card_t* card)
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{
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esp_err_t err;
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printf("Write bytes to slave's W0_REG using CMD52\n");
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const size_t scratch_area_reg = SLCHOST_CONF_W0 - DR_REG_SLCHOST_BASE;
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const uint8_t test_byte_1 = 0xa5;
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const uint8_t test_byte_2 = 0xb6;
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// used to check Read-After-Write
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uint8_t test_byte_1_raw;
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uint8_t test_byte_2_raw;
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uint8_t val = 0;
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err = sdmmc_io_write_byte(card, 1, scratch_area_reg, test_byte_1, &test_byte_1_raw);
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TEST_ESP_OK(err);
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TEST_ASSERT_EQUAL_UINT8(test_byte_1, test_byte_1_raw);
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err = sdmmc_io_write_byte(card, 1, scratch_area_reg + 1, test_byte_2, &test_byte_2_raw);
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TEST_ESP_OK(err);
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TEST_ASSERT_EQUAL_UINT8(test_byte_2, test_byte_2_raw);
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printf("Read back bytes using CMD52\n");
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TEST_ESP_OK(sdmmc_io_read_byte(card, 1, scratch_area_reg, &val));
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TEST_ASSERT_EQUAL_UINT8(test_byte_1, val);
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TEST_ESP_OK(sdmmc_io_read_byte(card, 1, scratch_area_reg + 1, &val));
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TEST_ASSERT_EQUAL_UINT8(test_byte_2, val);
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}
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static void test_cmd53_read_write_multiple_bytes(sdmmc_card_t* card, size_t n_bytes)
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{
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printf("Write multiple bytes using CMD53\n");
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const size_t scratch_area_reg = SLCHOST_CONF_W0 - DR_REG_SLCHOST_BASE;
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uint8_t* src = heap_caps_malloc(512, MALLOC_CAP_DMA);
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uint32_t* src_32 = (uint32_t*) src;
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for (size_t i = 0; i < (n_bytes + 3) / 4; ++i) {
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src_32[i] = rand();
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}
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TEST_ESP_OK(sdmmc_io_write_bytes(card, 1, scratch_area_reg, src, n_bytes));
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ESP_LOG_BUFFER_HEX(TAG, src, n_bytes);
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printf("Read back using CMD52\n");
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uint8_t* dst = heap_caps_malloc(512, MALLOC_CAP_DMA);
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for (size_t i = 0; i < n_bytes; ++i) {
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TEST_ESP_OK(sdmmc_io_read_byte(card, 1, scratch_area_reg + i, &dst[i]));
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}
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ESP_LOG_BUFFER_HEX(TAG, dst, n_bytes);
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TEST_ASSERT_EQUAL_UINT8_ARRAY(src, dst, n_bytes);
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printf("Read back using CMD53\n");
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TEST_ESP_OK(sdmmc_io_read_bytes(card, 1, scratch_area_reg, dst, n_bytes));
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ESP_LOG_BUFFER_HEX(TAG, dst, n_bytes);
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TEST_ASSERT_EQUAL_UINT8_ARRAY(src, dst, n_bytes);
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free(src);
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free(dst);
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}
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TEST_CASE("can probe and talk to ESP32 SDIO slave", "[sdio][ignore]")
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{
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reset_slave();
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/* Probe */
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sdmmc_host_t config = SDMMC_HOST_DEFAULT();
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config.flags = SDMMC_HOST_FLAG_1BIT;
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config.max_freq_khz = SDMMC_FREQ_PROBING;
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sdmmc_slot_config_t slot_config = SDMMC_SLOT_CONFIG_DEFAULT();
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(sdmmc_host_init());
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(sdmmc_host_init_slot(SDMMC_HOST_SLOT_1, &slot_config));
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sdmmc_card_t* card = malloc(sizeof(sdmmc_card_t));
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TEST_ASSERT_NOT_NULL(card);
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TEST_ESP_OK(sdmmc_card_init(&config, card));
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sdmmc_card_print_info(stdout, card);
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/* Set up standard SDIO registers */
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sdio_slave_common_init(card);
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srand(0);
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for (int repeat = 0; repeat < 4; ++repeat) {
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test_cmd52_read_write_single_byte(card);
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test_cmd53_read_write_multiple_bytes(card, 1);
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test_cmd53_read_write_multiple_bytes(card, 2);
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test_cmd53_read_write_multiple_bytes(card, 3);
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test_cmd53_read_write_multiple_bytes(card, 4);
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test_cmd53_read_write_multiple_bytes(card, 5);
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test_cmd53_read_write_multiple_bytes(card, 23);
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test_cmd53_read_write_multiple_bytes(card, 24);
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}
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sdio_slave_set_blocksize(card, 0, 512);
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sdio_slave_set_blocksize(card, 1, 512);
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esp32_slave_init_extra(card);
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esp32_send_sip_command(card);
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TEST_ESP_OK(sdmmc_host_deinit());
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free(card);
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}
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#endif |