OVMS3-idf/components/soc/include/hal
Michael (XIAO Xufeng) 571864e8ae esp_flash: fix set qe bit and write command issues
There used to be dummy phase before out phase in common command
transactions. This corrupts the data.

The code before never actually operate (clear) the QE bit, once it finds
the QE bit is set. It's hard to check whether the QE set/disable
functions work well.

This commit:

1. Cancel the dummy phase

2. Set and clear the QE bit according to chip settings, allowing tests
   for QE bits. However for some chips (Winbond for example), it's not
   forced to clear the QE bit if not able to.

3. Also refactor to allow chip_generic and other chips to share the same
   code to read and write qe bit; let common command and read command share
   configure_host_io_mode.

4. Rename read mode to io mode since maybe we will write data with quad
   mode one day.
2019-10-14 17:25:58 +08:00
..
esp_flash_err.h Fix error code collision and CI check 2019-08-29 08:14:08 +00:00
hal_defs.h spi_master: refactor and add HAL support 2019-03-28 17:14:50 +08:00
readme.md spi_slave: add HAL support 2019-05-20 07:34:34 +00:00
spi_flash_hal.h esp_flash: fix set qe bit and write command issues 2019-10-14 17:25:58 +08:00
spi_flash_types.h esp_flash: fix set qe bit and write command issues 2019-10-14 17:25:58 +08:00
spi_hal.h spi: multichip support 2019-06-20 10:38:52 +08:00
spi_ll.h spi: multichip support 2019-06-20 10:38:52 +08:00
spi_slave_hal.h spi: multichip support 2019-06-20 10:38:52 +08:00
spi_types.h spi: multichip support 2019-06-20 10:38:52 +08:00
timer_types.h esp_attr: add flag_attr to support enums used as flags 2019-08-09 13:46:32 +08:00

HAL Layer Readme

The HAL layer is designed to be used by the drivers. We don't guarantee the stability and back-compatibility among versions. The HAL layer may update very frequently with the driver. Please don't use them in the applications or treat them as stable APIs.

The HAL layer consists of two layers: HAL (upper) and Lowlevel(bottom). The HAL layer defines the steps and data required by the peripheral. The lowlevel is a translation layer converting general conceptions to register configurations.

Lowlevel

This layer should be all static inline. The first argument of LL functions is usually a pointer to the beginning address of the peripheral register. Each chip should have its own LL layer. The functions in this layer should be atomic and independent from each other so that the upper layer can change/perform one of the options/operation without touching the others.

HAL

This layer should depend on the operating system as little as possible. It's a wrapping of LL functions, so that the upper layer can combine basic steps into different working ways (polling, non-polling, interrupt, etc.). Without using queues/locks/delay/loop/etc., this layer can be easily port to other os or simulation systems.

To get better performance and better porting ability, contexts are used to hold sustainable data and pass the parameters.

To develop your own driver, it is suggested to copy the HAL layer to your own code and keep them until manual update.