OVMS3-idf/components/soc
Angus Gratton 32756b165e bootloader: Add fault injection resistance to Secure Boot bootloader verification
Goal is that multiple faults would be required to bypass a boot-time signature check.

- Also strengthens some address range checks for safe app memory addresses
- Change pre-enable logic to also check the bootloader signature before enabling SBV2 on ESP32

Add some additional checks for invalid sections:

- Sections only partially in DRAM or IRAM are invalid
- If a section is in D/IRAM, allow the possibility only some is in D/IRAM
- Only pass sections that are entirely in the same type of RTC memory region
2020-03-06 01:16:04 +05:30
..
esp32 bootloader: Add fault injection resistance to Secure Boot bootloader verification 2020-03-06 01:16:04 +05:30
esp32s2beta bootloader: Add fault injection resistance to Secure Boot bootloader verification 2020-03-06 01:16:04 +05:30
include bootloader: Add fault injection resistance to Secure Boot bootloader verification 2020-03-06 01:16:04 +05:30
src can: Refactor CAN to use HAL and LowLevel layers 2020-01-09 16:13:51 +08:00
test soc: fix unit tests not included in the build 2019-11-18 15:58:49 +07:00
CMakeLists.txt can: Refactor CAN to use HAL and LowLevel layers 2020-01-09 16:13:51 +08:00
component.mk add esp32s2beta in soc component 2019-06-11 13:06:32 +08:00
linker.lf ble_mesh_wifi_coexist example: Disable Wi-Fi RX IRAM optimisation 2019-11-28 09:20:00 +08:00